1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/mlx4/cq.h> 35 #include <linux/mlx4/qp.h> 36 #include <linux/mlx4/srq.h> 37 #include <linux/slab.h> 38 39 #include "mlx4_ib.h" 40 #include <rdma/mlx4-abi.h> 41 #include <rdma/uverbs_ioctl.h> 42 43 static void mlx4_ib_cq_comp(struct mlx4_cq *cq) 44 { 45 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 46 ibcq->comp_handler(ibcq, ibcq->cq_context); 47 } 48 49 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) 50 { 51 struct ib_event event; 52 struct ib_cq *ibcq; 53 54 if (type != MLX4_EVENT_TYPE_CQ_ERROR) { 55 pr_warn("Unexpected event type %d " 56 "on CQ %06x\n", type, cq->cqn); 57 return; 58 } 59 60 ibcq = &to_mibcq(cq)->ibcq; 61 if (ibcq->event_handler) { 62 event.device = ibcq->device; 63 event.event = IB_EVENT_CQ_ERR; 64 event.element.cq = ibcq; 65 ibcq->event_handler(&event, ibcq->cq_context); 66 } 67 } 68 69 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) 70 { 71 return mlx4_buf_offset(&buf->buf, n * buf->entry_size); 72 } 73 74 static void *get_cqe(struct mlx4_ib_cq *cq, int n) 75 { 76 return get_cqe_from_buf(&cq->buf, n); 77 } 78 79 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) 80 { 81 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); 82 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); 83 84 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ 85 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; 86 } 87 88 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) 89 { 90 return get_sw_cqe(cq, cq->mcq.cons_index); 91 } 92 93 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 94 { 95 struct mlx4_ib_cq *mcq = to_mcq(cq); 96 struct mlx4_ib_dev *dev = to_mdev(cq->device); 97 98 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); 99 } 100 101 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) 102 { 103 int err; 104 105 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, 106 PAGE_SIZE * 2, &buf->buf); 107 108 if (err) 109 goto out; 110 111 buf->entry_size = dev->dev->caps.cqe_size; 112 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, 113 &buf->mtt); 114 if (err) 115 goto err_buf; 116 117 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf); 118 if (err) 119 goto err_mtt; 120 121 return 0; 122 123 err_mtt: 124 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 125 126 err_buf: 127 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); 128 129 out: 130 return err; 131 } 132 133 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) 134 { 135 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); 136 } 137 138 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, 139 struct mlx4_ib_cq_buf *buf, 140 struct ib_umem **umem, u64 buf_addr, int cqe) 141 { 142 int err; 143 int cqe_size = dev->dev->caps.cqe_size; 144 int shift; 145 int n; 146 147 *umem = ib_umem_get(&dev->ib_dev, buf_addr, cqe * cqe_size, 148 IB_ACCESS_LOCAL_WRITE); 149 if (IS_ERR(*umem)) 150 return PTR_ERR(*umem); 151 152 shift = mlx4_ib_umem_calc_optimal_mtt_size(*umem, 0, &n); 153 err = mlx4_mtt_init(dev->dev, n, shift, &buf->mtt); 154 155 if (err) 156 goto err_buf; 157 158 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); 159 if (err) 160 goto err_mtt; 161 162 return 0; 163 164 err_mtt: 165 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 166 167 err_buf: 168 ib_umem_release(*umem); 169 170 return err; 171 } 172 173 #define CQ_CREATE_FLAGS_SUPPORTED IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION 174 int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 175 struct uverbs_attr_bundle *attrs) 176 { 177 struct ib_udata *udata = &attrs->driver_udata; 178 struct ib_device *ibdev = ibcq->device; 179 int entries = attr->cqe; 180 int vector = attr->comp_vector; 181 struct mlx4_ib_dev *dev = to_mdev(ibdev); 182 struct mlx4_ib_cq *cq = to_mcq(ibcq); 183 struct mlx4_uar *uar; 184 void *buf_addr; 185 int err; 186 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 187 udata, struct mlx4_ib_ucontext, ibucontext); 188 189 if (entries < 1 || entries > dev->dev->caps.max_cqes) 190 return -EINVAL; 191 192 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED) 193 return -EINVAL; 194 195 entries = roundup_pow_of_two(entries + 1); 196 cq->ibcq.cqe = entries - 1; 197 mutex_init(&cq->resize_mutex); 198 spin_lock_init(&cq->lock); 199 cq->resize_buf = NULL; 200 cq->resize_umem = NULL; 201 cq->create_flags = attr->flags; 202 INIT_LIST_HEAD(&cq->send_qp_list); 203 INIT_LIST_HEAD(&cq->recv_qp_list); 204 205 if (udata) { 206 struct mlx4_ib_create_cq ucmd; 207 208 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 209 err = -EFAULT; 210 goto err_cq; 211 } 212 213 buf_addr = (void *)(unsigned long)ucmd.buf_addr; 214 err = mlx4_ib_get_cq_umem(dev, &cq->buf, &cq->umem, 215 ucmd.buf_addr, entries); 216 if (err) 217 goto err_cq; 218 219 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &cq->db); 220 if (err) 221 goto err_mtt; 222 223 uar = &context->uar; 224 cq->mcq.usage = MLX4_RES_USAGE_USER_VERBS; 225 } else { 226 err = mlx4_db_alloc(dev->dev, &cq->db, 1); 227 if (err) 228 goto err_cq; 229 230 cq->mcq.set_ci_db = cq->db.db; 231 cq->mcq.arm_db = cq->db.db + 1; 232 *cq->mcq.set_ci_db = 0; 233 *cq->mcq.arm_db = 0; 234 235 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); 236 if (err) 237 goto err_db; 238 239 buf_addr = &cq->buf.buf; 240 241 uar = &dev->priv_uar; 242 cq->mcq.usage = MLX4_RES_USAGE_DRIVER; 243 } 244 245 if (dev->eq_table) 246 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 247 248 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, cq->db.dma, 249 &cq->mcq, vector, 0, 250 !!(cq->create_flags & 251 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION), 252 buf_addr, !!udata); 253 if (err) 254 goto err_dbmap; 255 256 if (udata) 257 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp; 258 else 259 cq->mcq.comp = mlx4_ib_cq_comp; 260 cq->mcq.event = mlx4_ib_cq_event; 261 262 if (udata) 263 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { 264 err = -EFAULT; 265 goto err_cq_free; 266 } 267 268 return 0; 269 270 err_cq_free: 271 mlx4_cq_free(dev->dev, &cq->mcq); 272 273 err_dbmap: 274 if (udata) 275 mlx4_ib_db_unmap_user(context, &cq->db); 276 277 err_mtt: 278 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); 279 280 ib_umem_release(cq->umem); 281 if (!udata) 282 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 283 284 err_db: 285 if (!udata) 286 mlx4_db_free(dev->dev, &cq->db); 287 err_cq: 288 return err; 289 } 290 291 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 292 int entries) 293 { 294 int err; 295 296 if (cq->resize_buf) 297 return -EBUSY; 298 299 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 300 if (!cq->resize_buf) 301 return -ENOMEM; 302 303 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); 304 if (err) { 305 kfree(cq->resize_buf); 306 cq->resize_buf = NULL; 307 return err; 308 } 309 310 cq->resize_buf->cqe = entries - 1; 311 312 return 0; 313 } 314 315 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 316 int entries, struct ib_udata *udata) 317 { 318 struct mlx4_ib_resize_cq ucmd; 319 int err; 320 321 if (cq->resize_umem) 322 return -EBUSY; 323 324 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) 325 return -EFAULT; 326 327 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 328 if (!cq->resize_buf) 329 return -ENOMEM; 330 331 err = mlx4_ib_get_cq_umem(dev, &cq->resize_buf->buf, &cq->resize_umem, 332 ucmd.buf_addr, entries); 333 if (err) { 334 kfree(cq->resize_buf); 335 cq->resize_buf = NULL; 336 return err; 337 } 338 339 cq->resize_buf->cqe = entries - 1; 340 341 return 0; 342 } 343 344 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) 345 { 346 u32 i; 347 348 i = cq->mcq.cons_index; 349 while (get_sw_cqe(cq, i)) 350 ++i; 351 352 return i - cq->mcq.cons_index; 353 } 354 355 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) 356 { 357 struct mlx4_cqe *cqe, *new_cqe; 358 int i; 359 int cqe_size = cq->buf.entry_size; 360 int cqe_inc = cqe_size == 64 ? 1 : 0; 361 362 i = cq->mcq.cons_index; 363 cqe = get_cqe(cq, i & cq->ibcq.cqe); 364 cqe += cqe_inc; 365 366 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { 367 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, 368 (i + 1) & cq->resize_buf->cqe); 369 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); 370 new_cqe += cqe_inc; 371 372 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | 373 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); 374 cqe = get_cqe(cq, ++i & cq->ibcq.cqe); 375 cqe += cqe_inc; 376 } 377 ++cq->mcq.cons_index; 378 } 379 380 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 381 { 382 struct mlx4_ib_dev *dev = to_mdev(ibcq->device); 383 struct mlx4_ib_cq *cq = to_mcq(ibcq); 384 struct mlx4_mtt mtt; 385 int outst_cqe; 386 int err; 387 388 mutex_lock(&cq->resize_mutex); 389 if (entries < 1 || entries > dev->dev->caps.max_cqes) { 390 err = -EINVAL; 391 goto out; 392 } 393 394 entries = roundup_pow_of_two(entries + 1); 395 if (entries == ibcq->cqe + 1) { 396 err = 0; 397 goto out; 398 } 399 400 if (entries > dev->dev->caps.max_cqes + 1) { 401 err = -EINVAL; 402 goto out; 403 } 404 405 if (ibcq->uobject) { 406 err = mlx4_alloc_resize_umem(dev, cq, entries, udata); 407 if (err) 408 goto out; 409 } else { 410 /* Can't be smaller than the number of outstanding CQEs */ 411 outst_cqe = mlx4_ib_get_outstanding_cqes(cq); 412 if (entries < outst_cqe + 1) { 413 err = -EINVAL; 414 goto out; 415 } 416 417 err = mlx4_alloc_resize_buf(dev, cq, entries); 418 if (err) 419 goto out; 420 } 421 422 mtt = cq->buf.mtt; 423 424 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); 425 if (err) 426 goto err_buf; 427 428 mlx4_mtt_cleanup(dev->dev, &mtt); 429 if (ibcq->uobject) { 430 cq->buf = cq->resize_buf->buf; 431 cq->ibcq.cqe = cq->resize_buf->cqe; 432 ib_umem_release(cq->umem); 433 cq->umem = cq->resize_umem; 434 435 kfree(cq->resize_buf); 436 cq->resize_buf = NULL; 437 cq->resize_umem = NULL; 438 } else { 439 struct mlx4_ib_cq_buf tmp_buf; 440 int tmp_cqe = 0; 441 442 spin_lock_irq(&cq->lock); 443 if (cq->resize_buf) { 444 mlx4_ib_cq_resize_copy_cqes(cq); 445 tmp_buf = cq->buf; 446 tmp_cqe = cq->ibcq.cqe; 447 cq->buf = cq->resize_buf->buf; 448 cq->ibcq.cqe = cq->resize_buf->cqe; 449 450 kfree(cq->resize_buf); 451 cq->resize_buf = NULL; 452 } 453 spin_unlock_irq(&cq->lock); 454 455 if (tmp_cqe) 456 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 457 } 458 459 goto out; 460 461 err_buf: 462 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 463 if (!ibcq->uobject) 464 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, 465 cq->resize_buf->cqe); 466 467 kfree(cq->resize_buf); 468 cq->resize_buf = NULL; 469 470 ib_umem_release(cq->resize_umem); 471 cq->resize_umem = NULL; 472 out: 473 mutex_unlock(&cq->resize_mutex); 474 475 return err; 476 } 477 478 int mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 479 { 480 struct mlx4_ib_dev *dev = to_mdev(cq->device); 481 struct mlx4_ib_cq *mcq = to_mcq(cq); 482 483 mlx4_cq_free(dev->dev, &mcq->mcq); 484 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); 485 486 if (udata) { 487 mlx4_ib_db_unmap_user( 488 rdma_udata_to_drv_context( 489 udata, 490 struct mlx4_ib_ucontext, 491 ibucontext), 492 &mcq->db); 493 } else { 494 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); 495 mlx4_db_free(dev->dev, &mcq->db); 496 } 497 ib_umem_release(mcq->umem); 498 return 0; 499 } 500 501 static void dump_cqe(void *cqe) 502 { 503 __be32 *buf = cqe; 504 505 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 506 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), 507 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), 508 be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); 509 } 510 511 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, 512 struct ib_wc *wc) 513 { 514 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { 515 pr_debug("local QP operation err " 516 "(QPN %06x, WQE index %x, vendor syndrome %02x, " 517 "opcode = %02x)\n", 518 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), 519 cqe->vendor_err_syndrome, 520 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 521 dump_cqe(cqe); 522 } 523 524 switch (cqe->syndrome) { 525 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: 526 wc->status = IB_WC_LOC_LEN_ERR; 527 break; 528 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: 529 wc->status = IB_WC_LOC_QP_OP_ERR; 530 break; 531 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: 532 wc->status = IB_WC_LOC_PROT_ERR; 533 break; 534 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: 535 wc->status = IB_WC_WR_FLUSH_ERR; 536 break; 537 case MLX4_CQE_SYNDROME_MW_BIND_ERR: 538 wc->status = IB_WC_MW_BIND_ERR; 539 break; 540 case MLX4_CQE_SYNDROME_BAD_RESP_ERR: 541 wc->status = IB_WC_BAD_RESP_ERR; 542 break; 543 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: 544 wc->status = IB_WC_LOC_ACCESS_ERR; 545 break; 546 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 547 wc->status = IB_WC_REM_INV_REQ_ERR; 548 break; 549 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: 550 wc->status = IB_WC_REM_ACCESS_ERR; 551 break; 552 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: 553 wc->status = IB_WC_REM_OP_ERR; 554 break; 555 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 556 wc->status = IB_WC_RETRY_EXC_ERR; 557 break; 558 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 559 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 560 break; 561 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: 562 wc->status = IB_WC_REM_ABORT_ERR; 563 break; 564 default: 565 wc->status = IB_WC_GENERAL_ERR; 566 break; 567 } 568 569 wc->vendor_err = cqe->vendor_err_syndrome; 570 } 571 572 static int mlx4_ib_ipoib_csum_ok(__be16 status, u8 badfcs_enc, __be16 checksum) 573 { 574 return ((badfcs_enc & MLX4_CQE_STATUS_L4_CSUM) || 575 ((status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 576 (status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 577 MLX4_CQE_STATUS_UDP)) && 578 (checksum == cpu_to_be16(0xffff)))); 579 } 580 581 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, 582 unsigned tail, struct mlx4_cqe *cqe, int is_eth) 583 { 584 struct mlx4_ib_proxy_sqp_hdr *hdr; 585 586 ib_dma_sync_single_for_cpu(qp->ibqp.device, 587 qp->sqp_proxy_rcv[tail].map, 588 sizeof (struct mlx4_ib_proxy_sqp_hdr), 589 DMA_FROM_DEVICE); 590 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); 591 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); 592 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; 593 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; 594 wc->dlid_path_bits = 0; 595 596 if (is_eth) { 597 wc->slid = 0; 598 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid); 599 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4); 600 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2); 601 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 602 } else { 603 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); 604 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); 605 } 606 } 607 608 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries, 609 struct ib_wc *wc, int *npolled, int is_send) 610 { 611 struct mlx4_ib_wq *wq; 612 unsigned cur; 613 int i; 614 615 wq = is_send ? &qp->sq : &qp->rq; 616 cur = wq->head - wq->tail; 617 618 if (cur == 0) 619 return; 620 621 for (i = 0; i < cur && *npolled < num_entries; i++) { 622 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 623 wc->status = IB_WC_WR_FLUSH_ERR; 624 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR; 625 wq->tail++; 626 (*npolled)++; 627 wc->qp = &qp->ibqp; 628 wc++; 629 } 630 } 631 632 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries, 633 struct ib_wc *wc, int *npolled) 634 { 635 struct mlx4_ib_qp *qp; 636 637 *npolled = 0; 638 /* Find uncompleted WQEs belonging to that cq and return 639 * simulated FLUSH_ERR completions 640 */ 641 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) { 642 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1); 643 if (*npolled >= num_entries) 644 goto out; 645 } 646 647 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) { 648 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0); 649 if (*npolled >= num_entries) 650 goto out; 651 } 652 653 out: 654 return; 655 } 656 657 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 658 struct mlx4_ib_qp **cur_qp, 659 struct ib_wc *wc) 660 { 661 struct mlx4_cqe *cqe; 662 struct mlx4_qp *mqp; 663 struct mlx4_ib_wq *wq; 664 struct mlx4_ib_srq *srq; 665 struct mlx4_srq *msrq = NULL; 666 int is_send; 667 int is_error; 668 int is_eth; 669 u32 g_mlpath_rqpn; 670 u16 wqe_ctr; 671 unsigned tail = 0; 672 673 repoll: 674 cqe = next_cqe_sw(cq); 675 if (!cqe) 676 return -EAGAIN; 677 678 if (cq->buf.entry_size == 64) 679 cqe++; 680 681 ++cq->mcq.cons_index; 682 683 /* 684 * Make sure we read CQ entry contents after we've checked the 685 * ownership bit. 686 */ 687 rmb(); 688 689 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; 690 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 691 MLX4_CQE_OPCODE_ERROR; 692 693 /* Resize CQ in progress */ 694 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { 695 if (cq->resize_buf) { 696 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); 697 698 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 699 cq->buf = cq->resize_buf->buf; 700 cq->ibcq.cqe = cq->resize_buf->cqe; 701 702 kfree(cq->resize_buf); 703 cq->resize_buf = NULL; 704 } 705 706 goto repoll; 707 } 708 709 if (!*cur_qp || 710 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 711 /* 712 * We do not have to take the QP table lock here, 713 * because CQs will be locked while QPs are removed 714 * from the table. 715 */ 716 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 717 be32_to_cpu(cqe->vlan_my_qpn)); 718 *cur_qp = to_mibqp(mqp); 719 } 720 721 wc->qp = &(*cur_qp)->ibqp; 722 723 if (wc->qp->qp_type == IB_QPT_XRC_TGT) { 724 u32 srq_num; 725 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 726 srq_num = g_mlpath_rqpn & 0xffffff; 727 /* SRQ is also in the radix tree */ 728 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev, 729 srq_num); 730 } 731 732 if (is_send) { 733 wq = &(*cur_qp)->sq; 734 if (!(*cur_qp)->sq_signal_bits) { 735 wqe_ctr = be16_to_cpu(cqe->wqe_index); 736 wq->tail += (u16) (wqe_ctr - (u16) wq->tail); 737 } 738 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 739 ++wq->tail; 740 } else if ((*cur_qp)->ibqp.srq) { 741 srq = to_msrq((*cur_qp)->ibqp.srq); 742 wqe_ctr = be16_to_cpu(cqe->wqe_index); 743 wc->wr_id = srq->wrid[wqe_ctr]; 744 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 745 } else if (msrq) { 746 srq = to_mibsrq(msrq); 747 wqe_ctr = be16_to_cpu(cqe->wqe_index); 748 wc->wr_id = srq->wrid[wqe_ctr]; 749 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 750 } else { 751 wq = &(*cur_qp)->rq; 752 tail = wq->tail & (wq->wqe_cnt - 1); 753 wc->wr_id = wq->wrid[tail]; 754 ++wq->tail; 755 } 756 757 if (unlikely(is_error)) { 758 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); 759 return 0; 760 } 761 762 wc->status = IB_WC_SUCCESS; 763 764 if (is_send) { 765 wc->wc_flags = 0; 766 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 767 case MLX4_OPCODE_RDMA_WRITE_IMM: 768 wc->wc_flags |= IB_WC_WITH_IMM; 769 fallthrough; 770 case MLX4_OPCODE_RDMA_WRITE: 771 wc->opcode = IB_WC_RDMA_WRITE; 772 break; 773 case MLX4_OPCODE_SEND_IMM: 774 wc->wc_flags |= IB_WC_WITH_IMM; 775 fallthrough; 776 case MLX4_OPCODE_SEND: 777 case MLX4_OPCODE_SEND_INVAL: 778 wc->opcode = IB_WC_SEND; 779 break; 780 case MLX4_OPCODE_RDMA_READ: 781 wc->opcode = IB_WC_RDMA_READ; 782 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 783 break; 784 case MLX4_OPCODE_ATOMIC_CS: 785 wc->opcode = IB_WC_COMP_SWAP; 786 wc->byte_len = 8; 787 break; 788 case MLX4_OPCODE_ATOMIC_FA: 789 wc->opcode = IB_WC_FETCH_ADD; 790 wc->byte_len = 8; 791 break; 792 case MLX4_OPCODE_MASKED_ATOMIC_CS: 793 wc->opcode = IB_WC_MASKED_COMP_SWAP; 794 wc->byte_len = 8; 795 break; 796 case MLX4_OPCODE_MASKED_ATOMIC_FA: 797 wc->opcode = IB_WC_MASKED_FETCH_ADD; 798 wc->byte_len = 8; 799 break; 800 case MLX4_OPCODE_LSO: 801 wc->opcode = IB_WC_LSO; 802 break; 803 case MLX4_OPCODE_FMR: 804 wc->opcode = IB_WC_REG_MR; 805 break; 806 case MLX4_OPCODE_LOCAL_INVAL: 807 wc->opcode = IB_WC_LOCAL_INV; 808 break; 809 } 810 } else { 811 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 812 813 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 814 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: 815 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 816 wc->wc_flags = IB_WC_WITH_IMM; 817 wc->ex.imm_data = cqe->immed_rss_invalid; 818 break; 819 case MLX4_RECV_OPCODE_SEND_INVAL: 820 wc->opcode = IB_WC_RECV; 821 wc->wc_flags = IB_WC_WITH_INVALIDATE; 822 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); 823 break; 824 case MLX4_RECV_OPCODE_SEND: 825 wc->opcode = IB_WC_RECV; 826 wc->wc_flags = 0; 827 break; 828 case MLX4_RECV_OPCODE_SEND_IMM: 829 wc->opcode = IB_WC_RECV; 830 wc->wc_flags = IB_WC_WITH_IMM; 831 wc->ex.imm_data = cqe->immed_rss_invalid; 832 break; 833 } 834 835 is_eth = (rdma_port_get_link_layer(wc->qp->device, 836 (*cur_qp)->port) == 837 IB_LINK_LAYER_ETHERNET); 838 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { 839 if ((*cur_qp)->mlx4_ib_qp_type & 840 (MLX4_IB_QPT_PROXY_SMI_OWNER | 841 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 842 use_tunnel_data(*cur_qp, cq, wc, tail, cqe, 843 is_eth); 844 return 0; 845 } 846 } 847 848 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 849 wc->src_qp = g_mlpath_rqpn & 0xffffff; 850 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 851 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 852 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 853 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, 854 cqe->badfcs_enc, 855 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; 856 if (is_eth) { 857 wc->slid = 0; 858 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; 859 if (be32_to_cpu(cqe->vlan_my_qpn) & 860 MLX4_CQE_CVLAN_PRESENT_MASK) { 861 wc->vlan_id = be16_to_cpu(cqe->sl_vid) & 862 MLX4_CQE_VID_MASK; 863 } else { 864 wc->vlan_id = 0xffff; 865 } 866 memcpy(wc->smac, cqe->smac, ETH_ALEN); 867 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 868 } else { 869 wc->slid = be16_to_cpu(cqe->rlid); 870 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; 871 wc->vlan_id = 0xffff; 872 } 873 } 874 875 return 0; 876 } 877 878 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 879 { 880 struct mlx4_ib_cq *cq = to_mcq(ibcq); 881 struct mlx4_ib_qp *cur_qp = NULL; 882 unsigned long flags; 883 int npolled; 884 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 885 886 spin_lock_irqsave(&cq->lock, flags); 887 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 888 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 889 goto out; 890 } 891 892 for (npolled = 0; npolled < num_entries; ++npolled) { 893 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled)) 894 break; 895 } 896 897 mlx4_cq_set_ci(&cq->mcq); 898 899 out: 900 spin_unlock_irqrestore(&cq->lock, flags); 901 902 return npolled; 903 } 904 905 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 906 { 907 mlx4_cq_arm(&to_mcq(ibcq)->mcq, 908 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 909 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, 910 to_mdev(ibcq->device)->uar_map, 911 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); 912 913 return 0; 914 } 915 916 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 917 { 918 u32 prod_index; 919 int nfreed = 0; 920 struct mlx4_cqe *cqe, *dest; 921 u8 owner_bit; 922 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; 923 924 /* 925 * First we need to find the current producer index, so we 926 * know where to start cleaning from. It doesn't matter if HW 927 * adds new entries after this loop -- the QP we're worried 928 * about is already in RESET, so the new entries won't come 929 * from our QP and therefore don't need to be checked. 930 */ 931 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) 932 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 933 break; 934 935 /* 936 * Now sweep backwards through the CQ, removing CQ entries 937 * that match our QP by copying older entries on top of them. 938 */ 939 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 940 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 941 cqe += cqe_inc; 942 943 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 944 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 945 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 946 ++nfreed; 947 } else if (nfreed) { 948 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 949 dest += cqe_inc; 950 951 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; 952 memcpy(dest, cqe, sizeof *cqe); 953 dest->owner_sr_opcode = owner_bit | 954 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 955 } 956 } 957 958 if (nfreed) { 959 cq->mcq.cons_index += nfreed; 960 /* 961 * Make sure update of buffer contents is done before 962 * updating consumer index. 963 */ 964 wmb(); 965 mlx4_cq_set_ci(&cq->mcq); 966 } 967 } 968 969 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 970 { 971 spin_lock_irq(&cq->lock); 972 __mlx4_ib_cq_clean(cq, qpn, srq); 973 spin_unlock_irq(&cq->lock); 974 } 975