1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "osdep.h" 4 #include "hmc.h" 5 #include "defs.h" 6 #include "type.h" 7 #include "protos.h" 8 #include "puda.h" 9 #include "ws.h" 10 11 static void irdma_ieq_receive(struct irdma_sc_vsi *vsi, 12 struct irdma_puda_buf *buf); 13 static void irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid); 14 static void irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 15 struct irdma_puda_buf *buf, u32 wqe_idx); 16 /** 17 * irdma_puda_get_listbuf - get buffer from puda list 18 * @list: list to use for buffers (ILQ or IEQ) 19 */ 20 static struct irdma_puda_buf *irdma_puda_get_listbuf(struct list_head *list) 21 { 22 struct irdma_puda_buf *buf = NULL; 23 24 if (!list_empty(list)) { 25 buf = (struct irdma_puda_buf *)list->next; 26 list_del((struct list_head *)&buf->list); 27 } 28 29 return buf; 30 } 31 32 /** 33 * irdma_puda_get_bufpool - return buffer from resource 34 * @rsrc: resource to use for buffer 35 */ 36 struct irdma_puda_buf *irdma_puda_get_bufpool(struct irdma_puda_rsrc *rsrc) 37 { 38 struct irdma_puda_buf *buf = NULL; 39 struct list_head *list = &rsrc->bufpool; 40 unsigned long flags; 41 42 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 43 buf = irdma_puda_get_listbuf(list); 44 if (buf) { 45 rsrc->avail_buf_count--; 46 buf->vsi = rsrc->vsi; 47 } else { 48 rsrc->stats_buf_alloc_fail++; 49 } 50 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 51 52 return buf; 53 } 54 55 /** 56 * irdma_puda_ret_bufpool - return buffer to rsrc list 57 * @rsrc: resource to use for buffer 58 * @buf: buffer to return to resource 59 */ 60 void irdma_puda_ret_bufpool(struct irdma_puda_rsrc *rsrc, 61 struct irdma_puda_buf *buf) 62 { 63 unsigned long flags; 64 65 buf->do_lpb = false; 66 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 67 list_add(&buf->list, &rsrc->bufpool); 68 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 69 rsrc->avail_buf_count++; 70 } 71 72 /** 73 * irdma_puda_post_recvbuf - set wqe for rcv buffer 74 * @rsrc: resource ptr 75 * @wqe_idx: wqe index to use 76 * @buf: puda buffer for rcv q 77 * @initial: flag if during init time 78 */ 79 static void irdma_puda_post_recvbuf(struct irdma_puda_rsrc *rsrc, u32 wqe_idx, 80 struct irdma_puda_buf *buf, bool initial) 81 { 82 __le64 *wqe; 83 struct irdma_sc_qp *qp = &rsrc->qp; 84 u64 offset24 = 0; 85 86 /* Synch buffer for use by device */ 87 dma_sync_single_for_device(rsrc->dev->hw->device, buf->mem.pa, 88 buf->mem.size, DMA_BIDIRECTIONAL); 89 qp->qp_uk.rq_wrid_array[wqe_idx] = (uintptr_t)buf; 90 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 91 if (!initial) 92 get_64bit_val(wqe, 24, &offset24); 93 94 offset24 = (offset24) ? 0 : FIELD_PREP(IRDMAQPSQ_VALID, 1); 95 96 set_64bit_val(wqe, 16, 0); 97 set_64bit_val(wqe, 0, buf->mem.pa); 98 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 99 set_64bit_val(wqe, 8, 100 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, buf->mem.size)); 101 } else { 102 set_64bit_val(wqe, 8, 103 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, buf->mem.size) | 104 offset24); 105 } 106 dma_wmb(); /* make sure WQE is written before valid bit is set */ 107 108 set_64bit_val(wqe, 24, offset24); 109 } 110 111 /** 112 * irdma_puda_replenish_rq - post rcv buffers 113 * @rsrc: resource to use for buffer 114 * @initial: flag if during init time 115 */ 116 static int irdma_puda_replenish_rq(struct irdma_puda_rsrc *rsrc, bool initial) 117 { 118 u32 i; 119 u32 invalid_cnt = rsrc->rxq_invalid_cnt; 120 struct irdma_puda_buf *buf = NULL; 121 122 for (i = 0; i < invalid_cnt; i++) { 123 buf = irdma_puda_get_bufpool(rsrc); 124 if (!buf) 125 return -ENOBUFS; 126 irdma_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf, initial); 127 rsrc->rx_wqe_idx = ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size); 128 rsrc->rxq_invalid_cnt--; 129 } 130 131 return 0; 132 } 133 134 /** 135 * irdma_puda_alloc_buf - allocate mem for buffer 136 * @dev: iwarp device 137 * @len: length of buffer 138 */ 139 static struct irdma_puda_buf *irdma_puda_alloc_buf(struct irdma_sc_dev *dev, 140 u32 len) 141 { 142 struct irdma_puda_buf *buf; 143 struct irdma_virt_mem buf_mem; 144 145 buf_mem.size = sizeof(struct irdma_puda_buf); 146 buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); 147 if (!buf_mem.va) 148 return NULL; 149 150 buf = buf_mem.va; 151 buf->mem.size = len; 152 buf->mem.va = kzalloc(buf->mem.size, GFP_KERNEL); 153 if (!buf->mem.va) 154 goto free_virt; 155 buf->mem.pa = dma_map_single(dev->hw->device, buf->mem.va, 156 buf->mem.size, DMA_BIDIRECTIONAL); 157 if (dma_mapping_error(dev->hw->device, buf->mem.pa)) { 158 kfree(buf->mem.va); 159 goto free_virt; 160 } 161 162 buf->buf_mem.va = buf_mem.va; 163 buf->buf_mem.size = buf_mem.size; 164 165 return buf; 166 167 free_virt: 168 kfree(buf_mem.va); 169 return NULL; 170 } 171 172 /** 173 * irdma_puda_dele_buf - delete buffer back to system 174 * @dev: iwarp device 175 * @buf: buffer to free 176 */ 177 static void irdma_puda_dele_buf(struct irdma_sc_dev *dev, 178 struct irdma_puda_buf *buf) 179 { 180 dma_unmap_single(dev->hw->device, buf->mem.pa, buf->mem.size, 181 DMA_BIDIRECTIONAL); 182 kfree(buf->mem.va); 183 kfree(buf->buf_mem.va); 184 } 185 186 /** 187 * irdma_puda_get_next_send_wqe - return next wqe for processing 188 * @qp: puda qp for wqe 189 * @wqe_idx: wqe index for caller 190 */ 191 static __le64 *irdma_puda_get_next_send_wqe(struct irdma_qp_uk *qp, 192 u32 *wqe_idx) 193 { 194 __le64 *wqe = NULL; 195 int ret_code = 0; 196 197 *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 198 if (!*wqe_idx) 199 qp->swqe_polarity = !qp->swqe_polarity; 200 IRDMA_RING_MOVE_HEAD(qp->sq_ring, ret_code); 201 if (ret_code) 202 return wqe; 203 204 wqe = qp->sq_base[*wqe_idx].elem; 205 206 return wqe; 207 } 208 209 /** 210 * irdma_puda_poll_info - poll cq for completion 211 * @cq: cq for poll 212 * @info: info return for successful completion 213 */ 214 static int irdma_puda_poll_info(struct irdma_sc_cq *cq, 215 struct irdma_puda_cmpl_info *info) 216 { 217 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 218 u64 qword0, qword2, qword3, qword6; 219 __le64 *cqe; 220 __le64 *ext_cqe = NULL; 221 u64 qword7 = 0; 222 u64 comp_ctx; 223 bool valid_bit; 224 bool ext_valid = 0; 225 u32 major_err, minor_err; 226 u32 peek_head; 227 bool error; 228 u8 polarity; 229 230 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&cq->cq_uk); 231 get_64bit_val(cqe, 24, &qword3); 232 valid_bit = (bool)FIELD_GET(IRDMA_CQ_VALID, qword3); 233 if (valid_bit != cq_uk->polarity) 234 return -ENOENT; 235 236 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 237 ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); 238 239 if (ext_valid) { 240 peek_head = (cq_uk->cq_ring.head + 1) % cq_uk->cq_ring.size; 241 ext_cqe = cq_uk->cq_base[peek_head].buf; 242 get_64bit_val(ext_cqe, 24, &qword7); 243 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 244 if (!peek_head) 245 polarity ^= 1; 246 if (polarity != cq_uk->polarity) 247 return -ENOENT; 248 249 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 250 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 251 cq_uk->polarity = !cq_uk->polarity; 252 /* update cq tail in cq shadow memory also */ 253 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 254 } 255 256 print_hex_dump_debug("PUDA: PUDA CQE", DUMP_PREFIX_OFFSET, 16, 8, cqe, 257 32, false); 258 if (ext_valid) 259 print_hex_dump_debug("PUDA: PUDA EXT-CQE", DUMP_PREFIX_OFFSET, 260 16, 8, ext_cqe, 32, false); 261 262 error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); 263 if (error) { 264 ibdev_dbg(to_ibdev(cq->dev), "PUDA: receive error\n"); 265 major_err = (u32)(FIELD_GET(IRDMA_CQ_MAJERR, qword3)); 266 minor_err = (u32)(FIELD_GET(IRDMA_CQ_MINERR, qword3)); 267 info->compl_error = major_err << 16 | minor_err; 268 return -EIO; 269 } 270 271 get_64bit_val(cqe, 0, &qword0); 272 get_64bit_val(cqe, 16, &qword2); 273 274 info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); 275 info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); 276 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 277 info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); 278 279 get_64bit_val(cqe, 8, &comp_ctx); 280 info->qp = (struct irdma_qp_uk *)(unsigned long)comp_ctx; 281 info->wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); 282 283 if (info->q_type == IRDMA_CQE_QTYPE_RQ) { 284 if (ext_valid) { 285 info->vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); 286 if (info->vlan_valid) { 287 get_64bit_val(ext_cqe, 16, &qword6); 288 info->vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); 289 } 290 info->smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); 291 if (info->smac_valid) { 292 get_64bit_val(ext_cqe, 16, &qword6); 293 info->smac[0] = (u8)((qword6 >> 40) & 0xFF); 294 info->smac[1] = (u8)((qword6 >> 32) & 0xFF); 295 info->smac[2] = (u8)((qword6 >> 24) & 0xFF); 296 info->smac[3] = (u8)((qword6 >> 16) & 0xFF); 297 info->smac[4] = (u8)((qword6 >> 8) & 0xFF); 298 info->smac[5] = (u8)(qword6 & 0xFF); 299 } 300 } 301 302 if (cq->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 303 info->vlan_valid = (bool)FIELD_GET(IRDMA_VLAN_TAG_VALID, qword3); 304 info->l4proto = (u8)FIELD_GET(IRDMA_UDA_L4PROTO, qword2); 305 info->l3proto = (u8)FIELD_GET(IRDMA_UDA_L3PROTO, qword2); 306 } 307 308 info->payload_len = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); 309 } 310 311 return 0; 312 } 313 314 /** 315 * irdma_puda_poll_cmpl - processes completion for cq 316 * @dev: iwarp device 317 * @cq: cq getting interrupt 318 * @compl_err: return any completion err 319 */ 320 int irdma_puda_poll_cmpl(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq, 321 u32 *compl_err) 322 { 323 struct irdma_qp_uk *qp; 324 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 325 struct irdma_puda_cmpl_info info = {}; 326 int ret = 0; 327 struct irdma_puda_buf *buf; 328 struct irdma_puda_rsrc *rsrc; 329 u8 cq_type = cq->cq_type; 330 unsigned long flags; 331 332 if (cq_type == IRDMA_CQ_TYPE_ILQ || cq_type == IRDMA_CQ_TYPE_IEQ) { 333 rsrc = (cq_type == IRDMA_CQ_TYPE_ILQ) ? cq->vsi->ilq : 334 cq->vsi->ieq; 335 } else { 336 ibdev_dbg(to_ibdev(dev), "PUDA: qp_type error\n"); 337 return -EINVAL; 338 } 339 340 ret = irdma_puda_poll_info(cq, &info); 341 *compl_err = info.compl_error; 342 if (ret == -ENOENT) 343 return ret; 344 if (ret) 345 goto done; 346 347 qp = info.qp; 348 if (!qp || !rsrc) { 349 ret = -EFAULT; 350 goto done; 351 } 352 353 if (qp->qp_id != rsrc->qp_id) { 354 ret = -EFAULT; 355 goto done; 356 } 357 358 if (info.q_type == IRDMA_CQE_QTYPE_RQ) { 359 buf = (struct irdma_puda_buf *)(uintptr_t) 360 qp->rq_wrid_array[info.wqe_idx]; 361 362 /* reusing so synch the buffer for CPU use */ 363 dma_sync_single_for_cpu(dev->hw->device, buf->mem.pa, 364 buf->mem.size, DMA_BIDIRECTIONAL); 365 /* Get all the tcpip information in the buf header */ 366 ret = irdma_puda_get_tcpip_info(&info, buf); 367 if (ret) { 368 rsrc->stats_rcvd_pkt_err++; 369 if (cq_type == IRDMA_CQ_TYPE_ILQ) { 370 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, 371 info.wqe_idx); 372 } else { 373 irdma_puda_ret_bufpool(rsrc, buf); 374 irdma_puda_replenish_rq(rsrc, false); 375 } 376 goto done; 377 } 378 379 rsrc->stats_pkt_rcvd++; 380 rsrc->compl_rxwqe_idx = info.wqe_idx; 381 ibdev_dbg(to_ibdev(dev), "PUDA: RQ completion\n"); 382 rsrc->receive(rsrc->vsi, buf); 383 if (cq_type == IRDMA_CQ_TYPE_ILQ) 384 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, info.wqe_idx); 385 else 386 irdma_puda_replenish_rq(rsrc, false); 387 388 } else { 389 ibdev_dbg(to_ibdev(dev), "PUDA: SQ completion\n"); 390 buf = (struct irdma_puda_buf *)(uintptr_t) 391 qp->sq_wrtrk_array[info.wqe_idx].wrid; 392 393 /* reusing so synch the buffer for CPU use */ 394 dma_sync_single_for_cpu(dev->hw->device, buf->mem.pa, 395 buf->mem.size, DMA_BIDIRECTIONAL); 396 IRDMA_RING_SET_TAIL(qp->sq_ring, info.wqe_idx); 397 rsrc->xmit_complete(rsrc->vsi, buf); 398 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 399 rsrc->tx_wqe_avail_cnt++; 400 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 401 if (!list_empty(&rsrc->txpend)) 402 irdma_puda_send_buf(rsrc, NULL); 403 } 404 405 done: 406 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 407 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 408 cq_uk->polarity = !cq_uk->polarity; 409 /* update cq tail in cq shadow memory also */ 410 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 411 set_64bit_val(cq_uk->shadow_area, 0, 412 IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)); 413 414 return ret; 415 } 416 417 /** 418 * irdma_puda_send - complete send wqe for transmit 419 * @qp: puda qp for send 420 * @info: buffer information for transmit 421 */ 422 int irdma_puda_send(struct irdma_sc_qp *qp, struct irdma_puda_send_info *info) 423 { 424 __le64 *wqe; 425 u32 iplen, l4len; 426 u64 hdr[2]; 427 u32 wqe_idx; 428 u8 iipt; 429 430 /* number of 32 bits DWORDS in header */ 431 l4len = info->tcplen >> 2; 432 if (info->ipv4) { 433 iipt = 3; 434 iplen = 5; 435 } else { 436 iipt = 1; 437 iplen = 10; 438 } 439 440 wqe = irdma_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx); 441 if (!wqe) 442 return -ENOMEM; 443 444 qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch; 445 /* Third line of WQE descriptor */ 446 /* maclen is in words */ 447 448 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 449 hdr[0] = 0; /* Dest_QPN and Dest_QKey only for UD */ 450 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 451 FIELD_PREP(IRDMA_UDA_QPSQ_L4LEN, l4len) | 452 FIELD_PREP(IRDMAQPSQ_AHID, info->ah_id) | 453 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 454 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, 455 qp->qp_uk.swqe_polarity); 456 457 /* Forth line of WQE descriptor */ 458 459 set_64bit_val(wqe, 0, info->paddr); 460 set_64bit_val(wqe, 8, 461 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, info->len) | 462 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity)); 463 } else { 464 hdr[0] = FIELD_PREP(IRDMA_UDA_QPSQ_MACLEN, info->maclen >> 1) | 465 FIELD_PREP(IRDMA_UDA_QPSQ_IPLEN, iplen) | 466 FIELD_PREP(IRDMA_UDA_QPSQ_L4T, 1) | 467 FIELD_PREP(IRDMA_UDA_QPSQ_IIPT, iipt) | 468 FIELD_PREP(IRDMA_GEN1_UDA_QPSQ_L4LEN, l4len); 469 470 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 471 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 472 FIELD_PREP(IRDMA_UDA_QPSQ_DOLOOPBACK, info->do_lpb) | 473 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity); 474 475 /* Forth line of WQE descriptor */ 476 477 set_64bit_val(wqe, 0, info->paddr); 478 set_64bit_val(wqe, 8, 479 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, info->len)); 480 } 481 482 set_64bit_val(wqe, 16, hdr[0]); 483 dma_wmb(); /* make sure WQE is written before valid bit is set */ 484 485 set_64bit_val(wqe, 24, hdr[1]); 486 487 print_hex_dump_debug("PUDA: PUDA SEND WQE", DUMP_PREFIX_OFFSET, 16, 8, 488 wqe, 32, false); 489 irdma_uk_qp_post_wr(&qp->qp_uk); 490 return 0; 491 } 492 493 /** 494 * irdma_puda_send_buf - transmit puda buffer 495 * @rsrc: resource to use for buffer 496 * @buf: puda buffer to transmit 497 */ 498 void irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc, 499 struct irdma_puda_buf *buf) 500 { 501 struct irdma_puda_send_info info; 502 int ret = 0; 503 unsigned long flags; 504 505 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 506 /* if no wqe available or not from a completion and we have 507 * pending buffers, we must queue new buffer 508 */ 509 if (!rsrc->tx_wqe_avail_cnt || (buf && !list_empty(&rsrc->txpend))) { 510 list_add_tail(&buf->list, &rsrc->txpend); 511 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 512 rsrc->stats_sent_pkt_q++; 513 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 514 ibdev_dbg(to_ibdev(rsrc->dev), 515 "PUDA: adding to txpend\n"); 516 return; 517 } 518 rsrc->tx_wqe_avail_cnt--; 519 /* if we are coming from a completion and have pending buffers 520 * then Get one from pending list 521 */ 522 if (!buf) { 523 buf = irdma_puda_get_listbuf(&rsrc->txpend); 524 if (!buf) 525 goto done; 526 } 527 528 info.scratch = buf; 529 info.paddr = buf->mem.pa; 530 info.len = buf->totallen; 531 info.tcplen = buf->tcphlen; 532 info.ipv4 = buf->ipv4; 533 534 if (rsrc->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 535 info.ah_id = buf->ah_id; 536 } else { 537 info.maclen = buf->maclen; 538 info.do_lpb = buf->do_lpb; 539 } 540 541 /* Synch buffer for use by device */ 542 dma_sync_single_for_cpu(rsrc->dev->hw->device, buf->mem.pa, 543 buf->mem.size, DMA_BIDIRECTIONAL); 544 ret = irdma_puda_send(&rsrc->qp, &info); 545 if (ret) { 546 rsrc->tx_wqe_avail_cnt++; 547 rsrc->stats_sent_pkt_q++; 548 list_add(&buf->list, &rsrc->txpend); 549 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 550 ibdev_dbg(to_ibdev(rsrc->dev), 551 "PUDA: adding to puda_send\n"); 552 } else { 553 rsrc->stats_pkt_sent++; 554 } 555 done: 556 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 557 } 558 559 /** 560 * irdma_puda_qp_setctx - during init, set qp's context 561 * @rsrc: qp's resource 562 */ 563 static void irdma_puda_qp_setctx(struct irdma_puda_rsrc *rsrc) 564 { 565 struct irdma_sc_qp *qp = &rsrc->qp; 566 __le64 *qp_ctx = qp->hw_host_ctx; 567 568 set_64bit_val(qp_ctx, 8, qp->sq_pa); 569 set_64bit_val(qp_ctx, 16, qp->rq_pa); 570 set_64bit_val(qp_ctx, 24, 571 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 572 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size)); 573 set_64bit_val(qp_ctx, 48, 574 FIELD_PREP(IRDMAQPC_SNDMSS, rsrc->buf_size)); 575 set_64bit_val(qp_ctx, 56, 0); 576 if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 577 set_64bit_val(qp_ctx, 64, 1); 578 set_64bit_val(qp_ctx, 136, 579 FIELD_PREP(IRDMAQPC_TXCQNUM, rsrc->cq_id) | 580 FIELD_PREP(IRDMAQPC_RXCQNUM, rsrc->cq_id)); 581 set_64bit_val(qp_ctx, 144, 582 FIELD_PREP(IRDMAQPC_STAT_INDEX, rsrc->stats_idx)); 583 set_64bit_val(qp_ctx, 160, 584 FIELD_PREP(IRDMAQPC_PRIVEN, 1) | 585 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, rsrc->stats_idx_valid)); 586 set_64bit_val(qp_ctx, 168, 587 FIELD_PREP(IRDMAQPC_QPCOMPCTX, (uintptr_t)qp)); 588 set_64bit_val(qp_ctx, 176, 589 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 590 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 591 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 592 593 print_hex_dump_debug("PUDA: PUDA QP CONTEXT", DUMP_PREFIX_OFFSET, 16, 594 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 595 } 596 597 /** 598 * irdma_puda_qp_wqe - setup wqe for qp create 599 * @dev: Device 600 * @qp: Resource qp 601 */ 602 static int irdma_puda_qp_wqe(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) 603 { 604 struct irdma_sc_cqp *cqp; 605 __le64 *wqe; 606 u64 hdr; 607 struct irdma_ccq_cqe_info compl_info; 608 int status = 0; 609 610 cqp = dev->cqp; 611 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 612 if (!wqe) 613 return -ENOMEM; 614 615 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 616 set_64bit_val(wqe, 40, qp->shadow_area_pa); 617 618 hdr = qp->qp_uk.qp_id | 619 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 620 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, IRDMA_QP_TYPE_UDA) | 621 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, 1) | 622 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, 2) | 623 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 624 dma_wmb(); /* make sure WQE is written before valid bit is set */ 625 626 set_64bit_val(wqe, 24, hdr); 627 628 print_hex_dump_debug("PUDA: PUDA QP CREATE", DUMP_PREFIX_OFFSET, 16, 629 8, wqe, 40, false); 630 irdma_sc_cqp_post_sq(cqp); 631 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_QP, 632 &compl_info); 633 634 return status; 635 } 636 637 /** 638 * irdma_puda_qp_create - create qp for resource 639 * @rsrc: resource to use for buffer 640 */ 641 static int irdma_puda_qp_create(struct irdma_puda_rsrc *rsrc) 642 { 643 struct irdma_sc_qp *qp = &rsrc->qp; 644 struct irdma_qp_uk *ukqp = &qp->qp_uk; 645 int ret = 0; 646 u32 sq_size, rq_size; 647 struct irdma_dma_mem *mem; 648 649 sq_size = rsrc->sq_size * IRDMA_QP_WQE_MIN_SIZE; 650 rq_size = rsrc->rq_size * IRDMA_QP_WQE_MIN_SIZE; 651 rsrc->qpmem.size = ALIGN((sq_size + rq_size + (IRDMA_SHADOW_AREA_SIZE << 3) + IRDMA_QP_CTX_SIZE), 652 IRDMA_HW_PAGE_SIZE); 653 rsrc->qpmem.va = dma_alloc_coherent(rsrc->dev->hw->device, 654 rsrc->qpmem.size, &rsrc->qpmem.pa, 655 GFP_KERNEL); 656 if (!rsrc->qpmem.va) 657 return -ENOMEM; 658 659 mem = &rsrc->qpmem; 660 memset(mem->va, 0, rsrc->qpmem.size); 661 qp->hw_sq_size = irdma_get_encoded_wqe_size(rsrc->sq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 662 qp->hw_rq_size = irdma_get_encoded_wqe_size(rsrc->rq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 663 qp->pd = &rsrc->sc_pd; 664 qp->qp_uk.qp_type = IRDMA_QP_TYPE_UDA; 665 qp->dev = rsrc->dev; 666 qp->qp_uk.back_qp = rsrc; 667 qp->sq_pa = mem->pa; 668 qp->rq_pa = qp->sq_pa + sq_size; 669 qp->vsi = rsrc->vsi; 670 ukqp->sq_base = mem->va; 671 ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size]; 672 ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem; 673 ukqp->uk_attrs = &qp->dev->hw_attrs.uk_attrs; 674 qp->shadow_area_pa = qp->rq_pa + rq_size; 675 qp->hw_host_ctx = ukqp->shadow_area + IRDMA_SHADOW_AREA_SIZE; 676 qp->hw_host_ctx_pa = qp->shadow_area_pa + (IRDMA_SHADOW_AREA_SIZE << 3); 677 qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; 678 ukqp->qp_id = rsrc->qp_id; 679 ukqp->sq_wrtrk_array = rsrc->sq_wrtrk_array; 680 ukqp->rq_wrid_array = rsrc->rq_wrid_array; 681 ukqp->sq_size = rsrc->sq_size; 682 ukqp->rq_size = rsrc->rq_size; 683 684 IRDMA_RING_INIT(ukqp->sq_ring, ukqp->sq_size); 685 IRDMA_RING_INIT(ukqp->initial_ring, ukqp->sq_size); 686 IRDMA_RING_INIT(ukqp->rq_ring, ukqp->rq_size); 687 ukqp->wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 688 689 ret = rsrc->dev->ws_add(qp->vsi, qp->user_pri); 690 if (ret) { 691 dma_free_coherent(rsrc->dev->hw->device, rsrc->qpmem.size, 692 rsrc->qpmem.va, rsrc->qpmem.pa); 693 rsrc->qpmem.va = NULL; 694 return ret; 695 } 696 697 irdma_qp_add_qos(qp); 698 irdma_puda_qp_setctx(rsrc); 699 700 if (rsrc->dev->ceq_valid) 701 ret = irdma_cqp_qp_create_cmd(rsrc->dev, qp); 702 else 703 ret = irdma_puda_qp_wqe(rsrc->dev, qp); 704 if (ret) { 705 irdma_qp_rem_qos(qp); 706 rsrc->dev->ws_remove(qp->vsi, qp->user_pri); 707 dma_free_coherent(rsrc->dev->hw->device, rsrc->qpmem.size, 708 rsrc->qpmem.va, rsrc->qpmem.pa); 709 rsrc->qpmem.va = NULL; 710 } 711 712 return ret; 713 } 714 715 /** 716 * irdma_puda_cq_wqe - setup wqe for CQ create 717 * @dev: Device 718 * @cq: resource for cq 719 */ 720 static int irdma_puda_cq_wqe(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq) 721 { 722 __le64 *wqe; 723 struct irdma_sc_cqp *cqp; 724 u64 hdr; 725 struct irdma_ccq_cqe_info compl_info; 726 int status = 0; 727 728 cqp = dev->cqp; 729 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 730 if (!wqe) 731 return -ENOMEM; 732 733 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 734 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1); 735 set_64bit_val(wqe, 16, 736 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 737 set_64bit_val(wqe, 32, cq->cq_pa); 738 set_64bit_val(wqe, 40, cq->shadow_area_pa); 739 set_64bit_val(wqe, 56, 740 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 741 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 742 743 hdr = cq->cq_uk.cq_id | 744 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 745 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, 1) | 746 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, 1) | 747 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, 1) | 748 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 749 dma_wmb(); /* make sure WQE is written before valid bit is set */ 750 751 set_64bit_val(wqe, 24, hdr); 752 753 print_hex_dump_debug("PUDA: PUDA CREATE CQ", DUMP_PREFIX_OFFSET, 16, 754 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 755 irdma_sc_cqp_post_sq(dev->cqp); 756 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_CQ, 757 &compl_info); 758 if (!status) { 759 struct irdma_sc_ceq *ceq = dev->ceq[0]; 760 761 if (ceq && ceq->reg_cq) 762 status = irdma_sc_add_cq_ctx(ceq, cq); 763 } 764 765 return status; 766 } 767 768 /** 769 * irdma_puda_cq_create - create cq for resource 770 * @rsrc: resource for which cq to create 771 */ 772 static int irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc) 773 { 774 struct irdma_sc_dev *dev = rsrc->dev; 775 struct irdma_sc_cq *cq = &rsrc->cq; 776 int ret = 0; 777 u32 cqsize; 778 struct irdma_dma_mem *mem; 779 struct irdma_cq_init_info info = {}; 780 struct irdma_cq_uk_init_info *init_info = &info.cq_uk_init_info; 781 782 cq->vsi = rsrc->vsi; 783 cqsize = rsrc->cq_size * (sizeof(struct irdma_cqe)); 784 rsrc->cqmem.size = ALIGN(cqsize + sizeof(struct irdma_cq_shadow_area), 785 IRDMA_CQ0_ALIGNMENT); 786 rsrc->cqmem.va = dma_alloc_coherent(dev->hw->device, rsrc->cqmem.size, 787 &rsrc->cqmem.pa, GFP_KERNEL); 788 if (!rsrc->cqmem.va) 789 return -ENOMEM; 790 791 mem = &rsrc->cqmem; 792 info.dev = dev; 793 info.type = (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) ? 794 IRDMA_CQ_TYPE_ILQ : IRDMA_CQ_TYPE_IEQ; 795 info.shadow_read_threshold = rsrc->cq_size >> 2; 796 info.cq_base_pa = mem->pa; 797 info.shadow_area_pa = mem->pa + cqsize; 798 init_info->cq_base = mem->va; 799 init_info->shadow_area = (__le64 *)((u8 *)mem->va + cqsize); 800 init_info->cq_size = rsrc->cq_size; 801 init_info->cq_id = rsrc->cq_id; 802 info.ceqe_mask = true; 803 info.ceq_id_valid = true; 804 info.vsi = rsrc->vsi; 805 806 ret = irdma_sc_cq_init(cq, &info); 807 if (ret) 808 goto error; 809 810 if (rsrc->dev->ceq_valid) 811 ret = irdma_cqp_cq_create_cmd(dev, cq); 812 else 813 ret = irdma_puda_cq_wqe(dev, cq); 814 error: 815 if (ret) { 816 dma_free_coherent(dev->hw->device, rsrc->cqmem.size, 817 rsrc->cqmem.va, rsrc->cqmem.pa); 818 rsrc->cqmem.va = NULL; 819 } 820 821 return ret; 822 } 823 824 /** 825 * irdma_puda_free_qp - free qp for resource 826 * @rsrc: resource for which qp to free 827 */ 828 static void irdma_puda_free_qp(struct irdma_puda_rsrc *rsrc) 829 { 830 int ret; 831 struct irdma_ccq_cqe_info compl_info; 832 struct irdma_sc_dev *dev = rsrc->dev; 833 834 if (rsrc->dev->ceq_valid) { 835 irdma_cqp_qp_destroy_cmd(dev, &rsrc->qp); 836 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 837 return; 838 } 839 840 ret = irdma_sc_qp_destroy(&rsrc->qp, 0, false, true, true); 841 if (ret) 842 ibdev_dbg(to_ibdev(dev), 843 "PUDA: error puda qp destroy wqe, status = %d\n", 844 ret); 845 if (!ret) { 846 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_QP, 847 &compl_info); 848 if (ret) 849 ibdev_dbg(to_ibdev(dev), 850 "PUDA: error puda qp destroy failed, status = %d\n", 851 ret); 852 } 853 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 854 } 855 856 /** 857 * irdma_puda_free_cq - free cq for resource 858 * @rsrc: resource for which cq to free 859 */ 860 static void irdma_puda_free_cq(struct irdma_puda_rsrc *rsrc) 861 { 862 int ret; 863 struct irdma_ccq_cqe_info compl_info; 864 struct irdma_sc_dev *dev = rsrc->dev; 865 866 if (rsrc->dev->ceq_valid) { 867 irdma_cqp_cq_destroy_cmd(dev, &rsrc->cq); 868 return; 869 } 870 871 ret = irdma_sc_cq_destroy(&rsrc->cq, 0, true); 872 if (ret) 873 ibdev_dbg(to_ibdev(dev), "PUDA: error ieq cq destroy\n"); 874 if (!ret) { 875 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_CQ, 876 &compl_info); 877 if (ret) 878 ibdev_dbg(to_ibdev(dev), 879 "PUDA: error ieq qp destroy done\n"); 880 } 881 } 882 883 /** 884 * irdma_puda_dele_rsrc - delete all resources during close 885 * @vsi: VSI structure of device 886 * @type: type of resource to dele 887 * @reset: true if reset chip 888 */ 889 void irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type, 890 bool reset) 891 { 892 struct irdma_sc_dev *dev = vsi->dev; 893 struct irdma_puda_rsrc *rsrc; 894 struct irdma_puda_buf *buf = NULL; 895 struct irdma_puda_buf *nextbuf = NULL; 896 struct irdma_virt_mem *vmem; 897 struct irdma_sc_ceq *ceq; 898 899 ceq = vsi->dev->ceq[0]; 900 switch (type) { 901 case IRDMA_PUDA_RSRC_TYPE_ILQ: 902 rsrc = vsi->ilq; 903 vmem = &vsi->ilq_mem; 904 vsi->ilq = NULL; 905 if (ceq && ceq->reg_cq) 906 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 907 break; 908 case IRDMA_PUDA_RSRC_TYPE_IEQ: 909 rsrc = vsi->ieq; 910 vmem = &vsi->ieq_mem; 911 vsi->ieq = NULL; 912 if (ceq && ceq->reg_cq) 913 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 914 break; 915 default: 916 ibdev_dbg(to_ibdev(dev), "PUDA: error resource type = 0x%x\n", 917 type); 918 return; 919 } 920 921 switch (rsrc->cmpl) { 922 case PUDA_HASH_CRC_COMPLETE: 923 irdma_free_hash_desc(rsrc->hash_desc); 924 fallthrough; 925 case PUDA_QP_CREATED: 926 irdma_qp_rem_qos(&rsrc->qp); 927 928 if (!reset) 929 irdma_puda_free_qp(rsrc); 930 931 dma_free_coherent(dev->hw->device, rsrc->qpmem.size, 932 rsrc->qpmem.va, rsrc->qpmem.pa); 933 rsrc->qpmem.va = NULL; 934 fallthrough; 935 case PUDA_CQ_CREATED: 936 if (!reset) 937 irdma_puda_free_cq(rsrc); 938 939 dma_free_coherent(dev->hw->device, rsrc->cqmem.size, 940 rsrc->cqmem.va, rsrc->cqmem.pa); 941 rsrc->cqmem.va = NULL; 942 break; 943 default: 944 ibdev_dbg(to_ibdev(rsrc->dev), "PUDA: error no resources\n"); 945 break; 946 } 947 /* Free all allocated puda buffers for both tx and rx */ 948 buf = rsrc->alloclist; 949 while (buf) { 950 nextbuf = buf->next; 951 irdma_puda_dele_buf(dev, buf); 952 buf = nextbuf; 953 rsrc->alloc_buf_count--; 954 } 955 956 kfree(vmem->va); 957 } 958 959 /** 960 * irdma_puda_allocbufs - allocate buffers for resource 961 * @rsrc: resource for buffer allocation 962 * @count: number of buffers to create 963 */ 964 static int irdma_puda_allocbufs(struct irdma_puda_rsrc *rsrc, u32 count) 965 { 966 u32 i; 967 struct irdma_puda_buf *buf; 968 struct irdma_puda_buf *nextbuf; 969 970 for (i = 0; i < count; i++) { 971 buf = irdma_puda_alloc_buf(rsrc->dev, rsrc->buf_size); 972 if (!buf) { 973 rsrc->stats_buf_alloc_fail++; 974 return -ENOMEM; 975 } 976 irdma_puda_ret_bufpool(rsrc, buf); 977 rsrc->alloc_buf_count++; 978 if (!rsrc->alloclist) { 979 rsrc->alloclist = buf; 980 } else { 981 nextbuf = rsrc->alloclist; 982 rsrc->alloclist = buf; 983 buf->next = nextbuf; 984 } 985 } 986 987 rsrc->avail_buf_count = rsrc->alloc_buf_count; 988 989 return 0; 990 } 991 992 /** 993 * irdma_puda_create_rsrc - create resource (ilq or ieq) 994 * @vsi: sc VSI struct 995 * @info: resource information 996 */ 997 int irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi, 998 struct irdma_puda_rsrc_info *info) 999 { 1000 struct irdma_sc_dev *dev = vsi->dev; 1001 int ret = 0; 1002 struct irdma_puda_rsrc *rsrc; 1003 u32 pudasize; 1004 u32 sqwridsize, rqwridsize; 1005 struct irdma_virt_mem *vmem; 1006 1007 info->count = 1; 1008 pudasize = sizeof(struct irdma_puda_rsrc); 1009 sqwridsize = info->sq_size * sizeof(struct irdma_sq_uk_wr_trk_info); 1010 rqwridsize = info->rq_size * 8; 1011 switch (info->type) { 1012 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1013 vmem = &vsi->ilq_mem; 1014 break; 1015 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1016 vmem = &vsi->ieq_mem; 1017 break; 1018 default: 1019 return -EOPNOTSUPP; 1020 } 1021 vmem->size = pudasize + sqwridsize + rqwridsize; 1022 vmem->va = kzalloc(vmem->size, GFP_KERNEL); 1023 if (!vmem->va) 1024 return -ENOMEM; 1025 1026 rsrc = vmem->va; 1027 spin_lock_init(&rsrc->bufpool_lock); 1028 switch (info->type) { 1029 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1030 vsi->ilq = vmem->va; 1031 vsi->ilq_count = info->count; 1032 rsrc->receive = info->receive; 1033 rsrc->xmit_complete = info->xmit_complete; 1034 break; 1035 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1036 vsi->ieq_count = info->count; 1037 vsi->ieq = vmem->va; 1038 rsrc->receive = irdma_ieq_receive; 1039 rsrc->xmit_complete = irdma_ieq_tx_compl; 1040 break; 1041 default: 1042 return -EOPNOTSUPP; 1043 } 1044 1045 rsrc->type = info->type; 1046 rsrc->sq_wrtrk_array = (struct irdma_sq_uk_wr_trk_info *) 1047 ((u8 *)vmem->va + pudasize); 1048 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize); 1049 /* Initialize all ieq lists */ 1050 INIT_LIST_HEAD(&rsrc->bufpool); 1051 INIT_LIST_HEAD(&rsrc->txpend); 1052 1053 rsrc->tx_wqe_avail_cnt = info->sq_size - 1; 1054 irdma_sc_pd_init(dev, &rsrc->sc_pd, info->pd_id, info->abi_ver); 1055 rsrc->qp_id = info->qp_id; 1056 rsrc->cq_id = info->cq_id; 1057 rsrc->sq_size = info->sq_size; 1058 rsrc->rq_size = info->rq_size; 1059 rsrc->cq_size = info->rq_size + info->sq_size; 1060 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1061 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 1062 rsrc->cq_size += info->rq_size; 1063 } 1064 rsrc->buf_size = info->buf_size; 1065 rsrc->dev = dev; 1066 rsrc->vsi = vsi; 1067 rsrc->stats_idx = info->stats_idx; 1068 rsrc->stats_idx_valid = info->stats_idx_valid; 1069 1070 ret = irdma_puda_cq_create(rsrc); 1071 if (!ret) { 1072 rsrc->cmpl = PUDA_CQ_CREATED; 1073 ret = irdma_puda_qp_create(rsrc); 1074 } 1075 if (ret) { 1076 ibdev_dbg(to_ibdev(dev), 1077 "PUDA: error qp_create type=%d, status=%d\n", 1078 rsrc->type, ret); 1079 goto error; 1080 } 1081 rsrc->cmpl = PUDA_QP_CREATED; 1082 1083 ret = irdma_puda_allocbufs(rsrc, info->tx_buf_cnt + info->rq_size); 1084 if (ret) { 1085 ibdev_dbg(to_ibdev(dev), "PUDA: error alloc_buf\n"); 1086 goto error; 1087 } 1088 1089 rsrc->rxq_invalid_cnt = info->rq_size; 1090 ret = irdma_puda_replenish_rq(rsrc, true); 1091 if (ret) 1092 goto error; 1093 1094 if (info->type == IRDMA_PUDA_RSRC_TYPE_IEQ) { 1095 if (!irdma_init_hash_desc(&rsrc->hash_desc)) { 1096 rsrc->check_crc = true; 1097 rsrc->cmpl = PUDA_HASH_CRC_COMPLETE; 1098 ret = 0; 1099 } 1100 } 1101 1102 irdma_sc_ccq_arm(&rsrc->cq); 1103 return ret; 1104 1105 error: 1106 irdma_puda_dele_rsrc(vsi, info->type, false); 1107 1108 return ret; 1109 } 1110 1111 /** 1112 * irdma_ilq_putback_rcvbuf - ilq buffer to put back on rq 1113 * @qp: ilq's qp resource 1114 * @buf: puda buffer for rcv q 1115 * @wqe_idx: wqe index of completed rcvbuf 1116 */ 1117 static void irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 1118 struct irdma_puda_buf *buf, u32 wqe_idx) 1119 { 1120 __le64 *wqe; 1121 u64 offset8, offset24; 1122 1123 /* Synch buffer for use by device */ 1124 dma_sync_single_for_device(qp->dev->hw->device, buf->mem.pa, 1125 buf->mem.size, DMA_BIDIRECTIONAL); 1126 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 1127 get_64bit_val(wqe, 24, &offset24); 1128 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1129 get_64bit_val(wqe, 8, &offset8); 1130 if (offset24) 1131 offset8 &= ~FIELD_PREP(IRDMAQPSQ_VALID, 1); 1132 else 1133 offset8 |= FIELD_PREP(IRDMAQPSQ_VALID, 1); 1134 set_64bit_val(wqe, 8, offset8); 1135 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1136 } 1137 if (offset24) 1138 offset24 = 0; 1139 else 1140 offset24 = FIELD_PREP(IRDMAQPSQ_VALID, 1); 1141 1142 set_64bit_val(wqe, 24, offset24); 1143 } 1144 1145 /** 1146 * irdma_ieq_get_fpdu_len - get length of fpdu with or without marker 1147 * @pfpdu: pointer to fpdu 1148 * @datap: pointer to data in the buffer 1149 * @rcv_seq: seqnum of the data buffer 1150 */ 1151 static u16 irdma_ieq_get_fpdu_len(struct irdma_pfpdu *pfpdu, u8 *datap, 1152 u32 rcv_seq) 1153 { 1154 u32 marker_seq, end_seq, blk_start; 1155 u8 marker_len = pfpdu->marker_len; 1156 u16 total_len = 0; 1157 u16 fpdu_len; 1158 1159 blk_start = (pfpdu->rcv_start_seq - rcv_seq) & (IRDMA_MRK_BLK_SZ - 1); 1160 if (!blk_start) { 1161 total_len = marker_len; 1162 marker_seq = rcv_seq + IRDMA_MRK_BLK_SZ; 1163 if (marker_len && *(u32 *)datap) 1164 return 0; 1165 } else { 1166 marker_seq = rcv_seq + blk_start; 1167 } 1168 1169 datap += total_len; 1170 fpdu_len = ntohs(*(__be16 *)datap); 1171 fpdu_len += IRDMA_IEQ_MPA_FRAMING; 1172 fpdu_len = (fpdu_len + 3) & 0xfffc; 1173 1174 if (fpdu_len > pfpdu->max_fpdu_data) 1175 return 0; 1176 1177 total_len += fpdu_len; 1178 end_seq = rcv_seq + total_len; 1179 while ((int)(marker_seq - end_seq) < 0) { 1180 total_len += marker_len; 1181 end_seq += marker_len; 1182 marker_seq += IRDMA_MRK_BLK_SZ; 1183 } 1184 1185 return total_len; 1186 } 1187 1188 /** 1189 * irdma_ieq_copy_to_txbuf - copydata from rcv buf to tx buf 1190 * @buf: rcv buffer with partial 1191 * @txbuf: tx buffer for sending back 1192 * @buf_offset: rcv buffer offset to copy from 1193 * @txbuf_offset: at offset in tx buf to copy 1194 * @len: length of data to copy 1195 */ 1196 static void irdma_ieq_copy_to_txbuf(struct irdma_puda_buf *buf, 1197 struct irdma_puda_buf *txbuf, 1198 u16 buf_offset, u32 txbuf_offset, u32 len) 1199 { 1200 void *mem1 = (u8 *)buf->mem.va + buf_offset; 1201 void *mem2 = (u8 *)txbuf->mem.va + txbuf_offset; 1202 1203 memcpy(mem2, mem1, len); 1204 } 1205 1206 /** 1207 * irdma_ieq_setup_tx_buf - setup tx buffer for partial handling 1208 * @buf: reeive buffer with partial 1209 * @txbuf: buffer to prepare 1210 */ 1211 static void irdma_ieq_setup_tx_buf(struct irdma_puda_buf *buf, 1212 struct irdma_puda_buf *txbuf) 1213 { 1214 txbuf->tcphlen = buf->tcphlen; 1215 txbuf->ipv4 = buf->ipv4; 1216 1217 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1218 txbuf->hdrlen = txbuf->tcphlen; 1219 irdma_ieq_copy_to_txbuf(buf, txbuf, IRDMA_TCP_OFFSET, 0, 1220 txbuf->hdrlen); 1221 } else { 1222 txbuf->maclen = buf->maclen; 1223 txbuf->hdrlen = buf->hdrlen; 1224 irdma_ieq_copy_to_txbuf(buf, txbuf, 0, 0, buf->hdrlen); 1225 } 1226 } 1227 1228 /** 1229 * irdma_ieq_check_first_buf - check if rcv buffer's seq is in range 1230 * @buf: receive exception buffer 1231 * @fps: first partial sequence number 1232 */ 1233 static void irdma_ieq_check_first_buf(struct irdma_puda_buf *buf, u32 fps) 1234 { 1235 u32 offset; 1236 1237 if (buf->seqnum < fps) { 1238 offset = fps - buf->seqnum; 1239 if (offset > buf->datalen) 1240 return; 1241 buf->data += offset; 1242 buf->datalen -= (u16)offset; 1243 buf->seqnum = fps; 1244 } 1245 } 1246 1247 /** 1248 * irdma_ieq_compl_pfpdu - write txbuf with full fpdu 1249 * @ieq: ieq resource 1250 * @rxlist: ieq's received buffer list 1251 * @pbufl: temporary list for buffers for fpddu 1252 * @txbuf: tx buffer for fpdu 1253 * @fpdu_len: total length of fpdu 1254 */ 1255 static void irdma_ieq_compl_pfpdu(struct irdma_puda_rsrc *ieq, 1256 struct list_head *rxlist, 1257 struct list_head *pbufl, 1258 struct irdma_puda_buf *txbuf, u16 fpdu_len) 1259 { 1260 struct irdma_puda_buf *buf; 1261 u32 nextseqnum; 1262 u16 txoffset, bufoffset; 1263 1264 buf = irdma_puda_get_listbuf(pbufl); 1265 if (!buf) 1266 return; 1267 1268 nextseqnum = buf->seqnum + fpdu_len; 1269 irdma_ieq_setup_tx_buf(buf, txbuf); 1270 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1271 txoffset = txbuf->hdrlen; 1272 txbuf->totallen = txbuf->hdrlen + fpdu_len; 1273 txbuf->data = (u8 *)txbuf->mem.va + txoffset; 1274 } else { 1275 txoffset = buf->hdrlen; 1276 txbuf->totallen = buf->hdrlen + fpdu_len; 1277 txbuf->data = (u8 *)txbuf->mem.va + buf->hdrlen; 1278 } 1279 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1280 1281 do { 1282 if (buf->datalen >= fpdu_len) { 1283 /* copied full fpdu */ 1284 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1285 fpdu_len); 1286 buf->datalen -= fpdu_len; 1287 buf->data += fpdu_len; 1288 buf->seqnum = nextseqnum; 1289 break; 1290 } 1291 /* copy partial fpdu */ 1292 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1293 buf->datalen); 1294 txoffset += buf->datalen; 1295 fpdu_len -= buf->datalen; 1296 irdma_puda_ret_bufpool(ieq, buf); 1297 buf = irdma_puda_get_listbuf(pbufl); 1298 if (!buf) 1299 return; 1300 1301 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1302 } while (1); 1303 1304 /* last buffer on the list*/ 1305 if (buf->datalen) 1306 list_add(&buf->list, rxlist); 1307 else 1308 irdma_puda_ret_bufpool(ieq, buf); 1309 } 1310 1311 /** 1312 * irdma_ieq_create_pbufl - create buffer list for single fpdu 1313 * @pfpdu: pointer to fpdu 1314 * @rxlist: resource list for receive ieq buffes 1315 * @pbufl: temp. list for buffers for fpddu 1316 * @buf: first receive buffer 1317 * @fpdu_len: total length of fpdu 1318 */ 1319 static int irdma_ieq_create_pbufl(struct irdma_pfpdu *pfpdu, 1320 struct list_head *rxlist, 1321 struct list_head *pbufl, 1322 struct irdma_puda_buf *buf, u16 fpdu_len) 1323 { 1324 int status = 0; 1325 struct irdma_puda_buf *nextbuf; 1326 u32 nextseqnum; 1327 u16 plen = fpdu_len - buf->datalen; 1328 bool done = false; 1329 1330 nextseqnum = buf->seqnum + buf->datalen; 1331 do { 1332 nextbuf = irdma_puda_get_listbuf(rxlist); 1333 if (!nextbuf) { 1334 status = -ENOBUFS; 1335 break; 1336 } 1337 list_add_tail(&nextbuf->list, pbufl); 1338 if (nextbuf->seqnum != nextseqnum) { 1339 pfpdu->bad_seq_num++; 1340 status = -ERANGE; 1341 break; 1342 } 1343 if (nextbuf->datalen >= plen) { 1344 done = true; 1345 } else { 1346 plen -= nextbuf->datalen; 1347 nextseqnum = nextbuf->seqnum + nextbuf->datalen; 1348 } 1349 1350 } while (!done); 1351 1352 return status; 1353 } 1354 1355 /** 1356 * irdma_ieq_handle_partial - process partial fpdu buffer 1357 * @ieq: ieq resource 1358 * @pfpdu: partial management per user qp 1359 * @buf: receive buffer 1360 * @fpdu_len: fpdu len in the buffer 1361 */ 1362 static int irdma_ieq_handle_partial(struct irdma_puda_rsrc *ieq, 1363 struct irdma_pfpdu *pfpdu, 1364 struct irdma_puda_buf *buf, u16 fpdu_len) 1365 { 1366 int status = 0; 1367 u8 *crcptr; 1368 u32 mpacrc; 1369 u32 seqnum = buf->seqnum; 1370 struct list_head pbufl; /* partial buffer list */ 1371 struct irdma_puda_buf *txbuf = NULL; 1372 struct list_head *rxlist = &pfpdu->rxlist; 1373 1374 ieq->partials_handled++; 1375 1376 INIT_LIST_HEAD(&pbufl); 1377 list_add(&buf->list, &pbufl); 1378 1379 status = irdma_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len); 1380 if (status) 1381 goto error; 1382 1383 txbuf = irdma_puda_get_bufpool(ieq); 1384 if (!txbuf) { 1385 pfpdu->no_tx_bufs++; 1386 status = -ENOBUFS; 1387 goto error; 1388 } 1389 1390 irdma_ieq_compl_pfpdu(ieq, rxlist, &pbufl, txbuf, fpdu_len); 1391 irdma_ieq_update_tcpip_info(txbuf, fpdu_len, seqnum); 1392 1393 crcptr = txbuf->data + fpdu_len - 4; 1394 mpacrc = *(u32 *)crcptr; 1395 if (ieq->check_crc) { 1396 status = irdma_ieq_check_mpacrc(ieq->hash_desc, txbuf->data, 1397 (fpdu_len - 4), mpacrc); 1398 if (status) { 1399 ibdev_dbg(to_ibdev(ieq->dev), "IEQ: error bad crc\n"); 1400 goto error; 1401 } 1402 } 1403 1404 print_hex_dump_debug("IEQ: IEQ TX BUFFER", DUMP_PREFIX_OFFSET, 16, 8, 1405 txbuf->mem.va, txbuf->totallen, false); 1406 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 1407 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1408 txbuf->do_lpb = true; 1409 irdma_puda_send_buf(ieq, txbuf); 1410 pfpdu->rcv_nxt = seqnum + fpdu_len; 1411 return status; 1412 1413 error: 1414 while (!list_empty(&pbufl)) { 1415 buf = list_last_entry(&pbufl, struct irdma_puda_buf, list); 1416 list_move(&buf->list, rxlist); 1417 } 1418 if (txbuf) 1419 irdma_puda_ret_bufpool(ieq, txbuf); 1420 1421 return status; 1422 } 1423 1424 /** 1425 * irdma_ieq_process_buf - process buffer rcvd for ieq 1426 * @ieq: ieq resource 1427 * @pfpdu: partial management per user qp 1428 * @buf: receive buffer 1429 */ 1430 static int irdma_ieq_process_buf(struct irdma_puda_rsrc *ieq, 1431 struct irdma_pfpdu *pfpdu, 1432 struct irdma_puda_buf *buf) 1433 { 1434 u16 fpdu_len = 0; 1435 u16 datalen = buf->datalen; 1436 u8 *datap = buf->data; 1437 u8 *crcptr; 1438 u16 ioffset = 0; 1439 u32 mpacrc; 1440 u32 seqnum = buf->seqnum; 1441 u16 len = 0; 1442 u16 full = 0; 1443 bool partial = false; 1444 struct irdma_puda_buf *txbuf; 1445 struct list_head *rxlist = &pfpdu->rxlist; 1446 int ret = 0; 1447 1448 ioffset = (u16)(buf->data - (u8 *)buf->mem.va); 1449 while (datalen) { 1450 fpdu_len = irdma_ieq_get_fpdu_len(pfpdu, datap, buf->seqnum); 1451 if (!fpdu_len) { 1452 ibdev_dbg(to_ibdev(ieq->dev), 1453 "IEQ: error bad fpdu len\n"); 1454 list_add(&buf->list, rxlist); 1455 return -EINVAL; 1456 } 1457 1458 if (datalen < fpdu_len) { 1459 partial = true; 1460 break; 1461 } 1462 crcptr = datap + fpdu_len - 4; 1463 mpacrc = *(u32 *)crcptr; 1464 if (ieq->check_crc) 1465 ret = irdma_ieq_check_mpacrc(ieq->hash_desc, datap, 1466 fpdu_len - 4, mpacrc); 1467 if (ret) { 1468 list_add(&buf->list, rxlist); 1469 ibdev_dbg(to_ibdev(ieq->dev), 1470 "ERR: IRDMA_ERR_MPA_CRC\n"); 1471 return -EINVAL; 1472 } 1473 full++; 1474 pfpdu->fpdu_processed++; 1475 ieq->fpdu_processed++; 1476 datap += fpdu_len; 1477 len += fpdu_len; 1478 datalen -= fpdu_len; 1479 } 1480 if (full) { 1481 /* copy full pdu's in the txbuf and send them out */ 1482 txbuf = irdma_puda_get_bufpool(ieq); 1483 if (!txbuf) { 1484 pfpdu->no_tx_bufs++; 1485 list_add(&buf->list, rxlist); 1486 return -ENOBUFS; 1487 } 1488 /* modify txbuf's buffer header */ 1489 irdma_ieq_setup_tx_buf(buf, txbuf); 1490 /* copy full fpdu's to new buffer */ 1491 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1492 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1493 txbuf->hdrlen, len); 1494 txbuf->totallen = txbuf->hdrlen + len; 1495 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1496 } else { 1497 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1498 buf->hdrlen, len); 1499 txbuf->totallen = buf->hdrlen + len; 1500 } 1501 irdma_ieq_update_tcpip_info(txbuf, len, buf->seqnum); 1502 print_hex_dump_debug("IEQ: IEQ TX BUFFER", DUMP_PREFIX_OFFSET, 1503 16, 8, txbuf->mem.va, txbuf->totallen, 1504 false); 1505 txbuf->do_lpb = true; 1506 irdma_puda_send_buf(ieq, txbuf); 1507 1508 if (!datalen) { 1509 pfpdu->rcv_nxt = buf->seqnum + len; 1510 irdma_puda_ret_bufpool(ieq, buf); 1511 return 0; 1512 } 1513 buf->data = datap; 1514 buf->seqnum = seqnum + len; 1515 buf->datalen = datalen; 1516 pfpdu->rcv_nxt = buf->seqnum; 1517 } 1518 if (partial) 1519 return irdma_ieq_handle_partial(ieq, pfpdu, buf, fpdu_len); 1520 1521 return 0; 1522 } 1523 1524 /** 1525 * irdma_ieq_process_fpdus - process fpdu's buffers on its list 1526 * @qp: qp for which partial fpdus 1527 * @ieq: ieq resource 1528 */ 1529 void irdma_ieq_process_fpdus(struct irdma_sc_qp *qp, 1530 struct irdma_puda_rsrc *ieq) 1531 { 1532 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1533 struct list_head *rxlist = &pfpdu->rxlist; 1534 struct irdma_puda_buf *buf; 1535 int status; 1536 1537 do { 1538 if (list_empty(rxlist)) 1539 break; 1540 buf = irdma_puda_get_listbuf(rxlist); 1541 if (!buf) { 1542 ibdev_dbg(to_ibdev(ieq->dev), "IEQ: error no buf\n"); 1543 break; 1544 } 1545 if (buf->seqnum != pfpdu->rcv_nxt) { 1546 /* This could be out of order or missing packet */ 1547 pfpdu->out_of_order++; 1548 list_add(&buf->list, rxlist); 1549 break; 1550 } 1551 /* keep processing buffers from the head of the list */ 1552 status = irdma_ieq_process_buf(ieq, pfpdu, buf); 1553 if (status == -EINVAL) { 1554 pfpdu->mpa_crc_err = true; 1555 while (!list_empty(rxlist)) { 1556 buf = irdma_puda_get_listbuf(rxlist); 1557 irdma_puda_ret_bufpool(ieq, buf); 1558 pfpdu->crc_err++; 1559 ieq->crc_err++; 1560 } 1561 /* create CQP for AE */ 1562 irdma_ieq_mpa_crc_ae(ieq->dev, qp); 1563 } 1564 } while (!status); 1565 } 1566 1567 /** 1568 * irdma_ieq_create_ah - create an address handle for IEQ 1569 * @qp: qp pointer 1570 * @buf: buf received on IEQ used to create AH 1571 */ 1572 static int irdma_ieq_create_ah(struct irdma_sc_qp *qp, struct irdma_puda_buf *buf) 1573 { 1574 struct irdma_ah_info ah_info = {}; 1575 1576 qp->pfpdu.ah_buf = buf; 1577 irdma_puda_ieq_get_ah_info(qp, &ah_info); 1578 return irdma_puda_create_ah(qp->vsi->dev, &ah_info, false, 1579 IRDMA_PUDA_RSRC_TYPE_IEQ, qp, 1580 &qp->pfpdu.ah); 1581 } 1582 1583 /** 1584 * irdma_ieq_handle_exception - handle qp's exception 1585 * @ieq: ieq resource 1586 * @qp: qp receiving excpetion 1587 * @buf: receive buffer 1588 */ 1589 static void irdma_ieq_handle_exception(struct irdma_puda_rsrc *ieq, 1590 struct irdma_sc_qp *qp, 1591 struct irdma_puda_buf *buf) 1592 { 1593 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1594 u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx; 1595 u32 rcv_wnd = hw_host_ctx[23]; 1596 /* first partial seq # in q2 */ 1597 u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET); 1598 struct list_head *rxlist = &pfpdu->rxlist; 1599 unsigned long flags = 0; 1600 u8 hw_rev = qp->dev->hw_attrs.uk_attrs.hw_rev; 1601 1602 print_hex_dump_debug("IEQ: IEQ RX BUFFER", DUMP_PREFIX_OFFSET, 16, 8, 1603 buf->mem.va, buf->totallen, false); 1604 1605 spin_lock_irqsave(&pfpdu->lock, flags); 1606 pfpdu->total_ieq_bufs++; 1607 if (pfpdu->mpa_crc_err) { 1608 pfpdu->crc_err++; 1609 goto error; 1610 } 1611 if (pfpdu->mode && fps != pfpdu->fps) { 1612 /* clean up qp as it is new partial sequence */ 1613 irdma_ieq_cleanup_qp(ieq, qp); 1614 ibdev_dbg(to_ibdev(ieq->dev), "IEQ: restarting new partial\n"); 1615 pfpdu->mode = false; 1616 } 1617 1618 if (!pfpdu->mode) { 1619 print_hex_dump_debug("IEQ: Q2 BUFFER", DUMP_PREFIX_OFFSET, 16, 1620 8, (u64 *)qp->q2_buf, 128, false); 1621 /* First_Partial_Sequence_Number check */ 1622 pfpdu->rcv_nxt = fps; 1623 pfpdu->fps = fps; 1624 pfpdu->mode = true; 1625 pfpdu->max_fpdu_data = (buf->ipv4) ? 1626 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV4) : 1627 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV6); 1628 pfpdu->pmode_count++; 1629 ieq->pmode_count++; 1630 INIT_LIST_HEAD(rxlist); 1631 irdma_ieq_check_first_buf(buf, fps); 1632 } 1633 1634 if (!(rcv_wnd >= (buf->seqnum - pfpdu->rcv_nxt))) { 1635 pfpdu->bad_seq_num++; 1636 ieq->bad_seq_num++; 1637 goto error; 1638 } 1639 1640 if (!list_empty(rxlist)) { 1641 if (buf->seqnum != pfpdu->nextseqnum) { 1642 irdma_send_ieq_ack(qp); 1643 /* throw away out-of-order, duplicates*/ 1644 goto error; 1645 } 1646 } 1647 /* Insert buf before head */ 1648 list_add_tail(&buf->list, rxlist); 1649 pfpdu->nextseqnum = buf->seqnum + buf->datalen; 1650 pfpdu->lastrcv_buf = buf; 1651 if (hw_rev >= IRDMA_GEN_2 && !pfpdu->ah) { 1652 irdma_ieq_create_ah(qp, buf); 1653 if (!pfpdu->ah) 1654 goto error; 1655 goto exit; 1656 } 1657 if (hw_rev == IRDMA_GEN_1) 1658 irdma_ieq_process_fpdus(qp, ieq); 1659 else if (pfpdu->ah && pfpdu->ah->ah_info.ah_valid) 1660 irdma_ieq_process_fpdus(qp, ieq); 1661 exit: 1662 spin_unlock_irqrestore(&pfpdu->lock, flags); 1663 1664 return; 1665 1666 error: 1667 irdma_puda_ret_bufpool(ieq, buf); 1668 spin_unlock_irqrestore(&pfpdu->lock, flags); 1669 } 1670 1671 /** 1672 * irdma_ieq_receive - received exception buffer 1673 * @vsi: VSI of device 1674 * @buf: exception buffer received 1675 */ 1676 static void irdma_ieq_receive(struct irdma_sc_vsi *vsi, 1677 struct irdma_puda_buf *buf) 1678 { 1679 struct irdma_puda_rsrc *ieq = vsi->ieq; 1680 struct irdma_sc_qp *qp = NULL; 1681 u32 wqe_idx = ieq->compl_rxwqe_idx; 1682 1683 qp = irdma_ieq_get_qp(vsi->dev, buf); 1684 if (!qp) { 1685 ieq->stats_bad_qp_id++; 1686 irdma_puda_ret_bufpool(ieq, buf); 1687 } else { 1688 irdma_ieq_handle_exception(ieq, qp, buf); 1689 } 1690 /* 1691 * ieq->rx_wqe_idx is used by irdma_puda_replenish_rq() 1692 * on which wqe_idx to start replenish rq 1693 */ 1694 if (!ieq->rxq_invalid_cnt) 1695 ieq->rx_wqe_idx = wqe_idx; 1696 ieq->rxq_invalid_cnt++; 1697 } 1698 1699 /** 1700 * irdma_ieq_tx_compl - put back after sending completed exception buffer 1701 * @vsi: sc VSI struct 1702 * @sqwrid: pointer to puda buffer 1703 */ 1704 static void irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid) 1705 { 1706 struct irdma_puda_rsrc *ieq = vsi->ieq; 1707 struct irdma_puda_buf *buf = sqwrid; 1708 1709 irdma_puda_ret_bufpool(ieq, buf); 1710 } 1711 1712 /** 1713 * irdma_ieq_cleanup_qp - qp is being destroyed 1714 * @ieq: ieq resource 1715 * @qp: all pending fpdu buffers 1716 */ 1717 void irdma_ieq_cleanup_qp(struct irdma_puda_rsrc *ieq, struct irdma_sc_qp *qp) 1718 { 1719 struct irdma_puda_buf *buf; 1720 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1721 struct list_head *rxlist = &pfpdu->rxlist; 1722 1723 if (qp->pfpdu.ah) { 1724 irdma_puda_free_ah(ieq->dev, qp->pfpdu.ah); 1725 qp->pfpdu.ah = NULL; 1726 qp->pfpdu.ah_buf = NULL; 1727 } 1728 1729 if (!pfpdu->mode) 1730 return; 1731 1732 while (!list_empty(rxlist)) { 1733 buf = irdma_puda_get_listbuf(rxlist); 1734 irdma_puda_ret_bufpool(ieq, buf); 1735 } 1736 } 1737