1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2017 - 2021 Intel Corporation */ 3 #ifndef IRDMA_H 4 #define IRDMA_H 5 6 #define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20) 7 8 #define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0) 9 #define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31) 10 11 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0) 12 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16) 13 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4) 14 #define IRDMA_GLINT_RATE_INTERVAL GENMASK(5, 0) 15 #define IRDMA_GLINT_RATE_INTRL_ENA BIT(6) 16 #define IRDMA_GLINT_DYN_CTL_INTENA BIT(0) 17 #define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1) 18 #define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3) 19 #define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5) 20 #define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11) 21 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA BIT(30) 22 #define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0) 23 #define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0) 24 #define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11) 25 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA BIT(30) 26 #define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0) 27 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL BIT(15) 28 #define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16) 29 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID BIT(0) 30 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE BIT(1) 31 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2) 32 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12) 33 #define IRDMA_PFHMC_SDCMD_PMSDWR BIT(31) 34 35 #define IRDMA_INVALID_CQ_IDX 0xffffffff 36 #define IRDMA_Q_INVALID_IDX 0xffff 37 38 enum irdma_dyn_idx_t { 39 IRDMA_IDX_ITR0 = 0, 40 IRDMA_IDX_ITR1 = 1, 41 IRDMA_IDX_ITR2 = 2, 42 IRDMA_IDX_NOITR = 3, 43 }; 44 45 enum irdma_registers { 46 IRDMA_CQPTAIL, 47 IRDMA_CQPDB, 48 IRDMA_CCQPSTATUS, 49 IRDMA_CCQPHIGH, 50 IRDMA_CCQPLOW, 51 IRDMA_CQARM, 52 IRDMA_CQACK, 53 IRDMA_AEQALLOC, 54 IRDMA_CQPERRCODES, 55 IRDMA_WQEALLOC, 56 IRDMA_GLINT_DYN_CTL, 57 IRDMA_DB_ADDR_OFFSET, 58 IRDMA_GLPCI_LBARCTRL, 59 IRDMA_GLPE_CPUSTATUS0, 60 IRDMA_GLPE_CPUSTATUS1, 61 IRDMA_GLPE_CPUSTATUS2, 62 IRDMA_PFINT_AEQCTL, 63 IRDMA_GLINT_CEQCTL, 64 IRDMA_VSIQF_PE_CTL1, 65 IRDMA_PFHMC_PDINV, 66 IRDMA_GLHMC_VFPDINV, 67 IRDMA_GLPE_CRITERR, 68 IRDMA_GLINT_RATE, 69 IRDMA_MAX_REGS, /* Must be last entry */ 70 }; 71 72 enum irdma_shifts { 73 IRDMA_CCQPSTATUS_CCQP_DONE_S, 74 IRDMA_CCQPSTATUS_CCQP_ERR_S, 75 IRDMA_CQPSQ_STAG_PDID_S, 76 IRDMA_CQPSQ_CQ_CEQID_S, 77 IRDMA_CQPSQ_CQ_CQID_S, 78 IRDMA_COMMIT_FPM_CQCNT_S, 79 IRDMA_CQPSQ_UPESD_HMCFNID_S, 80 IRDMA_MAX_SHIFTS, 81 }; 82 83 enum irdma_masks { 84 IRDMA_CCQPSTATUS_CCQP_DONE_M, 85 IRDMA_CCQPSTATUS_CCQP_ERR_M, 86 IRDMA_CQPSQ_STAG_PDID_M, 87 IRDMA_CQPSQ_CQ_CEQID_M, 88 IRDMA_CQPSQ_CQ_CQID_M, 89 IRDMA_COMMIT_FPM_CQCNT_M, 90 IRDMA_CQPSQ_UPESD_HMCFNID_M, 91 IRDMA_MAX_MASKS, /* Must be last entry */ 92 }; 93 94 #define IRDMA_MAX_MGS_PER_CTX 8 95 96 struct irdma_mcast_grp_ctx_entry_info { 97 u32 qp_id; 98 bool valid_entry; 99 u16 dest_port; 100 u32 use_cnt; 101 }; 102 103 struct irdma_mcast_grp_info { 104 u8 dest_mac_addr[ETH_ALEN]; 105 u16 vlan_id; 106 u16 hmc_fcn_id; 107 bool ipv4_valid:1; 108 bool vlan_valid:1; 109 u16 mg_id; 110 u32 no_of_mgs; 111 u32 dest_ip_addr[4]; 112 u16 qs_handle; 113 struct irdma_dma_mem dma_mem_mc; 114 struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX]; 115 }; 116 117 enum irdma_vers { 118 IRDMA_GEN_RSVD, 119 IRDMA_GEN_1, 120 IRDMA_GEN_2, 121 IRDMA_GEN_3, 122 IRDMA_GEN_NEXT, 123 IRDMA_GEN_MAX = IRDMA_GEN_NEXT-1 124 }; 125 126 struct irdma_uk_attrs { 127 u64 feature_flags; 128 u32 max_hw_wq_frags; 129 u32 max_hw_read_sges; 130 u32 max_hw_inline; 131 u32 max_hw_rq_quanta; 132 u32 max_hw_wq_quanta; 133 u32 min_hw_cq_size; 134 u32 max_hw_cq_size; 135 u32 max_hw_srq_quanta; 136 u16 max_hw_sq_chunk; 137 u16 min_hw_wq_size; 138 u8 hw_rev; 139 }; 140 141 struct irdma_hw_attrs { 142 struct irdma_uk_attrs uk_attrs; 143 u64 max_hw_outbound_msg_size; 144 u64 max_hw_inbound_msg_size; 145 u64 max_mr_size; 146 u64 page_size_cap; 147 u32 min_hw_qp_id; 148 u32 min_hw_aeq_size; 149 u32 max_hw_aeq_size; 150 u32 min_hw_ceq_size; 151 u32 max_hw_ceq_size; 152 u32 max_hw_device_pages; 153 u32 max_hw_vf_fpm_id; 154 u32 first_hw_vf_fpm_id; 155 u32 max_hw_ird; 156 u32 max_hw_ord; 157 u32 max_hw_wqes; 158 u32 max_hw_pds; 159 u32 max_hw_ena_vf_count; 160 u32 max_qp_wr; 161 u32 max_pe_ready_count; 162 u32 max_done_count; 163 u32 max_sleep_count; 164 u32 max_cqp_compl_wait_time_ms; 165 u32 min_hw_srq_id; 166 u16 max_stat_inst; 167 u16 max_stat_idx; 168 }; 169 170 void i40iw_init_hw(struct irdma_sc_dev *dev); 171 void icrdma_init_hw(struct irdma_sc_dev *dev); 172 void ig3rdma_init_hw(struct irdma_sc_dev *dev); 173 void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset); 174 #endif /* IRDMA_H*/ 175