1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "main.h" 4 5 static struct irdma_rsrc_limits rsrc_limits_table[] = { 6 [0] = { 7 .qplimit = SZ_128, 8 }, 9 [1] = { 10 .qplimit = SZ_1K, 11 }, 12 [2] = { 13 .qplimit = SZ_2K, 14 }, 15 [3] = { 16 .qplimit = SZ_4K, 17 }, 18 [4] = { 19 .qplimit = SZ_16K, 20 }, 21 [5] = { 22 .qplimit = SZ_64K, 23 }, 24 [6] = { 25 .qplimit = SZ_128K, 26 }, 27 [7] = { 28 .qplimit = SZ_256K, 29 }, 30 }; 31 32 /* types of hmc objects */ 33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 34 IRDMA_HMC_IW_QP, 35 IRDMA_HMC_IW_CQ, 36 IRDMA_HMC_IW_HTE, 37 IRDMA_HMC_IW_ARP, 38 IRDMA_HMC_IW_APBVT_ENTRY, 39 IRDMA_HMC_IW_MR, 40 IRDMA_HMC_IW_XF, 41 IRDMA_HMC_IW_XFFL, 42 IRDMA_HMC_IW_Q1, 43 IRDMA_HMC_IW_Q1FL, 44 IRDMA_HMC_IW_TIMER, 45 IRDMA_HMC_IW_FSIMC, 46 IRDMA_HMC_IW_FSIAV, 47 IRDMA_HMC_IW_RRF, 48 IRDMA_HMC_IW_RRFFL, 49 IRDMA_HMC_IW_HDR, 50 IRDMA_HMC_IW_MD, 51 IRDMA_HMC_IW_OOISC, 52 IRDMA_HMC_IW_OOISCFFL, 53 }; 54 55 /** 56 * irdma_iwarp_ce_handler - handle iwarp completions 57 * @iwcq: iwarp cq receiving event 58 */ 59 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 60 { 61 struct irdma_cq *cq = iwcq->back_cq; 62 63 if (cq->ibcq.comp_handler) 64 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 65 } 66 67 /** 68 * irdma_puda_ce_handler - handle puda completion events 69 * @rf: RDMA PCI function 70 * @cq: puda completion q for event 71 */ 72 static void irdma_puda_ce_handler(struct irdma_pci_f *rf, 73 struct irdma_sc_cq *cq) 74 { 75 struct irdma_sc_dev *dev = &rf->sc_dev; 76 enum irdma_status_code status; 77 u32 compl_error; 78 79 do { 80 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 81 if (status == IRDMA_ERR_Q_EMPTY) 82 break; 83 if (status) { 84 ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status); 85 break; 86 } 87 if (compl_error) { 88 ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err =0x%x\n", 89 compl_error); 90 break; 91 } 92 } while (1); 93 94 irdma_sc_ccq_arm(cq); 95 } 96 97 /** 98 * irdma_process_ceq - handle ceq for completions 99 * @rf: RDMA PCI function 100 * @ceq: ceq having cq for completion 101 */ 102 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 103 { 104 struct irdma_sc_dev *dev = &rf->sc_dev; 105 struct irdma_sc_ceq *sc_ceq; 106 struct irdma_sc_cq *cq; 107 unsigned long flags; 108 109 sc_ceq = &ceq->sc_ceq; 110 do { 111 spin_lock_irqsave(&ceq->ce_lock, flags); 112 cq = irdma_sc_process_ceq(dev, sc_ceq); 113 if (!cq) { 114 spin_unlock_irqrestore(&ceq->ce_lock, flags); 115 break; 116 } 117 118 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 119 irdma_iwarp_ce_handler(cq); 120 121 spin_unlock_irqrestore(&ceq->ce_lock, flags); 122 123 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 124 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 125 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 126 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 127 irdma_puda_ce_handler(rf, cq); 128 } while (1); 129 } 130 131 static void irdma_set_flush_fields(struct irdma_sc_qp *qp, 132 struct irdma_aeqe_info *info) 133 { 134 qp->sq_flush_code = info->sq; 135 qp->rq_flush_code = info->rq; 136 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 137 138 switch (info->ae_id) { 139 case IRDMA_AE_AMP_UNALLOCATED_STAG: 140 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 141 case IRDMA_AE_AMP_INVALID_STAG: 142 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 143 fallthrough; 144 case IRDMA_AE_AMP_BAD_PD: 145 case IRDMA_AE_UDA_XMIT_BAD_PD: 146 qp->flush_code = FLUSH_PROT_ERR; 147 break; 148 case IRDMA_AE_AMP_BAD_QP: 149 qp->flush_code = FLUSH_LOC_QP_OP_ERR; 150 break; 151 case IRDMA_AE_AMP_BAD_STAG_KEY: 152 case IRDMA_AE_AMP_BAD_STAG_INDEX: 153 case IRDMA_AE_AMP_TO_WRAP: 154 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 155 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 156 case IRDMA_AE_PRIV_OPERATION_DENIED: 157 case IRDMA_AE_IB_INVALID_REQUEST: 158 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 159 case IRDMA_AE_IB_REMOTE_OP_ERROR: 160 qp->flush_code = FLUSH_REM_ACCESS_ERR; 161 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 162 break; 163 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 164 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 165 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 166 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 167 case IRDMA_AE_UDA_L4LEN_INVALID: 168 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 169 qp->flush_code = FLUSH_LOC_LEN_ERR; 170 break; 171 case IRDMA_AE_LCE_QP_CATASTROPHIC: 172 qp->flush_code = FLUSH_FATAL_ERR; 173 break; 174 case IRDMA_AE_DDP_UBE_INVALID_MO: 175 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 176 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 177 qp->flush_code = FLUSH_GENERAL_ERR; 178 break; 179 default: 180 qp->flush_code = FLUSH_FATAL_ERR; 181 break; 182 } 183 } 184 185 /** 186 * irdma_process_aeq - handle aeq events 187 * @rf: RDMA PCI function 188 */ 189 static void irdma_process_aeq(struct irdma_pci_f *rf) 190 { 191 struct irdma_sc_dev *dev = &rf->sc_dev; 192 struct irdma_aeq *aeq = &rf->aeq; 193 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 194 struct irdma_aeqe_info aeinfo; 195 struct irdma_aeqe_info *info = &aeinfo; 196 int ret; 197 struct irdma_qp *iwqp = NULL; 198 struct irdma_sc_cq *cq = NULL; 199 struct irdma_cq *iwcq = NULL; 200 struct irdma_sc_qp *qp = NULL; 201 struct irdma_qp_host_ctx_info *ctx_info = NULL; 202 struct irdma_device *iwdev = rf->iwdev; 203 unsigned long flags; 204 205 u32 aeqcnt = 0; 206 207 if (!sc_aeq->size) 208 return; 209 210 do { 211 memset(info, 0, sizeof(*info)); 212 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 213 if (ret) 214 break; 215 216 aeqcnt++; 217 ibdev_dbg(&iwdev->ibdev, 218 "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 219 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, 220 info->iwarp_state, info->ae_src); 221 222 if (info->qp) { 223 spin_lock_irqsave(&rf->qptable_lock, flags); 224 iwqp = rf->qp_table[info->qp_cq_id]; 225 if (!iwqp) { 226 spin_unlock_irqrestore(&rf->qptable_lock, 227 flags); 228 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 229 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 230 wake_up(&iwdev->suspend_wq); 231 continue; 232 } 233 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n", 234 info->qp_cq_id); 235 continue; 236 } 237 irdma_qp_add_ref(&iwqp->ibqp); 238 spin_unlock_irqrestore(&rf->qptable_lock, flags); 239 qp = &iwqp->sc_qp; 240 spin_lock_irqsave(&iwqp->lock, flags); 241 iwqp->hw_tcp_state = info->tcp_state; 242 iwqp->hw_iwarp_state = info->iwarp_state; 243 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 244 iwqp->last_aeq = info->ae_id; 245 spin_unlock_irqrestore(&iwqp->lock, flags); 246 ctx_info = &iwqp->ctx_info; 247 if (rdma_protocol_roce(&iwqp->iwdev->ibdev, 1)) 248 ctx_info->roce_info->err_rq_idx_valid = true; 249 else 250 ctx_info->iwarp_info->err_rq_idx_valid = true; 251 } else { 252 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 253 continue; 254 } 255 256 switch (info->ae_id) { 257 struct irdma_cm_node *cm_node; 258 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 259 cm_node = iwqp->cm_node; 260 if (cm_node->accept_pend) { 261 atomic_dec(&cm_node->listener->pend_accepts_cnt); 262 cm_node->accept_pend = 0; 263 } 264 iwqp->rts_ae_rcvd = 1; 265 wake_up_interruptible(&iwqp->waitq); 266 break; 267 case IRDMA_AE_LLP_FIN_RECEIVED: 268 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 269 if (qp->term_flags) 270 break; 271 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 272 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 273 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT && 274 iwqp->ibqp_state == IB_QPS_RTS) { 275 irdma_next_iw_state(iwqp, 276 IRDMA_QP_STATE_CLOSING, 277 0, 0, 0); 278 irdma_cm_disconn(iwqp); 279 } 280 irdma_schedule_cm_timer(iwqp->cm_node, 281 (struct irdma_puda_buf *)iwqp, 282 IRDMA_TIMER_TYPE_CLOSE, 283 1, 0); 284 } 285 break; 286 case IRDMA_AE_LLP_CLOSE_COMPLETE: 287 if (qp->term_flags) 288 irdma_terminate_done(qp, 0); 289 else 290 irdma_cm_disconn(iwqp); 291 break; 292 case IRDMA_AE_BAD_CLOSE: 293 case IRDMA_AE_RESET_SENT: 294 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 295 0); 296 irdma_cm_disconn(iwqp); 297 break; 298 case IRDMA_AE_LLP_CONNECTION_RESET: 299 if (atomic_read(&iwqp->close_timer_started)) 300 break; 301 irdma_cm_disconn(iwqp); 302 break; 303 case IRDMA_AE_QP_SUSPEND_COMPLETE: 304 if (iwqp->iwdev->vsi.tc_change_pending) { 305 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs); 306 wake_up(&iwqp->iwdev->suspend_wq); 307 } 308 break; 309 case IRDMA_AE_TERMINATE_SENT: 310 irdma_terminate_send_fin(qp); 311 break; 312 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 313 irdma_terminate_received(qp, info); 314 break; 315 case IRDMA_AE_CQ_OPERATION_ERROR: 316 ibdev_err(&iwdev->ibdev, 317 "Processing an iWARP related AE for CQ misc = 0x%04X\n", 318 info->ae_id); 319 cq = (struct irdma_sc_cq *)(unsigned long) 320 info->compl_ctx; 321 322 iwcq = cq->back_cq; 323 324 if (iwcq->ibcq.event_handler) { 325 struct ib_event ibevent; 326 327 ibevent.device = iwcq->ibcq.device; 328 ibevent.event = IB_EVENT_CQ_ERR; 329 ibevent.element.cq = &iwcq->ibcq; 330 iwcq->ibcq.event_handler(&ibevent, 331 iwcq->ibcq.cq_context); 332 } 333 break; 334 case IRDMA_AE_RESET_NOT_SENT: 335 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 336 case IRDMA_AE_RESOURCE_EXHAUSTION: 337 break; 338 case IRDMA_AE_PRIV_OPERATION_DENIED: 339 case IRDMA_AE_STAG_ZERO_INVALID: 340 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 341 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 342 case IRDMA_AE_DDP_UBE_INVALID_MO: 343 case IRDMA_AE_DDP_UBE_INVALID_QN: 344 case IRDMA_AE_DDP_NO_L_BIT: 345 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 346 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 347 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 348 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 349 case IRDMA_AE_INVALID_ARP_ENTRY: 350 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 351 case IRDMA_AE_STALE_ARP_ENTRY: 352 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 353 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 354 case IRDMA_AE_LLP_SYN_RECEIVED: 355 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 356 case IRDMA_AE_LCE_QP_CATASTROPHIC: 357 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 358 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 359 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 360 if (rdma_protocol_roce(&iwdev->ibdev, 1)) 361 ctx_info->roce_info->err_rq_idx_valid = false; 362 else 363 ctx_info->iwarp_info->err_rq_idx_valid = false; 364 fallthrough; 365 default: 366 ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d\n", 367 info->ae_id, info->qp, info->qp_cq_id); 368 if (rdma_protocol_roce(&iwdev->ibdev, 1)) { 369 if (!info->sq && ctx_info->roce_info->err_rq_idx_valid) { 370 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 371 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 372 ctx_info); 373 } 374 irdma_set_flush_fields(qp, info); 375 irdma_cm_disconn(iwqp); 376 break; 377 } 378 if (!info->sq && ctx_info->iwarp_info->err_rq_idx_valid) { 379 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 380 ctx_info->tcp_info_valid = false; 381 ctx_info->iwarp_info_valid = true; 382 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 383 ctx_info); 384 } 385 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 386 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 387 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 388 irdma_cm_disconn(iwqp); 389 } else { 390 irdma_terminate_connection(qp, info); 391 } 392 break; 393 } 394 if (info->qp) 395 irdma_qp_rem_ref(&iwqp->ibqp); 396 } while (1); 397 398 if (aeqcnt) 399 irdma_sc_repost_aeq_entries(dev, aeqcnt); 400 } 401 402 /** 403 * irdma_ena_intr - set up device interrupts 404 * @dev: hardware control device structure 405 * @msix_id: id of the interrupt to be enabled 406 */ 407 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 408 { 409 dev->irq_ops->irdma_en_irq(dev, msix_id); 410 } 411 412 /** 413 * irdma_dpc - tasklet for aeq and ceq 0 414 * @t: tasklet_struct ptr 415 */ 416 static void irdma_dpc(struct tasklet_struct *t) 417 { 418 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet); 419 420 if (rf->msix_shared) 421 irdma_process_ceq(rf, rf->ceqlist); 422 irdma_process_aeq(rf); 423 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 424 } 425 426 /** 427 * irdma_ceq_dpc - dpc handler for CEQ 428 * @t: tasklet_struct ptr 429 */ 430 static void irdma_ceq_dpc(struct tasklet_struct *t) 431 { 432 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet); 433 struct irdma_pci_f *rf = iwceq->rf; 434 435 irdma_process_ceq(rf, iwceq); 436 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 437 } 438 439 /** 440 * irdma_save_msix_info - copy msix vector information to iwarp device 441 * @rf: RDMA PCI function 442 * 443 * Allocate iwdev msix table and copy the msix info to the table 444 * Return 0 if successful, otherwise return error 445 */ 446 static enum irdma_status_code irdma_save_msix_info(struct irdma_pci_f *rf) 447 { 448 struct irdma_qvlist_info *iw_qvlist; 449 struct irdma_qv_info *iw_qvinfo; 450 struct msix_entry *pmsix; 451 u32 ceq_idx; 452 u32 i; 453 size_t size; 454 455 if (!rf->msix_count) 456 return IRDMA_ERR_NO_INTR; 457 458 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 459 size += struct_size(iw_qvlist, qv_info, rf->msix_count); 460 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 461 if (!rf->iw_msixtbl) 462 return IRDMA_ERR_NO_MEMORY; 463 464 rf->iw_qvlist = (struct irdma_qvlist_info *) 465 (&rf->iw_msixtbl[rf->msix_count]); 466 iw_qvlist = rf->iw_qvlist; 467 iw_qvinfo = iw_qvlist->qv_info; 468 iw_qvlist->num_vectors = rf->msix_count; 469 if (rf->msix_count <= num_online_cpus()) 470 rf->msix_shared = true; 471 472 pmsix = rf->msix_entries; 473 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 474 rf->iw_msixtbl[i].idx = pmsix->entry; 475 rf->iw_msixtbl[i].irq = pmsix->vector; 476 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 477 if (!i) { 478 iw_qvinfo->aeq_idx = 0; 479 if (rf->msix_shared) 480 iw_qvinfo->ceq_idx = ceq_idx++; 481 else 482 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 483 } else { 484 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 485 iw_qvinfo->ceq_idx = ceq_idx++; 486 } 487 iw_qvinfo->itr_idx = 3; 488 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 489 pmsix++; 490 } 491 492 return 0; 493 } 494 495 /** 496 * irdma_irq_handler - interrupt handler for aeq and ceq0 497 * @irq: Interrupt request number 498 * @data: RDMA PCI function 499 */ 500 static irqreturn_t irdma_irq_handler(int irq, void *data) 501 { 502 struct irdma_pci_f *rf = data; 503 504 tasklet_schedule(&rf->dpc_tasklet); 505 506 return IRQ_HANDLED; 507 } 508 509 /** 510 * irdma_ceq_handler - interrupt handler for ceq 511 * @irq: interrupt request number 512 * @data: ceq pointer 513 */ 514 static irqreturn_t irdma_ceq_handler(int irq, void *data) 515 { 516 struct irdma_ceq *iwceq = data; 517 518 if (iwceq->irq != irq) 519 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n", 520 iwceq->irq, irq); 521 tasklet_schedule(&iwceq->dpc_tasklet); 522 523 return IRQ_HANDLED; 524 } 525 526 /** 527 * irdma_destroy_irq - destroy device interrupts 528 * @rf: RDMA PCI function 529 * @msix_vec: msix vector to disable irq 530 * @dev_id: parameter to pass to free_irq (used during irq setup) 531 * 532 * The function is called when destroying aeq/ceq 533 */ 534 static void irdma_destroy_irq(struct irdma_pci_f *rf, 535 struct irdma_msix_vector *msix_vec, void *dev_id) 536 { 537 struct irdma_sc_dev *dev = &rf->sc_dev; 538 539 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 540 irq_set_affinity_hint(msix_vec->irq, NULL); 541 free_irq(msix_vec->irq, dev_id); 542 } 543 544 /** 545 * irdma_destroy_cqp - destroy control qp 546 * @rf: RDMA PCI function 547 * @free_hwcqp: 1 if hw cqp should be freed 548 * 549 * Issue destroy cqp request and 550 * free the resources associated with the cqp 551 */ 552 static void irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) 553 { 554 enum irdma_status_code status = 0; 555 struct irdma_sc_dev *dev = &rf->sc_dev; 556 struct irdma_cqp *cqp = &rf->cqp; 557 558 if (rf->cqp_cmpl_wq) 559 destroy_workqueue(rf->cqp_cmpl_wq); 560 if (free_hwcqp) 561 status = irdma_sc_cqp_destroy(dev->cqp); 562 if (status) 563 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status); 564 565 irdma_cleanup_pending_cqp_op(rf); 566 dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va, 567 cqp->sq.pa); 568 cqp->sq.va = NULL; 569 kfree(cqp->scratch_array); 570 cqp->scratch_array = NULL; 571 kfree(cqp->cqp_requests); 572 cqp->cqp_requests = NULL; 573 } 574 575 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 576 { 577 struct irdma_aeq *aeq = &rf->aeq; 578 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 579 dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 580 581 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 582 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 583 vfree(aeq->mem.va); 584 } 585 586 /** 587 * irdma_destroy_aeq - destroy aeq 588 * @rf: RDMA PCI function 589 * 590 * Issue a destroy aeq request and 591 * free the resources associated with the aeq 592 * The function is called during driver unload 593 */ 594 static void irdma_destroy_aeq(struct irdma_pci_f *rf) 595 { 596 enum irdma_status_code status = IRDMA_ERR_NOT_READY; 597 struct irdma_sc_dev *dev = &rf->sc_dev; 598 struct irdma_aeq *aeq = &rf->aeq; 599 600 if (!rf->msix_shared) { 601 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 602 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 603 } 604 if (rf->reset) 605 goto exit; 606 607 aeq->sc_aeq.size = 0; 608 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 609 if (status) 610 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status); 611 612 exit: 613 if (aeq->virtual_map) { 614 irdma_destroy_virt_aeq(rf); 615 } else { 616 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 617 aeq->mem.pa); 618 aeq->mem.va = NULL; 619 } 620 } 621 622 /** 623 * irdma_destroy_ceq - destroy ceq 624 * @rf: RDMA PCI function 625 * @iwceq: ceq to be destroyed 626 * 627 * Issue a destroy ceq request and 628 * free the resources associated with the ceq 629 */ 630 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 631 { 632 enum irdma_status_code status; 633 struct irdma_sc_dev *dev = &rf->sc_dev; 634 635 if (rf->reset) 636 goto exit; 637 638 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 639 if (status) { 640 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status); 641 goto exit; 642 } 643 644 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 645 if (status) 646 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n", 647 status); 648 exit: 649 dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va, 650 iwceq->mem.pa); 651 iwceq->mem.va = NULL; 652 } 653 654 /** 655 * irdma_del_ceq_0 - destroy ceq 0 656 * @rf: RDMA PCI function 657 * 658 * Disable the ceq 0 interrupt and destroy the ceq 0 659 */ 660 static void irdma_del_ceq_0(struct irdma_pci_f *rf) 661 { 662 struct irdma_ceq *iwceq = rf->ceqlist; 663 struct irdma_msix_vector *msix_vec; 664 665 if (rf->msix_shared) { 666 msix_vec = &rf->iw_msixtbl[0]; 667 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 668 msix_vec->ceq_id, 669 msix_vec->idx, false); 670 irdma_destroy_irq(rf, msix_vec, rf); 671 } else { 672 msix_vec = &rf->iw_msixtbl[1]; 673 irdma_destroy_irq(rf, msix_vec, iwceq); 674 } 675 676 irdma_destroy_ceq(rf, iwceq); 677 rf->sc_dev.ceq_valid = false; 678 rf->ceqs_count = 0; 679 } 680 681 /** 682 * irdma_del_ceqs - destroy all ceq's except CEQ 0 683 * @rf: RDMA PCI function 684 * 685 * Go through all of the device ceq's, except 0, and for each 686 * ceq disable the ceq interrupt and destroy the ceq 687 */ 688 static void irdma_del_ceqs(struct irdma_pci_f *rf) 689 { 690 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 691 struct irdma_msix_vector *msix_vec; 692 u32 i = 0; 693 694 if (rf->msix_shared) 695 msix_vec = &rf->iw_msixtbl[1]; 696 else 697 msix_vec = &rf->iw_msixtbl[2]; 698 699 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 700 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 701 msix_vec->idx, false); 702 irdma_destroy_irq(rf, msix_vec, iwceq); 703 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 704 IRDMA_OP_CEQ_DESTROY); 705 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size, 706 iwceq->mem.va, iwceq->mem.pa); 707 iwceq->mem.va = NULL; 708 } 709 rf->ceqs_count = 1; 710 } 711 712 /** 713 * irdma_destroy_ccq - destroy control cq 714 * @rf: RDMA PCI function 715 * 716 * Issue destroy ccq request and 717 * free the resources associated with the ccq 718 */ 719 static void irdma_destroy_ccq(struct irdma_pci_f *rf) 720 { 721 struct irdma_sc_dev *dev = &rf->sc_dev; 722 struct irdma_ccq *ccq = &rf->ccq; 723 enum irdma_status_code status = 0; 724 725 if (!rf->reset) 726 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 727 if (status) 728 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status); 729 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va, 730 ccq->mem_cq.pa); 731 ccq->mem_cq.va = NULL; 732 } 733 734 /** 735 * irdma_close_hmc_objects_type - delete hmc objects of a given type 736 * @dev: iwarp device 737 * @obj_type: the hmc object type to be deleted 738 * @hmc_info: host memory info struct 739 * @privileged: permission to close HMC objects 740 * @reset: true if called before reset 741 */ 742 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 743 enum irdma_hmc_rsrc_type obj_type, 744 struct irdma_hmc_info *hmc_info, 745 bool privileged, bool reset) 746 { 747 struct irdma_hmc_del_obj_info info = {}; 748 749 info.hmc_info = hmc_info; 750 info.rsrc_type = obj_type; 751 info.count = hmc_info->hmc_obj[obj_type].cnt; 752 info.privileged = privileged; 753 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 754 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n", 755 obj_type); 756 } 757 758 /** 759 * irdma_del_hmc_objects - remove all device hmc objects 760 * @dev: iwarp device 761 * @hmc_info: hmc_info to free 762 * @privileged: permission to delete HMC objects 763 * @reset: true if called before reset 764 * @vers: hardware version 765 */ 766 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev, 767 struct irdma_hmc_info *hmc_info, bool privileged, 768 bool reset, enum irdma_vers vers) 769 { 770 unsigned int i; 771 772 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 773 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 774 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 775 hmc_info, privileged, reset); 776 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 777 break; 778 } 779 } 780 781 /** 782 * irdma_create_hmc_obj_type - create hmc object of a given type 783 * @dev: hardware control device structure 784 * @info: information for the hmc object to create 785 */ 786 static enum irdma_status_code 787 irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 788 struct irdma_hmc_create_obj_info *info) 789 { 790 return irdma_sc_create_hmc_obj(dev, info); 791 } 792 793 /** 794 * irdma_create_hmc_objs - create all hmc objects for the device 795 * @rf: RDMA PCI function 796 * @privileged: permission to create HMC objects 797 * @vers: HW version 798 * 799 * Create the device hmc objects and allocate hmc pages 800 * Return 0 if successful, otherwise clean up and return error 801 */ 802 static enum irdma_status_code 803 irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, enum irdma_vers vers) 804 { 805 struct irdma_sc_dev *dev = &rf->sc_dev; 806 struct irdma_hmc_create_obj_info info = {}; 807 enum irdma_status_code status = 0; 808 int i; 809 810 info.hmc_info = dev->hmc_info; 811 info.privileged = privileged; 812 info.entry_type = rf->sd_type; 813 814 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 815 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 816 info.rsrc_type = iw_hmc_obj_types[i]; 817 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 818 info.add_sd_cnt = 0; 819 status = irdma_create_hmc_obj_type(dev, &info); 820 if (status) { 821 ibdev_dbg(to_ibdev(dev), 822 "ERR: create obj type %d status = %d\n", 823 iw_hmc_obj_types[i], status); 824 break; 825 } 826 } 827 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 828 break; 829 } 830 831 if (!status) 832 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 833 true, true); 834 835 while (i) { 836 i--; 837 /* destroy the hmc objects of a given type */ 838 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 839 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 840 dev->hmc_info, privileged, 841 false); 842 } 843 844 return status; 845 } 846 847 /** 848 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 849 * @rf: RDMA PCI function 850 * @memptr: points to the memory addresses 851 * @size: size of memory needed 852 * @mask: mask for the aligned memory 853 * 854 * Get aligned memory of the requested size and 855 * update the memptr to point to the new aligned memory 856 * Return 0 if successful, otherwise return no memory error 857 */ 858 static enum irdma_status_code 859 irdma_obj_aligned_mem(struct irdma_pci_f *rf, struct irdma_dma_mem *memptr, 860 u32 size, u32 mask) 861 { 862 unsigned long va, newva; 863 unsigned long extra; 864 865 va = (unsigned long)rf->obj_next.va; 866 newva = va; 867 if (mask) 868 newva = ALIGN(va, (unsigned long)mask + 1ULL); 869 extra = newva - va; 870 memptr->va = (u8 *)va + extra; 871 memptr->pa = rf->obj_next.pa + extra; 872 memptr->size = size; 873 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 874 return IRDMA_ERR_NO_MEMORY; 875 876 rf->obj_next.va = (u8 *)memptr->va + size; 877 rf->obj_next.pa = memptr->pa + size; 878 879 return 0; 880 } 881 882 /** 883 * irdma_create_cqp - create control qp 884 * @rf: RDMA PCI function 885 * 886 * Return 0, if the cqp and all the resources associated with it 887 * are successfully created, otherwise return error 888 */ 889 static enum irdma_status_code irdma_create_cqp(struct irdma_pci_f *rf) 890 { 891 enum irdma_status_code status; 892 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 893 struct irdma_dma_mem mem; 894 struct irdma_sc_dev *dev = &rf->sc_dev; 895 struct irdma_cqp_init_info cqp_init_info = {}; 896 struct irdma_cqp *cqp = &rf->cqp; 897 u16 maj_err, min_err; 898 int i; 899 900 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 901 if (!cqp->cqp_requests) 902 return IRDMA_ERR_NO_MEMORY; 903 904 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 905 if (!cqp->scratch_array) { 906 kfree(cqp->cqp_requests); 907 return IRDMA_ERR_NO_MEMORY; 908 } 909 910 dev->cqp = &cqp->sc_cqp; 911 dev->cqp->dev = dev; 912 cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize, 913 IRDMA_CQP_ALIGNMENT); 914 cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size, 915 &cqp->sq.pa, GFP_KERNEL); 916 if (!cqp->sq.va) { 917 kfree(cqp->scratch_array); 918 kfree(cqp->cqp_requests); 919 return IRDMA_ERR_NO_MEMORY; 920 } 921 922 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 923 IRDMA_HOST_CTX_ALIGNMENT_M); 924 if (status) 925 goto exit; 926 927 dev->cqp->host_ctx_pa = mem.pa; 928 dev->cqp->host_ctx = mem.va; 929 /* populate the cqp init info */ 930 cqp_init_info.dev = dev; 931 cqp_init_info.sq_size = sqsize; 932 cqp_init_info.sq = cqp->sq.va; 933 cqp_init_info.sq_pa = cqp->sq.pa; 934 cqp_init_info.host_ctx_pa = mem.pa; 935 cqp_init_info.host_ctx = mem.va; 936 cqp_init_info.hmc_profile = rf->rsrc_profile; 937 cqp_init_info.scratch_array = cqp->scratch_array; 938 cqp_init_info.protocol_used = rf->protocol_used; 939 940 switch (rf->rdma_ver) { 941 case IRDMA_GEN_1: 942 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 943 break; 944 case IRDMA_GEN_2: 945 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 946 break; 947 } 948 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 949 if (status) { 950 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status); 951 goto exit; 952 } 953 954 spin_lock_init(&cqp->req_lock); 955 spin_lock_init(&cqp->compl_lock); 956 957 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 958 if (status) { 959 ibdev_dbg(to_ibdev(dev), 960 "ERR: cqp create failed - status %d maj_err %d min_err %d\n", 961 status, maj_err, min_err); 962 goto exit; 963 } 964 965 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 966 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 967 968 /* init the waitqueue of the cqp_requests and add them to the list */ 969 for (i = 0; i < sqsize; i++) { 970 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 971 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 972 } 973 init_waitqueue_head(&cqp->remove_wq); 974 return 0; 975 976 exit: 977 irdma_destroy_cqp(rf, false); 978 979 return status; 980 } 981 982 /** 983 * irdma_create_ccq - create control cq 984 * @rf: RDMA PCI function 985 * 986 * Return 0, if the ccq and the resources associated with it 987 * are successfully created, otherwise return error 988 */ 989 static enum irdma_status_code irdma_create_ccq(struct irdma_pci_f *rf) 990 { 991 struct irdma_sc_dev *dev = &rf->sc_dev; 992 enum irdma_status_code status; 993 struct irdma_ccq_init_info info = {}; 994 struct irdma_ccq *ccq = &rf->ccq; 995 996 dev->ccq = &ccq->sc_cq; 997 dev->ccq->dev = dev; 998 info.dev = dev; 999 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1000 ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE, 1001 IRDMA_CQ0_ALIGNMENT); 1002 ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size, 1003 &ccq->mem_cq.pa, GFP_KERNEL); 1004 if (!ccq->mem_cq.va) 1005 return IRDMA_ERR_NO_MEMORY; 1006 1007 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1008 ccq->shadow_area.size, 1009 IRDMA_SHADOWAREA_M); 1010 if (status) 1011 goto exit; 1012 1013 ccq->sc_cq.back_cq = ccq; 1014 /* populate the ccq init info */ 1015 info.cq_base = ccq->mem_cq.va; 1016 info.cq_pa = ccq->mem_cq.pa; 1017 info.num_elem = IW_CCQ_SIZE; 1018 info.shadow_area = ccq->shadow_area.va; 1019 info.shadow_area_pa = ccq->shadow_area.pa; 1020 info.ceqe_mask = false; 1021 info.ceq_id_valid = true; 1022 info.shadow_read_threshold = 16; 1023 info.vsi = &rf->default_vsi; 1024 status = irdma_sc_ccq_init(dev->ccq, &info); 1025 if (!status) 1026 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1027 exit: 1028 if (status) { 1029 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, 1030 ccq->mem_cq.va, ccq->mem_cq.pa); 1031 ccq->mem_cq.va = NULL; 1032 } 1033 1034 return status; 1035 } 1036 1037 /** 1038 * irdma_alloc_set_mac - set up a mac address table entry 1039 * @iwdev: irdma device 1040 * 1041 * Allocate a mac ip entry and add it to the hw table Return 0 1042 * if successful, otherwise return error 1043 */ 1044 static enum irdma_status_code irdma_alloc_set_mac(struct irdma_device *iwdev) 1045 { 1046 enum irdma_status_code status; 1047 1048 status = irdma_alloc_local_mac_entry(iwdev->rf, 1049 &iwdev->mac_ip_table_idx); 1050 if (!status) { 1051 status = irdma_add_local_mac_entry(iwdev->rf, 1052 (u8 *)iwdev->netdev->dev_addr, 1053 (u8)iwdev->mac_ip_table_idx); 1054 if (status) 1055 irdma_del_local_mac_entry(iwdev->rf, 1056 (u8)iwdev->mac_ip_table_idx); 1057 } 1058 return status; 1059 } 1060 1061 /** 1062 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1063 * ceq 1064 * @rf: RDMA PCI function 1065 * @iwceq: ceq associated with the vector 1066 * @ceq_id: the id number of the iwceq 1067 * @msix_vec: interrupt vector information 1068 * 1069 * Allocate interrupt resources and enable irq handling 1070 * Return 0 if successful, otherwise return error 1071 */ 1072 static enum irdma_status_code 1073 irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1074 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1075 { 1076 int status; 1077 1078 if (rf->msix_shared && !ceq_id) { 1079 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1080 status = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1081 "AEQCEQ", rf); 1082 } else { 1083 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1084 1085 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0, 1086 "CEQ", iwceq); 1087 } 1088 cpumask_clear(&msix_vec->mask); 1089 cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask); 1090 irq_set_affinity_hint(msix_vec->irq, &msix_vec->mask); 1091 if (status) { 1092 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n"); 1093 return IRDMA_ERR_CFG; 1094 } 1095 1096 msix_vec->ceq_id = ceq_id; 1097 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1098 1099 return 0; 1100 } 1101 1102 /** 1103 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1104 * @rf: RDMA PCI function 1105 * 1106 * Allocate interrupt resources and enable irq handling 1107 * Return 0 if successful, otherwise return error 1108 */ 1109 static enum irdma_status_code irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1110 { 1111 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1112 u32 ret = 0; 1113 1114 if (!rf->msix_shared) { 1115 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1116 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1117 "irdma", rf); 1118 } 1119 if (ret) { 1120 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n"); 1121 return IRDMA_ERR_CFG; 1122 } 1123 1124 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1125 1126 return 0; 1127 } 1128 1129 /** 1130 * irdma_create_ceq - create completion event queue 1131 * @rf: RDMA PCI function 1132 * @iwceq: pointer to the ceq resources to be created 1133 * @ceq_id: the id number of the iwceq 1134 * @vsi: SC vsi struct 1135 * 1136 * Return 0, if the ceq and the resources associated with it 1137 * are successfully created, otherwise return error 1138 */ 1139 static enum irdma_status_code irdma_create_ceq(struct irdma_pci_f *rf, 1140 struct irdma_ceq *iwceq, 1141 u32 ceq_id, 1142 struct irdma_sc_vsi *vsi) 1143 { 1144 enum irdma_status_code status; 1145 struct irdma_ceq_init_info info = {}; 1146 struct irdma_sc_dev *dev = &rf->sc_dev; 1147 u64 scratch; 1148 u32 ceq_size; 1149 1150 info.ceq_id = ceq_id; 1151 iwceq->rf = rf; 1152 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1153 dev->hw_attrs.max_hw_ceq_size); 1154 iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size, 1155 IRDMA_CEQ_ALIGNMENT); 1156 iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size, 1157 &iwceq->mem.pa, GFP_KERNEL); 1158 if (!iwceq->mem.va) 1159 return IRDMA_ERR_NO_MEMORY; 1160 1161 info.ceq_id = ceq_id; 1162 info.ceqe_base = iwceq->mem.va; 1163 info.ceqe_pa = iwceq->mem.pa; 1164 info.elem_cnt = ceq_size; 1165 iwceq->sc_ceq.ceq_id = ceq_id; 1166 info.dev = dev; 1167 info.vsi = vsi; 1168 scratch = (uintptr_t)&rf->cqp.sc_cqp; 1169 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1170 if (!status) { 1171 if (dev->ceq_valid) 1172 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1173 IRDMA_OP_CEQ_CREATE); 1174 else 1175 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch); 1176 } 1177 1178 if (status) { 1179 dma_free_coherent(dev->hw->device, iwceq->mem.size, 1180 iwceq->mem.va, iwceq->mem.pa); 1181 iwceq->mem.va = NULL; 1182 } 1183 1184 return status; 1185 } 1186 1187 /** 1188 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1189 * @rf: RDMA PCI function 1190 * 1191 * Allocate a list for all device completion event queues 1192 * Create the ceq 0 and configure it's msix interrupt vector 1193 * Return 0, if successfully set up, otherwise return error 1194 */ 1195 static enum irdma_status_code irdma_setup_ceq_0(struct irdma_pci_f *rf) 1196 { 1197 struct irdma_ceq *iwceq; 1198 struct irdma_msix_vector *msix_vec; 1199 u32 i; 1200 enum irdma_status_code status = 0; 1201 u32 num_ceqs; 1202 1203 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1204 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1205 if (!rf->ceqlist) { 1206 status = IRDMA_ERR_NO_MEMORY; 1207 goto exit; 1208 } 1209 1210 iwceq = &rf->ceqlist[0]; 1211 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1212 if (status) { 1213 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n", 1214 status); 1215 goto exit; 1216 } 1217 1218 spin_lock_init(&iwceq->ce_lock); 1219 i = rf->msix_shared ? 0 : 1; 1220 msix_vec = &rf->iw_msixtbl[i]; 1221 iwceq->irq = msix_vec->irq; 1222 iwceq->msix_idx = msix_vec->idx; 1223 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1224 if (status) { 1225 irdma_destroy_ceq(rf, iwceq); 1226 goto exit; 1227 } 1228 1229 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1230 rf->ceqs_count++; 1231 1232 exit: 1233 if (status && !rf->ceqs_count) { 1234 kfree(rf->ceqlist); 1235 rf->ceqlist = NULL; 1236 return status; 1237 } 1238 rf->sc_dev.ceq_valid = true; 1239 1240 return 0; 1241 } 1242 1243 /** 1244 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1245 * @rf: RDMA PCI function 1246 * @vsi: VSI structure for this CEQ 1247 * 1248 * Allocate a list for all device completion event queues 1249 * Create the ceq's and configure their msix interrupt vectors 1250 * Return 0, if ceqs are successfully set up, otherwise return error 1251 */ 1252 static enum irdma_status_code irdma_setup_ceqs(struct irdma_pci_f *rf, 1253 struct irdma_sc_vsi *vsi) 1254 { 1255 u32 i; 1256 u32 ceq_id; 1257 struct irdma_ceq *iwceq; 1258 struct irdma_msix_vector *msix_vec; 1259 enum irdma_status_code status; 1260 u32 num_ceqs; 1261 1262 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1263 i = (rf->msix_shared) ? 1 : 2; 1264 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1265 iwceq = &rf->ceqlist[ceq_id]; 1266 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1267 if (status) { 1268 ibdev_dbg(&rf->iwdev->ibdev, 1269 "ERR: create ceq status = %d\n", status); 1270 goto del_ceqs; 1271 } 1272 spin_lock_init(&iwceq->ce_lock); 1273 msix_vec = &rf->iw_msixtbl[i]; 1274 iwceq->irq = msix_vec->irq; 1275 iwceq->msix_idx = msix_vec->idx; 1276 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1277 if (status) { 1278 irdma_destroy_ceq(rf, iwceq); 1279 goto del_ceqs; 1280 } 1281 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1282 rf->ceqs_count++; 1283 } 1284 1285 return 0; 1286 1287 del_ceqs: 1288 irdma_del_ceqs(rf); 1289 1290 return status; 1291 } 1292 1293 static enum irdma_status_code irdma_create_virt_aeq(struct irdma_pci_f *rf, 1294 u32 size) 1295 { 1296 enum irdma_status_code status = IRDMA_ERR_NO_MEMORY; 1297 struct irdma_aeq *aeq = &rf->aeq; 1298 dma_addr_t *pg_arr; 1299 u32 pg_cnt; 1300 1301 if (rf->rdma_ver < IRDMA_GEN_2) 1302 return IRDMA_NOT_SUPPORTED; 1303 1304 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1305 aeq->mem.va = vzalloc(aeq->mem.size); 1306 1307 if (!aeq->mem.va) 1308 return status; 1309 1310 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1311 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1312 if (status) { 1313 vfree(aeq->mem.va); 1314 return status; 1315 } 1316 1317 pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 1318 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1319 if (status) { 1320 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1321 vfree(aeq->mem.va); 1322 return status; 1323 } 1324 1325 return 0; 1326 } 1327 1328 /** 1329 * irdma_create_aeq - create async event queue 1330 * @rf: RDMA PCI function 1331 * 1332 * Return 0, if the aeq and the resources associated with it 1333 * are successfully created, otherwise return error 1334 */ 1335 static enum irdma_status_code irdma_create_aeq(struct irdma_pci_f *rf) 1336 { 1337 enum irdma_status_code status; 1338 struct irdma_aeq_init_info info = {}; 1339 struct irdma_sc_dev *dev = &rf->sc_dev; 1340 struct irdma_aeq *aeq = &rf->aeq; 1341 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1342 u32 aeq_size; 1343 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1344 1345 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1346 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1347 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1348 1349 aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size, 1350 IRDMA_AEQ_ALIGNMENT); 1351 aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size, 1352 &aeq->mem.pa, 1353 GFP_KERNEL | __GFP_NOWARN); 1354 if (aeq->mem.va) 1355 goto skip_virt_aeq; 1356 1357 /* physically mapped aeq failed. setup virtual aeq */ 1358 status = irdma_create_virt_aeq(rf, aeq_size); 1359 if (status) 1360 return status; 1361 1362 info.virtual_map = true; 1363 aeq->virtual_map = info.virtual_map; 1364 info.pbl_chunk_size = 1; 1365 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1366 1367 skip_virt_aeq: 1368 info.aeqe_base = aeq->mem.va; 1369 info.aeq_elem_pa = aeq->mem.pa; 1370 info.elem_cnt = aeq_size; 1371 info.dev = dev; 1372 info.msix_idx = rf->iw_msixtbl->idx; 1373 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1374 if (status) 1375 goto err; 1376 1377 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1378 if (status) 1379 goto err; 1380 1381 return 0; 1382 1383 err: 1384 if (aeq->virtual_map) { 1385 irdma_destroy_virt_aeq(rf); 1386 } else { 1387 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 1388 aeq->mem.pa); 1389 aeq->mem.va = NULL; 1390 } 1391 1392 return status; 1393 } 1394 1395 /** 1396 * irdma_setup_aeq - set up the device aeq 1397 * @rf: RDMA PCI function 1398 * 1399 * Create the aeq and configure its msix interrupt vector 1400 * Return 0 if successful, otherwise return error 1401 */ 1402 static enum irdma_status_code irdma_setup_aeq(struct irdma_pci_f *rf) 1403 { 1404 struct irdma_sc_dev *dev = &rf->sc_dev; 1405 enum irdma_status_code status; 1406 1407 status = irdma_create_aeq(rf); 1408 if (status) 1409 return status; 1410 1411 status = irdma_cfg_aeq_vector(rf); 1412 if (status) { 1413 irdma_destroy_aeq(rf); 1414 return status; 1415 } 1416 1417 if (!rf->msix_shared) 1418 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1419 1420 return 0; 1421 } 1422 1423 /** 1424 * irdma_initialize_ilq - create iwarp local queue for cm 1425 * @iwdev: irdma device 1426 * 1427 * Return 0 if successful, otherwise return error 1428 */ 1429 static enum irdma_status_code irdma_initialize_ilq(struct irdma_device *iwdev) 1430 { 1431 struct irdma_puda_rsrc_info info = {}; 1432 enum irdma_status_code status; 1433 1434 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1435 info.cq_id = 1; 1436 info.qp_id = 1; 1437 info.count = 1; 1438 info.pd_id = 1; 1439 info.abi_ver = IRDMA_ABI_VER; 1440 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1441 info.rq_size = info.sq_size; 1442 info.buf_size = 1024; 1443 info.tx_buf_cnt = 2 * info.sq_size; 1444 info.receive = irdma_receive_ilq; 1445 info.xmit_complete = irdma_free_sqbuf; 1446 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1447 if (status) 1448 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n"); 1449 1450 return status; 1451 } 1452 1453 /** 1454 * irdma_initialize_ieq - create iwarp exception queue 1455 * @iwdev: irdma device 1456 * 1457 * Return 0 if successful, otherwise return error 1458 */ 1459 static enum irdma_status_code irdma_initialize_ieq(struct irdma_device *iwdev) 1460 { 1461 struct irdma_puda_rsrc_info info = {}; 1462 enum irdma_status_code status; 1463 1464 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1465 info.cq_id = 2; 1466 info.qp_id = iwdev->vsi.exception_lan_q; 1467 info.count = 1; 1468 info.pd_id = 2; 1469 info.abi_ver = IRDMA_ABI_VER; 1470 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1471 info.rq_size = info.sq_size; 1472 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1473 info.tx_buf_cnt = 4096; 1474 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1475 if (status) 1476 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n"); 1477 1478 return status; 1479 } 1480 1481 /** 1482 * irdma_reinitialize_ieq - destroy and re-create ieq 1483 * @vsi: VSI structure 1484 */ 1485 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1486 { 1487 struct irdma_device *iwdev = vsi->back_vsi; 1488 struct irdma_pci_f *rf = iwdev->rf; 1489 1490 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1491 if (irdma_initialize_ieq(iwdev)) { 1492 iwdev->reset = true; 1493 rf->gen_ops.request_reset(rf); 1494 } 1495 } 1496 1497 /** 1498 * irdma_hmc_setup - create hmc objects for the device 1499 * @rf: RDMA PCI function 1500 * 1501 * Set up the device private memory space for the number and size of 1502 * the hmc objects and create the objects 1503 * Return 0 if successful, otherwise return error 1504 */ 1505 static enum irdma_status_code irdma_hmc_setup(struct irdma_pci_f *rf) 1506 { 1507 enum irdma_status_code status; 1508 u32 qpcnt; 1509 1510 if (rf->rdma_ver == IRDMA_GEN_1) 1511 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit * 2; 1512 else 1513 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1514 1515 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1516 status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt); 1517 if (status) 1518 return status; 1519 1520 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1521 1522 return status; 1523 } 1524 1525 /** 1526 * irdma_del_init_mem - deallocate memory resources 1527 * @rf: RDMA PCI function 1528 */ 1529 static void irdma_del_init_mem(struct irdma_pci_f *rf) 1530 { 1531 struct irdma_sc_dev *dev = &rf->sc_dev; 1532 1533 kfree(dev->hmc_info->sd_table.sd_entry); 1534 dev->hmc_info->sd_table.sd_entry = NULL; 1535 kfree(rf->mem_rsrc); 1536 rf->mem_rsrc = NULL; 1537 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1538 rf->obj_mem.pa); 1539 rf->obj_mem.va = NULL; 1540 if (rf->rdma_ver != IRDMA_GEN_1) { 1541 kfree(rf->allocated_ws_nodes); 1542 rf->allocated_ws_nodes = NULL; 1543 } 1544 kfree(rf->ceqlist); 1545 rf->ceqlist = NULL; 1546 kfree(rf->iw_msixtbl); 1547 rf->iw_msixtbl = NULL; 1548 kfree(rf->hmc_info_mem); 1549 rf->hmc_info_mem = NULL; 1550 } 1551 1552 /** 1553 * irdma_initialize_dev - initialize device 1554 * @rf: RDMA PCI function 1555 * 1556 * Allocate memory for the hmc objects and initialize iwdev 1557 * Return 0 if successful, otherwise clean up the resources 1558 * and return error 1559 */ 1560 static enum irdma_status_code irdma_initialize_dev(struct irdma_pci_f *rf) 1561 { 1562 enum irdma_status_code status; 1563 struct irdma_sc_dev *dev = &rf->sc_dev; 1564 struct irdma_device_init_info info = {}; 1565 struct irdma_dma_mem mem; 1566 u32 size; 1567 1568 size = sizeof(struct irdma_hmc_pble_rsrc) + 1569 sizeof(struct irdma_hmc_info) + 1570 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1571 1572 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1573 if (!rf->hmc_info_mem) 1574 return IRDMA_ERR_NO_MEMORY; 1575 1576 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1577 dev->hmc_info = &rf->hw.hmc; 1578 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1579 (rf->pble_rsrc + 1); 1580 1581 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1582 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1583 if (status) 1584 goto error; 1585 1586 info.fpm_query_buf_pa = mem.pa; 1587 info.fpm_query_buf = mem.va; 1588 1589 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1590 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1591 if (status) 1592 goto error; 1593 1594 info.fpm_commit_buf_pa = mem.pa; 1595 info.fpm_commit_buf = mem.va; 1596 1597 info.bar0 = rf->hw.hw_addr; 1598 info.hmc_fn_id = PCI_FUNC(rf->pcidev->devfn); 1599 info.hw = &rf->hw; 1600 status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info); 1601 if (status) 1602 goto error; 1603 1604 return status; 1605 error: 1606 kfree(rf->hmc_info_mem); 1607 rf->hmc_info_mem = NULL; 1608 1609 return status; 1610 } 1611 1612 /** 1613 * irdma_rt_deinit_hw - clean up the irdma device resources 1614 * @iwdev: irdma device 1615 * 1616 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1617 * device queues and free the pble and the hmc objects 1618 */ 1619 void irdma_rt_deinit_hw(struct irdma_device *iwdev) 1620 { 1621 ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state); 1622 1623 switch (iwdev->init_state) { 1624 case IP_ADDR_REGISTERED: 1625 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1626 irdma_del_local_mac_entry(iwdev->rf, 1627 (u8)iwdev->mac_ip_table_idx); 1628 fallthrough; 1629 case AEQ_CREATED: 1630 case PBLE_CHUNK_MEM: 1631 case CEQS_CREATED: 1632 case IEQ_CREATED: 1633 if (!iwdev->roce_mode) 1634 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1635 iwdev->reset); 1636 fallthrough; 1637 case ILQ_CREATED: 1638 if (!iwdev->roce_mode) 1639 irdma_puda_dele_rsrc(&iwdev->vsi, 1640 IRDMA_PUDA_RSRC_TYPE_ILQ, 1641 iwdev->reset); 1642 break; 1643 default: 1644 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); 1645 break; 1646 } 1647 1648 irdma_cleanup_cm_core(&iwdev->cm_core); 1649 if (iwdev->vsi.pestat) { 1650 irdma_vsi_stats_free(&iwdev->vsi); 1651 kfree(iwdev->vsi.pestat); 1652 } 1653 if (iwdev->cleanup_wq) 1654 destroy_workqueue(iwdev->cleanup_wq); 1655 } 1656 1657 static enum irdma_status_code irdma_setup_init_state(struct irdma_pci_f *rf) 1658 { 1659 enum irdma_status_code status; 1660 1661 status = irdma_save_msix_info(rf); 1662 if (status) 1663 return status; 1664 1665 rf->hw.device = &rf->pcidev->dev; 1666 rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE); 1667 rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size, 1668 &rf->obj_mem.pa, GFP_KERNEL); 1669 if (!rf->obj_mem.va) { 1670 status = IRDMA_ERR_NO_MEMORY; 1671 goto clean_msixtbl; 1672 } 1673 1674 rf->obj_next = rf->obj_mem; 1675 status = irdma_initialize_dev(rf); 1676 if (status) 1677 goto clean_obj_mem; 1678 1679 return 0; 1680 1681 clean_obj_mem: 1682 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1683 rf->obj_mem.pa); 1684 rf->obj_mem.va = NULL; 1685 clean_msixtbl: 1686 kfree(rf->iw_msixtbl); 1687 rf->iw_msixtbl = NULL; 1688 return status; 1689 } 1690 1691 /** 1692 * irdma_get_used_rsrc - determine resources used internally 1693 * @iwdev: irdma device 1694 * 1695 * Called at the end of open to get all internal allocations 1696 */ 1697 static void irdma_get_used_rsrc(struct irdma_device *iwdev) 1698 { 1699 iwdev->rf->used_pds = find_next_zero_bit(iwdev->rf->allocated_pds, 1700 iwdev->rf->max_pd, 0); 1701 iwdev->rf->used_qps = find_next_zero_bit(iwdev->rf->allocated_qps, 1702 iwdev->rf->max_qp, 0); 1703 iwdev->rf->used_cqs = find_next_zero_bit(iwdev->rf->allocated_cqs, 1704 iwdev->rf->max_cq, 0); 1705 iwdev->rf->used_mrs = find_next_zero_bit(iwdev->rf->allocated_mrs, 1706 iwdev->rf->max_mr, 0); 1707 } 1708 1709 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1710 { 1711 enum init_completion_state state = rf->init_state; 1712 1713 rf->init_state = INVALID_STATE; 1714 if (rf->rsrc_created) { 1715 irdma_destroy_aeq(rf); 1716 irdma_destroy_pble_prm(rf->pble_rsrc); 1717 irdma_del_ceqs(rf); 1718 rf->rsrc_created = false; 1719 } 1720 switch (state) { 1721 case CEQ0_CREATED: 1722 irdma_del_ceq_0(rf); 1723 fallthrough; 1724 case CCQ_CREATED: 1725 irdma_destroy_ccq(rf); 1726 fallthrough; 1727 case HW_RSRC_INITIALIZED: 1728 case HMC_OBJS_CREATED: 1729 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1730 rf->reset, rf->rdma_ver); 1731 fallthrough; 1732 case CQP_CREATED: 1733 irdma_destroy_cqp(rf, true); 1734 fallthrough; 1735 case INITIAL_STATE: 1736 irdma_del_init_mem(rf); 1737 break; 1738 case INVALID_STATE: 1739 default: 1740 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); 1741 break; 1742 } 1743 } 1744 1745 /** 1746 * irdma_rt_init_hw - Initializes runtime portion of HW 1747 * @iwdev: irdma device 1748 * @l2params: qos, tc, mtu info from netdev driver 1749 * 1750 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1751 * device resource objects. 1752 */ 1753 enum irdma_status_code irdma_rt_init_hw(struct irdma_device *iwdev, 1754 struct irdma_l2params *l2params) 1755 { 1756 struct irdma_pci_f *rf = iwdev->rf; 1757 struct irdma_sc_dev *dev = &rf->sc_dev; 1758 enum irdma_status_code status; 1759 struct irdma_vsi_init_info vsi_info = {}; 1760 struct irdma_vsi_stats_info stats_info = {}; 1761 1762 vsi_info.dev = dev; 1763 vsi_info.back_vsi = iwdev; 1764 vsi_info.params = l2params; 1765 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1766 vsi_info.register_qset = rf->gen_ops.register_qset; 1767 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1768 vsi_info.exception_lan_q = 2; 1769 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1770 1771 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1772 if (status) 1773 return status; 1774 1775 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1776 if (!stats_info.pestat) { 1777 irdma_cleanup_cm_core(&iwdev->cm_core); 1778 return IRDMA_ERR_NO_MEMORY; 1779 } 1780 stats_info.fcn_id = dev->hmc_fn_id; 1781 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1782 if (status) { 1783 irdma_cleanup_cm_core(&iwdev->cm_core); 1784 kfree(stats_info.pestat); 1785 return status; 1786 } 1787 1788 do { 1789 if (!iwdev->roce_mode) { 1790 status = irdma_initialize_ilq(iwdev); 1791 if (status) 1792 break; 1793 iwdev->init_state = ILQ_CREATED; 1794 status = irdma_initialize_ieq(iwdev); 1795 if (status) 1796 break; 1797 iwdev->init_state = IEQ_CREATED; 1798 } 1799 if (!rf->rsrc_created) { 1800 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1801 if (status) 1802 break; 1803 1804 iwdev->init_state = CEQS_CREATED; 1805 1806 status = irdma_hmc_init_pble(&rf->sc_dev, 1807 rf->pble_rsrc); 1808 if (status) { 1809 irdma_del_ceqs(rf); 1810 break; 1811 } 1812 1813 iwdev->init_state = PBLE_CHUNK_MEM; 1814 1815 status = irdma_setup_aeq(rf); 1816 if (status) { 1817 irdma_destroy_pble_prm(rf->pble_rsrc); 1818 irdma_del_ceqs(rf); 1819 break; 1820 } 1821 iwdev->init_state = AEQ_CREATED; 1822 rf->rsrc_created = true; 1823 } 1824 1825 iwdev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY | 1826 IB_DEVICE_MEM_WINDOW | 1827 IB_DEVICE_MEM_MGT_EXTENSIONS; 1828 1829 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1830 irdma_alloc_set_mac(iwdev); 1831 irdma_add_ip(iwdev); 1832 iwdev->init_state = IP_ADDR_REGISTERED; 1833 1834 /* handles asynch cleanup tasks - disconnect CM , free qp, 1835 * free cq bufs 1836 */ 1837 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1838 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1839 if (!iwdev->cleanup_wq) 1840 return IRDMA_ERR_NO_MEMORY; 1841 irdma_get_used_rsrc(iwdev); 1842 init_waitqueue_head(&iwdev->suspend_wq); 1843 1844 return 0; 1845 } while (0); 1846 1847 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", 1848 status, iwdev->init_state); 1849 irdma_rt_deinit_hw(iwdev); 1850 1851 return status; 1852 } 1853 1854 /** 1855 * irdma_ctrl_init_hw - Initializes control portion of HW 1856 * @rf: RDMA PCI function 1857 * 1858 * Create admin queues, HMC obejcts and RF resource objects 1859 */ 1860 enum irdma_status_code irdma_ctrl_init_hw(struct irdma_pci_f *rf) 1861 { 1862 struct irdma_sc_dev *dev = &rf->sc_dev; 1863 enum irdma_status_code status; 1864 do { 1865 status = irdma_setup_init_state(rf); 1866 if (status) 1867 break; 1868 rf->init_state = INITIAL_STATE; 1869 1870 status = irdma_create_cqp(rf); 1871 if (status) 1872 break; 1873 rf->init_state = CQP_CREATED; 1874 1875 status = irdma_hmc_setup(rf); 1876 if (status) 1877 break; 1878 rf->init_state = HMC_OBJS_CREATED; 1879 1880 status = irdma_initialize_hw_rsrc(rf); 1881 if (status) 1882 break; 1883 rf->init_state = HW_RSRC_INITIALIZED; 1884 1885 status = irdma_create_ccq(rf); 1886 if (status) 1887 break; 1888 rf->init_state = CCQ_CREATED; 1889 1890 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 1891 if (rf->rdma_ver != IRDMA_GEN_1) { 1892 status = irdma_get_rdma_features(dev); 1893 if (status) 1894 break; 1895 } 1896 1897 status = irdma_setup_ceq_0(rf); 1898 if (status) 1899 break; 1900 rf->init_state = CEQ0_CREATED; 1901 /* Handles processing of CQP completions */ 1902 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq", 1903 WQ_HIGHPRI | WQ_UNBOUND); 1904 if (!rf->cqp_cmpl_wq) { 1905 status = IRDMA_ERR_NO_MEMORY; 1906 break; 1907 } 1908 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 1909 irdma_sc_ccq_arm(dev->ccq); 1910 return 0; 1911 } while (0); 1912 1913 dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n", 1914 rf->init_state, status); 1915 irdma_ctrl_deinit_hw(rf); 1916 return status; 1917 } 1918 1919 /** 1920 * irdma_set_hw_rsrc - set hw memory resources. 1921 * @rf: RDMA PCI function 1922 */ 1923 static u32 irdma_set_hw_rsrc(struct irdma_pci_f *rf) 1924 { 1925 rf->allocated_qps = (void *)(rf->mem_rsrc + 1926 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 1927 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 1928 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 1929 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 1930 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 1931 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 1932 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 1933 rf->qp_table = (struct irdma_qp **) 1934 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 1935 1936 spin_lock_init(&rf->rsrc_lock); 1937 spin_lock_init(&rf->arp_lock); 1938 spin_lock_init(&rf->qptable_lock); 1939 spin_lock_init(&rf->qh_list_lock); 1940 1941 return 0; 1942 } 1943 1944 /** 1945 * irdma_calc_mem_rsrc_size - calculate memory resources size. 1946 * @rf: RDMA PCI function 1947 */ 1948 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf) 1949 { 1950 u32 rsrc_size; 1951 1952 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 1953 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 1954 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 1955 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 1956 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 1957 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 1958 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 1959 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 1960 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 1961 1962 return rsrc_size; 1963 } 1964 1965 /** 1966 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 1967 * @rf: RDMA PCI function 1968 */ 1969 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 1970 { 1971 u32 rsrc_size; 1972 u32 mrdrvbits; 1973 u32 ret; 1974 1975 if (rf->rdma_ver != IRDMA_GEN_1) { 1976 rf->allocated_ws_nodes = 1977 kcalloc(BITS_TO_LONGS(IRDMA_MAX_WS_NODES), 1978 sizeof(unsigned long), GFP_KERNEL); 1979 if (!rf->allocated_ws_nodes) 1980 return -ENOMEM; 1981 1982 set_bit(0, rf->allocated_ws_nodes); 1983 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 1984 } 1985 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 1986 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 1987 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 1988 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1989 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 1990 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 1991 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 1992 rf->max_mcg = rf->max_qp; 1993 1994 rsrc_size = irdma_calc_mem_rsrc_size(rf); 1995 rf->mem_rsrc = kzalloc(rsrc_size, GFP_KERNEL); 1996 if (!rf->mem_rsrc) { 1997 ret = -ENOMEM; 1998 goto mem_rsrc_kzalloc_fail; 1999 } 2000 2001 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 2002 2003 ret = irdma_set_hw_rsrc(rf); 2004 if (ret) 2005 goto set_hw_rsrc_fail; 2006 2007 set_bit(0, rf->allocated_mrs); 2008 set_bit(0, rf->allocated_qps); 2009 set_bit(0, rf->allocated_cqs); 2010 set_bit(0, rf->allocated_pds); 2011 set_bit(0, rf->allocated_arps); 2012 set_bit(0, rf->allocated_ahs); 2013 set_bit(0, rf->allocated_mcgs); 2014 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2015 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2016 set_bit(1, rf->allocated_cqs); 2017 set_bit(1, rf->allocated_pds); 2018 set_bit(2, rf->allocated_cqs); 2019 set_bit(2, rf->allocated_pds); 2020 2021 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2022 /* stag index mask has a minimum of 14 bits */ 2023 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2024 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2025 2026 return 0; 2027 2028 set_hw_rsrc_fail: 2029 kfree(rf->mem_rsrc); 2030 rf->mem_rsrc = NULL; 2031 mem_rsrc_kzalloc_fail: 2032 kfree(rf->allocated_ws_nodes); 2033 rf->allocated_ws_nodes = NULL; 2034 2035 return ret; 2036 } 2037 2038 /** 2039 * irdma_cqp_ce_handler - handle cqp completions 2040 * @rf: RDMA PCI function 2041 * @cq: cq for cqp completions 2042 */ 2043 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2044 { 2045 struct irdma_cqp_request *cqp_request; 2046 struct irdma_sc_dev *dev = &rf->sc_dev; 2047 u32 cqe_count = 0; 2048 struct irdma_ccq_cqe_info info; 2049 unsigned long flags; 2050 int ret; 2051 2052 do { 2053 memset(&info, 0, sizeof(info)); 2054 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2055 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2056 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2057 if (ret) 2058 break; 2059 2060 cqp_request = (struct irdma_cqp_request *) 2061 (unsigned long)info.scratch; 2062 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2063 info.maj_err_code, 2064 info.min_err_code)) 2065 ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2066 info.op_code, info.maj_err_code, info.min_err_code); 2067 if (cqp_request) { 2068 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2069 cqp_request->compl_info.min_err_code = info.min_err_code; 2070 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2071 cqp_request->compl_info.error = info.error; 2072 2073 if (cqp_request->waiting) { 2074 cqp_request->request_done = true; 2075 wake_up(&cqp_request->waitq); 2076 irdma_put_cqp_request(&rf->cqp, cqp_request); 2077 } else { 2078 if (cqp_request->callback_fcn) 2079 cqp_request->callback_fcn(cqp_request); 2080 irdma_put_cqp_request(&rf->cqp, cqp_request); 2081 } 2082 } 2083 2084 cqe_count++; 2085 } while (1); 2086 2087 if (cqe_count) { 2088 irdma_process_bh(dev); 2089 irdma_sc_ccq_arm(cq); 2090 } 2091 } 2092 2093 /** 2094 * cqp_compl_worker - Handle cqp completions 2095 * @work: Pointer to work structure 2096 */ 2097 void cqp_compl_worker(struct work_struct *work) 2098 { 2099 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2100 cqp_cmpl_work); 2101 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2102 2103 irdma_cqp_ce_handler(rf, cq); 2104 } 2105 2106 /** 2107 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2108 * @cm_core: cm's core 2109 * @port: port to identify apbvt entry 2110 */ 2111 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2112 u16 port) 2113 { 2114 struct irdma_apbvt_entry *entry; 2115 2116 hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2117 if (entry->port == port) { 2118 entry->use_cnt++; 2119 return entry; 2120 } 2121 } 2122 2123 return NULL; 2124 } 2125 2126 /** 2127 * irdma_next_iw_state - modify qp state 2128 * @iwqp: iwarp qp to modify 2129 * @state: next state for qp 2130 * @del_hash: del hash 2131 * @term: term message 2132 * @termlen: length of term message 2133 */ 2134 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2135 u8 termlen) 2136 { 2137 struct irdma_modify_qp_info info = {}; 2138 2139 info.next_iwarp_state = state; 2140 info.remove_hash_idx = del_hash; 2141 info.cq_num_valid = true; 2142 info.arp_cache_idx_valid = true; 2143 info.dont_send_term = true; 2144 info.dont_send_fin = true; 2145 info.termlen = termlen; 2146 2147 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2148 info.dont_send_term = false; 2149 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2150 info.dont_send_fin = false; 2151 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2152 info.reset_tcp_conn = true; 2153 iwqp->hw_iwarp_state = state; 2154 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2155 iwqp->iwarp_state = info.next_iwarp_state; 2156 } 2157 2158 /** 2159 * irdma_del_local_mac_entry - remove a mac entry from the hw 2160 * table 2161 * @rf: RDMA PCI function 2162 * @idx: the index of the mac ip address to delete 2163 */ 2164 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2165 { 2166 struct irdma_cqp *iwcqp = &rf->cqp; 2167 struct irdma_cqp_request *cqp_request; 2168 struct cqp_cmds_info *cqp_info; 2169 2170 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2171 if (!cqp_request) 2172 return; 2173 2174 cqp_info = &cqp_request->info; 2175 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2176 cqp_info->post_sq = 1; 2177 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2178 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2179 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2180 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2181 2182 irdma_handle_cqp_op(rf, cqp_request); 2183 irdma_put_cqp_request(iwcqp, cqp_request); 2184 } 2185 2186 /** 2187 * irdma_add_local_mac_entry - add a mac ip address entry to the 2188 * hw table 2189 * @rf: RDMA PCI function 2190 * @mac_addr: pointer to mac address 2191 * @idx: the index of the mac ip address to add 2192 */ 2193 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, u8 *mac_addr, u16 idx) 2194 { 2195 struct irdma_local_mac_entry_info *info; 2196 struct irdma_cqp *iwcqp = &rf->cqp; 2197 struct irdma_cqp_request *cqp_request; 2198 struct cqp_cmds_info *cqp_info; 2199 enum irdma_status_code status; 2200 2201 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2202 if (!cqp_request) 2203 return IRDMA_ERR_NO_MEMORY; 2204 2205 cqp_info = &cqp_request->info; 2206 cqp_info->post_sq = 1; 2207 info = &cqp_info->in.u.add_local_mac_entry.info; 2208 ether_addr_copy(info->mac_addr, mac_addr); 2209 info->entry_idx = idx; 2210 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2211 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2212 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2213 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2214 2215 status = irdma_handle_cqp_op(rf, cqp_request); 2216 irdma_put_cqp_request(iwcqp, cqp_request); 2217 2218 return status; 2219 } 2220 2221 /** 2222 * irdma_alloc_local_mac_entry - allocate a mac entry 2223 * @rf: RDMA PCI function 2224 * @mac_tbl_idx: the index of the new mac address 2225 * 2226 * Allocate a mac address entry and update the mac_tbl_idx 2227 * to hold the index of the newly created mac address 2228 * Return 0 if successful, otherwise return error 2229 */ 2230 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2231 { 2232 struct irdma_cqp *iwcqp = &rf->cqp; 2233 struct irdma_cqp_request *cqp_request; 2234 struct cqp_cmds_info *cqp_info; 2235 enum irdma_status_code status = 0; 2236 2237 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2238 if (!cqp_request) 2239 return IRDMA_ERR_NO_MEMORY; 2240 2241 cqp_info = &cqp_request->info; 2242 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2243 cqp_info->post_sq = 1; 2244 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2245 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2246 status = irdma_handle_cqp_op(rf, cqp_request); 2247 if (!status) 2248 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2249 2250 irdma_put_cqp_request(iwcqp, cqp_request); 2251 2252 return status; 2253 } 2254 2255 /** 2256 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2257 * @iwdev: irdma device 2258 * @accel_local_port: port for apbvt 2259 * @add_port: add ordelete port 2260 */ 2261 static enum irdma_status_code 2262 irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, u16 accel_local_port, 2263 bool add_port) 2264 { 2265 struct irdma_apbvt_info *info; 2266 struct irdma_cqp_request *cqp_request; 2267 struct cqp_cmds_info *cqp_info; 2268 enum irdma_status_code status; 2269 2270 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2271 if (!cqp_request) 2272 return IRDMA_ERR_NO_MEMORY; 2273 2274 cqp_info = &cqp_request->info; 2275 info = &cqp_info->in.u.manage_apbvt_entry.info; 2276 memset(info, 0, sizeof(*info)); 2277 info->add = add_port; 2278 info->port = accel_local_port; 2279 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2280 cqp_info->post_sq = 1; 2281 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2282 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2283 ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n", 2284 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2285 2286 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2287 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2288 2289 return status; 2290 } 2291 2292 /** 2293 * irdma_add_apbvt - add tcp port to HW apbvt table 2294 * @iwdev: irdma device 2295 * @port: port for apbvt 2296 */ 2297 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2298 { 2299 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2300 struct irdma_apbvt_entry *entry; 2301 unsigned long flags; 2302 2303 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2304 entry = irdma_lookup_apbvt_entry(cm_core, port); 2305 if (entry) { 2306 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2307 return entry; 2308 } 2309 2310 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2311 if (!entry) { 2312 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2313 return NULL; 2314 } 2315 2316 entry->port = port; 2317 entry->use_cnt = 1; 2318 hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2319 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2320 2321 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2322 kfree(entry); 2323 return NULL; 2324 } 2325 2326 return entry; 2327 } 2328 2329 /** 2330 * irdma_del_apbvt - delete tcp port from HW apbvt table 2331 * @iwdev: irdma device 2332 * @entry: apbvt entry object 2333 */ 2334 void irdma_del_apbvt(struct irdma_device *iwdev, 2335 struct irdma_apbvt_entry *entry) 2336 { 2337 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2338 unsigned long flags; 2339 2340 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2341 if (--entry->use_cnt) { 2342 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2343 return; 2344 } 2345 2346 hash_del(&entry->hlist); 2347 /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to 2348 * protect against race where add APBVT CQP can race ahead of the delete 2349 * APBVT for same port. 2350 */ 2351 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2352 kfree(entry); 2353 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2354 } 2355 2356 /** 2357 * irdma_manage_arp_cache - manage hw arp cache 2358 * @rf: RDMA PCI function 2359 * @mac_addr: mac address ptr 2360 * @ip_addr: ip addr for arp cache 2361 * @ipv4: flag inicating IPv4 2362 * @action: add, delete or modify 2363 */ 2364 void irdma_manage_arp_cache(struct irdma_pci_f *rf, unsigned char *mac_addr, 2365 u32 *ip_addr, bool ipv4, u32 action) 2366 { 2367 struct irdma_add_arp_cache_entry_info *info; 2368 struct irdma_cqp_request *cqp_request; 2369 struct cqp_cmds_info *cqp_info; 2370 int arp_index; 2371 2372 arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action); 2373 if (arp_index == -1) 2374 return; 2375 2376 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2377 if (!cqp_request) 2378 return; 2379 2380 cqp_info = &cqp_request->info; 2381 if (action == IRDMA_ARP_ADD) { 2382 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2383 info = &cqp_info->in.u.add_arp_cache_entry.info; 2384 memset(info, 0, sizeof(*info)); 2385 info->arp_index = (u16)arp_index; 2386 info->permanent = true; 2387 ether_addr_copy(info->mac_addr, mac_addr); 2388 cqp_info->in.u.add_arp_cache_entry.scratch = 2389 (uintptr_t)cqp_request; 2390 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2391 } else { 2392 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2393 cqp_info->in.u.del_arp_cache_entry.scratch = 2394 (uintptr_t)cqp_request; 2395 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2396 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2397 } 2398 2399 cqp_info->post_sq = 1; 2400 irdma_handle_cqp_op(rf, cqp_request); 2401 irdma_put_cqp_request(&rf->cqp, cqp_request); 2402 } 2403 2404 /** 2405 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2406 * @cqp_request: qhash cqp completion 2407 */ 2408 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2409 { 2410 struct irdma_cm_node *cm_node = cqp_request->param; 2411 2412 irdma_send_syn(cm_node, 1); 2413 irdma_rem_ref_cm_node(cm_node); 2414 } 2415 2416 /** 2417 * irdma_manage_qhash - add or modify qhash 2418 * @iwdev: irdma device 2419 * @cminfo: cm info for qhash 2420 * @etype: type (syn or quad) 2421 * @mtype: type of qhash 2422 * @cmnode: cmnode associated with connection 2423 * @wait: wait for completion 2424 */ 2425 enum irdma_status_code 2426 irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2427 enum irdma_quad_entry_type etype, 2428 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2429 bool wait) 2430 { 2431 struct irdma_qhash_table_info *info; 2432 enum irdma_status_code status; 2433 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2434 struct irdma_cqp_request *cqp_request; 2435 struct cqp_cmds_info *cqp_info; 2436 struct irdma_cm_node *cm_node = cmnode; 2437 2438 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2439 if (!cqp_request) 2440 return IRDMA_ERR_NO_MEMORY; 2441 2442 cqp_info = &cqp_request->info; 2443 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2444 memset(info, 0, sizeof(*info)); 2445 info->vsi = &iwdev->vsi; 2446 info->manage = mtype; 2447 info->entry_type = etype; 2448 if (cminfo->vlan_id < VLAN_N_VID) { 2449 info->vlan_valid = true; 2450 info->vlan_id = cminfo->vlan_id; 2451 } else { 2452 info->vlan_valid = false; 2453 } 2454 info->ipv4_valid = cminfo->ipv4; 2455 info->user_pri = cminfo->user_pri; 2456 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr); 2457 info->qp_num = cminfo->qh_qpid; 2458 info->dest_port = cminfo->loc_port; 2459 info->dest_ip[0] = cminfo->loc_addr[0]; 2460 info->dest_ip[1] = cminfo->loc_addr[1]; 2461 info->dest_ip[2] = cminfo->loc_addr[2]; 2462 info->dest_ip[3] = cminfo->loc_addr[3]; 2463 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2464 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2465 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2466 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2467 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2468 info->src_port = cminfo->rem_port; 2469 info->src_ip[0] = cminfo->rem_addr[0]; 2470 info->src_ip[1] = cminfo->rem_addr[1]; 2471 info->src_ip[2] = cminfo->rem_addr[2]; 2472 info->src_ip[3] = cminfo->rem_addr[3]; 2473 } 2474 if (cmnode) { 2475 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2476 cqp_request->param = cmnode; 2477 if (!wait) 2478 refcount_inc(&cm_node->refcnt); 2479 } 2480 if (info->ipv4_valid) 2481 ibdev_dbg(&iwdev->ibdev, 2482 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2483 (!mtype) ? "DELETE" : "ADD", 2484 __builtin_return_address(0), info->dest_port, 2485 info->src_port, info->dest_ip, info->src_ip, 2486 info->mac_addr, cminfo->vlan_id, 2487 cmnode ? cmnode : NULL); 2488 else 2489 ibdev_dbg(&iwdev->ibdev, 2490 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2491 (!mtype) ? "DELETE" : "ADD", 2492 __builtin_return_address(0), info->dest_port, 2493 info->src_port, info->dest_ip, info->src_ip, 2494 info->mac_addr, cminfo->vlan_id, 2495 cmnode ? cmnode : NULL); 2496 2497 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2498 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2499 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2500 cqp_info->post_sq = 1; 2501 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2502 if (status && cm_node && !wait) 2503 irdma_rem_ref_cm_node(cm_node); 2504 2505 irdma_put_cqp_request(iwcqp, cqp_request); 2506 2507 return status; 2508 } 2509 2510 /** 2511 * irdma_hw_flush_wqes_callback - Check return code after flush 2512 * @cqp_request: qhash cqp completion 2513 */ 2514 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request) 2515 { 2516 struct irdma_qp_flush_info *hw_info; 2517 struct irdma_sc_qp *qp; 2518 struct irdma_qp *iwqp; 2519 struct cqp_cmds_info *cqp_info; 2520 2521 cqp_info = &cqp_request->info; 2522 hw_info = &cqp_info->in.u.qp_flush_wqes.info; 2523 qp = cqp_info->in.u.qp_flush_wqes.qp; 2524 iwqp = qp->qp_uk.back_qp; 2525 2526 if (cqp_request->compl_info.maj_err_code) 2527 return; 2528 2529 if (hw_info->rq && 2530 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2531 cqp_request->compl_info.min_err_code == 0)) { 2532 /* RQ WQE flush was requested but did not happen */ 2533 qp->qp_uk.rq_flush_complete = true; 2534 } 2535 if (hw_info->sq && 2536 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2537 cqp_request->compl_info.min_err_code == 0)) { 2538 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2539 ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work", 2540 qp->qp_uk.qp_id); 2541 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2542 } 2543 qp->qp_uk.sq_flush_complete = true; 2544 } 2545 } 2546 2547 /** 2548 * irdma_hw_flush_wqes - flush qp's wqe 2549 * @rf: RDMA PCI function 2550 * @qp: hardware control qp 2551 * @info: info for flush 2552 * @wait: flag wait for completion 2553 */ 2554 enum irdma_status_code irdma_hw_flush_wqes(struct irdma_pci_f *rf, 2555 struct irdma_sc_qp *qp, 2556 struct irdma_qp_flush_info *info, 2557 bool wait) 2558 { 2559 enum irdma_status_code status; 2560 struct irdma_qp_flush_info *hw_info; 2561 struct irdma_cqp_request *cqp_request; 2562 struct cqp_cmds_info *cqp_info; 2563 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2564 2565 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2566 if (!cqp_request) 2567 return IRDMA_ERR_NO_MEMORY; 2568 2569 cqp_info = &cqp_request->info; 2570 if (!wait) 2571 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback; 2572 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2573 memcpy(hw_info, info, sizeof(*hw_info)); 2574 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2575 cqp_info->post_sq = 1; 2576 cqp_info->in.u.qp_flush_wqes.qp = qp; 2577 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2578 status = irdma_handle_cqp_op(rf, cqp_request); 2579 if (status) { 2580 qp->qp_uk.sq_flush_complete = true; 2581 qp->qp_uk.rq_flush_complete = true; 2582 irdma_put_cqp_request(&rf->cqp, cqp_request); 2583 return status; 2584 } 2585 2586 if (!wait || cqp_request->compl_info.maj_err_code) 2587 goto put_cqp; 2588 2589 if (info->rq) { 2590 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2591 cqp_request->compl_info.min_err_code == 0) { 2592 /* RQ WQE flush was requested but did not happen */ 2593 qp->qp_uk.rq_flush_complete = true; 2594 } 2595 } 2596 if (info->sq) { 2597 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2598 cqp_request->compl_info.min_err_code == 0) { 2599 /* 2600 * Handling case where WQE is posted to empty SQ when 2601 * flush has not completed 2602 */ 2603 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2604 struct irdma_cqp_request *new_req; 2605 2606 if (!qp->qp_uk.sq_flush_complete) 2607 goto put_cqp; 2608 qp->qp_uk.sq_flush_complete = false; 2609 qp->flush_sq = false; 2610 2611 info->rq = false; 2612 info->sq = true; 2613 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 2614 if (!new_req) { 2615 status = IRDMA_ERR_NO_MEMORY; 2616 goto put_cqp; 2617 } 2618 cqp_info = &new_req->info; 2619 hw_info = &new_req->info.in.u.qp_flush_wqes.info; 2620 memcpy(hw_info, info, sizeof(*hw_info)); 2621 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2622 cqp_info->post_sq = 1; 2623 cqp_info->in.u.qp_flush_wqes.qp = qp; 2624 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req; 2625 2626 status = irdma_handle_cqp_op(rf, new_req); 2627 if (new_req->compl_info.maj_err_code || 2628 new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2629 status) { 2630 ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d", 2631 iwqp->ibqp.qp_num); 2632 qp->qp_uk.sq_flush_complete = false; 2633 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2634 } 2635 irdma_put_cqp_request(&rf->cqp, new_req); 2636 } else { 2637 /* SQ WQE flush was requested but did not happen */ 2638 qp->qp_uk.sq_flush_complete = true; 2639 } 2640 } else { 2641 if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) 2642 qp->qp_uk.sq_flush_complete = true; 2643 } 2644 } 2645 2646 ibdev_dbg(&rf->iwdev->ibdev, 2647 "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2648 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2649 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2650 cqp_request->compl_info.maj_err_code, 2651 cqp_request->compl_info.min_err_code); 2652 put_cqp: 2653 irdma_put_cqp_request(&rf->cqp, cqp_request); 2654 2655 return status; 2656 } 2657 2658 /** 2659 * irdma_gen_ae - generate AE 2660 * @rf: RDMA PCI function 2661 * @qp: qp associated with AE 2662 * @info: info for ae 2663 * @wait: wait for completion 2664 */ 2665 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2666 struct irdma_gen_ae_info *info, bool wait) 2667 { 2668 struct irdma_gen_ae_info *ae_info; 2669 struct irdma_cqp_request *cqp_request; 2670 struct cqp_cmds_info *cqp_info; 2671 2672 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2673 if (!cqp_request) 2674 return; 2675 2676 cqp_info = &cqp_request->info; 2677 ae_info = &cqp_request->info.in.u.gen_ae.info; 2678 memcpy(ae_info, info, sizeof(*ae_info)); 2679 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2680 cqp_info->post_sq = 1; 2681 cqp_info->in.u.gen_ae.qp = qp; 2682 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2683 2684 irdma_handle_cqp_op(rf, cqp_request); 2685 irdma_put_cqp_request(&rf->cqp, cqp_request); 2686 } 2687 2688 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2689 { 2690 struct irdma_qp_flush_info info = {}; 2691 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2692 u8 flush_code = iwqp->sc_qp.flush_code; 2693 2694 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2695 return; 2696 2697 /* Set flush info fields*/ 2698 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2699 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2700 2701 if (flush_mask & IRDMA_REFLUSH) { 2702 if (info.sq) 2703 iwqp->sc_qp.flush_sq = false; 2704 if (info.rq) 2705 iwqp->sc_qp.flush_rq = false; 2706 } 2707 2708 /* Generate userflush errors in CQE */ 2709 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2710 info.sq_minor_code = FLUSH_GENERAL_ERR; 2711 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2712 info.rq_minor_code = FLUSH_GENERAL_ERR; 2713 info.userflushcode = true; 2714 if (flush_code) { 2715 if (info.sq && iwqp->sc_qp.sq_flush_code) 2716 info.sq_minor_code = flush_code; 2717 if (info.rq && iwqp->sc_qp.rq_flush_code) 2718 info.rq_minor_code = flush_code; 2719 } 2720 2721 /* Issue flush */ 2722 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2723 flush_mask & IRDMA_FLUSH_WAIT); 2724 iwqp->flush_issued = true; 2725 } 2726