1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include <linux/etherdevice.h> 4 5 #include "osdep.h" 6 #include "hmc.h" 7 #include "defs.h" 8 #include "type.h" 9 #include "ws.h" 10 #include "protos.h" 11 12 /** 13 * irdma_get_qp_from_list - get next qp from a list 14 * @head: Listhead of qp's 15 * @qp: current qp 16 */ 17 struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head, 18 struct irdma_sc_qp *qp) 19 { 20 struct list_head *lastentry; 21 struct list_head *entry = NULL; 22 23 if (list_empty(head)) 24 return NULL; 25 26 if (!qp) { 27 entry = head->next; 28 } else { 29 lastentry = &qp->list; 30 entry = lastentry->next; 31 if (entry == head) 32 return NULL; 33 } 34 35 return container_of(entry, struct irdma_sc_qp, list); 36 } 37 38 /** 39 * irdma_sc_suspend_resume_qps - suspend/resume all qp's on VSI 40 * @vsi: the VSI struct pointer 41 * @op: Set to IRDMA_OP_RESUME or IRDMA_OP_SUSPEND 42 */ 43 void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 op) 44 { 45 struct irdma_sc_qp *qp = NULL; 46 u8 i; 47 48 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 49 mutex_lock(&vsi->qos[i].qos_mutex); 50 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 51 while (qp) { 52 if (op == IRDMA_OP_RESUME) { 53 if (!qp->dev->ws_add(vsi, i)) { 54 qp->qs_handle = 55 vsi->qos[qp->user_pri].qs_handle; 56 irdma_cqp_qp_suspend_resume(qp, op); 57 } else { 58 irdma_cqp_qp_suspend_resume(qp, op); 59 irdma_modify_qp_to_err(qp); 60 } 61 } else if (op == IRDMA_OP_SUSPEND) { 62 /* issue cqp suspend command */ 63 if (!irdma_cqp_qp_suspend_resume(qp, op)) 64 atomic_inc(&vsi->qp_suspend_reqs); 65 } 66 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 67 } 68 mutex_unlock(&vsi->qos[i].qos_mutex); 69 } 70 } 71 72 static void irdma_set_qos_info(struct irdma_sc_vsi *vsi, 73 struct irdma_l2params *l2p) 74 { 75 u8 i; 76 77 if (vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 78 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 79 vsi->qos[i].qs_handle = vsi->dev->qos[i].qs_handle; 80 vsi->qos[i].valid = true; 81 } 82 83 return; 84 } 85 vsi->qos_rel_bw = l2p->vsi_rel_bw; 86 vsi->qos_prio_type = l2p->vsi_prio_type; 87 vsi->dscp_mode = l2p->dscp_mode; 88 if (l2p->dscp_mode) { 89 memcpy(vsi->dscp_map, l2p->dscp_map, sizeof(vsi->dscp_map)); 90 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) 91 l2p->up2tc[i] = i; 92 } 93 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 94 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 95 vsi->qos[i].qs_handle = l2p->qs_handle_list[i]; 96 vsi->qos[i].traffic_class = l2p->up2tc[i]; 97 vsi->qos[i].rel_bw = 98 l2p->tc_info[vsi->qos[i].traffic_class].rel_bw; 99 vsi->qos[i].prio_type = 100 l2p->tc_info[vsi->qos[i].traffic_class].prio_type; 101 vsi->qos[i].valid = false; 102 } 103 } 104 105 /** 106 * irdma_change_l2params - given the new l2 parameters, change all qp 107 * @vsi: RDMA VSI pointer 108 * @l2params: New parameters from l2 109 */ 110 void irdma_change_l2params(struct irdma_sc_vsi *vsi, 111 struct irdma_l2params *l2params) 112 { 113 if (l2params->mtu_changed) { 114 vsi->mtu = l2params->mtu; 115 if (vsi->ieq) 116 irdma_reinitialize_ieq(vsi); 117 } 118 119 if (!l2params->tc_changed) 120 return; 121 122 vsi->tc_change_pending = false; 123 irdma_set_qos_info(vsi, l2params); 124 irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME); 125 } 126 127 /** 128 * irdma_qp_rem_qos - remove qp from qos lists during destroy qp 129 * @qp: qp to be removed from qos 130 */ 131 void irdma_qp_rem_qos(struct irdma_sc_qp *qp) 132 { 133 struct irdma_sc_vsi *vsi = qp->vsi; 134 135 ibdev_dbg(to_ibdev(qp->dev), 136 "DCB: DCB: Remove qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 137 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 138 qp->on_qoslist); 139 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 140 if (qp->on_qoslist) { 141 qp->on_qoslist = false; 142 list_del(&qp->list); 143 } 144 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 145 } 146 147 /** 148 * irdma_qp_add_qos - called during setctx for qp to be added to qos 149 * @qp: qp to be added to qos 150 */ 151 void irdma_qp_add_qos(struct irdma_sc_qp *qp) 152 { 153 struct irdma_sc_vsi *vsi = qp->vsi; 154 155 ibdev_dbg(to_ibdev(qp->dev), 156 "DCB: DCB: Add qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 157 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 158 qp->on_qoslist); 159 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 160 if (!qp->on_qoslist) { 161 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist); 162 qp->on_qoslist = true; 163 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle; 164 } 165 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 166 } 167 168 /** 169 * irdma_sc_pd_init - initialize sc pd struct 170 * @dev: sc device struct 171 * @pd: sc pd ptr 172 * @pd_id: pd_id for allocated pd 173 * @abi_ver: User/Kernel ABI version 174 */ 175 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, 176 int abi_ver) 177 { 178 pd->pd_id = pd_id; 179 pd->abi_ver = abi_ver; 180 pd->dev = dev; 181 } 182 183 /** 184 * irdma_sc_add_arp_cache_entry - cqp wqe add arp cache entry 185 * @cqp: struct for cqp hw 186 * @info: arp entry information 187 * @scratch: u64 saved to be used during cqp completion 188 * @post_sq: flag for cqp db to ring 189 */ 190 static int irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp, 191 struct irdma_add_arp_cache_entry_info *info, 192 u64 scratch, bool post_sq) 193 { 194 __le64 *wqe; 195 u64 hdr; 196 197 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 198 if (!wqe) 199 return -ENOMEM; 200 set_64bit_val(wqe, 8, info->reach_max); 201 set_64bit_val(wqe, 16, ether_addr_to_u64(info->mac_addr)); 202 203 hdr = info->arp_index | 204 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 205 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) | 206 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) | 207 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 208 dma_wmb(); /* make sure WQE is written before valid bit is set */ 209 210 set_64bit_val(wqe, 24, hdr); 211 212 print_hex_dump_debug("WQE: ARP_CACHE_ENTRY WQE", DUMP_PREFIX_OFFSET, 213 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 214 if (post_sq) 215 irdma_sc_cqp_post_sq(cqp); 216 217 return 0; 218 } 219 220 /** 221 * irdma_sc_del_arp_cache_entry - dele arp cache entry 222 * @cqp: struct for cqp hw 223 * @scratch: u64 saved to be used during cqp completion 224 * @arp_index: arp index to delete arp entry 225 * @post_sq: flag for cqp db to ring 226 */ 227 static int irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch, 228 u16 arp_index, bool post_sq) 229 { 230 __le64 *wqe; 231 u64 hdr; 232 233 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 234 if (!wqe) 235 return -ENOMEM; 236 237 hdr = arp_index | 238 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 239 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 240 dma_wmb(); /* make sure WQE is written before valid bit is set */ 241 242 set_64bit_val(wqe, 24, hdr); 243 244 print_hex_dump_debug("WQE: ARP_CACHE_DEL_ENTRY WQE", 245 DUMP_PREFIX_OFFSET, 16, 8, wqe, 246 IRDMA_CQP_WQE_SIZE * 8, false); 247 if (post_sq) 248 irdma_sc_cqp_post_sq(cqp); 249 250 return 0; 251 } 252 253 /** 254 * irdma_sc_manage_apbvt_entry - for adding and deleting apbvt entries 255 * @cqp: struct for cqp hw 256 * @info: info for apbvt entry to add or delete 257 * @scratch: u64 saved to be used during cqp completion 258 * @post_sq: flag for cqp db to ring 259 */ 260 static int irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp, 261 struct irdma_apbvt_info *info, 262 u64 scratch, bool post_sq) 263 { 264 __le64 *wqe; 265 u64 hdr; 266 267 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 268 if (!wqe) 269 return -ENOMEM; 270 271 set_64bit_val(wqe, 16, info->port); 272 273 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | 274 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | 275 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 276 dma_wmb(); /* make sure WQE is written before valid bit is set */ 277 278 set_64bit_val(wqe, 24, hdr); 279 280 print_hex_dump_debug("WQE: MANAGE_APBVT WQE", DUMP_PREFIX_OFFSET, 16, 281 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 282 if (post_sq) 283 irdma_sc_cqp_post_sq(cqp); 284 285 return 0; 286 } 287 288 /** 289 * irdma_sc_manage_qhash_table_entry - manage quad hash entries 290 * @cqp: struct for cqp hw 291 * @info: info for quad hash to manage 292 * @scratch: u64 saved to be used during cqp completion 293 * @post_sq: flag for cqp db to ring 294 * 295 * This is called before connection establishment is started. 296 * For passive connections, when listener is created, it will 297 * call with entry type of IRDMA_QHASH_TYPE_TCP_SYN with local 298 * ip address and tcp port. When SYN is received (passive 299 * connections) or sent (active connections), this routine is 300 * called with entry type of IRDMA_QHASH_TYPE_TCP_ESTABLISHED 301 * and quad is passed in info. 302 * 303 * When iwarp connection is done and its state moves to RTS, the 304 * quad hash entry in the hardware will point to iwarp's qp 305 * number and requires no calls from the driver. 306 */ 307 static int 308 irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp, 309 struct irdma_qhash_table_info *info, 310 u64 scratch, bool post_sq) 311 { 312 __le64 *wqe; 313 u64 qw1 = 0; 314 u64 qw2 = 0; 315 u64 temp; 316 struct irdma_sc_vsi *vsi = info->vsi; 317 318 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 319 if (!wqe) 320 return -ENOMEM; 321 322 set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr)); 323 324 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | 325 FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port); 326 if (info->ipv4_valid) { 327 set_64bit_val(wqe, 48, 328 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0])); 329 } else { 330 set_64bit_val(wqe, 56, 331 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) | 332 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1])); 333 334 set_64bit_val(wqe, 48, 335 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) | 336 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3])); 337 } 338 qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE, 339 vsi->qos[info->user_pri].qs_handle); 340 if (info->vlan_valid) 341 qw2 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id); 342 set_64bit_val(wqe, 16, qw2); 343 if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) { 344 qw1 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port); 345 if (!info->ipv4_valid) { 346 set_64bit_val(wqe, 40, 347 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) | 348 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1])); 349 set_64bit_val(wqe, 32, 350 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) | 351 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3])); 352 } else { 353 set_64bit_val(wqe, 32, 354 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0])); 355 } 356 } 357 358 set_64bit_val(wqe, 8, qw1); 359 temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) | 360 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE, 361 IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) | 362 FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) | 363 FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) | 364 FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) | 365 FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type); 366 dma_wmb(); /* make sure WQE is written before valid bit is set */ 367 368 set_64bit_val(wqe, 24, temp); 369 370 print_hex_dump_debug("WQE: MANAGE_QHASH WQE", DUMP_PREFIX_OFFSET, 16, 371 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 372 if (post_sq) 373 irdma_sc_cqp_post_sq(cqp); 374 375 return 0; 376 } 377 378 /** 379 * irdma_sc_qp_init - initialize qp 380 * @qp: sc qp 381 * @info: initialization qp info 382 */ 383 int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info) 384 { 385 int ret_code; 386 u32 pble_obj_cnt; 387 u16 wqe_size; 388 389 if (info->qp_uk_init_info.max_sq_frag_cnt > 390 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags || 391 info->qp_uk_init_info.max_rq_frag_cnt > 392 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags) 393 return -EINVAL; 394 395 qp->dev = info->pd->dev; 396 qp->vsi = info->vsi; 397 qp->ieq_qp = info->vsi->exception_lan_q; 398 qp->sq_pa = info->sq_pa; 399 qp->rq_pa = info->rq_pa; 400 qp->hw_host_ctx_pa = info->host_ctx_pa; 401 qp->q2_pa = info->q2_pa; 402 qp->shadow_area_pa = info->shadow_area_pa; 403 qp->q2_buf = info->q2; 404 qp->pd = info->pd; 405 qp->hw_host_ctx = info->host_ctx; 406 info->qp_uk_init_info.wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 407 ret_code = irdma_uk_qp_init(&qp->qp_uk, &info->qp_uk_init_info); 408 if (ret_code) 409 return ret_code; 410 411 qp->virtual_map = info->virtual_map; 412 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 413 414 if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) || 415 (!info->qp_uk_init_info.srq_uk && 416 info->virtual_map && info->rq_pa >= pble_obj_cnt)) 417 return -EINVAL; 418 419 qp->llp_stream_handle = (void *)(-1); 420 qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size, 421 IRDMA_QUEUE_TYPE_SQ_RQ); 422 ibdev_dbg(to_ibdev(qp->dev), 423 "WQE: hw_sq_size[%04d] sq_ring.size[%04d]\n", 424 qp->hw_sq_size, qp->qp_uk.sq_ring.size); 425 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1 && qp->pd->abi_ver > 4) 426 wqe_size = IRDMA_WQE_SIZE_128; 427 else 428 ret_code = irdma_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt, 429 &wqe_size); 430 if (ret_code) 431 return ret_code; 432 433 qp->hw_rq_size = irdma_get_encoded_wqe_size(qp->qp_uk.rq_size * 434 (wqe_size / IRDMA_QP_WQE_MIN_SIZE), IRDMA_QUEUE_TYPE_SQ_RQ); 435 ibdev_dbg(to_ibdev(qp->dev), 436 "WQE: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n", 437 qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size); 438 qp->sq_tph_val = info->sq_tph_val; 439 qp->rq_tph_val = info->rq_tph_val; 440 qp->sq_tph_en = info->sq_tph_en; 441 qp->rq_tph_en = info->rq_tph_en; 442 qp->rcv_tph_en = info->rcv_tph_en; 443 qp->xmit_tph_en = info->xmit_tph_en; 444 qp->qp_uk.first_sq_wq = info->qp_uk_init_info.first_sq_wq; 445 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle; 446 447 return 0; 448 } 449 450 /** 451 * irdma_sc_srq_init - init sc_srq structure 452 * @srq: srq sc struct 453 * @info: parameters for srq init 454 */ 455 int irdma_sc_srq_init(struct irdma_sc_srq *srq, 456 struct irdma_srq_init_info *info) 457 { 458 u32 srq_size_quanta; 459 int ret_code; 460 461 ret_code = irdma_uk_srq_init(&srq->srq_uk, &info->srq_uk_init_info); 462 if (ret_code) 463 return ret_code; 464 465 srq->dev = info->pd->dev; 466 srq->pd = info->pd; 467 srq->vsi = info->vsi; 468 srq->srq_pa = info->srq_pa; 469 srq->first_pm_pbl_idx = info->first_pm_pbl_idx; 470 srq->pasid = info->pasid; 471 srq->pasid_valid = info->pasid_valid; 472 srq->srq_limit = info->srq_limit; 473 srq->leaf_pbl_size = info->leaf_pbl_size; 474 srq->virtual_map = info->virtual_map; 475 srq->tph_en = info->tph_en; 476 srq->arm_limit_event = info->arm_limit_event; 477 srq->tph_val = info->tph_value; 478 srq->shadow_area_pa = info->shadow_area_pa; 479 480 /* Smallest SRQ size is 256B i.e. 8 quanta */ 481 srq_size_quanta = max((u32)IRDMA_SRQ_MIN_QUANTA, 482 srq->srq_uk.srq_size * 483 srq->srq_uk.wqe_size_multiplier); 484 srq->hw_srq_size = irdma_get_encoded_wqe_size(srq_size_quanta, 485 IRDMA_QUEUE_TYPE_SRQ); 486 487 return 0; 488 } 489 490 /** 491 * irdma_sc_srq_create - send srq create CQP WQE 492 * @srq: srq sc struct 493 * @scratch: u64 saved to be used during cqp completion 494 * @post_sq: flag for cqp db to ring 495 */ 496 static int irdma_sc_srq_create(struct irdma_sc_srq *srq, u64 scratch, 497 bool post_sq) 498 { 499 struct irdma_sc_cqp *cqp; 500 __le64 *wqe; 501 u64 hdr; 502 503 cqp = srq->pd->dev->cqp; 504 if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id || 505 srq->srq_uk.srq_id > 506 (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1)) 507 return -EINVAL; 508 509 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 510 if (!wqe) 511 return -ENOMEM; 512 513 set_64bit_val(wqe, 0, 514 FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, srq->srq_limit) | 515 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) | 516 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size)); 517 set_64bit_val(wqe, 8, (uintptr_t)srq); 518 set_64bit_val(wqe, 16, 519 FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id)); 520 set_64bit_val(wqe, 32, 521 FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR, 522 srq->srq_pa >> 523 IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S)); 524 set_64bit_val(wqe, 40, 525 FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR, 526 srq->shadow_area_pa >> 527 IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S)); 528 set_64bit_val(wqe, 48, 529 FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX, 530 srq->first_pm_pbl_idx)); 531 532 hdr = srq->srq_uk.srq_id | 533 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_SRQ) | 534 FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) | 535 FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) | 536 FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT, 537 srq->arm_limit_event) | 538 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 539 540 dma_wmb(); /* make sure WQE is written before valid bit is set */ 541 542 set_64bit_val(wqe, 24, hdr); 543 544 print_hex_dump_debug("WQE: SRQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 545 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 546 if (post_sq) 547 irdma_sc_cqp_post_sq(cqp); 548 549 return 0; 550 } 551 552 /** 553 * irdma_sc_srq_modify - send modify_srq CQP WQE 554 * @srq: srq sc struct 555 * @info: parameters for srq modification 556 * @scratch: u64 saved to be used during cqp completion 557 * @post_sq: flag for cqp db to ring 558 */ 559 static int irdma_sc_srq_modify(struct irdma_sc_srq *srq, 560 struct irdma_modify_srq_info *info, u64 scratch, 561 bool post_sq) 562 { 563 struct irdma_sc_cqp *cqp; 564 __le64 *wqe; 565 u64 hdr; 566 567 cqp = srq->dev->cqp; 568 if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id || 569 srq->srq_uk.srq_id > 570 (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1)) 571 return -EINVAL; 572 573 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 574 if (!wqe) 575 return -ENOMEM; 576 577 set_64bit_val(wqe, 0, 578 FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, info->srq_limit) | 579 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) | 580 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size)); 581 set_64bit_val(wqe, 8, 582 FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQCTX, srq->srq_uk.srq_id)); 583 set_64bit_val(wqe, 16, 584 FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id)); 585 set_64bit_val(wqe, 32, 586 FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR, 587 srq->srq_pa >> 588 IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S)); 589 set_64bit_val(wqe, 40, 590 FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR, 591 srq->shadow_area_pa >> 592 IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S)); 593 set_64bit_val(wqe, 48, 594 FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX, 595 srq->first_pm_pbl_idx)); 596 597 hdr = srq->srq_uk.srq_id | 598 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_SRQ) | 599 FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) | 600 FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) | 601 FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT, 602 info->arm_limit_event) | 603 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 604 dma_wmb(); /* make sure WQE is written before valid bit is set */ 605 606 set_64bit_val(wqe, 24, hdr); 607 608 print_hex_dump_debug("WQE: SRQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 609 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 610 if (post_sq) 611 irdma_sc_cqp_post_sq(cqp); 612 613 return 0; 614 } 615 616 /** 617 * irdma_sc_srq_destroy - send srq_destroy CQP WQE 618 * @srq: srq sc struct 619 * @scratch: u64 saved to be used during cqp completion 620 * @post_sq: flag for cqp db to ring 621 */ 622 static int irdma_sc_srq_destroy(struct irdma_sc_srq *srq, u64 scratch, 623 bool post_sq) 624 { 625 struct irdma_sc_cqp *cqp; 626 __le64 *wqe; 627 u64 hdr; 628 629 cqp = srq->dev->cqp; 630 631 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 632 if (!wqe) 633 return -ENOMEM; 634 635 set_64bit_val(wqe, 8, (uintptr_t)srq); 636 637 hdr = srq->srq_uk.srq_id | 638 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_SRQ) | 639 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 640 dma_wmb(); /* make sure WQE is written before valid bit is set */ 641 642 set_64bit_val(wqe, 24, hdr); 643 644 print_hex_dump_debug("WQE: SRQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 645 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 646 if (post_sq) 647 irdma_sc_cqp_post_sq(cqp); 648 649 return 0; 650 } 651 652 /** 653 * irdma_sc_qp_create - create qp 654 * @qp: sc qp 655 * @info: qp create info 656 * @scratch: u64 saved to be used during cqp completion 657 * @post_sq: flag for cqp db to ring 658 */ 659 int irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info, 660 u64 scratch, bool post_sq) 661 { 662 struct irdma_sc_cqp *cqp; 663 __le64 *wqe; 664 u64 hdr; 665 666 cqp = qp->dev->cqp; 667 if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id || 668 qp->qp_uk.qp_id >= cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt) 669 return -EINVAL; 670 671 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 672 if (!wqe) 673 return -ENOMEM; 674 675 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 676 set_64bit_val(wqe, 40, qp->shadow_area_pa); 677 678 hdr = qp->qp_uk.qp_id | 679 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 680 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, (info->ord_valid ? 1 : 0)) | 681 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 682 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 683 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 684 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 685 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 686 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 687 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 688 info->arp_cache_idx_valid) | 689 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 690 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 691 dma_wmb(); /* make sure WQE is written before valid bit is set */ 692 693 set_64bit_val(wqe, 24, hdr); 694 695 print_hex_dump_debug("WQE: QP_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 696 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 697 if (post_sq) 698 irdma_sc_cqp_post_sq(cqp); 699 700 return 0; 701 } 702 703 /** 704 * irdma_sc_qp_modify - modify qp cqp wqe 705 * @qp: sc qp 706 * @info: modify qp info 707 * @scratch: u64 saved to be used during cqp completion 708 * @post_sq: flag for cqp db to ring 709 */ 710 int irdma_sc_qp_modify(struct irdma_sc_qp *qp, struct irdma_modify_qp_info *info, 711 u64 scratch, bool post_sq) 712 { 713 __le64 *wqe; 714 struct irdma_sc_cqp *cqp; 715 u64 hdr; 716 u8 term_actions = 0; 717 u8 term_len = 0; 718 719 cqp = qp->dev->cqp; 720 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 721 if (!wqe) 722 return -ENOMEM; 723 724 if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) { 725 if (info->dont_send_fin) 726 term_actions += IRDMAQP_TERM_SEND_TERM_ONLY; 727 if (info->dont_send_term) 728 term_actions += IRDMAQP_TERM_SEND_FIN_ONLY; 729 if (term_actions == IRDMAQP_TERM_SEND_TERM_AND_FIN || 730 term_actions == IRDMAQP_TERM_SEND_TERM_ONLY) 731 term_len = info->termlen; 732 } 733 734 set_64bit_val(wqe, 8, 735 FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) | 736 FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len)); 737 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 738 set_64bit_val(wqe, 40, qp->shadow_area_pa); 739 740 hdr = qp->qp_uk.qp_id | 741 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) | 742 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) | 743 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 744 FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID, 745 info->cached_var_valid) | 746 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 747 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 748 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 749 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 750 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 751 FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) | 752 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, 753 info->remove_hash_idx) | 754 FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) | 755 FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) | 756 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 757 info->arp_cache_idx_valid) | 758 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 759 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 760 dma_wmb(); /* make sure WQE is written before valid bit is set */ 761 762 set_64bit_val(wqe, 24, hdr); 763 764 print_hex_dump_debug("WQE: QP_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 765 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 766 if (post_sq) 767 irdma_sc_cqp_post_sq(cqp); 768 769 return 0; 770 } 771 772 /** 773 * irdma_sc_qp_destroy - cqp destroy qp 774 * @qp: sc qp 775 * @scratch: u64 saved to be used during cqp completion 776 * @remove_hash_idx: flag if to remove hash idx 777 * @ignore_mw_bnd: memory window bind flag 778 * @post_sq: flag for cqp db to ring 779 */ 780 int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch, 781 bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq) 782 { 783 __le64 *wqe; 784 struct irdma_sc_cqp *cqp; 785 u64 hdr; 786 787 cqp = qp->dev->cqp; 788 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 789 if (!wqe) 790 return -ENOMEM; 791 792 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 793 set_64bit_val(wqe, 40, qp->shadow_area_pa); 794 795 hdr = qp->qp_uk.qp_id | 796 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) | 797 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 798 FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) | 799 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) | 800 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 801 dma_wmb(); /* make sure WQE is written before valid bit is set */ 802 803 set_64bit_val(wqe, 24, hdr); 804 805 print_hex_dump_debug("WQE: QP_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 806 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 807 if (post_sq) 808 irdma_sc_cqp_post_sq(cqp); 809 810 return 0; 811 } 812 813 /** 814 * irdma_sc_get_encoded_ird_size - 815 * @ird_size: IRD size 816 * The ird from the connection is rounded to a supported HW setting and then encoded 817 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based 818 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input 819 */ 820 static u8 irdma_sc_get_encoded_ird_size(u16 ird_size) 821 { 822 switch (ird_size ? 823 roundup_pow_of_two(2 * ird_size) : 4) { 824 case 256: 825 return IRDMA_IRD_HW_SIZE_256; 826 case 128: 827 return IRDMA_IRD_HW_SIZE_128; 828 case 64: 829 case 32: 830 return IRDMA_IRD_HW_SIZE_64; 831 case 16: 832 case 8: 833 return IRDMA_IRD_HW_SIZE_16; 834 case 4: 835 default: 836 break; 837 } 838 839 return IRDMA_IRD_HW_SIZE_4; 840 } 841 842 /** 843 * irdma_sc_qp_setctx_roce_gen_2 - set qp's context 844 * @qp: sc qp 845 * @qp_ctx: context ptr 846 * @info: ctx info 847 */ 848 static void irdma_sc_qp_setctx_roce_gen_2(struct irdma_sc_qp *qp, 849 __le64 *qp_ctx, 850 struct irdma_qp_host_ctx_info *info) 851 { 852 struct irdma_roce_offload_info *roce_info; 853 struct irdma_udp_offload_info *udp; 854 u8 push_mode_en; 855 u32 push_idx; 856 857 roce_info = info->roce_info; 858 udp = info->udp_info; 859 qp->user_pri = info->user_pri; 860 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 861 push_mode_en = 0; 862 push_idx = 0; 863 } else { 864 push_mode_en = 1; 865 push_idx = qp->push_idx; 866 } 867 set_64bit_val(qp_ctx, 0, 868 FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 869 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 870 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 871 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 872 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 873 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 874 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | 875 FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) | 876 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | 877 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) | 878 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | 879 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | 880 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | 881 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag)); 882 set_64bit_val(qp_ctx, 8, qp->sq_pa); 883 set_64bit_val(qp_ctx, 16, qp->rq_pa); 884 if ((roce_info->dcqcn_en || roce_info->dctcp_en) && 885 !(udp->tos & 0x03)) 886 udp->tos |= ECN_CODE_PT_VAL; 887 set_64bit_val(qp_ctx, 24, 888 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 889 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | 890 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) | 891 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | 892 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port)); 893 set_64bit_val(qp_ctx, 32, 894 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | 895 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); 896 set_64bit_val(qp_ctx, 40, 897 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | 898 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); 899 set_64bit_val(qp_ctx, 48, 900 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | 901 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | 902 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); 903 set_64bit_val(qp_ctx, 56, 904 FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | 905 FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) | 906 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | 907 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label)); 908 set_64bit_val(qp_ctx, 64, 909 FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | 910 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp)); 911 set_64bit_val(qp_ctx, 80, 912 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | 913 FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); 914 set_64bit_val(qp_ctx, 88, 915 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); 916 set_64bit_val(qp_ctx, 96, 917 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | 918 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); 919 set_64bit_val(qp_ctx, 112, 920 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); 921 set_64bit_val(qp_ctx, 128, 922 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) | 923 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | 924 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | 925 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); 926 set_64bit_val(qp_ctx, 136, 927 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 928 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 929 set_64bit_val(qp_ctx, 144, 930 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 931 set_64bit_val(qp_ctx, 152, ether_addr_to_u64(roce_info->mac_addr) << 16); 932 set_64bit_val(qp_ctx, 160, 933 FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) | 934 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) | 935 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | 936 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | 937 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 938 FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | 939 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | 940 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | 941 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | 942 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) | 943 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) | 944 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | 945 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); 946 set_64bit_val(qp_ctx, 168, 947 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 948 set_64bit_val(qp_ctx, 176, 949 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 950 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 951 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 952 set_64bit_val(qp_ctx, 184, 953 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | 954 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); 955 set_64bit_val(qp_ctx, 192, 956 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | 957 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); 958 set_64bit_val(qp_ctx, 200, 959 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | 960 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); 961 set_64bit_val(qp_ctx, 208, 962 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 963 964 print_hex_dump_debug("WQE: QP_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16, 965 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 966 } 967 968 /** 969 * irdma_sc_get_encoded_ird_size_gen_3 - get encoded IRD size for GEN 3 970 * @ird_size: IRD size 971 * The ird from the connection is rounded to a supported HW setting and then encoded 972 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based 973 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input. 974 */ 975 static u8 irdma_sc_get_encoded_ird_size_gen_3(u16 ird_size) 976 { 977 switch (ird_size ? 978 roundup_pow_of_two(2 * ird_size) : 4) { 979 case 4096: 980 return IRDMA_IRD_HW_SIZE_4096_GEN3; 981 case 2048: 982 return IRDMA_IRD_HW_SIZE_2048_GEN3; 983 case 1024: 984 return IRDMA_IRD_HW_SIZE_1024_GEN3; 985 case 512: 986 return IRDMA_IRD_HW_SIZE_512_GEN3; 987 case 256: 988 return IRDMA_IRD_HW_SIZE_256_GEN3; 989 case 128: 990 return IRDMA_IRD_HW_SIZE_128_GEN3; 991 case 64: 992 return IRDMA_IRD_HW_SIZE_64_GEN3; 993 case 32: 994 return IRDMA_IRD_HW_SIZE_32_GEN3; 995 case 16: 996 return IRDMA_IRD_HW_SIZE_16_GEN3; 997 case 8: 998 return IRDMA_IRD_HW_SIZE_8_GEN3; 999 case 4: 1000 default: 1001 break; 1002 } 1003 1004 return IRDMA_IRD_HW_SIZE_4_GEN3; 1005 } 1006 1007 /** 1008 * irdma_sc_qp_setctx_roce_gen_3 - set qp's context 1009 * @qp: sc qp 1010 * @qp_ctx: context ptr 1011 * @info: ctx info 1012 */ 1013 static void irdma_sc_qp_setctx_roce_gen_3(struct irdma_sc_qp *qp, 1014 __le64 *qp_ctx, 1015 struct irdma_qp_host_ctx_info *info) 1016 { 1017 struct irdma_roce_offload_info *roce_info = info->roce_info; 1018 struct irdma_udp_offload_info *udp = info->udp_info; 1019 u64 qw0, qw3, qw7 = 0, qw8 = 0; 1020 u8 push_mode_en; 1021 u32 push_idx; 1022 1023 qp->user_pri = info->user_pri; 1024 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 1025 push_mode_en = 0; 1026 push_idx = 0; 1027 } else { 1028 push_mode_en = 1; 1029 push_idx = qp->push_idx; 1030 } 1031 1032 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 1033 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 1034 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 1035 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 1036 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 1037 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 1038 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | 1039 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | 1040 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | 1041 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | 1042 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | 1043 FIELD_PREP(IRDMAQPC_USE_SRQ, !qp->qp_uk.srq_uk ? 0 : 1) | 1044 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag); 1045 set_64bit_val(qp_ctx, 0, qw0); 1046 set_64bit_val(qp_ctx, 8, qp->sq_pa); 1047 set_64bit_val(qp_ctx, 16, qp->rq_pa); 1048 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 1049 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | 1050 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | 1051 FIELD_PREP(IRDMAQPC_TOS, udp->tos) | 1052 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | 1053 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port); 1054 set_64bit_val(qp_ctx, 24, qw3); 1055 set_64bit_val(qp_ctx, 32, 1056 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | 1057 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); 1058 set_64bit_val(qp_ctx, 40, 1059 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | 1060 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); 1061 set_64bit_val(qp_ctx, 48, 1062 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | 1063 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | 1064 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); 1065 qw7 = FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | 1066 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | 1067 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label); 1068 set_64bit_val(qp_ctx, 56, qw7); 1069 qw8 = FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | 1070 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp); 1071 set_64bit_val(qp_ctx, 64, qw8); 1072 set_64bit_val(qp_ctx, 80, 1073 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | 1074 FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); 1075 set_64bit_val(qp_ctx, 88, 1076 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); 1077 set_64bit_val(qp_ctx, 96, 1078 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | 1079 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); 1080 set_64bit_val(qp_ctx, 112, 1081 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); 1082 set_64bit_val(qp_ctx, 128, 1083 FIELD_PREP(IRDMAQPC_MINRNR_TIMER, udp->min_rnr_timer) | 1084 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | 1085 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | 1086 FIELD_PREP(IRDMAQPC_RNRNAK_TMR, udp->rnr_nak_tmr) | 1087 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); 1088 set_64bit_val(qp_ctx, 136, 1089 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 1090 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 1091 set_64bit_val(qp_ctx, 152, 1092 FIELD_PREP(IRDMAQPC_MACADDRESS, 1093 ether_addr_to_u64(roce_info->mac_addr)) | 1094 FIELD_PREP(IRDMAQPC_LOCALACKTIMEOUT, 1095 roce_info->local_ack_timeout)); 1096 set_64bit_val(qp_ctx, 160, 1097 FIELD_PREP(IRDMAQPC_ORDSIZE_GEN3, roce_info->ord_size) | 1098 FIELD_PREP(IRDMAQPC_IRDSIZE_GEN3, 1099 irdma_sc_get_encoded_ird_size_gen_3(roce_info->ird_size)) | 1100 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | 1101 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | 1102 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, 1103 info->stats_idx_valid) | 1104 FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | 1105 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | 1106 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | 1107 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | 1108 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, 1109 roce_info->fw_cc_enable) | 1110 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, 1111 roce_info->udprivcq_en) | 1112 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | 1113 FIELD_PREP(IRDMAQPC_REMOTE_ATOMIC_EN, 1114 info->remote_atomics_en) | 1115 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); 1116 set_64bit_val(qp_ctx, 168, 1117 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 1118 set_64bit_val(qp_ctx, 176, 1119 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 1120 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 1121 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 1122 set_64bit_val(qp_ctx, 184, 1123 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | 1124 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); 1125 set_64bit_val(qp_ctx, 192, 1126 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | 1127 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); 1128 set_64bit_val(qp_ctx, 200, 1129 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | 1130 FIELD_PREP(IRDMAQPC_SRQ_ID, 1131 !qp->qp_uk.srq_uk ? 1132 0 : qp->qp_uk.srq_uk->srq_id) | 1133 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); 1134 set_64bit_val(qp_ctx, 208, roce_info->pd_id | 1135 FIELD_PREP(IRDMAQPC_STAT_INDEX_GEN3, info->stats_idx) | 1136 FIELD_PREP(IRDMAQPC_PKT_LIMIT, qp->pkt_limit)); 1137 1138 print_hex_dump_debug("WQE: QP_HOST ROCE CTX WQE", DUMP_PREFIX_OFFSET, 1139 16, 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 1140 } 1141 1142 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, 1143 struct irdma_qp_host_ctx_info *info) 1144 { 1145 if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) 1146 irdma_sc_qp_setctx_roce_gen_2(qp, qp_ctx, info); 1147 else 1148 irdma_sc_qp_setctx_roce_gen_3(qp, qp_ctx, info); 1149 } 1150 1151 /* irdma_sc_alloc_local_mac_entry - allocate a mac entry 1152 * @cqp: struct for cqp hw 1153 * @scratch: u64 saved to be used during cqp completion 1154 * @post_sq: flag for cqp db to ring 1155 */ 1156 static int irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 1157 bool post_sq) 1158 { 1159 __le64 *wqe; 1160 u64 hdr; 1161 1162 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1163 if (!wqe) 1164 return -ENOMEM; 1165 1166 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 1167 IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) | 1168 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1169 1170 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1171 1172 set_64bit_val(wqe, 24, hdr); 1173 1174 print_hex_dump_debug("WQE: ALLOCATE_LOCAL_MAC WQE", 1175 DUMP_PREFIX_OFFSET, 16, 8, wqe, 1176 IRDMA_CQP_WQE_SIZE * 8, false); 1177 1178 if (post_sq) 1179 irdma_sc_cqp_post_sq(cqp); 1180 return 0; 1181 } 1182 1183 /** 1184 * irdma_sc_add_local_mac_entry - add mac enry 1185 * @cqp: struct for cqp hw 1186 * @info:mac addr info 1187 * @scratch: u64 saved to be used during cqp completion 1188 * @post_sq: flag for cqp db to ring 1189 */ 1190 static int irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp, 1191 struct irdma_local_mac_entry_info *info, 1192 u64 scratch, bool post_sq) 1193 { 1194 __le64 *wqe; 1195 u64 header; 1196 1197 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1198 if (!wqe) 1199 return -ENOMEM; 1200 1201 set_64bit_val(wqe, 32, ether_addr_to_u64(info->mac_addr)); 1202 1203 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) | 1204 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 1205 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 1206 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1207 1208 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1209 1210 set_64bit_val(wqe, 24, header); 1211 1212 print_hex_dump_debug("WQE: ADD_LOCAL_MAC WQE", DUMP_PREFIX_OFFSET, 16, 1213 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1214 1215 if (post_sq) 1216 irdma_sc_cqp_post_sq(cqp); 1217 return 0; 1218 } 1219 1220 /** 1221 * irdma_sc_del_local_mac_entry - cqp wqe to dele local mac 1222 * @cqp: struct for cqp hw 1223 * @scratch: u64 saved to be used during cqp completion 1224 * @entry_idx: index of mac entry 1225 * @ignore_ref_count: to force mac adde delete 1226 * @post_sq: flag for cqp db to ring 1227 */ 1228 static int irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 1229 u16 entry_idx, u8 ignore_ref_count, 1230 bool post_sq) 1231 { 1232 __le64 *wqe; 1233 u64 header; 1234 1235 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1236 if (!wqe) 1237 return -ENOMEM; 1238 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) | 1239 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 1240 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 1241 FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) | 1242 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 1243 FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count); 1244 1245 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1246 1247 set_64bit_val(wqe, 24, header); 1248 1249 print_hex_dump_debug("WQE: DEL_LOCAL_MAC_IPADDR WQE", 1250 DUMP_PREFIX_OFFSET, 16, 8, wqe, 1251 IRDMA_CQP_WQE_SIZE * 8, false); 1252 1253 if (post_sq) 1254 irdma_sc_cqp_post_sq(cqp); 1255 return 0; 1256 } 1257 1258 /** 1259 * irdma_sc_qp_setctx - set qp's context 1260 * @qp: sc qp 1261 * @qp_ctx: context ptr 1262 * @info: ctx info 1263 */ 1264 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx, 1265 struct irdma_qp_host_ctx_info *info) 1266 { 1267 struct irdma_iwarp_offload_info *iw; 1268 struct irdma_tcp_offload_info *tcp; 1269 struct irdma_sc_dev *dev; 1270 u8 push_mode_en; 1271 u32 push_idx; 1272 u64 qw0, qw3, qw7 = 0, qw16 = 0; 1273 u64 mac = 0; 1274 1275 iw = info->iwarp_info; 1276 tcp = info->tcp_info; 1277 dev = qp->dev; 1278 if (iw->rcv_mark_en) { 1279 qp->pfpdu.marker_len = 4; 1280 qp->pfpdu.rcv_start_seq = tcp->rcv_nxt; 1281 } 1282 qp->user_pri = info->user_pri; 1283 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 1284 push_mode_en = 0; 1285 push_idx = 0; 1286 } else { 1287 push_mode_en = 1; 1288 push_idx = qp->push_idx; 1289 } 1290 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 1291 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 1292 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 1293 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 1294 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 1295 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 1296 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en); 1297 1298 set_64bit_val(qp_ctx, 8, qp->sq_pa); 1299 set_64bit_val(qp_ctx, 16, qp->rq_pa); 1300 1301 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 1302 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size); 1303 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1304 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, 1305 qp->src_mac_addr_idx); 1306 set_64bit_val(qp_ctx, 136, 1307 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 1308 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 1309 set_64bit_val(qp_ctx, 168, 1310 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 1311 set_64bit_val(qp_ctx, 176, 1312 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 1313 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 1314 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) | 1315 FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp)); 1316 if (info->iwarp_info_valid) { 1317 qw0 |= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) | 1318 FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) | 1319 FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) | 1320 FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) | 1321 FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) | 1322 FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) | 1323 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, 1324 iw->err_rq_idx_valid); 1325 qw7 |= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id); 1326 qw16 |= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) | 1327 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin); 1328 set_64bit_val(qp_ctx, 144, 1329 FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) | 1330 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 1331 1332 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 1333 mac = ether_addr_to_u64(iw->mac_addr); 1334 1335 set_64bit_val(qp_ctx, 152, 1336 mac << 16 | FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent)); 1337 set_64bit_val(qp_ctx, 160, 1338 FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) | 1339 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) | 1340 FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) | 1341 FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) | 1342 FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) | 1343 FIELD_PREP(IRDMAQPC_BINDEN, iw->bind_en) | 1344 FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) | 1345 FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) | 1346 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 1347 FIELD_PREP(IRDMAQPC_IWARPMODE, 1) | 1348 FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) | 1349 FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) | 1350 FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) | 1351 FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset || !tcp ? iw->rcv_mark_offset : tcp->rcv_nxt) | 1352 FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset || !tcp ? iw->snd_mark_offset : tcp->snd_nxt) | 1353 FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en)); 1354 } 1355 if (info->tcp_info_valid) { 1356 qw0 |= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) | 1357 FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) | 1358 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, 1359 tcp->insert_vlan_tag) | 1360 FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) | 1361 FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) | 1362 FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) | 1363 FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh); 1364 1365 if ((iw->ecn_en || iw->dctcp_en) && !(tcp->tos & 0x03)) 1366 tcp->tos |= ECN_CODE_PT_VAL; 1367 1368 qw3 |= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) | 1369 FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) | 1370 FIELD_PREP(IRDMAQPC_TOS, tcp->tos) | 1371 FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) | 1372 FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port); 1373 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 1374 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx); 1375 1376 qp->src_mac_addr_idx = tcp->src_mac_addr_idx; 1377 } 1378 set_64bit_val(qp_ctx, 32, 1379 FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) | 1380 FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3])); 1381 set_64bit_val(qp_ctx, 40, 1382 FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) | 1383 FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1])); 1384 set_64bit_val(qp_ctx, 48, 1385 FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) | 1386 FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) | 1387 FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) | 1388 FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx)); 1389 qw7 |= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) | 1390 FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) | 1391 FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT, 1392 tcp->ignore_tcp_opt) | 1393 FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT, 1394 tcp->ignore_tcp_uns_opt) | 1395 FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) | 1396 FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) | 1397 FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale); 1398 set_64bit_val(qp_ctx, 72, 1399 FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) | 1400 FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age)); 1401 set_64bit_val(qp_ctx, 80, 1402 FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) | 1403 FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd)); 1404 set_64bit_val(qp_ctx, 88, 1405 FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) | 1406 FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd)); 1407 set_64bit_val(qp_ctx, 96, 1408 FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) | 1409 FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una)); 1410 set_64bit_val(qp_ctx, 104, 1411 FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) | 1412 FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var)); 1413 set_64bit_val(qp_ctx, 112, 1414 FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) | 1415 FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd)); 1416 set_64bit_val(qp_ctx, 120, 1417 FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) | 1418 FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2)); 1419 qw16 |= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) | 1420 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh); 1421 set_64bit_val(qp_ctx, 184, 1422 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) | 1423 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2])); 1424 set_64bit_val(qp_ctx, 192, 1425 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) | 1426 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0])); 1427 set_64bit_val(qp_ctx, 200, 1428 FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) | 1429 FIELD_PREP(IRDMAQPC_TLOW, iw->t_low)); 1430 set_64bit_val(qp_ctx, 208, 1431 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 1432 } 1433 1434 set_64bit_val(qp_ctx, 0, qw0); 1435 set_64bit_val(qp_ctx, 24, qw3); 1436 set_64bit_val(qp_ctx, 56, qw7); 1437 set_64bit_val(qp_ctx, 128, qw16); 1438 1439 print_hex_dump_debug("WQE: QP_HOST CTX", DUMP_PREFIX_OFFSET, 16, 8, 1440 qp_ctx, IRDMA_QP_CTX_SIZE, false); 1441 } 1442 1443 /** 1444 * irdma_sc_alloc_stag - mr stag alloc 1445 * @dev: sc device struct 1446 * @info: stag info 1447 * @scratch: u64 saved to be used during cqp completion 1448 * @post_sq: flag for cqp db to ring 1449 */ 1450 static int irdma_sc_alloc_stag(struct irdma_sc_dev *dev, 1451 struct irdma_allocate_stag_info *info, 1452 u64 scratch, bool post_sq) 1453 { 1454 __le64 *wqe; 1455 struct irdma_sc_cqp *cqp; 1456 u64 hdr; 1457 enum irdma_page_size page_size; 1458 1459 if (!info->total_len && !info->all_memory) 1460 return -EINVAL; 1461 1462 if (info->page_size == 0x40000000) 1463 page_size = IRDMA_PAGE_SIZE_1G; 1464 else if (info->page_size == 0x200000) 1465 page_size = IRDMA_PAGE_SIZE_2M; 1466 else 1467 page_size = IRDMA_PAGE_SIZE_4K; 1468 1469 cqp = dev->cqp; 1470 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1471 if (!wqe) 1472 return -ENOMEM; 1473 1474 set_64bit_val(wqe, 8, 1475 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) | 1476 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len)); 1477 set_64bit_val(wqe, 16, 1478 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx) | 1479 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); 1480 set_64bit_val(wqe, 40, 1481 FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index)); 1482 1483 if (info->chunk_size) 1484 set_64bit_val(wqe, 48, 1485 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx)); 1486 1487 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1488 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1489 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1490 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1491 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1492 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) | 1493 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1494 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1495 FIELD_PREP(IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN, 1496 info->remote_atomics_en) | 1497 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1498 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1499 1500 set_64bit_val(wqe, 24, hdr); 1501 1502 print_hex_dump_debug("WQE: ALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1503 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1504 if (post_sq) 1505 irdma_sc_cqp_post_sq(cqp); 1506 1507 return 0; 1508 } 1509 1510 /** 1511 * irdma_sc_mr_reg_non_shared - non-shared mr registration 1512 * @dev: sc device struct 1513 * @info: mr info 1514 * @scratch: u64 saved to be used during cqp completion 1515 * @post_sq: flag for cqp db to ring 1516 */ 1517 static int irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev, 1518 struct irdma_reg_ns_stag_info *info, 1519 u64 scratch, bool post_sq) 1520 { 1521 __le64 *wqe; 1522 u64 fbo; 1523 struct irdma_sc_cqp *cqp; 1524 u64 hdr; 1525 u32 pble_obj_cnt; 1526 bool remote_access; 1527 u8 addr_type; 1528 enum irdma_page_size page_size; 1529 1530 if (!info->total_len && !info->all_memory) 1531 return -EINVAL; 1532 1533 if (info->page_size == 0x40000000) 1534 page_size = IRDMA_PAGE_SIZE_1G; 1535 else if (info->page_size == 0x200000) 1536 page_size = IRDMA_PAGE_SIZE_2M; 1537 else if (info->page_size == 0x1000) 1538 page_size = IRDMA_PAGE_SIZE_4K; 1539 else 1540 return -EINVAL; 1541 1542 if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY | 1543 IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY)) 1544 remote_access = true; 1545 else 1546 remote_access = false; 1547 1548 pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 1549 if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt) 1550 return -EINVAL; 1551 1552 cqp = dev->cqp; 1553 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1554 if (!wqe) 1555 return -ENOMEM; 1556 fbo = info->va & (info->page_size - 1); 1557 1558 set_64bit_val(wqe, 0, 1559 (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ? 1560 info->va : fbo)); 1561 set_64bit_val(wqe, 8, 1562 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) | 1563 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1564 set_64bit_val(wqe, 16, 1565 FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) | 1566 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18) | 1567 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1568 if (!info->chunk_size) { 1569 set_64bit_val(wqe, 32, info->reg_addr_pa); 1570 set_64bit_val(wqe, 48, 0); 1571 } else { 1572 set_64bit_val(wqe, 32, 0); 1573 set_64bit_val(wqe, 48, 1574 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index)); 1575 } 1576 set_64bit_val(wqe, 40, info->hmc_fcn_index); 1577 set_64bit_val(wqe, 56, 0); 1578 1579 addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0; 1580 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) | 1581 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1582 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1583 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1584 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1585 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) | 1586 FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) | 1587 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1588 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1589 FIELD_PREP(IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN, 1590 info->remote_atomics_en) | 1591 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1592 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1593 1594 set_64bit_val(wqe, 24, hdr); 1595 1596 print_hex_dump_debug("WQE: MR_REG_NS WQE", DUMP_PREFIX_OFFSET, 16, 8, 1597 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1598 if (post_sq) 1599 irdma_sc_cqp_post_sq(cqp); 1600 1601 return 0; 1602 } 1603 1604 /** 1605 * irdma_sc_dealloc_stag - deallocate stag 1606 * @dev: sc device struct 1607 * @info: dealloc stag info 1608 * @scratch: u64 saved to be used during cqp completion 1609 * @post_sq: flag for cqp db to ring 1610 */ 1611 static int irdma_sc_dealloc_stag(struct irdma_sc_dev *dev, 1612 struct irdma_dealloc_stag_info *info, 1613 u64 scratch, bool post_sq) 1614 { 1615 u64 hdr; 1616 __le64 *wqe; 1617 struct irdma_sc_cqp *cqp; 1618 1619 cqp = dev->cqp; 1620 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1621 if (!wqe) 1622 return -ENOMEM; 1623 1624 set_64bit_val(wqe, 8, 1625 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1626 set_64bit_val(wqe, 16, 1627 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx) | 1628 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); 1629 1630 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) | 1631 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) | 1632 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1633 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1634 1635 set_64bit_val(wqe, 24, hdr); 1636 1637 print_hex_dump_debug("WQE: DEALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 1638 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1639 if (post_sq) 1640 irdma_sc_cqp_post_sq(cqp); 1641 1642 return 0; 1643 } 1644 1645 /** 1646 * irdma_sc_mw_alloc - mw allocate 1647 * @dev: sc device struct 1648 * @info: memory window allocation information 1649 * @scratch: u64 saved to be used during cqp completion 1650 * @post_sq: flag for cqp db to ring 1651 */ 1652 static int irdma_sc_mw_alloc(struct irdma_sc_dev *dev, 1653 struct irdma_mw_alloc_info *info, u64 scratch, 1654 bool post_sq) 1655 { 1656 u64 hdr; 1657 struct irdma_sc_cqp *cqp; 1658 __le64 *wqe; 1659 1660 cqp = dev->cqp; 1661 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1662 if (!wqe) 1663 return -ENOMEM; 1664 1665 set_64bit_val(wqe, 8, 1666 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1667 set_64bit_val(wqe, 16, 1668 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index) | 1669 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); 1670 1671 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1672 FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) | 1673 FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY, 1674 info->mw1_bind_dont_vldt_key) | 1675 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1676 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1677 1678 set_64bit_val(wqe, 24, hdr); 1679 1680 print_hex_dump_debug("WQE: MW_ALLOC WQE", DUMP_PREFIX_OFFSET, 16, 8, 1681 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1682 if (post_sq) 1683 irdma_sc_cqp_post_sq(cqp); 1684 1685 return 0; 1686 } 1687 1688 /** 1689 * irdma_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp 1690 * @qp: sc qp struct 1691 * @info: fast mr info 1692 * @post_sq: flag for cqp db to ring 1693 */ 1694 int irdma_sc_mr_fast_register(struct irdma_sc_qp *qp, 1695 struct irdma_fast_reg_stag_info *info, 1696 bool post_sq) 1697 { 1698 u64 temp, hdr; 1699 __le64 *wqe; 1700 u32 wqe_idx; 1701 enum irdma_page_size page_size; 1702 struct irdma_post_sq_info sq_info = {}; 1703 1704 if (info->page_size == 0x40000000) 1705 page_size = IRDMA_PAGE_SIZE_1G; 1706 else if (info->page_size == 0x200000) 1707 page_size = IRDMA_PAGE_SIZE_2M; 1708 else 1709 page_size = IRDMA_PAGE_SIZE_4K; 1710 1711 sq_info.wr_id = info->wr_id; 1712 sq_info.signaled = info->signaled; 1713 1714 wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, 1715 IRDMA_QP_WQE_MIN_QUANTA, 0, &sq_info); 1716 if (!wqe) 1717 return -ENOMEM; 1718 1719 irdma_clr_wqes(&qp->qp_uk, wqe_idx); 1720 1721 ibdev_dbg(to_ibdev(qp->dev), 1722 "MR: wr_id[%llxh] wqe_idx[%04d] location[%p]\n", 1723 info->wr_id, wqe_idx, 1724 &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid); 1725 1726 temp = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1727 (uintptr_t)info->va : info->fbo; 1728 set_64bit_val(wqe, 0, temp); 1729 1730 temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI, 1731 info->first_pm_pbl_index >> 16); 1732 set_64bit_val(wqe, 8, 1733 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) | 1734 FIELD_PREP(IRDMAQPSQ_PBLADDR >> IRDMA_HW_PAGE_SHIFT, info->reg_addr_pa)); 1735 set_64bit_val(wqe, 16, 1736 info->total_len | 1737 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index)); 1738 1739 hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) | 1740 FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) | 1741 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) | 1742 FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) | 1743 FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) | 1744 FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) | 1745 FIELD_PREP(IRDMAQPSQ_VABASEDTO, info->addr_type) | 1746 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | 1747 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 1748 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 1749 FIELD_PREP(IRDMAQPSQ_REMOTE_ATOMICS_EN, info->remote_atomics_en) | 1750 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1751 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1752 1753 set_64bit_val(wqe, 24, hdr); 1754 1755 print_hex_dump_debug("WQE: FAST_REG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1756 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1757 1758 if (post_sq) 1759 irdma_uk_qp_post_wr(&qp->qp_uk); 1760 1761 return 0; 1762 } 1763 1764 /** 1765 * irdma_sc_gen_rts_ae - request AE generated after RTS 1766 * @qp: sc qp struct 1767 */ 1768 static void irdma_sc_gen_rts_ae(struct irdma_sc_qp *qp) 1769 { 1770 __le64 *wqe; 1771 u64 hdr; 1772 struct irdma_qp_uk *qp_uk; 1773 1774 qp_uk = &qp->qp_uk; 1775 1776 wqe = qp_uk->sq_base[1].elem; 1777 1778 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | 1779 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) | 1780 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1781 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1782 1783 set_64bit_val(wqe, 24, hdr); 1784 print_hex_dump_debug("QP: NOP W/LOCAL FENCE WQE", DUMP_PREFIX_OFFSET, 1785 16, 8, wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1786 1787 wqe = qp_uk->sq_base[2].elem; 1788 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) | 1789 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1790 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1791 1792 set_64bit_val(wqe, 24, hdr); 1793 print_hex_dump_debug("QP: CONN EST WQE", DUMP_PREFIX_OFFSET, 16, 8, 1794 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1795 } 1796 1797 /** 1798 * irdma_sc_send_lsmm - send last streaming mode message 1799 * @qp: sc qp struct 1800 * @lsmm_buf: buffer with lsmm message 1801 * @size: size of lsmm buffer 1802 * @stag: stag of lsmm buffer 1803 */ 1804 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size, 1805 irdma_stag stag) 1806 { 1807 __le64 *wqe; 1808 u64 hdr; 1809 struct irdma_qp_uk *qp_uk; 1810 1811 qp_uk = &qp->qp_uk; 1812 wqe = qp_uk->sq_base->elem; 1813 1814 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf); 1815 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1816 set_64bit_val(wqe, 8, 1817 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) | 1818 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag)); 1819 } else { 1820 set_64bit_val(wqe, 8, 1821 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) | 1822 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) | 1823 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1824 } 1825 set_64bit_val(wqe, 16, 0); 1826 1827 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) | 1828 FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) | 1829 FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) | 1830 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1831 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1832 1833 set_64bit_val(wqe, 24, hdr); 1834 1835 print_hex_dump_debug("WQE: SEND_LSMM WQE", DUMP_PREFIX_OFFSET, 16, 8, 1836 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1837 1838 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1839 irdma_sc_gen_rts_ae(qp); 1840 } 1841 1842 /** 1843 * irdma_sc_send_rtt - send last read0 or write0 1844 * @qp: sc qp struct 1845 * @read: Do read0 or write0 1846 */ 1847 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read) 1848 { 1849 __le64 *wqe; 1850 u64 hdr; 1851 struct irdma_qp_uk *qp_uk; 1852 1853 qp_uk = &qp->qp_uk; 1854 wqe = qp_uk->sq_base->elem; 1855 1856 set_64bit_val(wqe, 0, 0); 1857 set_64bit_val(wqe, 16, 0); 1858 if (read) { 1859 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1860 set_64bit_val(wqe, 8, 1861 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd)); 1862 } else { 1863 set_64bit_val(wqe, 8, 1864 (u64)0xabcd | FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1865 } 1866 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) | 1867 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) | 1868 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1869 1870 } else { 1871 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1872 set_64bit_val(wqe, 8, 0); 1873 } else { 1874 set_64bit_val(wqe, 8, 1875 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1876 } 1877 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) | 1878 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1879 } 1880 1881 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1882 1883 set_64bit_val(wqe, 24, hdr); 1884 1885 print_hex_dump_debug("WQE: RTR WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 1886 IRDMA_QP_WQE_MIN_SIZE, false); 1887 1888 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1889 irdma_sc_gen_rts_ae(qp); 1890 } 1891 1892 /** 1893 * irdma_iwarp_opcode - determine if incoming is rdma layer 1894 * @info: aeq info for the packet 1895 * @pkt: packet for error 1896 */ 1897 static u32 irdma_iwarp_opcode(struct irdma_aeqe_info *info, u8 *pkt) 1898 { 1899 __be16 *mpa; 1900 u32 opcode = 0xffffffff; 1901 1902 if (info->q2_data_written) { 1903 mpa = (__be16 *)pkt; 1904 opcode = ntohs(mpa[1]) & 0xf; 1905 } 1906 1907 return opcode; 1908 } 1909 1910 /** 1911 * irdma_locate_mpa - return pointer to mpa in the pkt 1912 * @pkt: packet with data 1913 */ 1914 static u8 *irdma_locate_mpa(u8 *pkt) 1915 { 1916 /* skip over ethernet header */ 1917 pkt += IRDMA_MAC_HLEN; 1918 1919 /* Skip over IP and TCP headers */ 1920 pkt += 4 * (pkt[0] & 0x0f); 1921 pkt += 4 * ((pkt[12] >> 4) & 0x0f); 1922 1923 return pkt; 1924 } 1925 1926 /** 1927 * irdma_bld_termhdr_ctrl - setup terminate hdr control fields 1928 * @qp: sc qp ptr for pkt 1929 * @hdr: term hdr 1930 * @opcode: flush opcode for termhdr 1931 * @layer_etype: error layer + error type 1932 * @err: error cod ein the header 1933 */ 1934 static void irdma_bld_termhdr_ctrl(struct irdma_sc_qp *qp, 1935 struct irdma_terminate_hdr *hdr, 1936 enum irdma_flush_opcode opcode, 1937 u8 layer_etype, u8 err) 1938 { 1939 qp->flush_code = opcode; 1940 hdr->layer_etype = layer_etype; 1941 hdr->error_code = err; 1942 } 1943 1944 /** 1945 * irdma_bld_termhdr_ddp_rdma - setup ddp and rdma hdrs in terminate hdr 1946 * @pkt: ptr to mpa in offending pkt 1947 * @hdr: term hdr 1948 * @copy_len: offending pkt length to be copied to term hdr 1949 * @is_tagged: DDP tagged or untagged 1950 */ 1951 static void irdma_bld_termhdr_ddp_rdma(u8 *pkt, struct irdma_terminate_hdr *hdr, 1952 int *copy_len, u8 *is_tagged) 1953 { 1954 u16 ddp_seg_len; 1955 1956 ddp_seg_len = ntohs(*(__be16 *)pkt); 1957 if (ddp_seg_len) { 1958 *copy_len = 2; 1959 hdr->hdrct = DDP_LEN_FLAG; 1960 if (pkt[2] & 0x80) { 1961 *is_tagged = 1; 1962 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) { 1963 *copy_len += TERM_DDP_LEN_TAGGED; 1964 hdr->hdrct |= DDP_HDR_FLAG; 1965 } 1966 } else { 1967 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) { 1968 *copy_len += TERM_DDP_LEN_UNTAGGED; 1969 hdr->hdrct |= DDP_HDR_FLAG; 1970 } 1971 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN) && 1972 ((pkt[3] & RDMA_OPCODE_M) == RDMA_READ_REQ_OPCODE)) { 1973 *copy_len += TERM_RDMA_LEN; 1974 hdr->hdrct |= RDMA_HDR_FLAG; 1975 } 1976 } 1977 } 1978 } 1979 1980 /** 1981 * irdma_bld_terminate_hdr - build terminate message header 1982 * @qp: qp associated with received terminate AE 1983 * @info: the struct contiaing AE information 1984 */ 1985 static int irdma_bld_terminate_hdr(struct irdma_sc_qp *qp, 1986 struct irdma_aeqe_info *info) 1987 { 1988 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 1989 int copy_len = 0; 1990 u8 is_tagged = 0; 1991 u32 opcode; 1992 struct irdma_terminate_hdr *termhdr; 1993 1994 termhdr = (struct irdma_terminate_hdr *)qp->q2_buf; 1995 memset(termhdr, 0, Q2_BAD_FRAME_OFFSET); 1996 1997 if (info->q2_data_written) { 1998 pkt = irdma_locate_mpa(pkt); 1999 irdma_bld_termhdr_ddp_rdma(pkt, termhdr, ©_len, &is_tagged); 2000 } 2001 2002 opcode = irdma_iwarp_opcode(info, pkt); 2003 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 2004 qp->sq_flush_code = info->sq; 2005 qp->rq_flush_code = info->rq; 2006 2007 switch (info->ae_id) { 2008 case IRDMA_AE_AMP_UNALLOCATED_STAG: 2009 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2010 if (opcode == IRDMA_OP_TYPE_RDMA_WRITE) 2011 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 2012 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2013 DDP_TAGGED_INV_STAG); 2014 else 2015 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2016 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2017 RDMAP_INV_STAG); 2018 break; 2019 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 2020 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2021 if (info->q2_data_written) 2022 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 2023 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2024 DDP_TAGGED_BOUNDS); 2025 else 2026 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2027 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2028 RDMAP_INV_BOUNDS); 2029 break; 2030 case IRDMA_AE_AMP_BAD_PD: 2031 switch (opcode) { 2032 case IRDMA_OP_TYPE_RDMA_WRITE: 2033 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 2034 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2035 DDP_TAGGED_UNASSOC_STAG); 2036 break; 2037 case IRDMA_OP_TYPE_SEND_INV: 2038 case IRDMA_OP_TYPE_SEND_SOL_INV: 2039 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2040 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2041 RDMAP_CANT_INV_STAG); 2042 break; 2043 default: 2044 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2045 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2046 RDMAP_UNASSOC_STAG); 2047 } 2048 break; 2049 case IRDMA_AE_AMP_INVALID_STAG: 2050 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2051 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2052 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2053 RDMAP_INV_STAG); 2054 break; 2055 case IRDMA_AE_AMP_BAD_QP: 2056 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_QP_OP_ERR, 2057 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2058 DDP_UNTAGGED_INV_QN); 2059 break; 2060 case IRDMA_AE_AMP_BAD_STAG_KEY: 2061 case IRDMA_AE_AMP_BAD_STAG_INDEX: 2062 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2063 switch (opcode) { 2064 case IRDMA_OP_TYPE_SEND_INV: 2065 case IRDMA_OP_TYPE_SEND_SOL_INV: 2066 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 2067 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2068 RDMAP_CANT_INV_STAG); 2069 break; 2070 default: 2071 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2072 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2073 RDMAP_INV_STAG); 2074 } 2075 break; 2076 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 2077 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 2078 case IRDMA_AE_PRIV_OPERATION_DENIED: 2079 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2080 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2081 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2082 RDMAP_ACCESS); 2083 break; 2084 case IRDMA_AE_AMP_TO_WRAP: 2085 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2086 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2087 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2088 RDMAP_TO_WRAP); 2089 break; 2090 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 2091 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2092 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC); 2093 break; 2094 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 2095 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 2096 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 2097 DDP_CATASTROPHIC_LOCAL); 2098 break; 2099 case IRDMA_AE_LCE_QP_CATASTROPHIC: 2100 case IRDMA_AE_DDP_NO_L_BIT: 2101 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 2102 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 2103 DDP_CATASTROPHIC_LOCAL); 2104 break; 2105 case IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN: 2106 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2107 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2108 DDP_UNTAGGED_INV_MSN_RANGE); 2109 break; 2110 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 2111 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2112 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 2113 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2114 DDP_UNTAGGED_INV_TOO_LONG); 2115 break; 2116 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 2117 if (is_tagged) 2118 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2119 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2120 DDP_TAGGED_INV_DDP_VER); 2121 else 2122 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2123 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2124 DDP_UNTAGGED_INV_DDP_VER); 2125 break; 2126 case IRDMA_AE_DDP_UBE_INVALID_MO: 2127 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2128 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2129 DDP_UNTAGGED_INV_MO); 2130 break; 2131 case IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: 2132 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 2133 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2134 DDP_UNTAGGED_INV_MSN_NO_BUF); 2135 break; 2136 case IRDMA_AE_DDP_UBE_INVALID_QN: 2137 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2138 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2139 DDP_UNTAGGED_INV_QN); 2140 break; 2141 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 2142 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2143 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2144 RDMAP_INV_RDMAP_VER); 2145 break; 2146 default: 2147 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 2148 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2149 RDMAP_UNSPECIFIED); 2150 break; 2151 } 2152 2153 if (copy_len) 2154 memcpy(termhdr + 1, pkt, copy_len); 2155 2156 return sizeof(struct irdma_terminate_hdr) + copy_len; 2157 } 2158 2159 /** 2160 * irdma_terminate_send_fin() - Send fin for terminate message 2161 * @qp: qp associated with received terminate AE 2162 */ 2163 void irdma_terminate_send_fin(struct irdma_sc_qp *qp) 2164 { 2165 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 2166 IRDMAQP_TERM_SEND_FIN_ONLY, 0); 2167 } 2168 2169 /** 2170 * irdma_terminate_connection() - Bad AE and send terminate to remote QP 2171 * @qp: qp associated with received terminate AE 2172 * @info: the struct contiaing AE information 2173 */ 2174 void irdma_terminate_connection(struct irdma_sc_qp *qp, 2175 struct irdma_aeqe_info *info) 2176 { 2177 u8 termlen = 0; 2178 2179 if (qp->term_flags & IRDMA_TERM_SENT) 2180 return; 2181 2182 termlen = irdma_bld_terminate_hdr(qp, info); 2183 irdma_terminate_start_timer(qp); 2184 qp->term_flags |= IRDMA_TERM_SENT; 2185 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 2186 IRDMAQP_TERM_SEND_TERM_ONLY, termlen); 2187 } 2188 2189 /** 2190 * irdma_terminate_received - handle terminate received AE 2191 * @qp: qp associated with received terminate AE 2192 * @info: the struct contiaing AE information 2193 */ 2194 void irdma_terminate_received(struct irdma_sc_qp *qp, 2195 struct irdma_aeqe_info *info) 2196 { 2197 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 2198 __be32 *mpa; 2199 u8 ddp_ctl; 2200 u8 rdma_ctl; 2201 u16 aeq_id = 0; 2202 struct irdma_terminate_hdr *termhdr; 2203 2204 mpa = (__be32 *)irdma_locate_mpa(pkt); 2205 if (info->q2_data_written) { 2206 /* did not validate the frame - do it now */ 2207 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff; 2208 rdma_ctl = ntohl(mpa[0]) & 0xff; 2209 if ((ddp_ctl & 0xc0) != 0x40) 2210 aeq_id = IRDMA_AE_LCE_QP_CATASTROPHIC; 2211 else if ((ddp_ctl & 0x03) != 1) 2212 aeq_id = IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION; 2213 else if (ntohl(mpa[2]) != 2) 2214 aeq_id = IRDMA_AE_DDP_UBE_INVALID_QN; 2215 else if (ntohl(mpa[3]) != 1) 2216 aeq_id = IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN; 2217 else if (ntohl(mpa[4]) != 0) 2218 aeq_id = IRDMA_AE_DDP_UBE_INVALID_MO; 2219 else if ((rdma_ctl & 0xc0) != 0x40) 2220 aeq_id = IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION; 2221 2222 info->ae_id = aeq_id; 2223 if (info->ae_id) { 2224 /* Bad terminate recvd - send back a terminate */ 2225 irdma_terminate_connection(qp, info); 2226 return; 2227 } 2228 } 2229 2230 qp->term_flags |= IRDMA_TERM_RCVD; 2231 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 2232 termhdr = (struct irdma_terminate_hdr *)&mpa[5]; 2233 if (termhdr->layer_etype == RDMAP_REMOTE_PROT || 2234 termhdr->layer_etype == RDMAP_REMOTE_OP) { 2235 irdma_terminate_done(qp, 0); 2236 } else { 2237 irdma_terminate_start_timer(qp); 2238 irdma_terminate_send_fin(qp); 2239 } 2240 } 2241 2242 static int irdma_null_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri) 2243 { 2244 return 0; 2245 } 2246 2247 static void irdma_null_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri) 2248 { 2249 /* do nothing */ 2250 } 2251 2252 static void irdma_null_ws_reset(struct irdma_sc_vsi *vsi) 2253 { 2254 /* do nothing */ 2255 } 2256 2257 /** 2258 * irdma_sc_vsi_init - Init the vsi structure 2259 * @vsi: pointer to vsi structure to initialize 2260 * @info: the info used to initialize the vsi struct 2261 */ 2262 void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi, 2263 struct irdma_vsi_init_info *info) 2264 { 2265 int i; 2266 2267 vsi->dev = info->dev; 2268 vsi->back_vsi = info->back_vsi; 2269 vsi->register_qset = info->register_qset; 2270 vsi->unregister_qset = info->unregister_qset; 2271 vsi->mtu = info->params->mtu; 2272 vsi->exception_lan_q = info->exception_lan_q; 2273 vsi->vsi_idx = info->pf_data_vsi_num; 2274 2275 irdma_set_qos_info(vsi, info->params); 2276 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 2277 mutex_init(&vsi->qos[i].qos_mutex); 2278 INIT_LIST_HEAD(&vsi->qos[i].qplist); 2279 } 2280 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) { 2281 vsi->dev->ws_add = irdma_ws_add; 2282 vsi->dev->ws_remove = irdma_ws_remove; 2283 vsi->dev->ws_reset = irdma_ws_reset; 2284 } else { 2285 vsi->dev->ws_add = irdma_null_ws_add; 2286 vsi->dev->ws_remove = irdma_null_ws_remove; 2287 vsi->dev->ws_reset = irdma_null_ws_reset; 2288 } 2289 } 2290 2291 /** 2292 * irdma_get_stats_idx - Return stats index 2293 * @vsi: pointer to the vsi 2294 */ 2295 static u16 irdma_get_stats_idx(struct irdma_sc_vsi *vsi) 2296 { 2297 struct irdma_stats_inst_info stats_info = {}; 2298 struct irdma_sc_dev *dev = vsi->dev; 2299 u8 i; 2300 2301 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 2302 if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE, 2303 &stats_info)) 2304 return stats_info.stats_idx; 2305 } 2306 2307 for (i = 0; i < IRDMA_MAX_STATS_COUNT_GEN_1; i++) { 2308 if (!dev->stats_idx_array[i]) { 2309 dev->stats_idx_array[i] = true; 2310 return i; 2311 } 2312 } 2313 2314 return IRDMA_INVALID_STATS_IDX; 2315 } 2316 2317 /** 2318 * irdma_hw_stats_init_gen1 - Initialize stat reg table used for gen1 2319 * @vsi: vsi structure where hw_regs are set 2320 * 2321 * Populate the HW stats table 2322 */ 2323 static void irdma_hw_stats_init_gen1(struct irdma_sc_vsi *vsi) 2324 { 2325 struct irdma_sc_dev *dev = vsi->dev; 2326 const struct irdma_hw_stat_map *map; 2327 u64 *stat_reg = vsi->hw_stats_regs; 2328 u64 *regs = dev->hw_stats_regs; 2329 u16 i, stats_reg_set = vsi->stats_idx; 2330 2331 map = dev->hw_stats_map; 2332 2333 /* First 4 stat instances are reserved for port level statistics. */ 2334 stats_reg_set += vsi->stats_inst_alloc ? IRDMA_FIRST_NON_PF_STAT : 0; 2335 2336 for (i = 0; i < dev->hw_attrs.max_stat_idx; i++) { 2337 if (map[i].bitmask <= IRDMA_MAX_STATS_32) 2338 stat_reg[i] = regs[i] + stats_reg_set * sizeof(u32); 2339 else 2340 stat_reg[i] = regs[i] + stats_reg_set * sizeof(u64); 2341 } 2342 } 2343 2344 /** 2345 * irdma_vsi_stats_init - Initialize the vsi statistics 2346 * @vsi: pointer to the vsi structure 2347 * @info: The info structure used for initialization 2348 */ 2349 int irdma_vsi_stats_init(struct irdma_sc_vsi *vsi, 2350 struct irdma_vsi_stats_info *info) 2351 { 2352 struct irdma_dma_mem *stats_buff_mem; 2353 2354 vsi->pestat = info->pestat; 2355 vsi->pestat->hw = vsi->dev->hw; 2356 vsi->pestat->vsi = vsi; 2357 stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem; 2358 stats_buff_mem->size = ALIGN(IRDMA_GATHER_STATS_BUF_SIZE * 2, 1); 2359 stats_buff_mem->va = dma_alloc_coherent(vsi->pestat->hw->device, 2360 stats_buff_mem->size, 2361 &stats_buff_mem->pa, 2362 GFP_KERNEL); 2363 if (!stats_buff_mem->va) 2364 return -ENOMEM; 2365 2366 vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va; 2367 vsi->pestat->gather_info.last_gather_stats_va = 2368 (void *)((uintptr_t)stats_buff_mem->va + 2369 IRDMA_GATHER_STATS_BUF_SIZE); 2370 2371 if (vsi->dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3) 2372 irdma_hw_stats_start_timer(vsi); 2373 2374 /* when stat allocation is not required default to fcn_id. */ 2375 vsi->stats_idx = info->fcn_id; 2376 if (info->alloc_stats_inst) { 2377 u16 stats_idx = irdma_get_stats_idx(vsi); 2378 2379 if (stats_idx != IRDMA_INVALID_STATS_IDX) { 2380 vsi->stats_inst_alloc = true; 2381 vsi->stats_idx = stats_idx; 2382 vsi->pestat->gather_info.use_stats_inst = true; 2383 vsi->pestat->gather_info.stats_inst_index = stats_idx; 2384 } 2385 } 2386 2387 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 2388 irdma_hw_stats_init_gen1(vsi); 2389 2390 return 0; 2391 } 2392 2393 /** 2394 * irdma_vsi_stats_free - Free the vsi stats 2395 * @vsi: pointer to the vsi structure 2396 */ 2397 void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi) 2398 { 2399 struct irdma_stats_inst_info stats_info = {}; 2400 struct irdma_sc_dev *dev = vsi->dev; 2401 u16 stats_idx = vsi->stats_idx; 2402 2403 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 2404 if (vsi->stats_inst_alloc) { 2405 stats_info.stats_idx = vsi->stats_idx; 2406 irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE, 2407 &stats_info); 2408 } 2409 } else { 2410 if (vsi->stats_inst_alloc && 2411 stats_idx < vsi->dev->hw_attrs.max_stat_inst) 2412 vsi->dev->stats_idx_array[stats_idx] = false; 2413 } 2414 2415 if (!vsi->pestat) 2416 return; 2417 2418 if (dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3) 2419 irdma_hw_stats_stop_timer(vsi); 2420 dma_free_coherent(vsi->pestat->hw->device, 2421 vsi->pestat->gather_info.stats_buff_mem.size, 2422 vsi->pestat->gather_info.stats_buff_mem.va, 2423 vsi->pestat->gather_info.stats_buff_mem.pa); 2424 vsi->pestat->gather_info.stats_buff_mem.va = NULL; 2425 } 2426 2427 /** 2428 * irdma_get_encoded_wqe_size - given wq size, returns hardware encoded size 2429 * @wqsize: size of the wq (sq, rq) to encoded_size 2430 * @queue_type: queue type selected for the calculation algorithm 2431 */ 2432 u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type) 2433 { 2434 u8 encoded_size = 0; 2435 2436 if (queue_type == IRDMA_QUEUE_TYPE_SRQ) { 2437 /* Smallest SRQ size is 256B (8 quanta) that gets 2438 * encoded to 0. 2439 */ 2440 encoded_size = ilog2(wqsize) - 3; 2441 2442 return encoded_size; 2443 } 2444 /* cqp sq's hw coded value starts from 1 for size of 4 2445 * while it starts from 0 for qp' wq's. 2446 */ 2447 if (queue_type == IRDMA_QUEUE_TYPE_CQP) 2448 encoded_size = 1; 2449 wqsize >>= 2; 2450 while (wqsize >>= 1) 2451 encoded_size++; 2452 2453 return encoded_size; 2454 } 2455 2456 /** 2457 * irdma_sc_gather_stats - collect the statistics 2458 * @cqp: struct for cqp hw 2459 * @info: gather stats info structure 2460 * @scratch: u64 saved to be used during cqp completion 2461 */ 2462 static int irdma_sc_gather_stats(struct irdma_sc_cqp *cqp, 2463 struct irdma_stats_gather_info *info, 2464 u64 scratch) 2465 { 2466 __le64 *wqe; 2467 u64 temp; 2468 2469 if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE) 2470 return -ENOMEM; 2471 2472 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2473 if (!wqe) 2474 return -ENOMEM; 2475 2476 set_64bit_val(wqe, 40, 2477 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index)); 2478 set_64bit_val(wqe, 32, info->stats_buff_mem.pa); 2479 2480 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2481 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) | 2482 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, 2483 info->stats_inst_index) | 2484 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2485 info->use_hmc_fcn_index) | 2486 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS); 2487 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2488 2489 set_64bit_val(wqe, 24, temp); 2490 2491 print_hex_dump_debug("STATS: GATHER_STATS WQE", DUMP_PREFIX_OFFSET, 2492 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2493 2494 irdma_sc_cqp_post_sq(cqp); 2495 ibdev_dbg(to_ibdev(cqp->dev), 2496 "STATS: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 2497 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 2498 2499 return 0; 2500 } 2501 2502 /** 2503 * irdma_sc_manage_stats_inst - allocate or free stats instance 2504 * @cqp: struct for cqp hw 2505 * @info: stats info structure 2506 * @alloc: alloc vs. delete flag 2507 * @scratch: u64 saved to be used during cqp completion 2508 */ 2509 static int irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp, 2510 struct irdma_stats_inst_info *info, 2511 bool alloc, u64 scratch) 2512 { 2513 __le64 *wqe; 2514 u64 temp; 2515 2516 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2517 if (!wqe) 2518 return -ENOMEM; 2519 2520 set_64bit_val(wqe, 40, 2521 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id)); 2522 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2523 FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) | 2524 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2525 info->use_hmc_fcn_index) | 2526 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) | 2527 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS); 2528 2529 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2530 2531 set_64bit_val(wqe, 24, temp); 2532 2533 print_hex_dump_debug("WQE: MANAGE_STATS WQE", DUMP_PREFIX_OFFSET, 16, 2534 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2535 2536 irdma_sc_cqp_post_sq(cqp); 2537 return 0; 2538 } 2539 2540 /** 2541 * irdma_sc_set_up_map - set the up map table 2542 * @cqp: struct for cqp hw 2543 * @info: User priority map info 2544 * @scratch: u64 saved to be used during cqp completion 2545 */ 2546 static int irdma_sc_set_up_map(struct irdma_sc_cqp *cqp, 2547 struct irdma_up_info *info, u64 scratch) 2548 { 2549 __le64 *wqe; 2550 u64 temp = 0; 2551 int i; 2552 2553 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2554 if (!wqe) 2555 return -ENOMEM; 2556 2557 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) 2558 temp |= (u64)info->map[i] << (i * 8); 2559 2560 set_64bit_val(wqe, 0, temp); 2561 set_64bit_val(wqe, 40, 2562 FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) | 2563 FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx)); 2564 2565 temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) | 2566 FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) | 2567 FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE, 2568 info->use_cnp_up_override) | 2569 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP); 2570 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2571 2572 set_64bit_val(wqe, 24, temp); 2573 2574 print_hex_dump_debug("WQE: UPMAP WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 2575 IRDMA_CQP_WQE_SIZE * 8, false); 2576 irdma_sc_cqp_post_sq(cqp); 2577 2578 return 0; 2579 } 2580 2581 /** 2582 * irdma_sc_manage_ws_node - create/modify/destroy WS node 2583 * @cqp: struct for cqp hw 2584 * @info: node info structure 2585 * @node_op: 0 for add 1 for modify, 2 for delete 2586 * @scratch: u64 saved to be used during cqp completion 2587 */ 2588 static int irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp, 2589 struct irdma_ws_node_info *info, 2590 enum irdma_ws_node_op node_op, u64 scratch) 2591 { 2592 __le64 *wqe; 2593 u64 temp = 0; 2594 2595 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2596 if (!wqe) 2597 return -ENOMEM; 2598 2599 set_64bit_val(wqe, 32, 2600 FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) | 2601 FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight)); 2602 2603 temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) | 2604 FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) | 2605 FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) | 2606 FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) | 2607 FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) | 2608 FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) | 2609 FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) | 2610 FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) | 2611 FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id); 2612 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2613 2614 set_64bit_val(wqe, 24, temp); 2615 2616 print_hex_dump_debug("WQE: MANAGE_WS WQE", DUMP_PREFIX_OFFSET, 16, 8, 2617 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2618 irdma_sc_cqp_post_sq(cqp); 2619 2620 return 0; 2621 } 2622 2623 /** 2624 * irdma_sc_qp_flush_wqes - flush qp's wqe 2625 * @qp: sc qp 2626 * @info: dlush information 2627 * @scratch: u64 saved to be used during cqp completion 2628 * @post_sq: flag for cqp db to ring 2629 */ 2630 int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp, 2631 struct irdma_qp_flush_info *info, u64 scratch, 2632 bool post_sq) 2633 { 2634 u64 temp = 0; 2635 __le64 *wqe; 2636 struct irdma_sc_cqp *cqp; 2637 u64 hdr; 2638 bool flush_sq = false, flush_rq = false; 2639 2640 if (info->rq && !qp->flush_rq) 2641 flush_rq = true; 2642 if (info->sq && !qp->flush_sq) 2643 flush_sq = true; 2644 qp->flush_sq |= flush_sq; 2645 qp->flush_rq |= flush_rq; 2646 2647 if (!flush_sq && !flush_rq) { 2648 ibdev_dbg(to_ibdev(qp->dev), 2649 "CQP: Additional flush request ignored for qp %x\n", 2650 qp->qp_uk.qp_id); 2651 return -EALREADY; 2652 } 2653 2654 cqp = qp->pd->dev->cqp; 2655 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2656 if (!wqe) 2657 return -ENOMEM; 2658 2659 if (info->userflushcode) { 2660 if (flush_rq) 2661 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR, 2662 info->rq_minor_code) | 2663 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR, 2664 info->rq_major_code); 2665 if (flush_sq) 2666 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR, 2667 info->sq_minor_code) | 2668 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR, 2669 info->sq_major_code); 2670 } 2671 set_64bit_val(wqe, 16, temp); 2672 2673 temp = (info->generate_ae) ? 2674 info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2675 info->ae_src) : 0; 2676 set_64bit_val(wqe, 8, temp); 2677 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 2678 set_64bit_val(wqe, 40, 2679 FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_SQ_IDX, info->err_sq_idx)); 2680 set_64bit_val(wqe, 48, 2681 FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_RQ_IDX, info->err_rq_idx)); 2682 } 2683 2684 hdr = qp->qp_uk.qp_id | 2685 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) | 2686 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) | 2687 FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) | 2688 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) | 2689 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) | 2690 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2691 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 2692 hdr |= FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_VALID, info->err_sq_idx_valid) | 2693 FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_RQ_IDX_VALID, info->err_rq_idx_valid); 2694 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2695 2696 set_64bit_val(wqe, 24, hdr); 2697 2698 print_hex_dump_debug("WQE: QP_FLUSH WQE", DUMP_PREFIX_OFFSET, 16, 8, 2699 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2700 if (post_sq) 2701 irdma_sc_cqp_post_sq(cqp); 2702 2703 return 0; 2704 } 2705 2706 /** 2707 * irdma_sc_gen_ae - generate AE, uses flush WQE CQP OP 2708 * @qp: sc qp 2709 * @info: gen ae information 2710 * @scratch: u64 saved to be used during cqp completion 2711 * @post_sq: flag for cqp db to ring 2712 */ 2713 static int irdma_sc_gen_ae(struct irdma_sc_qp *qp, 2714 struct irdma_gen_ae_info *info, u64 scratch, 2715 bool post_sq) 2716 { 2717 u64 temp; 2718 __le64 *wqe; 2719 struct irdma_sc_cqp *cqp; 2720 u64 hdr; 2721 2722 cqp = qp->pd->dev->cqp; 2723 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2724 if (!wqe) 2725 return -ENOMEM; 2726 2727 temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2728 info->ae_src); 2729 set_64bit_val(wqe, 8, temp); 2730 2731 hdr = qp->qp_uk.qp_id | FIELD_PREP(IRDMA_CQPSQ_OPCODE, 2732 IRDMA_CQP_OP_GEN_AE) | 2733 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) | 2734 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2735 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2736 2737 set_64bit_val(wqe, 24, hdr); 2738 2739 print_hex_dump_debug("WQE: GEN_AE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2740 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2741 if (post_sq) 2742 irdma_sc_cqp_post_sq(cqp); 2743 2744 return 0; 2745 } 2746 2747 /*** irdma_sc_qp_upload_context - upload qp's context 2748 * @dev: sc device struct 2749 * @info: upload context info ptr for return 2750 * @scratch: u64 saved to be used during cqp completion 2751 * @post_sq: flag for cqp db to ring 2752 */ 2753 static int irdma_sc_qp_upload_context(struct irdma_sc_dev *dev, 2754 struct irdma_upload_context_info *info, 2755 u64 scratch, bool post_sq) 2756 { 2757 __le64 *wqe; 2758 struct irdma_sc_cqp *cqp; 2759 u64 hdr; 2760 2761 cqp = dev->cqp; 2762 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2763 if (!wqe) 2764 return -ENOMEM; 2765 2766 set_64bit_val(wqe, 16, info->buf_pa); 2767 2768 hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) | 2769 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) | 2770 FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) | 2771 FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) | 2772 FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) | 2773 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2774 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2775 2776 set_64bit_val(wqe, 24, hdr); 2777 2778 print_hex_dump_debug("WQE: QP_UPLOAD_CTX WQE", DUMP_PREFIX_OFFSET, 16, 2779 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2780 if (post_sq) 2781 irdma_sc_cqp_post_sq(cqp); 2782 2783 return 0; 2784 } 2785 2786 /** 2787 * irdma_sc_manage_push_page - Handle push page 2788 * @cqp: struct for cqp hw 2789 * @info: push page info 2790 * @scratch: u64 saved to be used during cqp completion 2791 * @post_sq: flag for cqp db to ring 2792 */ 2793 static int irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp, 2794 struct irdma_cqp_manage_push_page_info *info, 2795 u64 scratch, bool post_sq) 2796 { 2797 __le64 *wqe; 2798 u64 hdr; 2799 2800 if (info->free_page && 2801 info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages) 2802 return -EINVAL; 2803 2804 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2805 if (!wqe) 2806 return -ENOMEM; 2807 2808 set_64bit_val(wqe, 16, info->qs_handle); 2809 hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) | 2810 FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) | 2811 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) | 2812 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 2813 FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page); 2814 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2815 2816 set_64bit_val(wqe, 24, hdr); 2817 2818 print_hex_dump_debug("WQE: MANAGE_PUSH_PAGES WQE", DUMP_PREFIX_OFFSET, 2819 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2820 if (post_sq) 2821 irdma_sc_cqp_post_sq(cqp); 2822 2823 return 0; 2824 } 2825 2826 /** 2827 * irdma_sc_suspend_qp - suspend qp for param change 2828 * @cqp: struct for cqp hw 2829 * @qp: sc qp struct 2830 * @scratch: u64 saved to be used during cqp completion 2831 */ 2832 static int irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp, 2833 u64 scratch) 2834 { 2835 u64 hdr; 2836 __le64 *wqe; 2837 2838 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2839 if (!wqe) 2840 return -ENOMEM; 2841 2842 hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) | 2843 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) | 2844 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2845 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2846 2847 set_64bit_val(wqe, 24, hdr); 2848 2849 print_hex_dump_debug("WQE: SUSPEND_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2850 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2851 irdma_sc_cqp_post_sq(cqp); 2852 2853 return 0; 2854 } 2855 2856 /** 2857 * irdma_sc_resume_qp - resume qp after suspend 2858 * @cqp: struct for cqp hw 2859 * @qp: sc qp struct 2860 * @scratch: u64 saved to be used during cqp completion 2861 */ 2862 static int irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp, 2863 u64 scratch) 2864 { 2865 u64 hdr; 2866 __le64 *wqe; 2867 2868 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2869 if (!wqe) 2870 return -ENOMEM; 2871 2872 set_64bit_val(wqe, 16, 2873 FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle)); 2874 2875 hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) | 2876 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) | 2877 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2878 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2879 2880 set_64bit_val(wqe, 24, hdr); 2881 2882 print_hex_dump_debug("WQE: RESUME_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2883 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2884 irdma_sc_cqp_post_sq(cqp); 2885 2886 return 0; 2887 } 2888 2889 /** 2890 * irdma_sc_cq_init - initialize completion q 2891 * @cq: cq struct 2892 * @info: cq initialization info 2893 */ 2894 int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info) 2895 { 2896 u32 pble_obj_cnt; 2897 2898 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 2899 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 2900 return -EINVAL; 2901 2902 cq->cq_pa = info->cq_base_pa; 2903 cq->dev = info->dev; 2904 cq->ceq_id = info->ceq_id; 2905 info->cq_uk_init_info.cqe_alloc_db = cq->dev->cq_arm_db; 2906 info->cq_uk_init_info.cq_ack_db = cq->dev->cq_ack_db; 2907 irdma_uk_cq_init(&cq->cq_uk, &info->cq_uk_init_info); 2908 2909 cq->virtual_map = info->virtual_map; 2910 cq->pbl_chunk_size = info->pbl_chunk_size; 2911 cq->ceqe_mask = info->ceqe_mask; 2912 cq->cq_type = (info->type) ? info->type : IRDMA_CQ_TYPE_IWARP; 2913 cq->shadow_area_pa = info->shadow_area_pa; 2914 cq->shadow_read_threshold = info->shadow_read_threshold; 2915 cq->ceq_id_valid = info->ceq_id_valid; 2916 cq->tph_en = info->tph_en; 2917 cq->tph_val = info->tph_val; 2918 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 2919 cq->vsi = info->vsi; 2920 2921 return 0; 2922 } 2923 2924 /** 2925 * irdma_sc_cq_create - create completion q 2926 * @cq: cq struct 2927 * @scratch: u64 saved to be used during cqp completion 2928 * @check_overflow: flag for overflow check 2929 * @post_sq: flag for cqp db to ring 2930 */ 2931 static int irdma_sc_cq_create(struct irdma_sc_cq *cq, u64 scratch, 2932 bool check_overflow, bool post_sq) 2933 { 2934 __le64 *wqe; 2935 struct irdma_sc_cqp *cqp; 2936 u64 hdr; 2937 2938 cqp = cq->dev->cqp; 2939 if (cq->cq_uk.cq_id >= cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt) 2940 return -EINVAL; 2941 2942 if (cq->ceq_id >= cq->dev->hmc_fpm_misc.max_ceqs) 2943 return -EINVAL; 2944 2945 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2946 if (!wqe) 2947 return -ENOMEM; 2948 2949 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 2950 set_64bit_val(wqe, 8, cq->cq_uk.cq_id); 2951 set_64bit_val(wqe, 16, 2952 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 2953 set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa)); 2954 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2955 set_64bit_val(wqe, 48, 2956 FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX, (cq->virtual_map ? cq->first_pm_pbl_idx : 0))); 2957 set_64bit_val(wqe, 56, 2958 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 2959 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 2960 2961 hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) | 2962 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 2963 IRDMA_CQPSQ_CQ_CEQID) | 2964 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 2965 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 2966 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) | 2967 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 2968 FIELD_PREP(IRDMA_CQPSQ_CQ_CQID_HIGH, cq->cq_uk.cq_id >> 22) | 2969 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQID_HIGH, 2970 (cq->ceq_id_valid ? cq->ceq_id : 0) >> 10) | 2971 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2972 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 2973 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2974 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 2975 cq->cq_uk.avoid_mem_cflct) | 2976 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2977 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2978 2979 set_64bit_val(wqe, 24, hdr); 2980 2981 print_hex_dump_debug("WQE: CQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2982 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2983 if (post_sq) 2984 irdma_sc_cqp_post_sq(cqp); 2985 2986 return 0; 2987 } 2988 2989 /** 2990 * irdma_sc_cq_destroy - destroy completion q 2991 * @cq: cq struct 2992 * @scratch: u64 saved to be used during cqp completion 2993 * @post_sq: flag for cqp db to ring 2994 */ 2995 int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq) 2996 { 2997 struct irdma_sc_cqp *cqp; 2998 __le64 *wqe; 2999 u64 hdr; 3000 3001 cqp = cq->dev->cqp; 3002 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3003 if (!wqe) 3004 return -ENOMEM; 3005 3006 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 3007 set_64bit_val(wqe, 8, cq->cq_uk.cq_id); 3008 set_64bit_val(wqe, 40, cq->shadow_area_pa); 3009 set_64bit_val(wqe, 48, 3010 (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); 3011 3012 hdr = cq->cq_uk.cq_id | 3013 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 3014 IRDMA_CQPSQ_CQ_CEQID) | 3015 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 3016 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 3017 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 3018 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 3019 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 3020 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 3021 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) | 3022 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3023 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3024 3025 set_64bit_val(wqe, 24, hdr); 3026 3027 print_hex_dump_debug("WQE: CQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 3028 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3029 if (post_sq) 3030 irdma_sc_cqp_post_sq(cqp); 3031 3032 return 0; 3033 } 3034 3035 /** 3036 * irdma_sc_cq_resize - set resized cq buffer info 3037 * @cq: resized cq 3038 * @info: resized cq buffer info 3039 */ 3040 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info) 3041 { 3042 cq->virtual_map = info->virtual_map; 3043 cq->cq_pa = info->cq_pa; 3044 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 3045 cq->pbl_chunk_size = info->pbl_chunk_size; 3046 irdma_uk_cq_resize(&cq->cq_uk, info->cq_base, info->cq_size); 3047 } 3048 3049 /** 3050 * irdma_sc_cq_modify - modify a Completion Queue 3051 * @cq: cq struct 3052 * @info: modification info struct 3053 * @scratch: u64 saved to be used during cqp completion 3054 * @post_sq: flag to post to sq 3055 */ 3056 static int irdma_sc_cq_modify(struct irdma_sc_cq *cq, 3057 struct irdma_modify_cq_info *info, u64 scratch, 3058 bool post_sq) 3059 { 3060 struct irdma_sc_cqp *cqp; 3061 __le64 *wqe; 3062 u64 hdr; 3063 u32 pble_obj_cnt; 3064 3065 pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 3066 if (info->cq_resize && info->virtual_map && 3067 info->first_pm_pbl_idx >= pble_obj_cnt) 3068 return -EINVAL; 3069 3070 cqp = cq->dev->cqp; 3071 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3072 if (!wqe) 3073 return -ENOMEM; 3074 3075 set_64bit_val(wqe, 0, info->cq_size); 3076 set_64bit_val(wqe, 8, cq->cq_uk.cq_id); 3077 set_64bit_val(wqe, 16, 3078 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold)); 3079 set_64bit_val(wqe, 32, info->cq_pa); 3080 set_64bit_val(wqe, 40, cq->shadow_area_pa); 3081 set_64bit_val(wqe, 48, info->first_pm_pbl_idx); 3082 set_64bit_val(wqe, 56, 3083 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 3084 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 3085 3086 hdr = cq->cq_uk.cq_id | 3087 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) | 3088 FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) | 3089 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) | 3090 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) | 3091 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) | 3092 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 3093 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 3094 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 3095 cq->cq_uk.avoid_mem_cflct) | 3096 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3097 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3098 3099 set_64bit_val(wqe, 24, hdr); 3100 3101 print_hex_dump_debug("WQE: CQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 3102 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3103 if (post_sq) 3104 irdma_sc_cqp_post_sq(cqp); 3105 3106 return 0; 3107 } 3108 3109 /** 3110 * irdma_sc_get_decoded_ird_size_gen_3 - get decoded IRD size for GEN 3 3111 * @ird_enc: IRD encoding 3112 * IRD size defaults to a value of 4 in case of invalid input. 3113 */ 3114 static u16 irdma_sc_get_decoded_ird_size_gen_3(u8 ird_enc) 3115 { 3116 switch (ird_enc) { 3117 case IRDMA_IRD_HW_SIZE_4096_GEN3: 3118 return 4096; 3119 case IRDMA_IRD_HW_SIZE_2048_GEN3: 3120 return 2048; 3121 case IRDMA_IRD_HW_SIZE_1024_GEN3: 3122 return 1024; 3123 case IRDMA_IRD_HW_SIZE_512_GEN3: 3124 return 512; 3125 case IRDMA_IRD_HW_SIZE_256_GEN3: 3126 return 256; 3127 case IRDMA_IRD_HW_SIZE_128_GEN3: 3128 return 128; 3129 case IRDMA_IRD_HW_SIZE_64_GEN3: 3130 return 64; 3131 case IRDMA_IRD_HW_SIZE_32_GEN3: 3132 return 32; 3133 case IRDMA_IRD_HW_SIZE_16_GEN3: 3134 return 16; 3135 case IRDMA_IRD_HW_SIZE_8_GEN3: 3136 return 8; 3137 case IRDMA_IRD_HW_SIZE_4_GEN3: 3138 return 4; 3139 default: 3140 return 4; 3141 } 3142 } 3143 3144 /** 3145 * irdma_check_cqp_progress - check cqp processing progress 3146 * @timeout: timeout info struct 3147 * @dev: sc device struct 3148 */ 3149 void irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout, struct irdma_sc_dev *dev) 3150 { 3151 u64 completed_ops = atomic64_read(&dev->cqp->completed_ops); 3152 3153 if (timeout->compl_cqp_cmds != completed_ops) { 3154 timeout->compl_cqp_cmds = completed_ops; 3155 timeout->count = 0; 3156 } else if (timeout->compl_cqp_cmds != dev->cqp->requested_ops) { 3157 timeout->count++; 3158 } 3159 } 3160 3161 /** 3162 * irdma_get_cqp_reg_info - get head and tail for cqp using registers 3163 * @cqp: struct for cqp hw 3164 * @val: cqp tail register value 3165 * @tail: wqtail register value 3166 * @error: cqp processing err 3167 */ 3168 static inline void irdma_get_cqp_reg_info(struct irdma_sc_cqp *cqp, u32 *val, 3169 u32 *tail, u32 *error) 3170 { 3171 *val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]); 3172 *tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, *val); 3173 *error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, *val); 3174 } 3175 3176 /** 3177 * irdma_sc_cqp_def_cmpl_ae_handler - remove completed requests from pending list 3178 * @dev: sc device struct 3179 * @info: AE entry info 3180 * @first: true if this is the first call to this handler for given AEQE 3181 * @scratch: (out) scratch entry pointer 3182 * @sw_def_info: (in/out) SW ticket value for this AE 3183 * 3184 * In case of AE_DEF_CMPL event, this function should be called in a loop 3185 * until it returns NULL-ptr via scratch. 3186 * For each call, it looks for a matching CQP request on pending list, 3187 * removes it from the list and returns the pointer to the associated scratch 3188 * entry. 3189 * If this is the first call to this function for given AEQE, sw_def_info 3190 * value is not used to find matching requests. Instead, it is populated 3191 * with the value from the first matching cqp_request on the list. 3192 * For subsequent calls, ooo_op->sw_def_info need to match the value passed 3193 * by a caller. 3194 * 3195 * Return: scratch entry pointer for cqp_request to be released or NULL 3196 * if no matching request is found. 3197 */ 3198 void irdma_sc_cqp_def_cmpl_ae_handler(struct irdma_sc_dev *dev, 3199 struct irdma_aeqe_info *info, 3200 bool first, u64 *scratch, 3201 u32 *sw_def_info) 3202 { 3203 struct irdma_ooo_cqp_op *ooo_op; 3204 unsigned long flags; 3205 3206 *scratch = 0; 3207 3208 spin_lock_irqsave(&dev->cqp->ooo_list_lock, flags); 3209 list_for_each_entry(ooo_op, &dev->cqp->ooo_pnd, list_entry) { 3210 if (ooo_op->deferred && 3211 ((first && ooo_op->def_info == info->def_info) || 3212 (!first && ooo_op->sw_def_info == *sw_def_info))) { 3213 *sw_def_info = ooo_op->sw_def_info; 3214 *scratch = ooo_op->scratch; 3215 3216 list_move(&ooo_op->list_entry, &dev->cqp->ooo_avail); 3217 atomic64_inc(&dev->cqp->completed_ops); 3218 3219 break; 3220 } 3221 } 3222 spin_unlock_irqrestore(&dev->cqp->ooo_list_lock, flags); 3223 3224 if (first && !*scratch) 3225 ibdev_dbg(to_ibdev(dev), 3226 "AEQ: deferred completion with unknown ticket: def_info 0x%x\n", 3227 info->def_info); 3228 } 3229 3230 /** 3231 * irdma_sc_cqp_cleanup_handler - remove requests from pending list 3232 * @dev: sc device struct 3233 * 3234 * This function should be called in a loop from irdma_cleanup_pending_cqp_op. 3235 * For each call, it returns first CQP request on pending list, removes it 3236 * from the list and returns the pointer to the associated scratch entry. 3237 * 3238 * Return: scratch entry pointer for cqp_request to be released or NULL 3239 * if pending list is empty. 3240 */ 3241 u64 irdma_sc_cqp_cleanup_handler(struct irdma_sc_dev *dev) 3242 { 3243 struct irdma_ooo_cqp_op *ooo_op; 3244 u64 scratch = 0; 3245 3246 list_for_each_entry(ooo_op, &dev->cqp->ooo_pnd, list_entry) { 3247 scratch = ooo_op->scratch; 3248 3249 list_del(&ooo_op->list_entry); 3250 list_add(&ooo_op->list_entry, &dev->cqp->ooo_avail); 3251 atomic64_inc(&dev->cqp->completed_ops); 3252 3253 break; 3254 } 3255 3256 return scratch; 3257 } 3258 3259 /** 3260 * irdma_cqp_poll_registers - poll cqp registers 3261 * @cqp: struct for cqp hw 3262 * @tail: wqtail register value 3263 * @count: how many times to try for completion 3264 */ 3265 static int irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp, u32 tail, 3266 u32 count) 3267 { 3268 u32 i = 0; 3269 u32 newtail, error, val; 3270 3271 while (i++ < count) { 3272 irdma_get_cqp_reg_info(cqp, &val, &newtail, &error); 3273 if (error) { 3274 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3275 ibdev_dbg(to_ibdev(cqp->dev), 3276 "CQP: CQPERRCODES error_code[x%08X]\n", 3277 error); 3278 return -EIO; 3279 } 3280 if (newtail != tail) { 3281 /* SUCCESS */ 3282 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 3283 atomic64_inc(&cqp->completed_ops); 3284 return 0; 3285 } 3286 udelay(cqp->dev->hw_attrs.max_sleep_count); 3287 } 3288 3289 return -ETIMEDOUT; 3290 } 3291 3292 /** 3293 * irdma_sc_decode_fpm_commit - decode a 64 bit value into count and base 3294 * @dev: sc device struct 3295 * @buf: pointer to commit buffer 3296 * @buf_idx: buffer index 3297 * @obj_info: object info pointer 3298 * @rsrc_idx: indexs of memory resource 3299 */ 3300 static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 *buf, 3301 u32 buf_idx, struct irdma_hmc_obj_info *obj_info, 3302 u32 rsrc_idx) 3303 { 3304 u64 temp; 3305 3306 get_64bit_val(buf, buf_idx, &temp); 3307 3308 switch (rsrc_idx) { 3309 case IRDMA_HMC_IW_QP: 3310 obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp); 3311 break; 3312 case IRDMA_HMC_IW_CQ: 3313 obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT); 3314 break; 3315 case IRDMA_HMC_IW_APBVT_ENTRY: 3316 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) 3317 obj_info[rsrc_idx].cnt = 1; 3318 else 3319 obj_info[rsrc_idx].cnt = 0; 3320 break; 3321 default: 3322 obj_info[rsrc_idx].cnt = (u32)temp; 3323 break; 3324 } 3325 3326 obj_info[rsrc_idx].base = (temp >> IRDMA_COMMIT_FPM_BASE_S) * 512; 3327 3328 return temp; 3329 } 3330 3331 /** 3332 * irdma_sc_parse_fpm_commit_buf - parse fpm commit buffer 3333 * @dev: pointer to dev struct 3334 * @buf: ptr to fpm commit buffer 3335 * @info: ptr to irdma_hmc_obj_info struct 3336 * @sd: number of SDs for HMC objects 3337 * 3338 * parses fpm commit info and copy base value 3339 * of hmc objects in hmc_info 3340 */ 3341 static void 3342 irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf, 3343 struct irdma_hmc_obj_info *info, u32 *sd) 3344 { 3345 u64 size; 3346 u32 i; 3347 u64 max_base = 0; 3348 u32 last_hmc_obj = 0; 3349 3350 irdma_sc_decode_fpm_commit(dev, buf, 0, info, 3351 IRDMA_HMC_IW_QP); 3352 irdma_sc_decode_fpm_commit(dev, buf, 8, info, 3353 IRDMA_HMC_IW_CQ); 3354 irdma_sc_decode_fpm_commit(dev, buf, 16, info, 3355 IRDMA_HMC_IW_SRQ); 3356 irdma_sc_decode_fpm_commit(dev, buf, 24, info, 3357 IRDMA_HMC_IW_HTE); 3358 irdma_sc_decode_fpm_commit(dev, buf, 32, info, 3359 IRDMA_HMC_IW_ARP); 3360 irdma_sc_decode_fpm_commit(dev, buf, 40, info, 3361 IRDMA_HMC_IW_APBVT_ENTRY); 3362 irdma_sc_decode_fpm_commit(dev, buf, 48, info, 3363 IRDMA_HMC_IW_MR); 3364 irdma_sc_decode_fpm_commit(dev, buf, 56, info, 3365 IRDMA_HMC_IW_XF); 3366 irdma_sc_decode_fpm_commit(dev, buf, 64, info, 3367 IRDMA_HMC_IW_XFFL); 3368 irdma_sc_decode_fpm_commit(dev, buf, 72, info, 3369 IRDMA_HMC_IW_Q1); 3370 irdma_sc_decode_fpm_commit(dev, buf, 80, info, 3371 IRDMA_HMC_IW_Q1FL); 3372 irdma_sc_decode_fpm_commit(dev, buf, 88, info, 3373 IRDMA_HMC_IW_TIMER); 3374 irdma_sc_decode_fpm_commit(dev, buf, 112, info, 3375 IRDMA_HMC_IW_PBLE); 3376 /* skipping RSVD. */ 3377 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 3378 irdma_sc_decode_fpm_commit(dev, buf, 96, info, 3379 IRDMA_HMC_IW_FSIMC); 3380 irdma_sc_decode_fpm_commit(dev, buf, 104, info, 3381 IRDMA_HMC_IW_FSIAV); 3382 irdma_sc_decode_fpm_commit(dev, buf, 128, info, 3383 IRDMA_HMC_IW_RRF); 3384 irdma_sc_decode_fpm_commit(dev, buf, 136, info, 3385 IRDMA_HMC_IW_RRFFL); 3386 irdma_sc_decode_fpm_commit(dev, buf, 144, info, 3387 IRDMA_HMC_IW_HDR); 3388 irdma_sc_decode_fpm_commit(dev, buf, 152, info, 3389 IRDMA_HMC_IW_MD); 3390 if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) { 3391 irdma_sc_decode_fpm_commit(dev, buf, 160, info, 3392 IRDMA_HMC_IW_OOISC); 3393 irdma_sc_decode_fpm_commit(dev, buf, 168, info, 3394 IRDMA_HMC_IW_OOISCFFL); 3395 } 3396 } 3397 3398 /* searching for the last object in HMC to find the size of the HMC area. */ 3399 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { 3400 if (info[i].base > max_base && info[i].cnt) { 3401 max_base = info[i].base; 3402 last_hmc_obj = i; 3403 } 3404 } 3405 3406 size = info[last_hmc_obj].cnt * info[last_hmc_obj].size + 3407 info[last_hmc_obj].base; 3408 3409 if (size & 0x1FFFFF) 3410 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */ 3411 else 3412 *sd = (u32)(size >> 21); 3413 3414 } 3415 3416 /** 3417 * irdma_sc_decode_fpm_query() - Decode a 64 bit value into max count and size 3418 * @buf: ptr to fpm query buffer 3419 * @buf_idx: index into buf 3420 * @obj_info: ptr to irdma_hmc_obj_info struct 3421 * @rsrc_idx: resource index into info 3422 * 3423 * Decode a 64 bit value from fpm query buffer into max count and size 3424 */ 3425 static u64 irdma_sc_decode_fpm_query(__le64 *buf, u32 buf_idx, 3426 struct irdma_hmc_obj_info *obj_info, 3427 u32 rsrc_idx) 3428 { 3429 u64 temp; 3430 u32 size; 3431 3432 get_64bit_val(buf, buf_idx, &temp); 3433 obj_info[rsrc_idx].max_cnt = (u32)temp; 3434 size = (u32)(temp >> 32); 3435 obj_info[rsrc_idx].size = BIT_ULL(size); 3436 3437 return temp; 3438 } 3439 3440 /** 3441 * irdma_sc_parse_fpm_query_buf() - parses fpm query buffer 3442 * @dev: ptr to shared code device 3443 * @buf: ptr to fpm query buffer 3444 * @hmc_info: ptr to irdma_hmc_obj_info struct 3445 * @hmc_fpm_misc: ptr to fpm data 3446 * 3447 * parses fpm query buffer and copy max_cnt and 3448 * size value of hmc objects in hmc_info 3449 */ 3450 static int irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf, 3451 struct irdma_hmc_info *hmc_info, 3452 struct irdma_hmc_fpm_misc *hmc_fpm_misc) 3453 { 3454 struct irdma_hmc_obj_info *obj_info; 3455 u8 ird_encoding; 3456 u64 temp; 3457 u32 size; 3458 u16 max_pe_sds; 3459 3460 obj_info = hmc_info->hmc_obj; 3461 3462 get_64bit_val(buf, 0, &temp); 3463 hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp); 3464 3465 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 3466 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS_GEN3, temp); 3467 else 3468 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp); 3469 3470 /* Reduce SD count for unprivleged functions by 1 to account for PBLE 3471 * backing page rounding 3472 */ 3473 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2 && 3474 (hmc_info->hmc_fn_id >= dev->hw_attrs.first_hw_vf_fpm_id || 3475 !dev->privileged)) 3476 max_pe_sds--; 3477 3478 hmc_fpm_misc->max_sds = max_pe_sds; 3479 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index; 3480 get_64bit_val(buf, 8, &temp); 3481 obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp); 3482 size = (u32)(temp >> 32); 3483 obj_info[IRDMA_HMC_IW_QP].size = BIT_ULL(size); 3484 3485 get_64bit_val(buf, 16, &temp); 3486 obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp); 3487 size = (u32)(temp >> 32); 3488 obj_info[IRDMA_HMC_IW_CQ].size = BIT_ULL(size); 3489 3490 irdma_sc_decode_fpm_query(buf, 24, obj_info, IRDMA_HMC_IW_SRQ); 3491 irdma_sc_decode_fpm_query(buf, 32, obj_info, IRDMA_HMC_IW_HTE); 3492 irdma_sc_decode_fpm_query(buf, 40, obj_info, IRDMA_HMC_IW_ARP); 3493 3494 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 3495 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 0; 3496 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 0; 3497 } else { 3498 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 8192; 3499 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 1; 3500 } 3501 3502 irdma_sc_decode_fpm_query(buf, 48, obj_info, IRDMA_HMC_IW_MR); 3503 irdma_sc_decode_fpm_query(buf, 56, obj_info, IRDMA_HMC_IW_XF); 3504 3505 get_64bit_val(buf, 64, &temp); 3506 obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp; 3507 obj_info[IRDMA_HMC_IW_XFFL].size = 4; 3508 hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp); 3509 if (obj_info[IRDMA_HMC_IW_XF].max_cnt && !hmc_fpm_misc->xf_block_size) 3510 return -EINVAL; 3511 3512 irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1); 3513 get_64bit_val(buf, 80, &temp); 3514 obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp; 3515 obj_info[IRDMA_HMC_IW_Q1FL].size = 4; 3516 3517 hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp); 3518 if (!hmc_fpm_misc->q1_block_size) 3519 return -EINVAL; 3520 3521 irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER); 3522 3523 get_64bit_val(buf, 112, &temp); 3524 obj_info[IRDMA_HMC_IW_PBLE].max_cnt = (u32)temp; 3525 obj_info[IRDMA_HMC_IW_PBLE].size = 8; 3526 3527 get_64bit_val(buf, 120, &temp); 3528 hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp); 3529 hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp); 3530 hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp); 3531 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, 3532 dev->feature_info[IRDMA_FTN_FLAGS])) { 3533 ird_encoding = (u8)FIELD_GET(IRDMA_QUERY_FPM_MAX_IRD, temp); 3534 hmc_fpm_misc->ird = 3535 irdma_sc_get_decoded_ird_size_gen_3(ird_encoding) / 2; 3536 dev->hw_attrs.max_hw_ird = hmc_fpm_misc->ird; 3537 dev->hw_attrs.max_hw_ord = hmc_fpm_misc->ird; 3538 } 3539 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 3540 return 0; 3541 irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC); 3542 irdma_sc_decode_fpm_query(buf, 104, obj_info, IRDMA_HMC_IW_FSIAV); 3543 irdma_sc_decode_fpm_query(buf, 128, obj_info, IRDMA_HMC_IW_RRF); 3544 3545 get_64bit_val(buf, 136, &temp); 3546 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp; 3547 obj_info[IRDMA_HMC_IW_RRFFL].size = 4; 3548 hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp); 3549 if (!hmc_fpm_misc->rrf_block_size && 3550 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt) 3551 return -EINVAL; 3552 3553 irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR); 3554 irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD); 3555 3556 if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) { 3557 irdma_sc_decode_fpm_query(buf, 160, obj_info, IRDMA_HMC_IW_OOISC); 3558 3559 get_64bit_val(buf, 168, &temp); 3560 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp; 3561 obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4; 3562 hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp); 3563 if (!hmc_fpm_misc->ooiscf_block_size && 3564 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt) 3565 return -EINVAL; 3566 } 3567 3568 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 3569 get_64bit_val(buf, 176, &temp); 3570 hmc_fpm_misc->loc_mem_pages = (u32)FIELD_GET(IRDMA_QUERY_FPM_LOC_MEM_PAGES, temp); 3571 if (!hmc_fpm_misc->loc_mem_pages) 3572 return -EINVAL; 3573 3574 get_64bit_val(buf, 184, &temp); 3575 if (temp) { 3576 hmc_fpm_misc->fw_scratch_buf0.size = temp; 3577 hmc_fpm_misc->fw_scratch_buf0.va = 3578 dma_alloc_coherent(dev->hw->device, 3579 hmc_fpm_misc->fw_scratch_buf0.size, 3580 &hmc_fpm_misc->fw_scratch_buf0.pa, 3581 GFP_KERNEL); 3582 3583 if (!hmc_fpm_misc->fw_scratch_buf0.va) { 3584 hmc_fpm_misc->fw_scratch_buf0.size = 0; 3585 return -ENOMEM; 3586 } 3587 } 3588 get_64bit_val(buf, 192, &temp); 3589 if (temp) { 3590 hmc_fpm_misc->fw_scratch_buf1.size = temp; 3591 hmc_fpm_misc->fw_scratch_buf1.va = 3592 dma_alloc_coherent(dev->hw->device, 3593 hmc_fpm_misc->fw_scratch_buf1.size, 3594 &hmc_fpm_misc->fw_scratch_buf1.pa, 3595 GFP_KERNEL); 3596 3597 if (!hmc_fpm_misc->fw_scratch_buf1.va) { 3598 hmc_fpm_misc->fw_scratch_buf1.size = 0; 3599 dma_free_coherent(dev->hw->device, 3600 hmc_fpm_misc->fw_scratch_buf0.size, 3601 hmc_fpm_misc->fw_scratch_buf0.va, 3602 hmc_fpm_misc->fw_scratch_buf0.pa); 3603 hmc_fpm_misc->fw_scratch_buf0.va = NULL; 3604 hmc_fpm_misc->fw_scratch_buf0.size = 0; 3605 return -ENOMEM; 3606 } 3607 } 3608 } 3609 3610 return 0; 3611 } 3612 3613 /** 3614 * irdma_sc_cqp_init - Initialize buffers for a control Queue Pair 3615 * @cqp: IWARP control queue pair pointer 3616 * @info: IWARP control queue pair init info pointer 3617 * 3618 * Initializes the object and context buffers for a control Queue Pair. 3619 */ 3620 int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp, 3621 struct irdma_cqp_init_info *info) 3622 { 3623 struct irdma_ooo_cqp_op *ooo_op; 3624 u32 num_ooo_ops; 3625 u8 hw_sq_size; 3626 3627 if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 || 3628 info->sq_size < IRDMA_CQP_SW_SQSIZE_4 || 3629 ((info->sq_size & (info->sq_size - 1)))) 3630 return -EINVAL; 3631 3632 hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size, 3633 IRDMA_QUEUE_TYPE_CQP); 3634 cqp->size = sizeof(*cqp); 3635 cqp->sq_size = info->sq_size; 3636 cqp->hw_sq_size = hw_sq_size; 3637 cqp->sq_base = info->sq; 3638 cqp->host_ctx = info->host_ctx; 3639 cqp->sq_pa = info->sq_pa; 3640 cqp->host_ctx_pa = info->host_ctx_pa; 3641 cqp->dev = info->dev; 3642 cqp->struct_ver = info->struct_ver; 3643 cqp->hw_maj_ver = info->hw_maj_ver; 3644 cqp->hw_min_ver = info->hw_min_ver; 3645 cqp->scratch_array = info->scratch_array; 3646 cqp->polarity = 0; 3647 cqp->en_datacenter_tcp = info->en_datacenter_tcp; 3648 cqp->ena_vf_count = info->ena_vf_count; 3649 cqp->hmc_profile = info->hmc_profile; 3650 cqp->ceqs_per_vf = info->ceqs_per_vf; 3651 cqp->disable_packed = info->disable_packed; 3652 cqp->rocev2_rto_policy = info->rocev2_rto_policy; 3653 cqp->protocol_used = info->protocol_used; 3654 memcpy(&cqp->dcqcn_params, &info->dcqcn_params, sizeof(cqp->dcqcn_params)); 3655 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 3656 cqp->ooisc_blksize = info->ooisc_blksize; 3657 cqp->rrsp_blksize = info->rrsp_blksize; 3658 cqp->q1_blksize = info->q1_blksize; 3659 cqp->xmit_blksize = info->xmit_blksize; 3660 cqp->blksizes_valid = info->blksizes_valid; 3661 cqp->ts_shift = info->ts_shift; 3662 cqp->ts_override = info->ts_override; 3663 cqp->en_fine_grained_timers = info->en_fine_grained_timers; 3664 cqp->pe_en_vf_cnt = info->pe_en_vf_cnt; 3665 cqp->ooo_op_array = info->ooo_op_array; 3666 /* initialize the OOO lists */ 3667 INIT_LIST_HEAD(&cqp->ooo_avail); 3668 INIT_LIST_HEAD(&cqp->ooo_pnd); 3669 if (cqp->ooo_op_array) { 3670 /* Populate avail list entries */ 3671 for (num_ooo_ops = 0, ooo_op = info->ooo_op_array; 3672 num_ooo_ops < cqp->sq_size; 3673 num_ooo_ops++, ooo_op++) 3674 list_add(&ooo_op->list_entry, &cqp->ooo_avail); 3675 } 3676 } 3677 info->dev->cqp = cqp; 3678 3679 IRDMA_RING_INIT(cqp->sq_ring, cqp->sq_size); 3680 cqp->last_def_cmpl_ticket = 0; 3681 cqp->sw_def_cmpl_ticket = 0; 3682 cqp->requested_ops = 0; 3683 atomic64_set(&cqp->completed_ops, 0); 3684 /* for the cqp commands backlog. */ 3685 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); 3686 3687 writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]); 3688 if (cqp->dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) { 3689 writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]); 3690 writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3691 } 3692 3693 ibdev_dbg(to_ibdev(cqp->dev), 3694 "WQE: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%p] cqp[%p] polarity[x%04x]\n", 3695 cqp->sq_size, cqp->hw_sq_size, cqp->sq_base, 3696 (u64 *)(uintptr_t)cqp->sq_pa, cqp, cqp->polarity); 3697 return 0; 3698 } 3699 3700 /** 3701 * irdma_sc_cqp_create - create cqp during bringup 3702 * @cqp: struct for cqp hw 3703 * @maj_err: If error, major err number 3704 * @min_err: If error, minor err number 3705 */ 3706 int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err) 3707 { 3708 u64 temp; 3709 u8 hw_rev; 3710 u32 cnt = 0, p1, p2, val = 0, err_code; 3711 int ret_code; 3712 3713 hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev; 3714 cqp->sdbuf.size = ALIGN(IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size, 3715 IRDMA_SD_BUF_ALIGNMENT); 3716 cqp->sdbuf.va = dma_alloc_coherent(cqp->dev->hw->device, 3717 cqp->sdbuf.size, &cqp->sdbuf.pa, 3718 GFP_KERNEL); 3719 if (!cqp->sdbuf.va) 3720 return -ENOMEM; 3721 3722 spin_lock_init(&cqp->dev->cqp_lock); 3723 spin_lock_init(&cqp->ooo_list_lock); 3724 3725 temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) | 3726 FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) | 3727 FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) | 3728 FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf); 3729 if (hw_rev >= IRDMA_GEN_2) { 3730 temp |= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY, 3731 cqp->rocev2_rto_policy) | 3732 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED, 3733 cqp->protocol_used); 3734 } 3735 if (hw_rev >= IRDMA_GEN_3) 3736 temp |= FIELD_PREP(IRDMA_CQPHC_EN_FINE_GRAINED_TIMERS, 3737 cqp->en_fine_grained_timers); 3738 3739 set_64bit_val(cqp->host_ctx, 0, temp); 3740 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa); 3741 3742 temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) | 3743 FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile); 3744 3745 if (hw_rev >= IRDMA_GEN_3) 3746 temp |= FIELD_PREP(IRDMA_CQPHC_OOISC_BLKSIZE, 3747 cqp->ooisc_blksize) | 3748 FIELD_PREP(IRDMA_CQPHC_RRSP_BLKSIZE, 3749 cqp->rrsp_blksize) | 3750 FIELD_PREP(IRDMA_CQPHC_Q1_BLKSIZE, cqp->q1_blksize) | 3751 FIELD_PREP(IRDMA_CQPHC_XMIT_BLKSIZE, 3752 cqp->xmit_blksize) | 3753 FIELD_PREP(IRDMA_CQPHC_BLKSIZES_VALID, 3754 cqp->blksizes_valid) | 3755 FIELD_PREP(IRDMA_CQPHC_TIMESTAMP_OVERRIDE, 3756 cqp->ts_override) | 3757 FIELD_PREP(IRDMA_CQPHC_TS_SHIFT, cqp->ts_shift); 3758 set_64bit_val(cqp->host_ctx, 16, temp); 3759 set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp); 3760 temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) | 3761 FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver); 3762 if (hw_rev >= IRDMA_GEN_2) { 3763 temp |= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) | 3764 FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor); 3765 } 3766 set_64bit_val(cqp->host_ctx, 32, temp); 3767 set_64bit_val(cqp->host_ctx, 40, 0); 3768 temp = 0; 3769 if (hw_rev >= IRDMA_GEN_2) { 3770 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) | 3771 FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) | 3772 FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor); 3773 } 3774 set_64bit_val(cqp->host_ctx, 48, temp); 3775 temp = 0; 3776 if (hw_rev >= IRDMA_GEN_2) { 3777 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) | 3778 FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) | 3779 FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) | 3780 FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod); 3781 } 3782 set_64bit_val(cqp->host_ctx, 56, temp); 3783 print_hex_dump_debug("WQE: CQP_HOST_CTX WQE", DUMP_PREFIX_OFFSET, 16, 3784 8, cqp->host_ctx, IRDMA_CQP_CTX_SIZE * 8, false); 3785 p1 = cqp->host_ctx_pa >> 32; 3786 p2 = (u32)cqp->host_ctx_pa; 3787 3788 writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3789 writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3790 3791 do { 3792 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3793 ret_code = -ETIMEDOUT; 3794 goto err; 3795 } 3796 udelay(cqp->dev->hw_attrs.max_sleep_count); 3797 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3798 } while (!val); 3799 3800 if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) { 3801 ret_code = -EOPNOTSUPP; 3802 goto err; 3803 } 3804 3805 cqp->process_cqp_sds = irdma_update_sds_noccq; 3806 return 0; 3807 3808 err: 3809 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3810 cqp->sdbuf.va, cqp->sdbuf.pa); 3811 cqp->sdbuf.va = NULL; 3812 err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3813 *min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code); 3814 *maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code); 3815 return ret_code; 3816 } 3817 3818 /** 3819 * irdma_sc_cqp_post_sq - post of cqp's sq 3820 * @cqp: struct for cqp hw 3821 */ 3822 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp) 3823 { 3824 writel(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db); 3825 3826 ibdev_dbg(to_ibdev(cqp->dev), 3827 "WQE: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 3828 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 3829 } 3830 3831 /** 3832 * irdma_sc_cqp_get_next_send_wqe_idx - get next wqe on cqp sq 3833 * and pass back index 3834 * @cqp: CQP HW structure 3835 * @scratch: private data for CQP WQE 3836 * @wqe_idx: WQE index of CQP SQ 3837 */ 3838 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch, 3839 u32 *wqe_idx) 3840 { 3841 __le64 *wqe = NULL; 3842 int ret_code; 3843 3844 if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) { 3845 ibdev_dbg(to_ibdev(cqp->dev), 3846 "WQE: CQP SQ is full, head 0x%x tail 0x%x size 0x%x\n", 3847 cqp->sq_ring.head, cqp->sq_ring.tail, 3848 cqp->sq_ring.size); 3849 return NULL; 3850 } 3851 IRDMA_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code); 3852 if (ret_code) 3853 return NULL; 3854 3855 cqp->requested_ops++; 3856 if (!*wqe_idx) 3857 cqp->polarity = !cqp->polarity; 3858 wqe = cqp->sq_base[*wqe_idx].elem; 3859 cqp->scratch_array[*wqe_idx] = scratch; 3860 IRDMA_CQP_INIT_WQE(wqe); 3861 3862 return wqe; 3863 } 3864 3865 /** 3866 * irdma_sc_cqp_destroy - destroy cqp during close 3867 * @cqp: struct for cqp hw 3868 */ 3869 int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp) 3870 { 3871 u32 cnt = 0, val; 3872 int ret_code = 0; 3873 3874 writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3875 writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3876 do { 3877 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3878 ret_code = -ETIMEDOUT; 3879 break; 3880 } 3881 udelay(cqp->dev->hw_attrs.max_sleep_count); 3882 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3883 } while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE)); 3884 3885 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3886 cqp->sdbuf.va, cqp->sdbuf.pa); 3887 cqp->sdbuf.va = NULL; 3888 return ret_code; 3889 } 3890 3891 /** 3892 * irdma_sc_ccq_arm - enable intr for control cq 3893 * @ccq: ccq sc struct 3894 */ 3895 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq) 3896 { 3897 unsigned long flags; 3898 u64 temp_val; 3899 u16 sw_cq_sel; 3900 u8 arm_next_se; 3901 u8 arm_seq_num; 3902 3903 spin_lock_irqsave(&ccq->dev->cqp_lock, flags); 3904 get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val); 3905 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 3906 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 3907 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 3908 arm_seq_num++; 3909 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 3910 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 3911 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 3912 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1); 3913 set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val); 3914 spin_unlock_irqrestore(&ccq->dev->cqp_lock, flags); 3915 3916 writel(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db); 3917 } 3918 3919 /** 3920 * irdma_sc_process_def_cmpl - process deferred or pending completion 3921 * @cqp: CQP sc struct 3922 * @info: CQP CQE info 3923 * @wqe_idx: CQP WQE descriptor index 3924 * @def_info: deferred op ticket value or out-of-order completion id 3925 * @def_cmpl: true for deferred completion, false for pending (RCA) 3926 */ 3927 static void irdma_sc_process_def_cmpl(struct irdma_sc_cqp *cqp, 3928 struct irdma_ccq_cqe_info *info, 3929 u32 wqe_idx, u32 def_info, bool def_cmpl) 3930 { 3931 struct irdma_ooo_cqp_op *ooo_op; 3932 unsigned long flags; 3933 3934 /* Deferred and out-of-order completions share the same list of pending 3935 * completions. Since the list can be also accessed from AE handler, 3936 * it must be protected by a lock. 3937 */ 3938 spin_lock_irqsave(&cqp->ooo_list_lock, flags); 3939 3940 /* For deferred completions bump up SW completion ticket value. */ 3941 if (def_cmpl) { 3942 cqp->last_def_cmpl_ticket = def_info; 3943 cqp->sw_def_cmpl_ticket++; 3944 } 3945 if (!list_empty(&cqp->ooo_avail)) { 3946 ooo_op = (struct irdma_ooo_cqp_op *) 3947 list_entry(cqp->ooo_avail.next, 3948 struct irdma_ooo_cqp_op, list_entry); 3949 3950 list_del(&ooo_op->list_entry); 3951 ooo_op->scratch = info->scratch; 3952 ooo_op->def_info = def_info; 3953 ooo_op->sw_def_info = cqp->sw_def_cmpl_ticket; 3954 ooo_op->deferred = def_cmpl; 3955 ooo_op->wqe_idx = wqe_idx; 3956 /* Pending completions must be chronologically ordered, 3957 * so adding at the end of list. 3958 */ 3959 list_add_tail(&ooo_op->list_entry, &cqp->ooo_pnd); 3960 } 3961 spin_unlock_irqrestore(&cqp->ooo_list_lock, flags); 3962 3963 info->pending = true; 3964 } 3965 3966 /** 3967 * irdma_sc_process_ooo_cmpl - process out-of-order (final) completion 3968 * @cqp: CQP sc struct 3969 * @info: CQP CQE info 3970 * @def_info: out-of-order completion id 3971 */ 3972 static void irdma_sc_process_ooo_cmpl(struct irdma_sc_cqp *cqp, 3973 struct irdma_ccq_cqe_info *info, 3974 u32 def_info) 3975 { 3976 struct irdma_ooo_cqp_op *ooo_op_tmp; 3977 struct irdma_ooo_cqp_op *ooo_op; 3978 unsigned long flags; 3979 3980 info->scratch = 0; 3981 3982 spin_lock_irqsave(&cqp->ooo_list_lock, flags); 3983 list_for_each_entry_safe(ooo_op, ooo_op_tmp, &cqp->ooo_pnd, 3984 list_entry) { 3985 if (!ooo_op->deferred && ooo_op->def_info == def_info) { 3986 list_del(&ooo_op->list_entry); 3987 info->scratch = ooo_op->scratch; 3988 list_add(&ooo_op->list_entry, &cqp->ooo_avail); 3989 break; 3990 } 3991 } 3992 spin_unlock_irqrestore(&cqp->ooo_list_lock, flags); 3993 3994 if (!info->scratch) 3995 ibdev_dbg(to_ibdev(cqp->dev), 3996 "CQP: DEBUG_FW_OOO out-of-order completion with unknown def_info = 0x%x\n", 3997 def_info); 3998 } 3999 4000 /** 4001 * irdma_sc_ccq_get_cqe_info - get ccq's cq entry 4002 * @ccq: ccq sc struct 4003 * @info: completion q entry to return 4004 */ 4005 int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq, 4006 struct irdma_ccq_cqe_info *info) 4007 { 4008 u32 def_info; 4009 bool def_cmpl = false; 4010 bool pend_cmpl = false; 4011 bool ooo_final_cmpl = false; 4012 u64 qp_ctx, temp, temp1; 4013 __le64 *cqe; 4014 struct irdma_sc_cqp *cqp; 4015 u32 wqe_idx; 4016 u32 error; 4017 u8 polarity; 4018 int ret_code = 0; 4019 unsigned long flags; 4020 4021 if (ccq->cq_uk.avoid_mem_cflct) 4022 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk); 4023 else 4024 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk); 4025 4026 get_64bit_val(cqe, 24, &temp); 4027 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp); 4028 if (polarity != ccq->cq_uk.polarity) 4029 return -ENOENT; 4030 4031 /* Ensure CEQE contents are read after valid bit is checked */ 4032 dma_rmb(); 4033 4034 get_64bit_val(cqe, 8, &qp_ctx); 4035 cqp = (struct irdma_sc_cqp *)(unsigned long)qp_ctx; 4036 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp); 4037 info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR; 4038 info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp); 4039 if (info->error) { 4040 info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp); 4041 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 4042 ibdev_dbg(to_ibdev(cqp->dev), 4043 "CQP: CQPERRCODES error_code[x%08X]\n", error); 4044 } 4045 4046 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp); 4047 info->scratch = cqp->scratch_array[wqe_idx]; 4048 4049 get_64bit_val(cqe, 16, &temp1); 4050 info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1); 4051 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 4052 def_cmpl = info->maj_err_code == IRDMA_CQPSQ_MAJ_NO_ERROR && 4053 info->min_err_code == IRDMA_CQPSQ_MIN_DEF_CMPL; 4054 def_info = (u32)FIELD_GET(IRDMA_CCQ_DEFINFO, temp1); 4055 4056 pend_cmpl = info->maj_err_code == IRDMA_CQPSQ_MAJ_NO_ERROR && 4057 info->min_err_code == IRDMA_CQPSQ_MIN_OOO_CMPL; 4058 4059 ooo_final_cmpl = (bool)FIELD_GET(IRDMA_OOO_CMPL, temp); 4060 4061 if (def_cmpl || pend_cmpl || ooo_final_cmpl) { 4062 if (ooo_final_cmpl) 4063 irdma_sc_process_ooo_cmpl(cqp, info, def_info); 4064 else 4065 irdma_sc_process_def_cmpl(cqp, info, wqe_idx, 4066 def_info, def_cmpl); 4067 } 4068 } 4069 4070 get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1); 4071 info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1); 4072 info->cqp = cqp; 4073 4074 /* move the head for cq */ 4075 IRDMA_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code); 4076 if (!IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)) 4077 ccq->cq_uk.polarity ^= 1; 4078 4079 /* update cq tail in cq shadow memory also */ 4080 IRDMA_RING_MOVE_TAIL(ccq->cq_uk.cq_ring); 4081 set_64bit_val(ccq->cq_uk.shadow_area, 0, 4082 IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)); 4083 4084 dma_wmb(); /* make sure shadow area is updated before moving tail */ 4085 4086 spin_lock_irqsave(&cqp->dev->cqp_lock, flags); 4087 if (!ooo_final_cmpl) 4088 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 4089 spin_unlock_irqrestore(&cqp->dev->cqp_lock, flags); 4090 4091 /* Do not increment completed_ops counter on pending or deferred 4092 * completions. 4093 */ 4094 if (pend_cmpl || def_cmpl) 4095 return ret_code; 4096 atomic64_inc(&cqp->completed_ops); 4097 4098 return ret_code; 4099 } 4100 4101 /** 4102 * irdma_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ 4103 * @cqp: struct for cqp hw 4104 * @op_code: cqp opcode for completion 4105 * @compl_info: completion q entry to return 4106 */ 4107 int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code, 4108 struct irdma_ccq_cqe_info *compl_info) 4109 { 4110 struct irdma_ccq_cqe_info info = {}; 4111 struct irdma_sc_cq *ccq; 4112 int ret_code = 0; 4113 u32 cnt = 0; 4114 4115 ccq = cqp->dev->ccq; 4116 while (1) { 4117 if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count) 4118 return -ETIMEDOUT; 4119 4120 if (irdma_sc_ccq_get_cqe_info(ccq, &info)) { 4121 udelay(cqp->dev->hw_attrs.max_sleep_count); 4122 continue; 4123 } 4124 if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) { 4125 ret_code = -EIO; 4126 break; 4127 } 4128 /* make sure op code matches*/ 4129 if (op_code == info.op_code) 4130 break; 4131 ibdev_dbg(to_ibdev(cqp->dev), 4132 "WQE: opcode mismatch for my op code 0x%x, returned opcode %x\n", 4133 op_code, info.op_code); 4134 } 4135 4136 if (compl_info) 4137 memcpy(compl_info, &info, sizeof(*compl_info)); 4138 4139 return ret_code; 4140 } 4141 4142 /** 4143 * irdma_sc_manage_hmc_pm_func_table - manage of function table 4144 * @cqp: struct for cqp hw 4145 * @scratch: u64 saved to be used during cqp completion 4146 * @info: info for the manage function table operation 4147 * @post_sq: flag for cqp db to ring 4148 */ 4149 static int irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp, 4150 struct irdma_hmc_fcn_info *info, 4151 u64 scratch, bool post_sq) 4152 { 4153 __le64 *wqe; 4154 u64 hdr; 4155 4156 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4157 if (!wqe) 4158 return -ENOMEM; 4159 4160 set_64bit_val(wqe, 0, 0); 4161 set_64bit_val(wqe, 8, 0); 4162 set_64bit_val(wqe, 16, 0); 4163 set_64bit_val(wqe, 32, 0); 4164 set_64bit_val(wqe, 40, 0); 4165 set_64bit_val(wqe, 48, 0); 4166 set_64bit_val(wqe, 56, 0); 4167 4168 hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) | 4169 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 4170 IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) | 4171 FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) | 4172 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4173 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4174 4175 set_64bit_val(wqe, 24, hdr); 4176 4177 print_hex_dump_debug("WQE: MANAGE_HMC_PM_FUNC_TABLE WQE", 4178 DUMP_PREFIX_OFFSET, 16, 8, wqe, 4179 IRDMA_CQP_WQE_SIZE * 8, false); 4180 if (post_sq) 4181 irdma_sc_cqp_post_sq(cqp); 4182 4183 return 0; 4184 } 4185 4186 /** 4187 * irdma_sc_commit_fpm_val_done - wait for cqp eqe completion 4188 * for fpm commit 4189 * @cqp: struct for cqp hw 4190 */ 4191 static int irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp) 4192 { 4193 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL, 4194 NULL); 4195 } 4196 4197 /** 4198 * irdma_sc_commit_fpm_val - cqp wqe for commit fpm values 4199 * @cqp: struct for cqp hw 4200 * @scratch: u64 saved to be used during cqp completion 4201 * @hmc_fn_id: hmc function id 4202 * @commit_fpm_mem: Memory for fpm values 4203 * @post_sq: flag for cqp db to ring 4204 * @wait_type: poll ccq or cqp registers for cqp completion 4205 */ 4206 static int irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, 4207 u8 hmc_fn_id, 4208 struct irdma_dma_mem *commit_fpm_mem, 4209 bool post_sq, u8 wait_type) 4210 { 4211 __le64 *wqe; 4212 u64 hdr; 4213 u32 tail, val, error; 4214 int ret_code = 0; 4215 4216 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4217 if (!wqe) 4218 return -ENOMEM; 4219 4220 set_64bit_val(wqe, 16, hmc_fn_id); 4221 set_64bit_val(wqe, 32, commit_fpm_mem->pa); 4222 4223 hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) | 4224 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) | 4225 FIELD_PREP(IRDMA_CQPSQ_CFPM_FW_SCRATCH_BUF_PRESENT, 4226 cqp->dev->hmc_fpm_misc.fw_scratch_buf0.va != NULL) | 4227 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4228 4229 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4230 4231 set_64bit_val(wqe, 24, hdr); 4232 4233 print_hex_dump_debug("WQE: COMMIT_FPM_VAL WQE", DUMP_PREFIX_OFFSET, 4234 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4235 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4236 4237 if (post_sq) { 4238 irdma_sc_cqp_post_sq(cqp); 4239 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 4240 ret_code = irdma_cqp_poll_registers(cqp, tail, 4241 cqp->dev->hw_attrs.max_done_count); 4242 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 4243 ret_code = irdma_sc_commit_fpm_val_done(cqp); 4244 } 4245 4246 return ret_code; 4247 } 4248 4249 /** 4250 * irdma_sc_query_fpm_val_done - poll for cqp wqe completion for 4251 * query fpm 4252 * @cqp: struct for cqp hw 4253 */ 4254 static int irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp) 4255 { 4256 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL, 4257 NULL); 4258 } 4259 4260 /** 4261 * irdma_sc_query_fpm_val - cqp wqe query fpm values 4262 * @cqp: struct for cqp hw 4263 * @scratch: u64 saved to be used during cqp completion 4264 * @hmc_fn_id: hmc function id 4265 * @query_fpm_mem: memory for return fpm values 4266 * @post_sq: flag for cqp db to ring 4267 * @wait_type: poll ccq or cqp registers for cqp completion 4268 */ 4269 static int irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, 4270 u8 hmc_fn_id, 4271 struct irdma_dma_mem *query_fpm_mem, 4272 bool post_sq, u8 wait_type) 4273 { 4274 __le64 *wqe; 4275 u64 hdr; 4276 u32 tail, val, error; 4277 int ret_code = 0; 4278 4279 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4280 if (!wqe) 4281 return -ENOMEM; 4282 4283 set_64bit_val(wqe, 16, hmc_fn_id); 4284 set_64bit_val(wqe, 32, query_fpm_mem->pa); 4285 4286 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) | 4287 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4288 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4289 4290 set_64bit_val(wqe, 24, hdr); 4291 4292 print_hex_dump_debug("WQE: QUERY_FPM WQE", DUMP_PREFIX_OFFSET, 16, 8, 4293 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4294 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4295 4296 if (post_sq) { 4297 irdma_sc_cqp_post_sq(cqp); 4298 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 4299 ret_code = irdma_cqp_poll_registers(cqp, tail, 4300 cqp->dev->hw_attrs.max_done_count); 4301 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 4302 ret_code = irdma_sc_query_fpm_val_done(cqp); 4303 } 4304 4305 return ret_code; 4306 } 4307 4308 /** 4309 * irdma_sc_ceq_init - initialize ceq 4310 * @ceq: ceq sc structure 4311 * @info: ceq initialization info 4312 */ 4313 int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq, 4314 struct irdma_ceq_init_info *info) 4315 { 4316 u32 pble_obj_cnt; 4317 4318 if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size || 4319 info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size) 4320 return -EINVAL; 4321 4322 if (info->ceq_id >= info->dev->hmc_fpm_misc.max_ceqs) 4323 return -EINVAL; 4324 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4325 4326 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4327 return -EINVAL; 4328 4329 ceq->size = sizeof(*ceq); 4330 ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base; 4331 ceq->ceq_id = info->ceq_id; 4332 ceq->dev = info->dev; 4333 ceq->elem_cnt = info->elem_cnt; 4334 ceq->ceq_elem_pa = info->ceqe_pa; 4335 ceq->virtual_map = info->virtual_map; 4336 ceq->itr_no_expire = info->itr_no_expire; 4337 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0); 4338 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0); 4339 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL); 4340 ceq->tph_en = info->tph_en; 4341 ceq->tph_val = info->tph_val; 4342 ceq->vsi_idx = info->vsi_idx; 4343 ceq->polarity = 1; 4344 IRDMA_RING_INIT(ceq->ceq_ring, ceq->elem_cnt); 4345 ceq->dev->ceq[info->ceq_id] = ceq; 4346 4347 return 0; 4348 } 4349 4350 /** 4351 * irdma_sc_ceq_create - create ceq wqe 4352 * @ceq: ceq sc structure 4353 * @scratch: u64 saved to be used during cqp completion 4354 * @post_sq: flag for cqp db to ring 4355 */ 4356 4357 static int irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch, 4358 bool post_sq) 4359 { 4360 struct irdma_sc_cqp *cqp; 4361 __le64 *wqe; 4362 u64 hdr; 4363 4364 cqp = ceq->dev->cqp; 4365 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4366 if (!wqe) 4367 return -ENOMEM; 4368 set_64bit_val(wqe, 16, ceq->elem_cnt); 4369 set_64bit_val(wqe, 32, 4370 (ceq->virtual_map ? 0 : ceq->ceq_elem_pa)); 4371 set_64bit_val(wqe, 48, 4372 (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0)); 4373 set_64bit_val(wqe, 56, 4374 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) | 4375 FIELD_PREP(IRDMA_CQPSQ_PASID, ceq->pasid) | 4376 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi_idx)); 4377 hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) | 4378 FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID_HIGH, ceq->ceq_id >> 10) | 4379 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) | 4380 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 4381 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 4382 FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) | 4383 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 4384 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, ceq->pasid_valid) | 4385 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4386 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4387 4388 set_64bit_val(wqe, 24, hdr); 4389 4390 print_hex_dump_debug("WQE: CEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 4391 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4392 if (post_sq) 4393 irdma_sc_cqp_post_sq(cqp); 4394 4395 return 0; 4396 } 4397 4398 /** 4399 * irdma_sc_cceq_create_done - poll for control ceq wqe to complete 4400 * @ceq: ceq sc structure 4401 */ 4402 static int irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq) 4403 { 4404 struct irdma_sc_cqp *cqp; 4405 4406 cqp = ceq->dev->cqp; 4407 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CEQ, 4408 NULL); 4409 } 4410 4411 /** 4412 * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete 4413 * @ceq: ceq sc structure 4414 */ 4415 int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq) 4416 { 4417 struct irdma_sc_cqp *cqp; 4418 4419 cqp = ceq->dev->cqp; 4420 cqp->process_cqp_sds = irdma_update_sds_noccq; 4421 4422 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_DESTROY_CEQ, 4423 NULL); 4424 } 4425 4426 /** 4427 * irdma_sc_cceq_create - create cceq 4428 * @ceq: ceq sc structure 4429 * @scratch: u64 saved to be used during cqp completion 4430 */ 4431 int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch) 4432 { 4433 int ret_code; 4434 struct irdma_sc_dev *dev = ceq->dev; 4435 4436 dev->ccq->vsi_idx = ceq->vsi_idx; 4437 4438 ret_code = irdma_sc_ceq_create(ceq, scratch, true); 4439 if (!ret_code) 4440 return irdma_sc_cceq_create_done(ceq); 4441 4442 return ret_code; 4443 } 4444 4445 /** 4446 * irdma_sc_ceq_destroy - destroy ceq 4447 * @ceq: ceq sc structure 4448 * @scratch: u64 saved to be used during cqp completion 4449 * @post_sq: flag for cqp db to ring 4450 */ 4451 int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq) 4452 { 4453 struct irdma_sc_cqp *cqp; 4454 __le64 *wqe; 4455 u64 hdr; 4456 4457 cqp = ceq->dev->cqp; 4458 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4459 if (!wqe) 4460 return -ENOMEM; 4461 4462 set_64bit_val(wqe, 16, ceq->elem_cnt); 4463 set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx); 4464 set_64bit_val(wqe, 56, 4465 FIELD_PREP(IRDMA_CQPSQ_PASID, ceq->pasid)); 4466 hdr = ceq->ceq_id | 4467 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) | 4468 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 4469 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 4470 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 4471 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, ceq->pasid_valid) | 4472 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4473 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4474 4475 set_64bit_val(wqe, 24, hdr); 4476 4477 print_hex_dump_debug("WQE: CEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 4478 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4479 if (post_sq) 4480 irdma_sc_cqp_post_sq(cqp); 4481 4482 return 0; 4483 } 4484 4485 /** 4486 * irdma_sc_process_ceq - process ceq 4487 * @dev: sc device struct 4488 * @ceq: ceq sc structure 4489 * @cq_idx: Pointer to a CQ ID that will be populated. 4490 * 4491 * It is expected caller serializes this function with cleanup_ceqes() 4492 * because these functions manipulate the same ceq 4493 * 4494 * Return: True if cq_idx has been populated with a CQ ID. 4495 */ 4496 bool irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq, 4497 u32 *cq_idx) 4498 { 4499 u64 temp; 4500 __le64 *ceqe; 4501 u8 polarity; 4502 4503 do { 4504 ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq); 4505 get_64bit_val(ceqe, 0, &temp); 4506 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 4507 if (polarity != ceq->polarity) 4508 return false; 4509 4510 /* Truncate. Discard valid bit which is MSb of temp. */ 4511 *cq_idx = temp; 4512 if (*cq_idx >= dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt) 4513 *cq_idx = IRDMA_INVALID_CQ_IDX; 4514 4515 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); 4516 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) 4517 ceq->polarity ^= 1; 4518 } while (*cq_idx == IRDMA_INVALID_CQ_IDX); 4519 4520 return true; 4521 } 4522 4523 /** 4524 * irdma_sc_cleanup_ceqes - clear the valid ceqes ctx matching the cq 4525 * @cq: cq for which the ceqes need to be cleaned up 4526 * @ceq: ceq ptr 4527 * 4528 * The function is called after the cq is destroyed to cleanup 4529 * its pending ceqe entries. It is expected caller serializes this 4530 * function with process_ceq() in interrupt context. 4531 */ 4532 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq) 4533 { 4534 u8 ceq_polarity = ceq->polarity; 4535 __le64 *ceqe; 4536 u8 polarity; 4537 u32 cq_idx; 4538 u64 temp; 4539 int next; 4540 u32 i; 4541 4542 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, 0); 4543 4544 for (i = 1; i <= IRDMA_RING_SIZE(*ceq); i++) { 4545 ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next); 4546 4547 get_64bit_val(ceqe, 0, &temp); 4548 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 4549 if (polarity != ceq_polarity) 4550 return; 4551 4552 cq_idx = temp; 4553 if (cq_idx == cq->cq_uk.cq_id) 4554 set_64bit_val(ceqe, 0, (temp & IRDMA_CEQE_VALID) | 4555 IRDMA_INVALID_CQ_IDX); 4556 4557 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i); 4558 if (!next) 4559 ceq_polarity ^= 1; 4560 } 4561 } 4562 4563 /** 4564 * irdma_sc_aeq_init - initialize aeq 4565 * @aeq: aeq structure ptr 4566 * @info: aeq initialization info 4567 */ 4568 int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, 4569 struct irdma_aeq_init_info *info) 4570 { 4571 u32 pble_obj_cnt; 4572 4573 if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size || 4574 info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size) 4575 return -EINVAL; 4576 4577 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4578 4579 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4580 return -EINVAL; 4581 4582 aeq->size = sizeof(*aeq); 4583 aeq->polarity = 1; 4584 aeq->aeqe_base = (struct irdma_sc_aeqe *)info->aeqe_base; 4585 aeq->dev = info->dev; 4586 aeq->elem_cnt = info->elem_cnt; 4587 aeq->aeq_elem_pa = info->aeq_elem_pa; 4588 IRDMA_RING_INIT(aeq->aeq_ring, aeq->elem_cnt); 4589 aeq->virtual_map = info->virtual_map; 4590 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL); 4591 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0); 4592 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0); 4593 aeq->msix_idx = info->msix_idx; 4594 info->dev->aeq = aeq; 4595 4596 return 0; 4597 } 4598 4599 /** 4600 * irdma_sc_aeq_create - create aeq 4601 * @aeq: aeq structure ptr 4602 * @scratch: u64 saved to be used during cqp completion 4603 * @post_sq: flag for cqp db to ring 4604 */ 4605 static int irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, u64 scratch, 4606 bool post_sq) 4607 { 4608 __le64 *wqe; 4609 struct irdma_sc_cqp *cqp; 4610 u64 hdr; 4611 4612 cqp = aeq->dev->cqp; 4613 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4614 if (!wqe) 4615 return -ENOMEM; 4616 set_64bit_val(wqe, 16, aeq->elem_cnt); 4617 set_64bit_val(wqe, 32, 4618 (aeq->virtual_map ? 0 : aeq->aeq_elem_pa)); 4619 set_64bit_val(wqe, 48, 4620 (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0)); 4621 set_64bit_val(wqe, 56, 4622 FIELD_PREP(IRDMA_CQPSQ_PASID, aeq->pasid)); 4623 4624 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) | 4625 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 4626 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 4627 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, aeq->pasid_valid) | 4628 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4629 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4630 4631 set_64bit_val(wqe, 24, hdr); 4632 4633 print_hex_dump_debug("WQE: AEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 4634 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4635 if (post_sq) 4636 irdma_sc_cqp_post_sq(cqp); 4637 4638 return 0; 4639 } 4640 4641 /** 4642 * irdma_sc_aeq_destroy - destroy aeq during close 4643 * @aeq: aeq structure ptr 4644 * @scratch: u64 saved to be used during cqp completion 4645 * @post_sq: flag for cqp db to ring 4646 */ 4647 static int irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch, 4648 bool post_sq) 4649 { 4650 __le64 *wqe; 4651 struct irdma_sc_cqp *cqp; 4652 struct irdma_sc_dev *dev; 4653 u64 hdr; 4654 4655 dev = aeq->dev; 4656 4657 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) 4658 writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 4659 4660 cqp = dev->cqp; 4661 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4662 if (!wqe) 4663 return -ENOMEM; 4664 set_64bit_val(wqe, 16, aeq->elem_cnt); 4665 set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx); 4666 set_64bit_val(wqe, 56, 4667 FIELD_PREP(IRDMA_CQPSQ_PASID, aeq->pasid)); 4668 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) | 4669 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 4670 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 4671 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, aeq->pasid_valid) | 4672 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4673 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4674 4675 set_64bit_val(wqe, 24, hdr); 4676 4677 print_hex_dump_debug("WQE: AEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 4678 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4679 if (post_sq) 4680 irdma_sc_cqp_post_sq(cqp); 4681 return 0; 4682 } 4683 4684 /** 4685 * irdma_sc_get_next_aeqe - get next aeq entry 4686 * @aeq: aeq structure ptr 4687 * @info: aeqe info to be returned 4688 */ 4689 int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, 4690 struct irdma_aeqe_info *info) 4691 { 4692 u64 temp, compl_ctx; 4693 __le64 *aeqe; 4694 u8 ae_src; 4695 u8 polarity; 4696 4697 aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq); 4698 get_64bit_val(aeqe, 8, &temp); 4699 polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp); 4700 4701 if (aeq->polarity != polarity) 4702 return -ENOENT; 4703 4704 /* Ensure AEQE contents are read after valid bit is checked */ 4705 dma_rmb(); 4706 4707 get_64bit_val(aeqe, 0, &compl_ctx); 4708 4709 print_hex_dump_debug("WQE: AEQ_ENTRY WQE", DUMP_PREFIX_OFFSET, 16, 8, 4710 aeqe, 16, false); 4711 4712 if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 4713 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC_GEN_3, temp); 4714 info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX_GEN_3, 4715 temp); 4716 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_GEN_3, temp); 4717 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE_GEN_3, temp); 4718 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE_GEN_3, compl_ctx); 4719 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE_GEN_3, temp); 4720 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA_GEN_3, compl_ctx); 4721 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW_GEN_3, temp); 4722 info->compl_ctx = FIELD_GET(IRDMA_AEQE_CMPL_CTXT, compl_ctx); 4723 compl_ctx = FIELD_GET(IRDMA_AEQE_CMPL_CTXT, compl_ctx) << IRDMA_AEQE_CMPL_CTXT_S; 4724 } else { 4725 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp); 4726 info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp); 4727 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) | 4728 ((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18); 4729 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp); 4730 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp); 4731 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp); 4732 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp); 4733 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, 4734 temp); 4735 } 4736 4737 info->ae_src = ae_src; 4738 switch (info->ae_id) { 4739 case IRDMA_AE_SRQ_LIMIT: 4740 info->srq = true; 4741 /* [63:6] from CMPL_CTXT, [5:0] from WQDESCIDX. */ 4742 info->compl_ctx = compl_ctx; 4743 ae_src = IRDMA_AE_SOURCE_RSVD; 4744 break; 4745 case IRDMA_AE_PRIV_OPERATION_DENIED: 4746 case IRDMA_AE_AMP_INVALIDATE_TYPE1_MW: 4747 case IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW: 4748 case IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG: 4749 case IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH: 4750 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 4751 case IRDMA_AE_UDA_XMIT_BAD_PD: 4752 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 4753 case IRDMA_AE_BAD_CLOSE: 4754 case IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO: 4755 case IRDMA_AE_STAG_ZERO_INVALID: 4756 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 4757 case IRDMA_AE_IB_INVALID_REQUEST: 4758 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 4759 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 4760 case IRDMA_AE_IB_REMOTE_OP_ERROR: 4761 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 4762 case IRDMA_AE_DDP_UBE_INVALID_MO: 4763 case IRDMA_AE_DDP_UBE_INVALID_QN: 4764 case IRDMA_AE_DDP_NO_L_BIT: 4765 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 4766 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 4767 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 4768 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 4769 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 4770 case IRDMA_AE_INVALID_ARP_ENTRY: 4771 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 4772 case IRDMA_AE_STALE_ARP_ENTRY: 4773 case IRDMA_AE_INVALID_AH_ENTRY: 4774 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 4775 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 4776 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 4777 case IRDMA_AE_LLP_TOO_MANY_RNRS: 4778 case IRDMA_AE_REMOTE_QP_CATASTROPHIC: 4779 case IRDMA_AE_LOCAL_QP_CATASTROPHIC: 4780 case IRDMA_AE_RCE_QP_CATASTROPHIC: 4781 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 4782 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 4783 case IRDMA_AE_RESET_SENT: 4784 case IRDMA_AE_TERMINATE_SENT: 4785 case IRDMA_AE_RESET_NOT_SENT: 4786 case IRDMA_AE_LCE_QP_CATASTROPHIC: 4787 case IRDMA_AE_QP_SUSPEND_COMPLETE: 4788 case IRDMA_AE_UDA_L4LEN_INVALID: 4789 info->qp = true; 4790 info->compl_ctx = compl_ctx; 4791 break; 4792 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 4793 info->cq = true; 4794 info->compl_ctx = compl_ctx << 1; 4795 ae_src = IRDMA_AE_SOURCE_RSVD; 4796 break; 4797 case IRDMA_AE_CQP_DEFERRED_COMPLETE: 4798 info->def_info = info->wqe_idx; 4799 ae_src = IRDMA_AE_SOURCE_RSVD; 4800 break; 4801 case IRDMA_AE_ROCE_EMPTY_MCG: 4802 case IRDMA_AE_ROCE_BAD_MC_IP_ADDR: 4803 case IRDMA_AE_ROCE_BAD_MC_QPID: 4804 case IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH: 4805 fallthrough; 4806 case IRDMA_AE_LLP_CONNECTION_RESET: 4807 case IRDMA_AE_LLP_SYN_RECEIVED: 4808 case IRDMA_AE_LLP_FIN_RECEIVED: 4809 case IRDMA_AE_LLP_CLOSE_COMPLETE: 4810 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 4811 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 4812 ae_src = IRDMA_AE_SOURCE_RSVD; 4813 info->qp = true; 4814 info->compl_ctx = compl_ctx; 4815 break; 4816 default: 4817 break; 4818 } 4819 4820 switch (ae_src) { 4821 case IRDMA_AE_SOURCE_RQ: 4822 case IRDMA_AE_SOURCE_RQ_0011: 4823 info->qp = true; 4824 info->rq = true; 4825 info->compl_ctx = compl_ctx; 4826 info->err_rq_idx_valid = true; 4827 break; 4828 case IRDMA_AE_SOURCE_CQ: 4829 case IRDMA_AE_SOURCE_CQ_0110: 4830 case IRDMA_AE_SOURCE_CQ_1010: 4831 case IRDMA_AE_SOURCE_CQ_1110: 4832 info->cq = true; 4833 info->compl_ctx = compl_ctx << 1; 4834 break; 4835 case IRDMA_AE_SOURCE_SQ: 4836 case IRDMA_AE_SOURCE_SQ_0111: 4837 info->qp = true; 4838 info->sq = true; 4839 info->compl_ctx = compl_ctx; 4840 break; 4841 case IRDMA_AE_SOURCE_IN_RR_WR: 4842 info->qp = true; 4843 if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 4844 info->err_rq_idx_valid = true; 4845 info->compl_ctx = compl_ctx; 4846 info->in_rdrsp_wr = true; 4847 break; 4848 case IRDMA_AE_SOURCE_IN_RR_WR_1011: 4849 info->qp = true; 4850 if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 4851 info->sq = true; 4852 info->err_rq_idx_valid = true; 4853 } 4854 info->compl_ctx = compl_ctx; 4855 info->in_rdrsp_wr = true; 4856 break; 4857 case IRDMA_AE_SOURCE_OUT_RR: 4858 case IRDMA_AE_SOURCE_OUT_RR_1111: 4859 info->qp = true; 4860 info->compl_ctx = compl_ctx; 4861 info->out_rdrsp = true; 4862 break; 4863 case IRDMA_AE_SOURCE_RSVD: 4864 default: 4865 break; 4866 } 4867 4868 IRDMA_RING_MOVE_TAIL(aeq->aeq_ring); 4869 if (!IRDMA_RING_CURRENT_TAIL(aeq->aeq_ring)) 4870 aeq->polarity ^= 1; 4871 4872 return 0; 4873 } 4874 4875 /** 4876 * irdma_sc_repost_aeq_entries - repost completed aeq entries 4877 * @dev: sc device struct 4878 * @count: allocate count 4879 */ 4880 void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count) 4881 { 4882 writel(count, dev->hw_regs[IRDMA_AEQALLOC]); 4883 } 4884 4885 /** 4886 * irdma_sc_ccq_init - initialize control cq 4887 * @cq: sc's cq ctruct 4888 * @info: info for control cq initialization 4889 */ 4890 int irdma_sc_ccq_init(struct irdma_sc_cq *cq, struct irdma_ccq_init_info *info) 4891 { 4892 u32 pble_obj_cnt; 4893 4894 if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size || 4895 info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size) 4896 return -EINVAL; 4897 4898 if (info->ceq_id >= info->dev->hmc_fpm_misc.max_ceqs) 4899 return -EINVAL; 4900 4901 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4902 4903 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4904 return -EINVAL; 4905 4906 cq->cq_pa = info->cq_pa; 4907 cq->cq_uk.cq_base = info->cq_base; 4908 cq->shadow_area_pa = info->shadow_area_pa; 4909 cq->cq_uk.shadow_area = info->shadow_area; 4910 cq->shadow_read_threshold = info->shadow_read_threshold; 4911 cq->dev = info->dev; 4912 cq->ceq_id = info->ceq_id; 4913 cq->cq_uk.cq_size = info->num_elem; 4914 cq->cq_type = IRDMA_CQ_TYPE_CQP; 4915 cq->ceqe_mask = info->ceqe_mask; 4916 IRDMA_RING_INIT(cq->cq_uk.cq_ring, info->num_elem); 4917 cq->cq_uk.cq_id = 0; /* control cq is id 0 always */ 4918 cq->ceq_id_valid = info->ceq_id_valid; 4919 cq->tph_en = info->tph_en; 4920 cq->tph_val = info->tph_val; 4921 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct; 4922 cq->pbl_list = info->pbl_list; 4923 cq->virtual_map = info->virtual_map; 4924 cq->pbl_chunk_size = info->pbl_chunk_size; 4925 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 4926 cq->cq_uk.polarity = true; 4927 cq->vsi = info->vsi; 4928 cq->cq_uk.cq_ack_db = cq->dev->cq_ack_db; 4929 4930 /* Only applicable to CQs other than CCQ so initialize to zero */ 4931 cq->cq_uk.cqe_alloc_db = NULL; 4932 4933 info->dev->ccq = cq; 4934 return 0; 4935 } 4936 4937 /** 4938 * irdma_sc_ccq_create_done - poll cqp for ccq create 4939 * @ccq: ccq sc struct 4940 */ 4941 static inline int irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq) 4942 { 4943 struct irdma_sc_cqp *cqp; 4944 4945 cqp = ccq->dev->cqp; 4946 4947 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CQ, NULL); 4948 } 4949 4950 /** 4951 * irdma_sc_ccq_create - create control cq 4952 * @ccq: ccq sc struct 4953 * @scratch: u64 saved to be used during cqp completion 4954 * @check_overflow: overlow flag for ccq 4955 * @post_sq: flag for cqp db to ring 4956 */ 4957 int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch, 4958 bool check_overflow, bool post_sq) 4959 { 4960 int ret_code; 4961 4962 ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq); 4963 if (ret_code) 4964 return ret_code; 4965 4966 if (post_sq) { 4967 ret_code = irdma_sc_ccq_create_done(ccq); 4968 if (ret_code) 4969 return ret_code; 4970 } 4971 ccq->dev->cqp->process_cqp_sds = irdma_cqp_sds_cmd; 4972 4973 return 0; 4974 } 4975 4976 /** 4977 * irdma_sc_ccq_destroy - destroy ccq during close 4978 * @ccq: ccq sc struct 4979 * @scratch: u64 saved to be used during cqp completion 4980 * @post_sq: flag for cqp db to ring 4981 */ 4982 int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq) 4983 { 4984 struct irdma_sc_cqp *cqp; 4985 __le64 *wqe; 4986 u64 hdr; 4987 int ret_code = 0; 4988 u32 tail, val, error; 4989 4990 cqp = ccq->dev->cqp; 4991 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4992 if (!wqe) 4993 return -ENOMEM; 4994 4995 set_64bit_val(wqe, 0, ccq->cq_uk.cq_size); 4996 set_64bit_val(wqe, 8, ccq->cq_uk.cq_id); 4997 set_64bit_val(wqe, 40, ccq->shadow_area_pa); 4998 4999 hdr = ccq->cq_uk.cq_id | 5000 FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0), 5001 IRDMA_CQPSQ_CQ_CEQID) | 5002 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 5003 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) | 5004 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) | 5005 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) | 5006 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) | 5007 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 5008 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5009 5010 set_64bit_val(wqe, 24, hdr); 5011 5012 print_hex_dump_debug("WQE: CCQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 5013 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 5014 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5015 5016 if (post_sq) { 5017 irdma_sc_cqp_post_sq(cqp); 5018 ret_code = irdma_cqp_poll_registers(cqp, tail, 5019 cqp->dev->hw_attrs.max_done_count); 5020 } 5021 5022 cqp->process_cqp_sds = irdma_update_sds_noccq; 5023 5024 return ret_code; 5025 } 5026 5027 /** 5028 * irdma_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info 5029 * @dev : ptr to irdma_dev struct 5030 * @hmc_fn_id: hmc function id 5031 */ 5032 int irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u8 hmc_fn_id) 5033 { 5034 struct irdma_hmc_info *hmc_info; 5035 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5036 struct irdma_dma_mem query_fpm_mem; 5037 int ret_code = 0; 5038 u8 wait_type; 5039 5040 hmc_info = dev->hmc_info; 5041 hmc_fpm_misc = &dev->hmc_fpm_misc; 5042 query_fpm_mem.pa = dev->fpm_query_buf_pa; 5043 query_fpm_mem.va = dev->fpm_query_buf; 5044 hmc_info->hmc_fn_id = hmc_fn_id; 5045 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 5046 5047 ret_code = irdma_sc_query_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 5048 &query_fpm_mem, true, wait_type); 5049 if (ret_code) 5050 return ret_code; 5051 5052 /* parse the fpm_query_buf and fill hmc obj info */ 5053 ret_code = irdma_sc_parse_fpm_query_buf(dev, query_fpm_mem.va, hmc_info, 5054 hmc_fpm_misc); 5055 5056 print_hex_dump_debug("HMC: QUERY FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 5057 8, query_fpm_mem.va, IRDMA_QUERY_FPM_BUF_SIZE, 5058 false); 5059 return ret_code; 5060 } 5061 5062 /** 5063 * irdma_set_loc_mem() - set a local memory bit field 5064 * @buf: ptr to a buffer where local memory gets enabled 5065 */ 5066 static void irdma_set_loc_mem(__le64 *buf) 5067 { 5068 u64 loc_mem_en = BIT_ULL(ENABLE_LOC_MEM); 5069 u32 offset; 5070 u64 temp; 5071 5072 for (offset = 0; offset < IRDMA_COMMIT_FPM_BUF_SIZE; 5073 offset += sizeof(__le64)) { 5074 if (offset == IRDMA_PBLE_COMMIT_OFFSET || 5075 offset == IRDMA_SCRATCH_BUF0_COMMIT_OFFSET || 5076 offset == IRDMA_SCRATCH_BUF1_COMMIT_OFFSET) 5077 continue; 5078 get_64bit_val(buf, offset, &temp); 5079 if (temp) 5080 set_64bit_val(buf, offset, temp | loc_mem_en); 5081 } 5082 } 5083 5084 /** 5085 * irdma_sc_cfg_iw_fpm() - commits hmc obj cnt values using cqp 5086 * command and populates fpm base address in hmc_info 5087 * @dev : ptr to irdma_dev struct 5088 * @hmc_fn_id: hmc function id 5089 */ 5090 static int irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, u8 hmc_fn_id) 5091 { 5092 struct irdma_hmc_info *hmc_info; 5093 struct irdma_hmc_obj_info *obj_info; 5094 __le64 *buf; 5095 struct irdma_dma_mem commit_fpm_mem; 5096 int ret_code = 0; 5097 u8 wait_type; 5098 5099 hmc_info = dev->hmc_info; 5100 obj_info = hmc_info->hmc_obj; 5101 buf = dev->fpm_commit_buf; 5102 5103 set_64bit_val(buf, 0, (u64)obj_info[IRDMA_HMC_IW_QP].cnt); 5104 set_64bit_val(buf, 8, (u64)obj_info[IRDMA_HMC_IW_CQ].cnt); 5105 set_64bit_val(buf, 16, (u64)obj_info[IRDMA_HMC_IW_SRQ].cnt); 5106 set_64bit_val(buf, 24, (u64)obj_info[IRDMA_HMC_IW_HTE].cnt); 5107 set_64bit_val(buf, 32, (u64)obj_info[IRDMA_HMC_IW_ARP].cnt); 5108 set_64bit_val(buf, 40, (u64)0); /* RSVD */ 5109 set_64bit_val(buf, 48, (u64)obj_info[IRDMA_HMC_IW_MR].cnt); 5110 set_64bit_val(buf, 56, (u64)obj_info[IRDMA_HMC_IW_XF].cnt); 5111 set_64bit_val(buf, 64, (u64)obj_info[IRDMA_HMC_IW_XFFL].cnt); 5112 set_64bit_val(buf, 72, (u64)obj_info[IRDMA_HMC_IW_Q1].cnt); 5113 set_64bit_val(buf, 80, (u64)obj_info[IRDMA_HMC_IW_Q1FL].cnt); 5114 set_64bit_val(buf, 88, 5115 (u64)obj_info[IRDMA_HMC_IW_TIMER].cnt); 5116 set_64bit_val(buf, 96, 5117 (u64)obj_info[IRDMA_HMC_IW_FSIMC].cnt); 5118 set_64bit_val(buf, 104, 5119 (u64)obj_info[IRDMA_HMC_IW_FSIAV].cnt); 5120 set_64bit_val(buf, 112, 5121 (u64)obj_info[IRDMA_HMC_IW_PBLE].cnt); 5122 set_64bit_val(buf, 120, (u64)0); /* RSVD */ 5123 set_64bit_val(buf, 128, (u64)obj_info[IRDMA_HMC_IW_RRF].cnt); 5124 set_64bit_val(buf, 136, 5125 (u64)obj_info[IRDMA_HMC_IW_RRFFL].cnt); 5126 set_64bit_val(buf, 144, (u64)obj_info[IRDMA_HMC_IW_HDR].cnt); 5127 set_64bit_val(buf, 152, (u64)obj_info[IRDMA_HMC_IW_MD].cnt); 5128 set_64bit_val(buf, 160, 5129 (u64)obj_info[IRDMA_HMC_IW_OOISC].cnt); 5130 set_64bit_val(buf, 168, 5131 (u64)obj_info[IRDMA_HMC_IW_OOISCFFL].cnt); 5132 set_64bit_val(buf, 192, dev->hmc_fpm_misc.fw_scratch_buf0.pa); 5133 set_64bit_val(buf, 200, dev->hmc_fpm_misc.fw_scratch_buf1.pa); 5134 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3 && 5135 dev->hmc_fpm_misc.loc_mem_pages) 5136 irdma_set_loc_mem(buf); 5137 commit_fpm_mem.pa = dev->fpm_commit_buf_pa; 5138 commit_fpm_mem.va = dev->fpm_commit_buf; 5139 5140 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 5141 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 5142 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 5143 false); 5144 ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 5145 &commit_fpm_mem, true, wait_type); 5146 if (!ret_code) 5147 irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf, 5148 hmc_info->hmc_obj, 5149 &hmc_info->sd_table.sd_cnt); 5150 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 5151 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 5152 false); 5153 5154 return ret_code; 5155 } 5156 5157 /** 5158 * cqp_sds_wqe_fill - fill cqp wqe doe sd 5159 * @cqp: struct for cqp hw 5160 * @info: sd info for wqe 5161 * @scratch: u64 saved to be used during cqp completion 5162 */ 5163 static int cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp, 5164 struct irdma_update_sds_info *info, u64 scratch) 5165 { 5166 u64 data; 5167 u64 hdr; 5168 __le64 *wqe; 5169 int mem_entries, wqe_entries; 5170 struct irdma_dma_mem *sdbuf = &cqp->sdbuf; 5171 u64 offset = 0; 5172 u32 wqe_idx; 5173 5174 wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); 5175 if (!wqe) 5176 return -ENOMEM; 5177 5178 wqe_entries = (info->cnt > 3) ? 3 : info->cnt; 5179 mem_entries = info->cnt - wqe_entries; 5180 5181 if (mem_entries) { 5182 offset = wqe_idx * IRDMA_UPDATE_SD_BUFF_SIZE; 5183 memcpy(((char *)sdbuf->va + offset), &info->entry[3], mem_entries << 4); 5184 5185 data = (u64)sdbuf->pa + offset; 5186 } else { 5187 data = 0; 5188 } 5189 data |= FIELD_PREP(IRDMA_CQPSQ_UPESD_HMCFNID, info->hmc_fn_id); 5190 set_64bit_val(wqe, 16, data); 5191 5192 switch (wqe_entries) { 5193 case 3: 5194 set_64bit_val(wqe, 48, 5195 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) | 5196 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 5197 5198 set_64bit_val(wqe, 56, info->entry[2].data); 5199 fallthrough; 5200 case 2: 5201 set_64bit_val(wqe, 32, 5202 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) | 5203 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 5204 5205 set_64bit_val(wqe, 40, info->entry[1].data); 5206 fallthrough; 5207 case 1: 5208 set_64bit_val(wqe, 0, 5209 FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd)); 5210 5211 set_64bit_val(wqe, 8, info->entry[0].data); 5212 break; 5213 default: 5214 break; 5215 } 5216 5217 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) | 5218 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 5219 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries); 5220 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5221 5222 set_64bit_val(wqe, 24, hdr); 5223 5224 if (mem_entries) 5225 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE Buffer", 5226 DUMP_PREFIX_OFFSET, 16, 8, 5227 (char *)sdbuf->va + offset, 5228 mem_entries << 4, false); 5229 5230 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE", DUMP_PREFIX_OFFSET, 16, 5231 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 5232 5233 return 0; 5234 } 5235 5236 /** 5237 * irdma_update_pe_sds - cqp wqe for sd 5238 * @dev: ptr to irdma_dev struct 5239 * @info: sd info for sd's 5240 * @scratch: u64 saved to be used during cqp completion 5241 */ 5242 static int irdma_update_pe_sds(struct irdma_sc_dev *dev, 5243 struct irdma_update_sds_info *info, u64 scratch) 5244 { 5245 struct irdma_sc_cqp *cqp = dev->cqp; 5246 int ret_code; 5247 5248 ret_code = cqp_sds_wqe_fill(cqp, info, scratch); 5249 if (!ret_code) 5250 irdma_sc_cqp_post_sq(cqp); 5251 5252 return ret_code; 5253 } 5254 5255 /** 5256 * irdma_update_sds_noccq - update sd before ccq created 5257 * @dev: sc device struct 5258 * @info: sd info for sd's 5259 */ 5260 int irdma_update_sds_noccq(struct irdma_sc_dev *dev, 5261 struct irdma_update_sds_info *info) 5262 { 5263 u32 error, val, tail; 5264 struct irdma_sc_cqp *cqp = dev->cqp; 5265 int ret_code; 5266 5267 ret_code = cqp_sds_wqe_fill(cqp, info, 0); 5268 if (ret_code) 5269 return ret_code; 5270 5271 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5272 5273 irdma_sc_cqp_post_sq(cqp); 5274 return irdma_cqp_poll_registers(cqp, tail, 5275 cqp->dev->hw_attrs.max_done_count); 5276 } 5277 5278 /** 5279 * irdma_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages 5280 * @cqp: struct for cqp hw 5281 * @scratch: u64 saved to be used during cqp completion 5282 * @hmc_fn_id: hmc function id 5283 * @post_sq: flag for cqp db to ring 5284 * @poll_registers: flag to poll register for cqp completion 5285 */ 5286 int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, 5287 u8 hmc_fn_id, bool post_sq, 5288 bool poll_registers) 5289 { 5290 u64 hdr; 5291 __le64 *wqe; 5292 u32 tail, val, error; 5293 5294 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 5295 if (!wqe) 5296 return -ENOMEM; 5297 5298 set_64bit_val(wqe, 16, 5299 FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id)); 5300 5301 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 5302 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) | 5303 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 5304 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5305 5306 set_64bit_val(wqe, 24, hdr); 5307 5308 print_hex_dump_debug("WQE: SHMC_PAGES_ALLOCATED WQE", 5309 DUMP_PREFIX_OFFSET, 16, 8, wqe, 5310 IRDMA_CQP_WQE_SIZE * 8, false); 5311 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5312 5313 if (post_sq) { 5314 irdma_sc_cqp_post_sq(cqp); 5315 if (poll_registers) 5316 /* check for cqp sq tail update */ 5317 return irdma_cqp_poll_registers(cqp, tail, 5318 cqp->dev->hw_attrs.max_done_count); 5319 else 5320 return irdma_sc_poll_for_cqp_op_done(cqp, 5321 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED, 5322 NULL); 5323 } 5324 5325 return 0; 5326 } 5327 5328 /** 5329 * irdma_cqp_ring_full - check if cqp ring is full 5330 * @cqp: struct for cqp hw 5331 */ 5332 static bool irdma_cqp_ring_full(struct irdma_sc_cqp *cqp) 5333 { 5334 return IRDMA_RING_FULL_ERR(cqp->sq_ring); 5335 } 5336 5337 /** 5338 * irdma_est_sd - returns approximate number of SDs for HMC 5339 * @dev: sc device struct 5340 * @hmc_info: hmc structure, size and count for HMC objects 5341 */ 5342 static u32 irdma_est_sd(struct irdma_sc_dev *dev, 5343 struct irdma_hmc_info *hmc_info) 5344 { 5345 struct irdma_hmc_obj_info *pble_info; 5346 int i; 5347 u64 size = 0; 5348 u64 sd; 5349 5350 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5351 if (i != IRDMA_HMC_IW_PBLE) 5352 size += round_up(hmc_info->hmc_obj[i].cnt * 5353 hmc_info->hmc_obj[i].size, 512); 5354 5355 pble_info = &hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE]; 5356 if (dev->privileged) 5357 size += round_up(pble_info->cnt * pble_info->size, 512); 5358 if (size & 0x1FFFFF) 5359 sd = (size >> 21) + 1; /* add 1 for remainder */ 5360 else 5361 sd = size >> 21; 5362 if (!dev->privileged && !dev->hmc_fpm_misc.loc_mem_pages) { 5363 /* 2MB alignment for VF PBLE HMC */ 5364 size = pble_info->cnt * pble_info->size; 5365 if (size & 0x1FFFFF) 5366 sd += (size >> 21) + 1; /* add 1 for remainder */ 5367 else 5368 sd += size >> 21; 5369 } 5370 if (sd > 0xFFFFFFFF) { 5371 ibdev_dbg(to_ibdev(dev), "HMC: sd overflow[%lld]\n", sd); 5372 sd = 0xFFFFFFFF - 1; 5373 } 5374 5375 return (u32)sd; 5376 } 5377 5378 /** 5379 * irdma_sc_query_rdma_features - query RDMA features and FW ver 5380 * @cqp: struct for cqp hw 5381 * @buf: buffer to hold query info 5382 * @scratch: u64 saved to be used during cqp completion 5383 */ 5384 static int irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp, 5385 struct irdma_dma_mem *buf, u64 scratch) 5386 { 5387 u32 tail, val, error; 5388 __le64 *wqe; 5389 int status; 5390 u64 temp; 5391 5392 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 5393 if (!wqe) 5394 return -ENOMEM; 5395 5396 temp = buf->pa; 5397 set_64bit_val(wqe, 32, temp); 5398 5399 temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID, 5400 cqp->polarity) | 5401 FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) | 5402 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES); 5403 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5404 5405 set_64bit_val(wqe, 24, temp); 5406 5407 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 5408 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 5409 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5410 5411 irdma_sc_cqp_post_sq(cqp); 5412 status = irdma_cqp_poll_registers(cqp, tail, 5413 cqp->dev->hw_attrs.max_done_count); 5414 if (error || status) 5415 status = -EINVAL; 5416 5417 return status; 5418 } 5419 5420 /** 5421 * irdma_get_rdma_features - get RDMA features 5422 * @dev: sc device struct 5423 */ 5424 int irdma_get_rdma_features(struct irdma_sc_dev *dev) 5425 { 5426 int ret_code; 5427 struct irdma_dma_mem feat_buf; 5428 u64 temp; 5429 u16 byte_idx, feat_type, feat_cnt, feat_idx; 5430 5431 feat_buf.size = ALIGN(IRDMA_FEATURE_BUF_SIZE, 5432 IRDMA_FEATURE_BUF_ALIGNMENT); 5433 feat_buf.va = dma_alloc_coherent(dev->hw->device, feat_buf.size, 5434 &feat_buf.pa, GFP_KERNEL); 5435 if (!feat_buf.va) 5436 return -ENOMEM; 5437 5438 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 5439 if (ret_code) 5440 goto exit; 5441 5442 get_64bit_val(feat_buf.va, 0, &temp); 5443 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 5444 if (feat_cnt < 2) { 5445 ret_code = -EINVAL; 5446 goto exit; 5447 } else if (feat_cnt > IRDMA_MAX_FEATURES) { 5448 ibdev_dbg(to_ibdev(dev), 5449 "DEV: feature buf size insufficient, retrying with larger buffer\n"); 5450 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 5451 feat_buf.pa); 5452 feat_buf.va = NULL; 5453 feat_buf.size = ALIGN(8 * feat_cnt, 5454 IRDMA_FEATURE_BUF_ALIGNMENT); 5455 feat_buf.va = dma_alloc_coherent(dev->hw->device, 5456 feat_buf.size, &feat_buf.pa, 5457 GFP_KERNEL); 5458 if (!feat_buf.va) 5459 return -ENOMEM; 5460 5461 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 5462 if (ret_code) 5463 goto exit; 5464 5465 get_64bit_val(feat_buf.va, 0, &temp); 5466 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 5467 if (feat_cnt < 2) { 5468 ret_code = -EINVAL; 5469 goto exit; 5470 } 5471 } 5472 5473 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 5474 16, 8, feat_buf.va, feat_cnt * 8, false); 5475 5476 for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, (u16)IRDMA_MAX_FEATURES); 5477 feat_idx++, byte_idx += 8) { 5478 get_64bit_val(feat_buf.va, byte_idx, &temp); 5479 feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp); 5480 if (feat_type >= IRDMA_MAX_FEATURES) { 5481 ibdev_dbg(to_ibdev(dev), 5482 "DEV: found unrecognized feature type %d\n", 5483 feat_type); 5484 continue; 5485 } 5486 dev->feature_info[feat_type] = temp; 5487 } 5488 5489 if (dev->feature_info[IRDMA_FTN_FLAGS] & IRDMA_ATOMICS_ALLOWED_BIT) 5490 dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_ATOMIC_OPS; 5491 5492 exit: 5493 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 5494 feat_buf.pa); 5495 feat_buf.va = NULL; 5496 return ret_code; 5497 } 5498 5499 static u32 irdma_q1_cnt(struct irdma_sc_dev *dev, 5500 struct irdma_hmc_info *hmc_info, u32 qpwanted) 5501 { 5502 u32 q1_cnt; 5503 5504 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 5505 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted); 5506 } else { 5507 if (dev->cqp->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) 5508 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted + 512); 5509 else 5510 q1_cnt = dev->hw_attrs.max_hw_ird * 2 * qpwanted; 5511 } 5512 5513 return q1_cnt; 5514 } 5515 5516 static void cfg_fpm_value_gen_1(struct irdma_sc_dev *dev, 5517 struct irdma_hmc_info *hmc_info, u32 qpwanted) 5518 { 5519 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = roundup_pow_of_two(qpwanted * dev->hw_attrs.max_hw_wqes); 5520 } 5521 5522 static void cfg_fpm_value_gen_2(struct irdma_sc_dev *dev, 5523 struct irdma_hmc_info *hmc_info, u32 qpwanted) 5524 { 5525 struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc; 5526 5527 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = 5528 4 * hmc_fpm_misc->xf_block_size * qpwanted; 5529 5530 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 5531 5532 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt) 5533 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 32 * qpwanted; 5534 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 5535 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = 5536 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 5537 hmc_fpm_misc->rrf_block_size; 5538 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt) 5539 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt = 32 * qpwanted; 5540 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt) 5541 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].cnt = 5542 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt / 5543 hmc_fpm_misc->ooiscf_block_size; 5544 } 5545 5546 /** 5547 * irdma_get_rsrc_mem_config - configure resources if local memory or host 5548 * @dev: sc device struct 5549 * @is_mrte_loc_mem: if true, MR's to be in local memory because sd=loc pages 5550 * 5551 * Only mr can be configured host or local memory if qp's are in local memory. 5552 * If qp is in local memory, then all resource object will be in local memory 5553 * except mr which can be either host or local memory. The only exception 5554 * is pble's which are always in host memory. 5555 */ 5556 static void irdma_get_rsrc_mem_config(struct irdma_sc_dev *dev, bool is_mrte_loc_mem) 5557 { 5558 struct irdma_hmc_info *hmc_info = dev->hmc_info; 5559 int i; 5560 5561 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5562 hmc_info->hmc_obj[i].mem_loc = IRDMA_LOC_MEM; 5563 5564 if (dev->feature_info[IRDMA_OBJ_1] && !is_mrte_loc_mem) { 5565 u8 mem_type; 5566 5567 mem_type = (u8)FIELD_GET(IRDMA_MR_MEM_LOC, dev->feature_info[IRDMA_OBJ_1]); 5568 5569 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc = 5570 (mem_type & IRDMA_OBJ_LOC_MEM_BIT) ? 5571 IRDMA_LOC_MEM : IRDMA_HOST_MEM; 5572 } else { 5573 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc = IRDMA_LOC_MEM; 5574 } 5575 5576 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].mem_loc = IRDMA_HOST_MEM; 5577 5578 ibdev_dbg(to_ibdev(dev), "HMC: INFO: mrte_mem_loc = %d pble = %d\n", 5579 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc, 5580 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].mem_loc); 5581 } 5582 5583 /** 5584 * irdma_cfg_sd_mem - allocate sd memory 5585 * @dev: sc device struct 5586 * @hmc_info: ptr to irdma_hmc_obj_info struct 5587 */ 5588 static int irdma_cfg_sd_mem(struct irdma_sc_dev *dev, 5589 struct irdma_hmc_info *hmc_info) 5590 { 5591 struct irdma_virt_mem virt_mem; 5592 u32 mem_size; 5593 5594 mem_size = sizeof(struct irdma_hmc_sd_entry) * hmc_info->sd_table.sd_cnt; 5595 virt_mem.size = mem_size; 5596 virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL); 5597 if (!virt_mem.va) 5598 return -ENOMEM; 5599 hmc_info->sd_table.sd_entry = virt_mem.va; 5600 5601 return 0; 5602 } 5603 5604 /** 5605 * irdma_get_objs_pages - get number of 2M pages needed 5606 * @dev: sc device struct 5607 * @hmc_info: pointer to the HMC configuration information struct 5608 * @mem_loc: pages for local or host memory 5609 */ 5610 static u32 irdma_get_objs_pages(struct irdma_sc_dev *dev, 5611 struct irdma_hmc_info *hmc_info, 5612 enum irdma_hmc_obj_mem mem_loc) 5613 { 5614 u64 size = 0; 5615 int i; 5616 5617 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { 5618 if (hmc_info->hmc_obj[i].mem_loc == mem_loc) { 5619 size += round_up(hmc_info->hmc_obj[i].cnt * 5620 hmc_info->hmc_obj[i].size, 512); 5621 } 5622 } 5623 5624 return DIV_ROUND_UP(size, IRDMA_HMC_PAGE_SIZE); 5625 } 5626 5627 /** 5628 * irdma_set_host_hmc_rsrc_gen_3 - calculate host hmc resources for gen 3 5629 * @dev: sc device struct 5630 */ 5631 static void irdma_set_host_hmc_rsrc_gen_3(struct irdma_sc_dev *dev) 5632 { 5633 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5634 struct irdma_hmc_info *hmc_info; 5635 enum irdma_hmc_obj_mem mrte_loc; 5636 u32 mrwanted, pblewanted; 5637 u32 avail_sds, mr_sds; 5638 5639 hmc_info = dev->hmc_info; 5640 hmc_fpm_misc = &dev->hmc_fpm_misc; 5641 avail_sds = hmc_fpm_misc->max_sds; 5642 mrte_loc = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc; 5643 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 5644 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; 5645 5646 if (mrte_loc == IRDMA_HOST_MEM && avail_sds > IRDMA_MIN_PBLE_PAGES) { 5647 mr_sds = avail_sds - IRDMA_MIN_PBLE_PAGES; 5648 mrwanted = min(mrwanted, mr_sds * MAX_MR_PER_SD); 5649 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; 5650 avail_sds -= DIV_ROUND_UP(mrwanted, MAX_MR_PER_SD); 5651 } 5652 5653 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS]) && 5654 pblewanted > avail_sds * MAX_PBLE_PER_SD) 5655 ibdev_dbg(to_ibdev(dev), 5656 "HMC: Warn: Resource version 2: pble wanted = 0x%x available = 0x%x\n", 5657 pblewanted, avail_sds * MAX_PBLE_PER_SD); 5658 5659 pblewanted = min(pblewanted, avail_sds * MAX_PBLE_PER_SD); 5660 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 5661 } 5662 5663 /** 5664 * irdma_verify_commit_fpm_gen_3 - verify query fpm values 5665 * @dev: sc device struct 5666 * @max_pages: max local memory available 5667 * @qpwanted: number of qp's wanted 5668 */ 5669 static int irdma_verify_commit_fpm_gen_3(struct irdma_sc_dev *dev, 5670 u32 max_pages, 5671 u32 qpwanted) 5672 { 5673 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5674 u32 rrf_cnt, xf_cnt, timer_cnt, pages_needed; 5675 struct irdma_hmc_info *hmc_info; 5676 u32 rrffl_cnt = 0; 5677 u32 xffl_cnt = 0; 5678 u32 q1fl_cnt; 5679 5680 hmc_info = dev->hmc_info; 5681 hmc_fpm_misc = &dev->hmc_fpm_misc; 5682 5683 rrf_cnt = roundup_pow_of_two(IRDMA_RRF_MULTIPLIER * qpwanted); 5684 5685 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 5686 rrffl_cnt = 5687 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 5688 hmc_fpm_misc->rrf_block_size; 5689 5690 xf_cnt = roundup_pow_of_two(IRDMA_XF_MULTIPLIER * qpwanted); 5691 5692 if (xf_cnt) 5693 xffl_cnt = xf_cnt / hmc_fpm_misc->xf_block_size; 5694 5695 timer_cnt = (round_up(qpwanted, 512) / 512 + 1) * 5696 hmc_fpm_misc->timer_bucket; 5697 5698 q1fl_cnt = hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 5699 5700 pages_needed = irdma_get_objs_pages(dev, hmc_info, IRDMA_LOC_MEM); 5701 if (pages_needed > max_pages) { 5702 ibdev_dbg(to_ibdev(dev), 5703 "HMC: FAIL: SW counts rrf_cnt = %u rrffl_cnt = %u timer_cnt = %u", 5704 rrf_cnt, rrffl_cnt, timer_cnt); 5705 ibdev_dbg(to_ibdev(dev), 5706 "HMC: FAIL: SW counts xf_cnt = %u xffl_cnt = %u q1fl_cnt = %u", 5707 xf_cnt, xffl_cnt, q1fl_cnt); 5708 5709 return -EINVAL; 5710 } 5711 5712 hmc_fpm_misc->max_sds -= pages_needed; 5713 hmc_fpm_misc->loc_mem_pages -= pages_needed; 5714 5715 return 0; 5716 } 5717 5718 /** 5719 * irdma_set_loc_hmc_rsrc_gen_3 - calculate hmc resources for gen 3 5720 * @dev: sc device struct 5721 * @max_pages: max local memory available 5722 * @qpwanted: number of qp's wanted 5723 */ 5724 static int irdma_set_loc_hmc_rsrc_gen_3(struct irdma_sc_dev *dev, 5725 u32 max_pages, 5726 u32 qpwanted) 5727 { 5728 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5729 u32 rrf_cnt, xf_cnt, timer_cnt, pages_needed; 5730 struct irdma_hmc_info *hmc_info; 5731 u32 ird, ord; 5732 5733 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5734 return irdma_verify_commit_fpm_gen_3(dev, max_pages, qpwanted); 5735 5736 hmc_info = dev->hmc_info; 5737 hmc_fpm_misc = &dev->hmc_fpm_misc; 5738 ird = dev->hw_attrs.max_hw_ird; 5739 ord = dev->hw_attrs.max_hw_ord; 5740 5741 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 5742 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; 5743 5744 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = 5745 min(hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, qpwanted * 2); 5746 5747 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = 5748 min(qpwanted * 8, hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); 5749 5750 rrf_cnt = roundup_pow_of_two(IRDMA_RRF_MULTIPLIER * qpwanted); 5751 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 5752 min(hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt, rrf_cnt); 5753 5754 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 5755 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = 5756 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 5757 hmc_fpm_misc->rrf_block_size; 5758 5759 xf_cnt = roundup_pow_of_two(IRDMA_XF_MULTIPLIER * qpwanted); 5760 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = 5761 min(hmc_info->hmc_obj[IRDMA_HMC_IW_XF].max_cnt, xf_cnt); 5762 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = 5763 xf_cnt / hmc_fpm_misc->xf_block_size; 5764 5765 timer_cnt = (round_up(qpwanted, 512) / 512 + 1) * 5766 hmc_fpm_misc->timer_bucket; 5767 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = 5768 min(timer_cnt, hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt); 5769 5770 do { 5771 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = roundup_pow_of_two(ird * 2 * qpwanted); 5772 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = 5773 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 5774 5775 pages_needed = irdma_get_objs_pages(dev, hmc_info, IRDMA_LOC_MEM); 5776 if (pages_needed <= max_pages) 5777 break; 5778 5779 ird /= 2; 5780 ord /= 2; 5781 } while (ird >= IRDMA_MIN_IRD); 5782 5783 if (ird < IRDMA_MIN_IRD) { 5784 ibdev_dbg(to_ibdev(dev), "HMC: FAIL: IRD=%u Q1 CNT = %u\n", 5785 ird, hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt); 5786 return -EINVAL; 5787 } 5788 5789 dev->hw_attrs.max_hw_ird = ird; 5790 dev->hw_attrs.max_hw_ord = ord; 5791 hmc_fpm_misc->max_sds -= pages_needed; 5792 5793 return 0; 5794 } 5795 5796 /** 5797 * cfg_fpm_value_gen_3 - configure fpm for gen 3 5798 * @dev: sc device struct 5799 * @hmc_info: ptr to irdma_hmc_obj_info struct 5800 * @hmc_fpm_misc: ptr to fpm data 5801 */ 5802 static int cfg_fpm_value_gen_3(struct irdma_sc_dev *dev, 5803 struct irdma_hmc_info *hmc_info, 5804 struct irdma_hmc_fpm_misc *hmc_fpm_misc) 5805 { 5806 enum irdma_hmc_obj_mem mrte_loc; 5807 u32 mrwanted, qpwanted; 5808 int i, ret_code = 0; 5809 u32 loc_mem_pages; 5810 bool is_mrte_loc_mem; 5811 5812 loc_mem_pages = hmc_fpm_misc->loc_mem_pages; 5813 is_mrte_loc_mem = hmc_fpm_misc->loc_mem_pages == hmc_fpm_misc->max_sds; 5814 5815 irdma_get_rsrc_mem_config(dev, is_mrte_loc_mem); 5816 mrte_loc = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc; 5817 5818 if (is_mrte_loc_mem) 5819 loc_mem_pages -= IRDMA_MIN_PBLE_PAGES; 5820 5821 ibdev_dbg(to_ibdev(dev), 5822 "HMC: mrte_loc %d loc_mem %u fpm max sds %u host_obj %d\n", 5823 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc, 5824 hmc_fpm_misc->loc_mem_pages, hmc_fpm_misc->max_sds, 5825 is_mrte_loc_mem); 5826 5827 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; 5828 qpwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt; 5829 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 5830 5831 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt = 0; 5832 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt = 0; 5833 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].max_cnt = 0; 5834 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt = 0; 5835 5836 if (!FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5837 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt = 5838 min(hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt, 5839 (u32)IRDMA_FSIAV_CNT_MAX); 5840 5841 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5842 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; 5843 5844 while (qpwanted >= IRDMA_MIN_QP_CNT) { 5845 if (!irdma_set_loc_hmc_rsrc_gen_3(dev, loc_mem_pages, qpwanted)) 5846 break; 5847 5848 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5849 return -EINVAL; 5850 5851 qpwanted /= 2; 5852 if (mrte_loc == IRDMA_LOC_MEM) { 5853 mrwanted = qpwanted * IRDMA_MIN_MR_PER_QP; 5854 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = 5855 min(hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, mrwanted); 5856 } 5857 } 5858 5859 if (qpwanted < IRDMA_MIN_QP_CNT) { 5860 ibdev_dbg(to_ibdev(dev), 5861 "HMC: ERROR: could not allocate fpm resources\n"); 5862 return -EINVAL; 5863 } 5864 5865 irdma_set_host_hmc_rsrc_gen_3(dev); 5866 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); 5867 if (ret_code) { 5868 ibdev_dbg(to_ibdev(dev), 5869 "HMC: cfg_iw_fpm returned error_code[x%08X]\n", 5870 readl(dev->hw_regs[IRDMA_CQPERRCODES])); 5871 5872 return ret_code; 5873 } 5874 5875 return irdma_cfg_sd_mem(dev, hmc_info); 5876 } 5877 5878 /** 5879 * irdma_cfg_fpm_val - configure HMC objects 5880 * @dev: sc device struct 5881 * @qp_count: desired qp count 5882 */ 5883 int irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count) 5884 { 5885 u32 qpwanted, mrwanted, pblewanted; 5886 u32 powerof2, hte, i; 5887 u32 sd_needed; 5888 u32 sd_diff; 5889 u32 loop_count = 0; 5890 struct irdma_hmc_info *hmc_info; 5891 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5892 int ret_code = 0; 5893 u32 max_sds; 5894 5895 hmc_info = dev->hmc_info; 5896 hmc_fpm_misc = &dev->hmc_fpm_misc; 5897 5898 ret_code = irdma_sc_init_iw_hmc(dev, dev->hmc_fn_id); 5899 if (ret_code) { 5900 ibdev_dbg(to_ibdev(dev), 5901 "HMC: irdma_sc_init_iw_hmc returned error_code = %d\n", 5902 ret_code); 5903 return ret_code; 5904 } 5905 5906 max_sds = hmc_fpm_misc->max_sds; 5907 5908 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 5909 return cfg_fpm_value_gen_3(dev, hmc_info, hmc_fpm_misc); 5910 5911 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5912 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; 5913 sd_needed = irdma_est_sd(dev, hmc_info); 5914 ibdev_dbg(to_ibdev(dev), "HMC: sd count %u where max sd is %u\n", 5915 hmc_info->sd_table.sd_cnt, max_sds); 5916 5917 qpwanted = min(qp_count, hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt); 5918 5919 powerof2 = 1; 5920 while (powerof2 <= qpwanted) 5921 powerof2 *= 2; 5922 powerof2 /= 2; 5923 qpwanted = powerof2; 5924 5925 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; 5926 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; 5927 5928 ibdev_dbg(to_ibdev(dev), 5929 "HMC: req_qp=%d max_sd=%u, max_qp = %u, max_cq=%u, max_mr=%u, max_pble=%u, mc=%d, av=%u\n", 5930 qp_count, max_sds, 5931 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt, 5932 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt, 5933 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, 5934 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt, 5935 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt, 5936 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); 5937 5938 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt = 5939 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt; 5940 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = 5941 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt; 5942 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt = 5943 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt; 5944 hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1; 5945 5946 while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt) 5947 qpwanted /= 2; 5948 5949 do { 5950 ++loop_count; 5951 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; 5952 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = 5953 min(2 * qpwanted, hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt); 5954 hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].cnt = 0; /* Reserved */ 5955 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; 5956 5957 hte = round_up(qpwanted + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 512); 5958 powerof2 = 1; 5959 while (powerof2 < hte) 5960 powerof2 *= 2; 5961 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].cnt = 5962 powerof2 * hmc_fpm_misc->ht_multiplier; 5963 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 5964 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted); 5965 else 5966 cfg_fpm_value_gen_2(dev, hmc_info, qpwanted); 5967 5968 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = irdma_q1_cnt(dev, hmc_info, qpwanted); 5969 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = 5970 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size; 5971 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = 5972 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 5973 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = 5974 (round_up(qpwanted, 512) / 512 + 1) * hmc_fpm_misc->timer_bucket; 5975 5976 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 5977 sd_needed = irdma_est_sd(dev, hmc_info); 5978 ibdev_dbg(to_ibdev(dev), 5979 "HMC: sd_needed = %d, hmc_fpm_misc->max_sds=%d, mrwanted=%d, pblewanted=%d qpwanted=%d\n", 5980 sd_needed, hmc_fpm_misc->max_sds, mrwanted, 5981 pblewanted, qpwanted); 5982 5983 /* Do not reduce resources further. All objects fit with max SDs */ 5984 if (sd_needed <= hmc_fpm_misc->max_sds) 5985 break; 5986 5987 sd_diff = sd_needed - hmc_fpm_misc->max_sds; 5988 if (sd_diff > 128) { 5989 if (!(loop_count % 2) && qpwanted > 128) { 5990 qpwanted /= 2; 5991 } else { 5992 pblewanted /= 2; 5993 mrwanted /= 2; 5994 } 5995 continue; 5996 } 5997 5998 if (dev->cqp->hmc_profile != IRDMA_HMC_PROFILE_FAVOR_VF && 5999 pblewanted > (512 * FPM_MULTIPLIER * sd_diff)) { 6000 pblewanted -= 256 * FPM_MULTIPLIER * sd_diff; 6001 continue; 6002 } else if (pblewanted > (100 * FPM_MULTIPLIER)) { 6003 pblewanted -= 10 * FPM_MULTIPLIER; 6004 } else if (pblewanted > FPM_MULTIPLIER) { 6005 pblewanted -= FPM_MULTIPLIER; 6006 } else if (qpwanted <= 128) { 6007 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt > 256) 6008 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt /= 2; 6009 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 6010 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 6011 } 6012 if (mrwanted > FPM_MULTIPLIER) 6013 mrwanted -= FPM_MULTIPLIER; 6014 if (!(loop_count % 10) && qpwanted > 128) { 6015 qpwanted /= 2; 6016 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 6017 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 6018 } 6019 } while (loop_count < 2000); 6020 6021 if (sd_needed > hmc_fpm_misc->max_sds) { 6022 ibdev_dbg(to_ibdev(dev), 6023 "HMC: cfg_fpm failed loop_cnt=%u, sd_needed=%u, max sd count %u\n", 6024 loop_count, sd_needed, hmc_info->sd_table.sd_cnt); 6025 return -EINVAL; 6026 } 6027 6028 if (loop_count > 1 && sd_needed < max_sds) { 6029 pblewanted += (max_sds - sd_needed) * 256 * FPM_MULTIPLIER; 6030 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 6031 sd_needed = irdma_est_sd(dev, hmc_info); 6032 } 6033 6034 ibdev_dbg(to_ibdev(dev), 6035 "HMC: loop_cnt=%d, sd_needed=%d, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d, mc=%d, ah=%d, max sd count %d, first sd index %d\n", 6036 loop_count, sd_needed, 6037 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt, 6038 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 6039 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt, 6040 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt, 6041 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 6042 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt, 6043 hmc_info->sd_table.sd_cnt, hmc_info->first_sd_index); 6044 6045 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); 6046 if (ret_code) { 6047 ibdev_dbg(to_ibdev(dev), 6048 "HMC: cfg_iw_fpm returned error_code[x%08X]\n", 6049 readl(dev->hw_regs[IRDMA_CQPERRCODES])); 6050 return ret_code; 6051 } 6052 6053 return irdma_cfg_sd_mem(dev, hmc_info); 6054 } 6055 6056 /** 6057 * irdma_exec_cqp_cmd - execute cqp cmd when wqe are available 6058 * @dev: rdma device 6059 * @pcmdinfo: cqp command info 6060 */ 6061 static int irdma_exec_cqp_cmd(struct irdma_sc_dev *dev, 6062 struct cqp_cmds_info *pcmdinfo) 6063 { 6064 int status; 6065 struct irdma_dma_mem val_mem; 6066 bool alloc = false; 6067 6068 dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++; 6069 switch (pcmdinfo->cqp_cmd) { 6070 case IRDMA_OP_CEQ_DESTROY: 6071 status = irdma_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq, 6072 pcmdinfo->in.u.ceq_destroy.scratch, 6073 pcmdinfo->post_sq); 6074 break; 6075 case IRDMA_OP_AEQ_DESTROY: 6076 status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq, 6077 pcmdinfo->in.u.aeq_destroy.scratch, 6078 pcmdinfo->post_sq); 6079 6080 break; 6081 case IRDMA_OP_CEQ_CREATE: 6082 status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq, 6083 pcmdinfo->in.u.ceq_create.scratch, 6084 pcmdinfo->post_sq); 6085 break; 6086 case IRDMA_OP_AEQ_CREATE: 6087 status = irdma_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq, 6088 pcmdinfo->in.u.aeq_create.scratch, 6089 pcmdinfo->post_sq); 6090 break; 6091 case IRDMA_OP_QP_UPLOAD_CONTEXT: 6092 status = irdma_sc_qp_upload_context(pcmdinfo->in.u.qp_upload_context.dev, 6093 &pcmdinfo->in.u.qp_upload_context.info, 6094 pcmdinfo->in.u.qp_upload_context.scratch, 6095 pcmdinfo->post_sq); 6096 break; 6097 case IRDMA_OP_CQ_CREATE: 6098 status = irdma_sc_cq_create(pcmdinfo->in.u.cq_create.cq, 6099 pcmdinfo->in.u.cq_create.scratch, 6100 pcmdinfo->in.u.cq_create.check_overflow, 6101 pcmdinfo->post_sq); 6102 break; 6103 case IRDMA_OP_CQ_MODIFY: 6104 status = irdma_sc_cq_modify(pcmdinfo->in.u.cq_modify.cq, 6105 &pcmdinfo->in.u.cq_modify.info, 6106 pcmdinfo->in.u.cq_modify.scratch, 6107 pcmdinfo->post_sq); 6108 break; 6109 case IRDMA_OP_CQ_DESTROY: 6110 status = irdma_sc_cq_destroy(pcmdinfo->in.u.cq_destroy.cq, 6111 pcmdinfo->in.u.cq_destroy.scratch, 6112 pcmdinfo->post_sq); 6113 break; 6114 case IRDMA_OP_QP_FLUSH_WQES: 6115 status = irdma_sc_qp_flush_wqes(pcmdinfo->in.u.qp_flush_wqes.qp, 6116 &pcmdinfo->in.u.qp_flush_wqes.info, 6117 pcmdinfo->in.u.qp_flush_wqes.scratch, 6118 pcmdinfo->post_sq); 6119 break; 6120 case IRDMA_OP_GEN_AE: 6121 status = irdma_sc_gen_ae(pcmdinfo->in.u.gen_ae.qp, 6122 &pcmdinfo->in.u.gen_ae.info, 6123 pcmdinfo->in.u.gen_ae.scratch, 6124 pcmdinfo->post_sq); 6125 break; 6126 case IRDMA_OP_MANAGE_PUSH_PAGE: 6127 status = irdma_sc_manage_push_page(pcmdinfo->in.u.manage_push_page.cqp, 6128 &pcmdinfo->in.u.manage_push_page.info, 6129 pcmdinfo->in.u.manage_push_page.scratch, 6130 pcmdinfo->post_sq); 6131 break; 6132 case IRDMA_OP_UPDATE_PE_SDS: 6133 status = irdma_update_pe_sds(pcmdinfo->in.u.update_pe_sds.dev, 6134 &pcmdinfo->in.u.update_pe_sds.info, 6135 pcmdinfo->in.u.update_pe_sds.scratch); 6136 break; 6137 case IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE: 6138 /* switch to calling through the call table */ 6139 status = 6140 irdma_sc_manage_hmc_pm_func_table(pcmdinfo->in.u.manage_hmc_pm.dev->cqp, 6141 &pcmdinfo->in.u.manage_hmc_pm.info, 6142 pcmdinfo->in.u.manage_hmc_pm.scratch, 6143 true); 6144 break; 6145 case IRDMA_OP_SUSPEND: 6146 status = irdma_sc_suspend_qp(pcmdinfo->in.u.suspend_resume.cqp, 6147 pcmdinfo->in.u.suspend_resume.qp, 6148 pcmdinfo->in.u.suspend_resume.scratch); 6149 break; 6150 case IRDMA_OP_RESUME: 6151 status = irdma_sc_resume_qp(pcmdinfo->in.u.suspend_resume.cqp, 6152 pcmdinfo->in.u.suspend_resume.qp, 6153 pcmdinfo->in.u.suspend_resume.scratch); 6154 break; 6155 case IRDMA_OP_QUERY_FPM_VAL: 6156 val_mem.pa = pcmdinfo->in.u.query_fpm_val.fpm_val_pa; 6157 val_mem.va = pcmdinfo->in.u.query_fpm_val.fpm_val_va; 6158 status = irdma_sc_query_fpm_val(pcmdinfo->in.u.query_fpm_val.cqp, 6159 pcmdinfo->in.u.query_fpm_val.scratch, 6160 pcmdinfo->in.u.query_fpm_val.hmc_fn_id, 6161 &val_mem, true, IRDMA_CQP_WAIT_EVENT); 6162 break; 6163 case IRDMA_OP_COMMIT_FPM_VAL: 6164 val_mem.pa = pcmdinfo->in.u.commit_fpm_val.fpm_val_pa; 6165 val_mem.va = pcmdinfo->in.u.commit_fpm_val.fpm_val_va; 6166 status = irdma_sc_commit_fpm_val(pcmdinfo->in.u.commit_fpm_val.cqp, 6167 pcmdinfo->in.u.commit_fpm_val.scratch, 6168 pcmdinfo->in.u.commit_fpm_val.hmc_fn_id, 6169 &val_mem, 6170 true, 6171 IRDMA_CQP_WAIT_EVENT); 6172 break; 6173 case IRDMA_OP_STATS_ALLOCATE: 6174 alloc = true; 6175 fallthrough; 6176 case IRDMA_OP_STATS_FREE: 6177 status = irdma_sc_manage_stats_inst(pcmdinfo->in.u.stats_manage.cqp, 6178 &pcmdinfo->in.u.stats_manage.info, 6179 alloc, 6180 pcmdinfo->in.u.stats_manage.scratch); 6181 break; 6182 case IRDMA_OP_STATS_GATHER: 6183 status = irdma_sc_gather_stats(pcmdinfo->in.u.stats_gather.cqp, 6184 &pcmdinfo->in.u.stats_gather.info, 6185 pcmdinfo->in.u.stats_gather.scratch); 6186 break; 6187 case IRDMA_OP_WS_MODIFY_NODE: 6188 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 6189 &pcmdinfo->in.u.ws_node.info, 6190 IRDMA_MODIFY_NODE, 6191 pcmdinfo->in.u.ws_node.scratch); 6192 break; 6193 case IRDMA_OP_WS_DELETE_NODE: 6194 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 6195 &pcmdinfo->in.u.ws_node.info, 6196 IRDMA_DEL_NODE, 6197 pcmdinfo->in.u.ws_node.scratch); 6198 break; 6199 case IRDMA_OP_WS_ADD_NODE: 6200 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 6201 &pcmdinfo->in.u.ws_node.info, 6202 IRDMA_ADD_NODE, 6203 pcmdinfo->in.u.ws_node.scratch); 6204 break; 6205 case IRDMA_OP_SET_UP_MAP: 6206 status = irdma_sc_set_up_map(pcmdinfo->in.u.up_map.cqp, 6207 &pcmdinfo->in.u.up_map.info, 6208 pcmdinfo->in.u.up_map.scratch); 6209 break; 6210 case IRDMA_OP_QUERY_RDMA_FEATURES: 6211 status = irdma_sc_query_rdma_features(pcmdinfo->in.u.query_rdma.cqp, 6212 &pcmdinfo->in.u.query_rdma.query_buff_mem, 6213 pcmdinfo->in.u.query_rdma.scratch); 6214 break; 6215 case IRDMA_OP_DELETE_ARP_CACHE_ENTRY: 6216 status = irdma_sc_del_arp_cache_entry(pcmdinfo->in.u.del_arp_cache_entry.cqp, 6217 pcmdinfo->in.u.del_arp_cache_entry.scratch, 6218 pcmdinfo->in.u.del_arp_cache_entry.arp_index, 6219 pcmdinfo->post_sq); 6220 break; 6221 case IRDMA_OP_MANAGE_APBVT_ENTRY: 6222 status = irdma_sc_manage_apbvt_entry(pcmdinfo->in.u.manage_apbvt_entry.cqp, 6223 &pcmdinfo->in.u.manage_apbvt_entry.info, 6224 pcmdinfo->in.u.manage_apbvt_entry.scratch, 6225 pcmdinfo->post_sq); 6226 break; 6227 case IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY: 6228 status = irdma_sc_manage_qhash_table_entry(pcmdinfo->in.u.manage_qhash_table_entry.cqp, 6229 &pcmdinfo->in.u.manage_qhash_table_entry.info, 6230 pcmdinfo->in.u.manage_qhash_table_entry.scratch, 6231 pcmdinfo->post_sq); 6232 break; 6233 case IRDMA_OP_QP_MODIFY: 6234 status = irdma_sc_qp_modify(pcmdinfo->in.u.qp_modify.qp, 6235 &pcmdinfo->in.u.qp_modify.info, 6236 pcmdinfo->in.u.qp_modify.scratch, 6237 pcmdinfo->post_sq); 6238 break; 6239 case IRDMA_OP_QP_CREATE: 6240 status = irdma_sc_qp_create(pcmdinfo->in.u.qp_create.qp, 6241 &pcmdinfo->in.u.qp_create.info, 6242 pcmdinfo->in.u.qp_create.scratch, 6243 pcmdinfo->post_sq); 6244 break; 6245 case IRDMA_OP_QP_DESTROY: 6246 status = irdma_sc_qp_destroy(pcmdinfo->in.u.qp_destroy.qp, 6247 pcmdinfo->in.u.qp_destroy.scratch, 6248 pcmdinfo->in.u.qp_destroy.remove_hash_idx, 6249 pcmdinfo->in.u.qp_destroy.ignore_mw_bnd, 6250 pcmdinfo->post_sq); 6251 break; 6252 case IRDMA_OP_ALLOC_STAG: 6253 status = irdma_sc_alloc_stag(pcmdinfo->in.u.alloc_stag.dev, 6254 &pcmdinfo->in.u.alloc_stag.info, 6255 pcmdinfo->in.u.alloc_stag.scratch, 6256 pcmdinfo->post_sq); 6257 break; 6258 case IRDMA_OP_MR_REG_NON_SHARED: 6259 status = irdma_sc_mr_reg_non_shared(pcmdinfo->in.u.mr_reg_non_shared.dev, 6260 &pcmdinfo->in.u.mr_reg_non_shared.info, 6261 pcmdinfo->in.u.mr_reg_non_shared.scratch, 6262 pcmdinfo->post_sq); 6263 break; 6264 case IRDMA_OP_DEALLOC_STAG: 6265 status = irdma_sc_dealloc_stag(pcmdinfo->in.u.dealloc_stag.dev, 6266 &pcmdinfo->in.u.dealloc_stag.info, 6267 pcmdinfo->in.u.dealloc_stag.scratch, 6268 pcmdinfo->post_sq); 6269 break; 6270 case IRDMA_OP_MW_ALLOC: 6271 status = irdma_sc_mw_alloc(pcmdinfo->in.u.mw_alloc.dev, 6272 &pcmdinfo->in.u.mw_alloc.info, 6273 pcmdinfo->in.u.mw_alloc.scratch, 6274 pcmdinfo->post_sq); 6275 break; 6276 case IRDMA_OP_ADD_ARP_CACHE_ENTRY: 6277 status = irdma_sc_add_arp_cache_entry(pcmdinfo->in.u.add_arp_cache_entry.cqp, 6278 &pcmdinfo->in.u.add_arp_cache_entry.info, 6279 pcmdinfo->in.u.add_arp_cache_entry.scratch, 6280 pcmdinfo->post_sq); 6281 break; 6282 case IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY: 6283 status = irdma_sc_alloc_local_mac_entry(pcmdinfo->in.u.alloc_local_mac_entry.cqp, 6284 pcmdinfo->in.u.alloc_local_mac_entry.scratch, 6285 pcmdinfo->post_sq); 6286 break; 6287 case IRDMA_OP_ADD_LOCAL_MAC_ENTRY: 6288 status = irdma_sc_add_local_mac_entry(pcmdinfo->in.u.add_local_mac_entry.cqp, 6289 &pcmdinfo->in.u.add_local_mac_entry.info, 6290 pcmdinfo->in.u.add_local_mac_entry.scratch, 6291 pcmdinfo->post_sq); 6292 break; 6293 case IRDMA_OP_DELETE_LOCAL_MAC_ENTRY: 6294 status = irdma_sc_del_local_mac_entry(pcmdinfo->in.u.del_local_mac_entry.cqp, 6295 pcmdinfo->in.u.del_local_mac_entry.scratch, 6296 pcmdinfo->in.u.del_local_mac_entry.entry_idx, 6297 pcmdinfo->in.u.del_local_mac_entry.ignore_ref_count, 6298 pcmdinfo->post_sq); 6299 break; 6300 case IRDMA_OP_AH_CREATE: 6301 status = irdma_sc_create_ah(pcmdinfo->in.u.ah_create.cqp, 6302 &pcmdinfo->in.u.ah_create.info, 6303 pcmdinfo->in.u.ah_create.scratch); 6304 break; 6305 case IRDMA_OP_AH_DESTROY: 6306 status = irdma_sc_destroy_ah(pcmdinfo->in.u.ah_destroy.cqp, 6307 &pcmdinfo->in.u.ah_destroy.info, 6308 pcmdinfo->in.u.ah_destroy.scratch); 6309 break; 6310 case IRDMA_OP_MC_CREATE: 6311 status = irdma_sc_create_mcast_grp(pcmdinfo->in.u.mc_create.cqp, 6312 &pcmdinfo->in.u.mc_create.info, 6313 pcmdinfo->in.u.mc_create.scratch); 6314 break; 6315 case IRDMA_OP_MC_DESTROY: 6316 status = irdma_sc_destroy_mcast_grp(pcmdinfo->in.u.mc_destroy.cqp, 6317 &pcmdinfo->in.u.mc_destroy.info, 6318 pcmdinfo->in.u.mc_destroy.scratch); 6319 break; 6320 case IRDMA_OP_MC_MODIFY: 6321 status = irdma_sc_modify_mcast_grp(pcmdinfo->in.u.mc_modify.cqp, 6322 &pcmdinfo->in.u.mc_modify.info, 6323 pcmdinfo->in.u.mc_modify.scratch); 6324 break; 6325 case IRDMA_OP_SRQ_CREATE: 6326 status = irdma_sc_srq_create(pcmdinfo->in.u.srq_create.srq, 6327 pcmdinfo->in.u.srq_create.scratch, 6328 pcmdinfo->post_sq); 6329 break; 6330 case IRDMA_OP_SRQ_MODIFY: 6331 status = irdma_sc_srq_modify(pcmdinfo->in.u.srq_modify.srq, 6332 &pcmdinfo->in.u.srq_modify.info, 6333 pcmdinfo->in.u.srq_modify.scratch, 6334 pcmdinfo->post_sq); 6335 break; 6336 case IRDMA_OP_SRQ_DESTROY: 6337 status = irdma_sc_srq_destroy(pcmdinfo->in.u.srq_destroy.srq, 6338 pcmdinfo->in.u.srq_destroy.scratch, 6339 pcmdinfo->post_sq); 6340 break; 6341 default: 6342 status = -EOPNOTSUPP; 6343 break; 6344 } 6345 6346 return status; 6347 } 6348 6349 /** 6350 * irdma_process_cqp_cmd - process all cqp commands 6351 * @dev: sc device struct 6352 * @pcmdinfo: cqp command info 6353 */ 6354 int irdma_process_cqp_cmd(struct irdma_sc_dev *dev, 6355 struct cqp_cmds_info *pcmdinfo) 6356 { 6357 int status = 0; 6358 unsigned long flags; 6359 6360 spin_lock_irqsave(&dev->cqp_lock, flags); 6361 if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp)) 6362 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 6363 else 6364 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head); 6365 spin_unlock_irqrestore(&dev->cqp_lock, flags); 6366 return status; 6367 } 6368 6369 /** 6370 * irdma_process_bh - called from tasklet for cqp list 6371 * @dev: sc device struct 6372 */ 6373 int irdma_process_bh(struct irdma_sc_dev *dev) 6374 { 6375 int status = 0; 6376 struct cqp_cmds_info *pcmdinfo; 6377 unsigned long flags; 6378 6379 spin_lock_irqsave(&dev->cqp_lock, flags); 6380 while (!list_empty(&dev->cqp_cmd_head) && 6381 !irdma_cqp_ring_full(dev->cqp)) { 6382 pcmdinfo = (struct cqp_cmds_info *)irdma_remove_cqp_head(dev); 6383 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 6384 if (status) 6385 break; 6386 } 6387 spin_unlock_irqrestore(&dev->cqp_lock, flags); 6388 return status; 6389 } 6390 6391 /** 6392 * irdma_cfg_aeq- Configure AEQ interrupt 6393 * @dev: pointer to the device structure 6394 * @idx: vector index 6395 * @enable: True to enable, False disables 6396 */ 6397 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable) 6398 { 6399 u32 reg_val; 6400 6401 reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) | 6402 FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) | 6403 FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, 3); 6404 writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 6405 } 6406 6407 /** 6408 * sc_vsi_update_stats - Update statistics 6409 * @vsi: sc_vsi instance to update 6410 */ 6411 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi) 6412 { 6413 struct irdma_dev_hw_stats *hw_stats = &vsi->pestat->hw_stats; 6414 struct irdma_gather_stats *gather_stats = 6415 vsi->pestat->gather_info.gather_stats_va; 6416 struct irdma_gather_stats *last_gather_stats = 6417 vsi->pestat->gather_info.last_gather_stats_va; 6418 const struct irdma_hw_stat_map *map = vsi->dev->hw_stats_map; 6419 u16 max_stat_idx = vsi->dev->hw_attrs.max_stat_idx; 6420 u16 i; 6421 6422 if (vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 6423 for (i = 0; i < max_stat_idx; i++) { 6424 u16 idx = map[i].byteoff / sizeof(u64); 6425 6426 hw_stats->stats_val[i] = gather_stats->val[idx]; 6427 } 6428 return; 6429 } 6430 6431 irdma_update_stats(hw_stats, gather_stats, last_gather_stats, 6432 map, max_stat_idx); 6433 } 6434 6435 /** 6436 * irdma_wait_pe_ready - Check if firmware is ready 6437 * @dev: provides access to registers 6438 */ 6439 static int irdma_wait_pe_ready(struct irdma_sc_dev *dev) 6440 { 6441 u32 statuscpu0; 6442 u32 statuscpu1; 6443 u32 statuscpu2; 6444 u32 retrycount = 0; 6445 6446 do { 6447 statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]); 6448 statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]); 6449 statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]); 6450 if (statuscpu0 == 0x80 && statuscpu1 == 0x80 && 6451 statuscpu2 == 0x80) 6452 return 0; 6453 mdelay(1000); 6454 } while (retrycount++ < dev->hw_attrs.max_pe_ready_count); 6455 return -1; 6456 } 6457 6458 static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev) 6459 { 6460 switch (dev->hw_attrs.uk_attrs.hw_rev) { 6461 case IRDMA_GEN_1: 6462 i40iw_init_hw(dev); 6463 break; 6464 case IRDMA_GEN_2: 6465 icrdma_init_hw(dev); 6466 break; 6467 case IRDMA_GEN_3: 6468 case IRDMA_GEN_4: 6469 ig3rdma_init_hw(dev); 6470 break; 6471 } 6472 } 6473 6474 /** 6475 * irdma_sc_dev_init - Initialize control part of device 6476 * @ver: version 6477 * @dev: Device pointer 6478 * @info: Device init info 6479 */ 6480 int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev, 6481 struct irdma_device_init_info *info) 6482 { 6483 u32 val; 6484 int ret_code = 0; 6485 u8 db_size; 6486 6487 spin_lock_init(&dev->puda_cq_lock); 6488 dev->ilq_cq = NULL; 6489 dev->ieq_cq = NULL; 6490 INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */ 6491 mutex_init(&dev->ws_mutex); 6492 dev->hmc_fn_id = info->hmc_fn_id; 6493 dev->fpm_query_buf_pa = info->fpm_query_buf_pa; 6494 dev->fpm_query_buf = info->fpm_query_buf; 6495 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa; 6496 dev->fpm_commit_buf = info->fpm_commit_buf; 6497 dev->hw = info->hw; 6498 dev->hw->hw_addr = info->bar0; 6499 dev->protocol_used = info->protocol_used; 6500 /* Setup the hardware limits, hmc may limit further */ 6501 dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID; 6502 dev->hw_attrs.min_hw_srq_id = IRDMA_MIN_IW_SRQ_ID; 6503 dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES; 6504 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 6505 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES_GEN_3; 6506 else 6507 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES; 6508 dev->hw_attrs.min_hw_ceq_size = IRDMA_MIN_CEQ_ENTRIES; 6509 dev->hw_attrs.max_hw_ceq_size = IRDMA_MAX_CEQ_ENTRIES; 6510 dev->hw_attrs.uk_attrs.min_hw_cq_size = IRDMA_MIN_CQ_SIZE; 6511 dev->hw_attrs.uk_attrs.max_hw_cq_size = IRDMA_MAX_CQ_SIZE; 6512 dev->hw_attrs.uk_attrs.max_hw_wq_frags = IRDMA_MAX_WQ_FRAGMENT_COUNT; 6513 dev->hw_attrs.uk_attrs.max_hw_read_sges = IRDMA_MAX_SGE_RD; 6514 dev->hw_attrs.max_hw_outbound_msg_size = IRDMA_MAX_OUTBOUND_MSG_SIZE; 6515 dev->hw_attrs.max_mr_size = IRDMA_MAX_MR_SIZE; 6516 dev->hw_attrs.max_hw_inbound_msg_size = IRDMA_MAX_INBOUND_MSG_SIZE; 6517 dev->hw_attrs.max_hw_device_pages = IRDMA_MAX_PUSH_PAGE_COUNT; 6518 dev->hw_attrs.uk_attrs.max_hw_inline = IRDMA_MAX_INLINE_DATA_SIZE; 6519 dev->hw_attrs.max_hw_wqes = IRDMA_MAX_WQ_ENTRIES; 6520 dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(IRDMA_MAX_QUANTA_PER_WR); 6521 6522 dev->hw_attrs.uk_attrs.max_hw_rq_quanta = IRDMA_QP_SW_MAX_RQ_QUANTA; 6523 dev->hw_attrs.uk_attrs.max_hw_wq_quanta = IRDMA_QP_SW_MAX_WQ_QUANTA; 6524 dev->hw_attrs.max_hw_pds = IRDMA_MAX_PDS; 6525 dev->hw_attrs.max_hw_ena_vf_count = IRDMA_MAX_PE_ENA_VF_COUNT; 6526 6527 dev->hw_attrs.max_pe_ready_count = 14; 6528 dev->hw_attrs.max_done_count = IRDMA_DONE_COUNT; 6529 dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT; 6530 dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS; 6531 6532 if (!dev->privileged) { 6533 ret_code = irdma_vchnl_req_get_hmc_fcn(dev); 6534 if (ret_code) { 6535 ibdev_dbg(to_ibdev(dev), 6536 "DEV: Get HMC function ret = %d\n", 6537 ret_code); 6538 6539 return ret_code; 6540 } 6541 } 6542 6543 irdma_sc_init_hw(dev); 6544 6545 if (dev->privileged) { 6546 if (irdma_wait_pe_ready(dev)) 6547 return -ETIMEDOUT; 6548 6549 val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]); 6550 db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val); 6551 if (db_size != IRDMA_PE_DB_SIZE_4M && 6552 db_size != IRDMA_PE_DB_SIZE_8M) { 6553 ibdev_dbg(to_ibdev(dev), 6554 "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n", 6555 val, db_size); 6556 return -ENODEV; 6557 } 6558 } else { 6559 ret_code = irdma_vchnl_req_get_reg_layout(dev); 6560 if (ret_code) 6561 ibdev_dbg(to_ibdev(dev), 6562 "DEV: Get Register layout failed ret = %d\n", 6563 ret_code); 6564 } 6565 6566 return ret_code; 6567 } 6568 6569 /** 6570 * irdma_stat_val - Extract HW counter value from statistics buffer 6571 * @stats_val: pointer to statistics buffer 6572 * @byteoff: byte offset of counter value in the buffer (8B-aligned) 6573 * @bitoff: bit offset of counter value within 8B entry 6574 * @bitmask: maximum counter value (e.g. 0xffffff for 24-bit counter) 6575 */ 6576 static inline u64 irdma_stat_val(const u64 *stats_val, u16 byteoff, u8 bitoff, 6577 u64 bitmask) 6578 { 6579 u16 idx = byteoff / sizeof(*stats_val); 6580 6581 return (stats_val[idx] >> bitoff) & bitmask; 6582 } 6583 6584 /** 6585 * irdma_stat_delta - Calculate counter delta 6586 * @new_val: updated counter value 6587 * @old_val: last counter value 6588 * @max_val: maximum counter value (e.g. 0xffffff for 24-bit counter) 6589 */ 6590 static inline u64 irdma_stat_delta(u64 new_val, u64 old_val, u64 max_val) 6591 { 6592 if (new_val >= old_val) 6593 return new_val - old_val; 6594 6595 /* roll-over case */ 6596 return max_val - old_val + new_val + 1; 6597 } 6598 6599 /** 6600 * irdma_update_stats - Update statistics 6601 * @hw_stats: hw_stats instance to update 6602 * @gather_stats: updated stat counters 6603 * @last_gather_stats: last stat counters 6604 * @map: HW stat map (hw_stats => gather_stats) 6605 * @max_stat_idx: number of HW stats 6606 */ 6607 void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats, 6608 struct irdma_gather_stats *gather_stats, 6609 struct irdma_gather_stats *last_gather_stats, 6610 const struct irdma_hw_stat_map *map, u16 max_stat_idx) 6611 { 6612 u64 *stats_val = hw_stats->stats_val; 6613 u16 i; 6614 6615 for (i = 0; i < max_stat_idx; i++) { 6616 u64 new_val = irdma_stat_val(gather_stats->val, map[i].byteoff, 6617 map[i].bitoff, map[i].bitmask); 6618 u64 last_val = irdma_stat_val(last_gather_stats->val, 6619 map[i].byteoff, map[i].bitoff, 6620 map[i].bitmask); 6621 6622 stats_val[i] += 6623 irdma_stat_delta(new_val, last_val, map[i].bitmask); 6624 } 6625 6626 memcpy(last_gather_stats, gather_stats, sizeof(*last_gather_stats)); 6627 } 6628