1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include <linux/etherdevice.h> 4 5 #include "osdep.h" 6 #include "hmc.h" 7 #include "defs.h" 8 #include "type.h" 9 #include "ws.h" 10 #include "protos.h" 11 12 /** 13 * irdma_get_qp_from_list - get next qp from a list 14 * @head: Listhead of qp's 15 * @qp: current qp 16 */ 17 struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head, 18 struct irdma_sc_qp *qp) 19 { 20 struct list_head *lastentry; 21 struct list_head *entry = NULL; 22 23 if (list_empty(head)) 24 return NULL; 25 26 if (!qp) { 27 entry = head->next; 28 } else { 29 lastentry = &qp->list; 30 entry = lastentry->next; 31 if (entry == head) 32 return NULL; 33 } 34 35 return container_of(entry, struct irdma_sc_qp, list); 36 } 37 38 /** 39 * irdma_sc_suspend_resume_qps - suspend/resume all qp's on VSI 40 * @vsi: the VSI struct pointer 41 * @op: Set to IRDMA_OP_RESUME or IRDMA_OP_SUSPEND 42 */ 43 void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 op) 44 { 45 struct irdma_sc_qp *qp = NULL; 46 u8 i; 47 48 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 49 mutex_lock(&vsi->qos[i].qos_mutex); 50 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 51 while (qp) { 52 if (op == IRDMA_OP_RESUME) { 53 if (!qp->dev->ws_add(vsi, i)) { 54 qp->qs_handle = 55 vsi->qos[qp->user_pri].qs_handle; 56 irdma_cqp_qp_suspend_resume(qp, op); 57 } else { 58 irdma_cqp_qp_suspend_resume(qp, op); 59 irdma_modify_qp_to_err(qp); 60 } 61 } else if (op == IRDMA_OP_SUSPEND) { 62 /* issue cqp suspend command */ 63 if (!irdma_cqp_qp_suspend_resume(qp, op)) 64 atomic_inc(&vsi->qp_suspend_reqs); 65 } 66 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 67 } 68 mutex_unlock(&vsi->qos[i].qos_mutex); 69 } 70 } 71 72 static void irdma_set_qos_info(struct irdma_sc_vsi *vsi, 73 struct irdma_l2params *l2p) 74 { 75 u8 i; 76 77 if (vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 78 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 79 vsi->qos[i].qs_handle = vsi->dev->qos[i].qs_handle; 80 vsi->qos[i].valid = true; 81 } 82 83 return; 84 } 85 vsi->qos_rel_bw = l2p->vsi_rel_bw; 86 vsi->qos_prio_type = l2p->vsi_prio_type; 87 vsi->dscp_mode = l2p->dscp_mode; 88 if (l2p->dscp_mode) { 89 memcpy(vsi->dscp_map, l2p->dscp_map, sizeof(vsi->dscp_map)); 90 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) 91 l2p->up2tc[i] = i; 92 } 93 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 94 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 95 vsi->qos[i].qs_handle = l2p->qs_handle_list[i]; 96 vsi->qos[i].traffic_class = l2p->up2tc[i]; 97 vsi->qos[i].rel_bw = 98 l2p->tc_info[vsi->qos[i].traffic_class].rel_bw; 99 vsi->qos[i].prio_type = 100 l2p->tc_info[vsi->qos[i].traffic_class].prio_type; 101 vsi->qos[i].valid = false; 102 } 103 } 104 105 /** 106 * irdma_change_l2params - given the new l2 parameters, change all qp 107 * @vsi: RDMA VSI pointer 108 * @l2params: New parameters from l2 109 */ 110 void irdma_change_l2params(struct irdma_sc_vsi *vsi, 111 struct irdma_l2params *l2params) 112 { 113 if (l2params->mtu_changed) { 114 vsi->mtu = l2params->mtu; 115 if (vsi->ieq) 116 irdma_reinitialize_ieq(vsi); 117 } 118 119 if (!l2params->tc_changed) 120 return; 121 122 vsi->tc_change_pending = false; 123 irdma_set_qos_info(vsi, l2params); 124 irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME); 125 } 126 127 /** 128 * irdma_qp_rem_qos - remove qp from qos lists during destroy qp 129 * @qp: qp to be removed from qos 130 */ 131 void irdma_qp_rem_qos(struct irdma_sc_qp *qp) 132 { 133 struct irdma_sc_vsi *vsi = qp->vsi; 134 135 ibdev_dbg(to_ibdev(qp->dev), 136 "DCB: DCB: Remove qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 137 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 138 qp->on_qoslist); 139 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 140 if (qp->on_qoslist) { 141 qp->on_qoslist = false; 142 list_del(&qp->list); 143 } 144 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 145 } 146 147 /** 148 * irdma_qp_add_qos - called during setctx for qp to be added to qos 149 * @qp: qp to be added to qos 150 */ 151 void irdma_qp_add_qos(struct irdma_sc_qp *qp) 152 { 153 struct irdma_sc_vsi *vsi = qp->vsi; 154 155 ibdev_dbg(to_ibdev(qp->dev), 156 "DCB: DCB: Add qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 157 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 158 qp->on_qoslist); 159 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 160 if (!qp->on_qoslist) { 161 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist); 162 qp->on_qoslist = true; 163 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle; 164 } 165 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 166 } 167 168 /** 169 * irdma_sc_pd_init - initialize sc pd struct 170 * @dev: sc device struct 171 * @pd: sc pd ptr 172 * @pd_id: pd_id for allocated pd 173 * @abi_ver: User/Kernel ABI version 174 */ 175 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, 176 int abi_ver) 177 { 178 pd->pd_id = pd_id; 179 pd->abi_ver = abi_ver; 180 pd->dev = dev; 181 } 182 183 /** 184 * irdma_sc_add_arp_cache_entry - cqp wqe add arp cache entry 185 * @cqp: struct for cqp hw 186 * @info: arp entry information 187 * @scratch: u64 saved to be used during cqp completion 188 * @post_sq: flag for cqp db to ring 189 */ 190 static int irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp, 191 struct irdma_add_arp_cache_entry_info *info, 192 u64 scratch, bool post_sq) 193 { 194 __le64 *wqe; 195 u64 hdr; 196 197 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 198 if (!wqe) 199 return -ENOMEM; 200 set_64bit_val(wqe, 8, info->reach_max); 201 set_64bit_val(wqe, 16, ether_addr_to_u64(info->mac_addr)); 202 203 hdr = info->arp_index | 204 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 205 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) | 206 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) | 207 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 208 dma_wmb(); /* make sure WQE is written before valid bit is set */ 209 210 set_64bit_val(wqe, 24, hdr); 211 212 print_hex_dump_debug("WQE: ARP_CACHE_ENTRY WQE", DUMP_PREFIX_OFFSET, 213 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 214 if (post_sq) 215 irdma_sc_cqp_post_sq(cqp); 216 217 return 0; 218 } 219 220 /** 221 * irdma_sc_del_arp_cache_entry - dele arp cache entry 222 * @cqp: struct for cqp hw 223 * @scratch: u64 saved to be used during cqp completion 224 * @arp_index: arp index to delete arp entry 225 * @post_sq: flag for cqp db to ring 226 */ 227 static int irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch, 228 u16 arp_index, bool post_sq) 229 { 230 __le64 *wqe; 231 u64 hdr; 232 233 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 234 if (!wqe) 235 return -ENOMEM; 236 237 hdr = arp_index | 238 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 239 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 240 dma_wmb(); /* make sure WQE is written before valid bit is set */ 241 242 set_64bit_val(wqe, 24, hdr); 243 244 print_hex_dump_debug("WQE: ARP_CACHE_DEL_ENTRY WQE", 245 DUMP_PREFIX_OFFSET, 16, 8, wqe, 246 IRDMA_CQP_WQE_SIZE * 8, false); 247 if (post_sq) 248 irdma_sc_cqp_post_sq(cqp); 249 250 return 0; 251 } 252 253 /** 254 * irdma_sc_manage_apbvt_entry - for adding and deleting apbvt entries 255 * @cqp: struct for cqp hw 256 * @info: info for apbvt entry to add or delete 257 * @scratch: u64 saved to be used during cqp completion 258 * @post_sq: flag for cqp db to ring 259 */ 260 static int irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp, 261 struct irdma_apbvt_info *info, 262 u64 scratch, bool post_sq) 263 { 264 __le64 *wqe; 265 u64 hdr; 266 267 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 268 if (!wqe) 269 return -ENOMEM; 270 271 set_64bit_val(wqe, 16, info->port); 272 273 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | 274 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | 275 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 276 dma_wmb(); /* make sure WQE is written before valid bit is set */ 277 278 set_64bit_val(wqe, 24, hdr); 279 280 print_hex_dump_debug("WQE: MANAGE_APBVT WQE", DUMP_PREFIX_OFFSET, 16, 281 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 282 if (post_sq) 283 irdma_sc_cqp_post_sq(cqp); 284 285 return 0; 286 } 287 288 /** 289 * irdma_sc_manage_qhash_table_entry - manage quad hash entries 290 * @cqp: struct for cqp hw 291 * @info: info for quad hash to manage 292 * @scratch: u64 saved to be used during cqp completion 293 * @post_sq: flag for cqp db to ring 294 * 295 * This is called before connection establishment is started. 296 * For passive connections, when listener is created, it will 297 * call with entry type of IRDMA_QHASH_TYPE_TCP_SYN with local 298 * ip address and tcp port. When SYN is received (passive 299 * connections) or sent (active connections), this routine is 300 * called with entry type of IRDMA_QHASH_TYPE_TCP_ESTABLISHED 301 * and quad is passed in info. 302 * 303 * When iwarp connection is done and its state moves to RTS, the 304 * quad hash entry in the hardware will point to iwarp's qp 305 * number and requires no calls from the driver. 306 */ 307 static int 308 irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp, 309 struct irdma_qhash_table_info *info, 310 u64 scratch, bool post_sq) 311 { 312 __le64 *wqe; 313 u64 qw1 = 0; 314 u64 qw2 = 0; 315 u64 temp; 316 struct irdma_sc_vsi *vsi = info->vsi; 317 318 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 319 if (!wqe) 320 return -ENOMEM; 321 322 set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr)); 323 324 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | 325 FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port); 326 if (info->ipv4_valid) { 327 set_64bit_val(wqe, 48, 328 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0])); 329 } else { 330 set_64bit_val(wqe, 56, 331 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) | 332 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1])); 333 334 set_64bit_val(wqe, 48, 335 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) | 336 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3])); 337 } 338 qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE, 339 vsi->qos[info->user_pri].qs_handle); 340 if (info->vlan_valid) 341 qw2 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id); 342 set_64bit_val(wqe, 16, qw2); 343 if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) { 344 qw1 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port); 345 if (!info->ipv4_valid) { 346 set_64bit_val(wqe, 40, 347 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) | 348 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1])); 349 set_64bit_val(wqe, 32, 350 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) | 351 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3])); 352 } else { 353 set_64bit_val(wqe, 32, 354 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0])); 355 } 356 } 357 358 set_64bit_val(wqe, 8, qw1); 359 temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) | 360 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE, 361 IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) | 362 FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) | 363 FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) | 364 FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) | 365 FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type); 366 dma_wmb(); /* make sure WQE is written before valid bit is set */ 367 368 set_64bit_val(wqe, 24, temp); 369 370 print_hex_dump_debug("WQE: MANAGE_QHASH WQE", DUMP_PREFIX_OFFSET, 16, 371 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 372 if (post_sq) 373 irdma_sc_cqp_post_sq(cqp); 374 375 return 0; 376 } 377 378 /** 379 * irdma_sc_qp_init - initialize qp 380 * @qp: sc qp 381 * @info: initialization qp info 382 */ 383 int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info) 384 { 385 int ret_code; 386 u32 pble_obj_cnt; 387 u16 wqe_size; 388 389 if (info->qp_uk_init_info.max_sq_frag_cnt > 390 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags || 391 info->qp_uk_init_info.max_rq_frag_cnt > 392 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags) 393 return -EINVAL; 394 395 qp->dev = info->pd->dev; 396 qp->vsi = info->vsi; 397 qp->ieq_qp = info->vsi->exception_lan_q; 398 qp->sq_pa = info->sq_pa; 399 qp->rq_pa = info->rq_pa; 400 qp->hw_host_ctx_pa = info->host_ctx_pa; 401 qp->q2_pa = info->q2_pa; 402 qp->shadow_area_pa = info->shadow_area_pa; 403 qp->q2_buf = info->q2; 404 qp->pd = info->pd; 405 qp->hw_host_ctx = info->host_ctx; 406 info->qp_uk_init_info.wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 407 ret_code = irdma_uk_qp_init(&qp->qp_uk, &info->qp_uk_init_info); 408 if (ret_code) 409 return ret_code; 410 411 qp->virtual_map = info->virtual_map; 412 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 413 414 if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) || 415 (!info->qp_uk_init_info.srq_uk && 416 info->virtual_map && info->rq_pa >= pble_obj_cnt)) 417 return -EINVAL; 418 419 qp->llp_stream_handle = (void *)(-1); 420 qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size, 421 IRDMA_QUEUE_TYPE_SQ_RQ); 422 ibdev_dbg(to_ibdev(qp->dev), 423 "WQE: hw_sq_size[%04d] sq_ring.size[%04d]\n", 424 qp->hw_sq_size, qp->qp_uk.sq_ring.size); 425 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1 && qp->pd->abi_ver > 4) 426 wqe_size = IRDMA_WQE_SIZE_128; 427 else 428 ret_code = irdma_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt, 429 &wqe_size); 430 if (ret_code) 431 return ret_code; 432 433 qp->hw_rq_size = irdma_get_encoded_wqe_size(qp->qp_uk.rq_size * 434 (wqe_size / IRDMA_QP_WQE_MIN_SIZE), IRDMA_QUEUE_TYPE_SQ_RQ); 435 ibdev_dbg(to_ibdev(qp->dev), 436 "WQE: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n", 437 qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size); 438 qp->sq_tph_val = info->sq_tph_val; 439 qp->rq_tph_val = info->rq_tph_val; 440 qp->sq_tph_en = info->sq_tph_en; 441 qp->rq_tph_en = info->rq_tph_en; 442 qp->rcv_tph_en = info->rcv_tph_en; 443 qp->xmit_tph_en = info->xmit_tph_en; 444 qp->qp_uk.first_sq_wq = info->qp_uk_init_info.first_sq_wq; 445 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle; 446 447 return 0; 448 } 449 450 /** 451 * irdma_sc_srq_init - init sc_srq structure 452 * @srq: srq sc struct 453 * @info: parameters for srq init 454 */ 455 int irdma_sc_srq_init(struct irdma_sc_srq *srq, 456 struct irdma_srq_init_info *info) 457 { 458 u32 srq_size_quanta; 459 int ret_code; 460 461 ret_code = irdma_uk_srq_init(&srq->srq_uk, &info->srq_uk_init_info); 462 if (ret_code) 463 return ret_code; 464 465 srq->dev = info->pd->dev; 466 srq->pd = info->pd; 467 srq->vsi = info->vsi; 468 srq->srq_pa = info->srq_pa; 469 srq->first_pm_pbl_idx = info->first_pm_pbl_idx; 470 srq->pasid = info->pasid; 471 srq->pasid_valid = info->pasid_valid; 472 srq->srq_limit = info->srq_limit; 473 srq->leaf_pbl_size = info->leaf_pbl_size; 474 srq->virtual_map = info->virtual_map; 475 srq->tph_en = info->tph_en; 476 srq->arm_limit_event = info->arm_limit_event; 477 srq->tph_val = info->tph_value; 478 srq->shadow_area_pa = info->shadow_area_pa; 479 480 /* Smallest SRQ size is 256B i.e. 8 quanta */ 481 srq_size_quanta = max((u32)IRDMA_SRQ_MIN_QUANTA, 482 srq->srq_uk.srq_size * 483 srq->srq_uk.wqe_size_multiplier); 484 srq->hw_srq_size = irdma_get_encoded_wqe_size(srq_size_quanta, 485 IRDMA_QUEUE_TYPE_SRQ); 486 487 return 0; 488 } 489 490 /** 491 * irdma_sc_srq_create - send srq create CQP WQE 492 * @srq: srq sc struct 493 * @scratch: u64 saved to be used during cqp completion 494 * @post_sq: flag for cqp db to ring 495 */ 496 static int irdma_sc_srq_create(struct irdma_sc_srq *srq, u64 scratch, 497 bool post_sq) 498 { 499 struct irdma_sc_cqp *cqp; 500 __le64 *wqe; 501 u64 hdr; 502 503 cqp = srq->pd->dev->cqp; 504 if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id || 505 srq->srq_uk.srq_id > 506 (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1)) 507 return -EINVAL; 508 509 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 510 if (!wqe) 511 return -ENOMEM; 512 513 set_64bit_val(wqe, 0, 514 FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, srq->srq_limit) | 515 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) | 516 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size)); 517 set_64bit_val(wqe, 8, (uintptr_t)srq); 518 set_64bit_val(wqe, 16, 519 FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id)); 520 set_64bit_val(wqe, 32, 521 FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR, 522 srq->srq_pa >> 523 IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S)); 524 set_64bit_val(wqe, 40, 525 FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR, 526 srq->shadow_area_pa >> 527 IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S)); 528 set_64bit_val(wqe, 48, 529 FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX, 530 srq->first_pm_pbl_idx)); 531 532 hdr = srq->srq_uk.srq_id | 533 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_SRQ) | 534 FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) | 535 FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) | 536 FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT, 537 srq->arm_limit_event) | 538 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 539 540 dma_wmb(); /* make sure WQE is written before valid bit is set */ 541 542 set_64bit_val(wqe, 24, hdr); 543 544 print_hex_dump_debug("WQE: SRQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 545 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 546 if (post_sq) 547 irdma_sc_cqp_post_sq(cqp); 548 549 return 0; 550 } 551 552 /** 553 * irdma_sc_srq_modify - send modify_srq CQP WQE 554 * @srq: srq sc struct 555 * @info: parameters for srq modification 556 * @scratch: u64 saved to be used during cqp completion 557 * @post_sq: flag for cqp db to ring 558 */ 559 static int irdma_sc_srq_modify(struct irdma_sc_srq *srq, 560 struct irdma_modify_srq_info *info, u64 scratch, 561 bool post_sq) 562 { 563 struct irdma_sc_cqp *cqp; 564 __le64 *wqe; 565 u64 hdr; 566 567 cqp = srq->dev->cqp; 568 if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id || 569 srq->srq_uk.srq_id > 570 (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1)) 571 return -EINVAL; 572 573 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 574 if (!wqe) 575 return -ENOMEM; 576 577 set_64bit_val(wqe, 0, 578 FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, info->srq_limit) | 579 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) | 580 FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size)); 581 set_64bit_val(wqe, 8, 582 FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQCTX, srq->srq_uk.srq_id)); 583 set_64bit_val(wqe, 16, 584 FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id)); 585 set_64bit_val(wqe, 32, 586 FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR, 587 srq->srq_pa >> 588 IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S)); 589 set_64bit_val(wqe, 40, 590 FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR, 591 srq->shadow_area_pa >> 592 IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S)); 593 set_64bit_val(wqe, 48, 594 FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX, 595 srq->first_pm_pbl_idx)); 596 597 hdr = srq->srq_uk.srq_id | 598 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_SRQ) | 599 FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) | 600 FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) | 601 FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT, 602 info->arm_limit_event) | 603 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 604 dma_wmb(); /* make sure WQE is written before valid bit is set */ 605 606 set_64bit_val(wqe, 24, hdr); 607 608 print_hex_dump_debug("WQE: SRQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 609 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 610 if (post_sq) 611 irdma_sc_cqp_post_sq(cqp); 612 613 return 0; 614 } 615 616 /** 617 * irdma_sc_srq_destroy - send srq_destroy CQP WQE 618 * @srq: srq sc struct 619 * @scratch: u64 saved to be used during cqp completion 620 * @post_sq: flag for cqp db to ring 621 */ 622 static int irdma_sc_srq_destroy(struct irdma_sc_srq *srq, u64 scratch, 623 bool post_sq) 624 { 625 struct irdma_sc_cqp *cqp; 626 __le64 *wqe; 627 u64 hdr; 628 629 cqp = srq->dev->cqp; 630 631 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 632 if (!wqe) 633 return -ENOMEM; 634 635 set_64bit_val(wqe, 8, (uintptr_t)srq); 636 637 hdr = srq->srq_uk.srq_id | 638 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_SRQ) | 639 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 640 dma_wmb(); /* make sure WQE is written before valid bit is set */ 641 642 set_64bit_val(wqe, 24, hdr); 643 644 print_hex_dump_debug("WQE: SRQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 645 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 646 if (post_sq) 647 irdma_sc_cqp_post_sq(cqp); 648 649 return 0; 650 } 651 652 /** 653 * irdma_sc_qp_create - create qp 654 * @qp: sc qp 655 * @info: qp create info 656 * @scratch: u64 saved to be used during cqp completion 657 * @post_sq: flag for cqp db to ring 658 */ 659 int irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info, 660 u64 scratch, bool post_sq) 661 { 662 struct irdma_sc_cqp *cqp; 663 __le64 *wqe; 664 u64 hdr; 665 666 cqp = qp->dev->cqp; 667 if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id || 668 qp->qp_uk.qp_id >= cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt) 669 return -EINVAL; 670 671 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 672 if (!wqe) 673 return -ENOMEM; 674 675 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 676 set_64bit_val(wqe, 40, qp->shadow_area_pa); 677 678 hdr = qp->qp_uk.qp_id | 679 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 680 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, (info->ord_valid ? 1 : 0)) | 681 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 682 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 683 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 684 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 685 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 686 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 687 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 688 info->arp_cache_idx_valid) | 689 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 690 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 691 dma_wmb(); /* make sure WQE is written before valid bit is set */ 692 693 set_64bit_val(wqe, 24, hdr); 694 695 print_hex_dump_debug("WQE: QP_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 696 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 697 if (post_sq) 698 irdma_sc_cqp_post_sq(cqp); 699 700 return 0; 701 } 702 703 /** 704 * irdma_sc_qp_modify - modify qp cqp wqe 705 * @qp: sc qp 706 * @info: modify qp info 707 * @scratch: u64 saved to be used during cqp completion 708 * @post_sq: flag for cqp db to ring 709 */ 710 int irdma_sc_qp_modify(struct irdma_sc_qp *qp, struct irdma_modify_qp_info *info, 711 u64 scratch, bool post_sq) 712 { 713 __le64 *wqe; 714 struct irdma_sc_cqp *cqp; 715 u64 hdr; 716 u8 term_actions = 0; 717 u8 term_len = 0; 718 719 cqp = qp->dev->cqp; 720 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 721 if (!wqe) 722 return -ENOMEM; 723 724 if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) { 725 if (info->dont_send_fin) 726 term_actions += IRDMAQP_TERM_SEND_TERM_ONLY; 727 if (info->dont_send_term) 728 term_actions += IRDMAQP_TERM_SEND_FIN_ONLY; 729 if (term_actions == IRDMAQP_TERM_SEND_TERM_AND_FIN || 730 term_actions == IRDMAQP_TERM_SEND_TERM_ONLY) 731 term_len = info->termlen; 732 } 733 734 set_64bit_val(wqe, 8, 735 FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) | 736 FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len)); 737 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 738 set_64bit_val(wqe, 40, qp->shadow_area_pa); 739 740 hdr = qp->qp_uk.qp_id | 741 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) | 742 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) | 743 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 744 FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID, 745 info->cached_var_valid) | 746 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 747 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 748 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 749 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 750 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 751 FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) | 752 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, 753 info->remove_hash_idx) | 754 FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) | 755 FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) | 756 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 757 info->arp_cache_idx_valid) | 758 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 759 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 760 dma_wmb(); /* make sure WQE is written before valid bit is set */ 761 762 set_64bit_val(wqe, 24, hdr); 763 764 print_hex_dump_debug("WQE: QP_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 765 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 766 if (post_sq) 767 irdma_sc_cqp_post_sq(cqp); 768 769 return 0; 770 } 771 772 /** 773 * irdma_sc_qp_destroy - cqp destroy qp 774 * @qp: sc qp 775 * @scratch: u64 saved to be used during cqp completion 776 * @remove_hash_idx: flag if to remove hash idx 777 * @ignore_mw_bnd: memory window bind flag 778 * @post_sq: flag for cqp db to ring 779 */ 780 int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch, 781 bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq) 782 { 783 __le64 *wqe; 784 struct irdma_sc_cqp *cqp; 785 u64 hdr; 786 787 cqp = qp->dev->cqp; 788 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 789 if (!wqe) 790 return -ENOMEM; 791 792 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 793 set_64bit_val(wqe, 40, qp->shadow_area_pa); 794 795 hdr = qp->qp_uk.qp_id | 796 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) | 797 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 798 FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) | 799 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) | 800 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 801 dma_wmb(); /* make sure WQE is written before valid bit is set */ 802 803 set_64bit_val(wqe, 24, hdr); 804 805 print_hex_dump_debug("WQE: QP_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 806 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 807 if (post_sq) 808 irdma_sc_cqp_post_sq(cqp); 809 810 return 0; 811 } 812 813 /** 814 * irdma_sc_get_encoded_ird_size - 815 * @ird_size: IRD size 816 * The ird from the connection is rounded to a supported HW setting and then encoded 817 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based 818 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input 819 */ 820 static u8 irdma_sc_get_encoded_ird_size(u16 ird_size) 821 { 822 switch (ird_size ? 823 roundup_pow_of_two(2 * ird_size) : 4) { 824 case 256: 825 return IRDMA_IRD_HW_SIZE_256; 826 case 128: 827 return IRDMA_IRD_HW_SIZE_128; 828 case 64: 829 case 32: 830 return IRDMA_IRD_HW_SIZE_64; 831 case 16: 832 case 8: 833 return IRDMA_IRD_HW_SIZE_16; 834 case 4: 835 default: 836 break; 837 } 838 839 return IRDMA_IRD_HW_SIZE_4; 840 } 841 842 /** 843 * irdma_sc_qp_setctx_roce_gen_2 - set qp's context 844 * @qp: sc qp 845 * @qp_ctx: context ptr 846 * @info: ctx info 847 */ 848 static void irdma_sc_qp_setctx_roce_gen_2(struct irdma_sc_qp *qp, 849 __le64 *qp_ctx, 850 struct irdma_qp_host_ctx_info *info) 851 { 852 struct irdma_roce_offload_info *roce_info; 853 struct irdma_udp_offload_info *udp; 854 u8 push_mode_en; 855 u32 push_idx; 856 857 roce_info = info->roce_info; 858 udp = info->udp_info; 859 qp->user_pri = info->user_pri; 860 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 861 push_mode_en = 0; 862 push_idx = 0; 863 } else { 864 push_mode_en = 1; 865 push_idx = qp->push_idx; 866 } 867 set_64bit_val(qp_ctx, 0, 868 FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 869 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 870 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 871 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 872 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 873 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 874 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | 875 FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) | 876 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | 877 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) | 878 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | 879 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | 880 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | 881 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag)); 882 set_64bit_val(qp_ctx, 8, qp->sq_pa); 883 set_64bit_val(qp_ctx, 16, qp->rq_pa); 884 if ((roce_info->dcqcn_en || roce_info->dctcp_en) && 885 !(udp->tos & 0x03)) 886 udp->tos |= ECN_CODE_PT_VAL; 887 set_64bit_val(qp_ctx, 24, 888 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 889 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | 890 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) | 891 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | 892 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port)); 893 set_64bit_val(qp_ctx, 32, 894 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | 895 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); 896 set_64bit_val(qp_ctx, 40, 897 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | 898 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); 899 set_64bit_val(qp_ctx, 48, 900 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | 901 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | 902 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); 903 set_64bit_val(qp_ctx, 56, 904 FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | 905 FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) | 906 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | 907 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label)); 908 set_64bit_val(qp_ctx, 64, 909 FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | 910 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp)); 911 set_64bit_val(qp_ctx, 80, 912 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | 913 FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); 914 set_64bit_val(qp_ctx, 88, 915 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); 916 set_64bit_val(qp_ctx, 96, 917 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | 918 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); 919 set_64bit_val(qp_ctx, 112, 920 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); 921 set_64bit_val(qp_ctx, 128, 922 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) | 923 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | 924 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | 925 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); 926 set_64bit_val(qp_ctx, 136, 927 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 928 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 929 set_64bit_val(qp_ctx, 144, 930 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 931 set_64bit_val(qp_ctx, 152, ether_addr_to_u64(roce_info->mac_addr) << 16); 932 set_64bit_val(qp_ctx, 160, 933 FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) | 934 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) | 935 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | 936 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | 937 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 938 FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | 939 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | 940 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | 941 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | 942 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) | 943 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) | 944 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | 945 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); 946 set_64bit_val(qp_ctx, 168, 947 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 948 set_64bit_val(qp_ctx, 176, 949 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 950 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 951 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 952 set_64bit_val(qp_ctx, 184, 953 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | 954 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); 955 set_64bit_val(qp_ctx, 192, 956 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | 957 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); 958 set_64bit_val(qp_ctx, 200, 959 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | 960 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); 961 set_64bit_val(qp_ctx, 208, 962 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 963 964 print_hex_dump_debug("WQE: QP_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16, 965 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 966 } 967 968 /** 969 * irdma_sc_get_encoded_ird_size_gen_3 - get encoded IRD size for GEN 3 970 * @ird_size: IRD size 971 * The ird from the connection is rounded to a supported HW setting and then encoded 972 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based 973 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input. 974 */ 975 static u8 irdma_sc_get_encoded_ird_size_gen_3(u16 ird_size) 976 { 977 switch (ird_size ? 978 roundup_pow_of_two(2 * ird_size) : 4) { 979 case 4096: 980 return IRDMA_IRD_HW_SIZE_4096_GEN3; 981 case 2048: 982 return IRDMA_IRD_HW_SIZE_2048_GEN3; 983 case 1024: 984 return IRDMA_IRD_HW_SIZE_1024_GEN3; 985 case 512: 986 return IRDMA_IRD_HW_SIZE_512_GEN3; 987 case 256: 988 return IRDMA_IRD_HW_SIZE_256_GEN3; 989 case 128: 990 return IRDMA_IRD_HW_SIZE_128_GEN3; 991 case 64: 992 return IRDMA_IRD_HW_SIZE_64_GEN3; 993 case 32: 994 return IRDMA_IRD_HW_SIZE_32_GEN3; 995 case 16: 996 return IRDMA_IRD_HW_SIZE_16_GEN3; 997 case 8: 998 return IRDMA_IRD_HW_SIZE_8_GEN3; 999 case 4: 1000 default: 1001 break; 1002 } 1003 1004 return IRDMA_IRD_HW_SIZE_4_GEN3; 1005 } 1006 1007 /** 1008 * irdma_sc_qp_setctx_roce_gen_3 - set qp's context 1009 * @qp: sc qp 1010 * @qp_ctx: context ptr 1011 * @info: ctx info 1012 */ 1013 static void irdma_sc_qp_setctx_roce_gen_3(struct irdma_sc_qp *qp, 1014 __le64 *qp_ctx, 1015 struct irdma_qp_host_ctx_info *info) 1016 { 1017 struct irdma_roce_offload_info *roce_info = info->roce_info; 1018 struct irdma_udp_offload_info *udp = info->udp_info; 1019 u64 qw0, qw3, qw7 = 0, qw8 = 0; 1020 u8 push_mode_en; 1021 u32 push_idx; 1022 1023 qp->user_pri = info->user_pri; 1024 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 1025 push_mode_en = 0; 1026 push_idx = 0; 1027 } else { 1028 push_mode_en = 1; 1029 push_idx = qp->push_idx; 1030 } 1031 1032 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 1033 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 1034 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 1035 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 1036 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 1037 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 1038 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | 1039 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | 1040 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | 1041 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | 1042 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | 1043 FIELD_PREP(IRDMAQPC_USE_SRQ, !qp->qp_uk.srq_uk ? 0 : 1) | 1044 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag); 1045 set_64bit_val(qp_ctx, 0, qw0); 1046 set_64bit_val(qp_ctx, 8, qp->sq_pa); 1047 set_64bit_val(qp_ctx, 16, qp->rq_pa); 1048 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 1049 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | 1050 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | 1051 FIELD_PREP(IRDMAQPC_TOS, udp->tos) | 1052 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | 1053 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port); 1054 set_64bit_val(qp_ctx, 24, qw3); 1055 set_64bit_val(qp_ctx, 32, 1056 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | 1057 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); 1058 set_64bit_val(qp_ctx, 40, 1059 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | 1060 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); 1061 set_64bit_val(qp_ctx, 48, 1062 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | 1063 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | 1064 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); 1065 qw7 = FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | 1066 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | 1067 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label); 1068 set_64bit_val(qp_ctx, 56, qw7); 1069 qw8 = FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | 1070 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp); 1071 set_64bit_val(qp_ctx, 64, qw8); 1072 set_64bit_val(qp_ctx, 80, 1073 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | 1074 FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); 1075 set_64bit_val(qp_ctx, 88, 1076 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); 1077 set_64bit_val(qp_ctx, 96, 1078 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | 1079 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); 1080 set_64bit_val(qp_ctx, 112, 1081 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); 1082 set_64bit_val(qp_ctx, 128, 1083 FIELD_PREP(IRDMAQPC_MINRNR_TIMER, udp->min_rnr_timer) | 1084 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | 1085 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | 1086 FIELD_PREP(IRDMAQPC_RNRNAK_TMR, udp->rnr_nak_tmr) | 1087 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); 1088 set_64bit_val(qp_ctx, 136, 1089 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 1090 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 1091 set_64bit_val(qp_ctx, 152, 1092 FIELD_PREP(IRDMAQPC_MACADDRESS, 1093 ether_addr_to_u64(roce_info->mac_addr)) | 1094 FIELD_PREP(IRDMAQPC_LOCALACKTIMEOUT, 1095 roce_info->local_ack_timeout)); 1096 set_64bit_val(qp_ctx, 160, 1097 FIELD_PREP(IRDMAQPC_ORDSIZE_GEN3, roce_info->ord_size) | 1098 FIELD_PREP(IRDMAQPC_IRDSIZE_GEN3, 1099 irdma_sc_get_encoded_ird_size_gen_3(roce_info->ird_size)) | 1100 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | 1101 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | 1102 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, 1103 info->stats_idx_valid) | 1104 FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | 1105 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | 1106 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | 1107 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | 1108 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, 1109 roce_info->fw_cc_enable) | 1110 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, 1111 roce_info->udprivcq_en) | 1112 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | 1113 FIELD_PREP(IRDMAQPC_REMOTE_ATOMIC_EN, 1114 info->remote_atomics_en) | 1115 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); 1116 set_64bit_val(qp_ctx, 168, 1117 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 1118 set_64bit_val(qp_ctx, 176, 1119 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 1120 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 1121 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 1122 set_64bit_val(qp_ctx, 184, 1123 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | 1124 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); 1125 set_64bit_val(qp_ctx, 192, 1126 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | 1127 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); 1128 set_64bit_val(qp_ctx, 200, 1129 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | 1130 FIELD_PREP(IRDMAQPC_SRQ_ID, 1131 !qp->qp_uk.srq_uk ? 1132 0 : qp->qp_uk.srq_uk->srq_id) | 1133 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); 1134 set_64bit_val(qp_ctx, 208, roce_info->pd_id | 1135 FIELD_PREP(IRDMAQPC_STAT_INDEX_GEN3, info->stats_idx) | 1136 FIELD_PREP(IRDMAQPC_PKT_LIMIT, qp->pkt_limit)); 1137 1138 print_hex_dump_debug("WQE: QP_HOST ROCE CTX WQE", DUMP_PREFIX_OFFSET, 1139 16, 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 1140 } 1141 1142 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, 1143 struct irdma_qp_host_ctx_info *info) 1144 { 1145 if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) 1146 irdma_sc_qp_setctx_roce_gen_2(qp, qp_ctx, info); 1147 else 1148 irdma_sc_qp_setctx_roce_gen_3(qp, qp_ctx, info); 1149 } 1150 1151 /* irdma_sc_alloc_local_mac_entry - allocate a mac entry 1152 * @cqp: struct for cqp hw 1153 * @scratch: u64 saved to be used during cqp completion 1154 * @post_sq: flag for cqp db to ring 1155 */ 1156 static int irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 1157 bool post_sq) 1158 { 1159 __le64 *wqe; 1160 u64 hdr; 1161 1162 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1163 if (!wqe) 1164 return -ENOMEM; 1165 1166 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 1167 IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) | 1168 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1169 1170 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1171 1172 set_64bit_val(wqe, 24, hdr); 1173 1174 print_hex_dump_debug("WQE: ALLOCATE_LOCAL_MAC WQE", 1175 DUMP_PREFIX_OFFSET, 16, 8, wqe, 1176 IRDMA_CQP_WQE_SIZE * 8, false); 1177 1178 if (post_sq) 1179 irdma_sc_cqp_post_sq(cqp); 1180 return 0; 1181 } 1182 1183 /** 1184 * irdma_sc_add_local_mac_entry - add mac enry 1185 * @cqp: struct for cqp hw 1186 * @info:mac addr info 1187 * @scratch: u64 saved to be used during cqp completion 1188 * @post_sq: flag for cqp db to ring 1189 */ 1190 static int irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp, 1191 struct irdma_local_mac_entry_info *info, 1192 u64 scratch, bool post_sq) 1193 { 1194 __le64 *wqe; 1195 u64 header; 1196 1197 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1198 if (!wqe) 1199 return -ENOMEM; 1200 1201 set_64bit_val(wqe, 32, ether_addr_to_u64(info->mac_addr)); 1202 1203 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) | 1204 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 1205 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 1206 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1207 1208 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1209 1210 set_64bit_val(wqe, 24, header); 1211 1212 print_hex_dump_debug("WQE: ADD_LOCAL_MAC WQE", DUMP_PREFIX_OFFSET, 16, 1213 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1214 1215 if (post_sq) 1216 irdma_sc_cqp_post_sq(cqp); 1217 return 0; 1218 } 1219 1220 /** 1221 * irdma_sc_del_local_mac_entry - cqp wqe to dele local mac 1222 * @cqp: struct for cqp hw 1223 * @scratch: u64 saved to be used during cqp completion 1224 * @entry_idx: index of mac entry 1225 * @ignore_ref_count: to force mac adde delete 1226 * @post_sq: flag for cqp db to ring 1227 */ 1228 static int irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 1229 u16 entry_idx, u8 ignore_ref_count, 1230 bool post_sq) 1231 { 1232 __le64 *wqe; 1233 u64 header; 1234 1235 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1236 if (!wqe) 1237 return -ENOMEM; 1238 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) | 1239 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 1240 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 1241 FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) | 1242 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 1243 FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count); 1244 1245 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1246 1247 set_64bit_val(wqe, 24, header); 1248 1249 print_hex_dump_debug("WQE: DEL_LOCAL_MAC_IPADDR WQE", 1250 DUMP_PREFIX_OFFSET, 16, 8, wqe, 1251 IRDMA_CQP_WQE_SIZE * 8, false); 1252 1253 if (post_sq) 1254 irdma_sc_cqp_post_sq(cqp); 1255 return 0; 1256 } 1257 1258 /** 1259 * irdma_sc_qp_setctx - set qp's context 1260 * @qp: sc qp 1261 * @qp_ctx: context ptr 1262 * @info: ctx info 1263 */ 1264 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx, 1265 struct irdma_qp_host_ctx_info *info) 1266 { 1267 struct irdma_iwarp_offload_info *iw; 1268 struct irdma_tcp_offload_info *tcp; 1269 struct irdma_sc_dev *dev; 1270 u8 push_mode_en; 1271 u32 push_idx; 1272 u64 qw0, qw3, qw7 = 0, qw16 = 0; 1273 u64 mac = 0; 1274 1275 iw = info->iwarp_info; 1276 tcp = info->tcp_info; 1277 dev = qp->dev; 1278 if (iw->rcv_mark_en) { 1279 qp->pfpdu.marker_len = 4; 1280 qp->pfpdu.rcv_start_seq = tcp->rcv_nxt; 1281 } 1282 qp->user_pri = info->user_pri; 1283 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 1284 push_mode_en = 0; 1285 push_idx = 0; 1286 } else { 1287 push_mode_en = 1; 1288 push_idx = qp->push_idx; 1289 } 1290 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 1291 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 1292 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 1293 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 1294 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 1295 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 1296 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en); 1297 1298 set_64bit_val(qp_ctx, 8, qp->sq_pa); 1299 set_64bit_val(qp_ctx, 16, qp->rq_pa); 1300 1301 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 1302 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size); 1303 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1304 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, 1305 qp->src_mac_addr_idx); 1306 set_64bit_val(qp_ctx, 136, 1307 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 1308 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 1309 set_64bit_val(qp_ctx, 168, 1310 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 1311 set_64bit_val(qp_ctx, 176, 1312 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 1313 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 1314 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) | 1315 FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp)); 1316 if (info->iwarp_info_valid) { 1317 qw0 |= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) | 1318 FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) | 1319 FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) | 1320 FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) | 1321 FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) | 1322 FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) | 1323 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, 1324 iw->err_rq_idx_valid); 1325 qw7 |= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id); 1326 qw16 |= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) | 1327 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin); 1328 set_64bit_val(qp_ctx, 144, 1329 FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) | 1330 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 1331 1332 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 1333 mac = ether_addr_to_u64(iw->mac_addr); 1334 1335 set_64bit_val(qp_ctx, 152, 1336 mac << 16 | FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent)); 1337 set_64bit_val(qp_ctx, 160, 1338 FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) | 1339 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) | 1340 FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) | 1341 FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) | 1342 FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) | 1343 FIELD_PREP(IRDMAQPC_BINDEN, iw->bind_en) | 1344 FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) | 1345 FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) | 1346 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 1347 FIELD_PREP(IRDMAQPC_IWARPMODE, 1) | 1348 FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) | 1349 FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) | 1350 FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) | 1351 FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset || !tcp ? iw->rcv_mark_offset : tcp->rcv_nxt) | 1352 FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset || !tcp ? iw->snd_mark_offset : tcp->snd_nxt) | 1353 FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en)); 1354 } 1355 if (info->tcp_info_valid) { 1356 qw0 |= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) | 1357 FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) | 1358 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, 1359 tcp->insert_vlan_tag) | 1360 FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) | 1361 FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) | 1362 FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) | 1363 FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh); 1364 1365 if ((iw->ecn_en || iw->dctcp_en) && !(tcp->tos & 0x03)) 1366 tcp->tos |= ECN_CODE_PT_VAL; 1367 1368 qw3 |= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) | 1369 FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) | 1370 FIELD_PREP(IRDMAQPC_TOS, tcp->tos) | 1371 FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) | 1372 FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port); 1373 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 1374 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx); 1375 1376 qp->src_mac_addr_idx = tcp->src_mac_addr_idx; 1377 } 1378 set_64bit_val(qp_ctx, 32, 1379 FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) | 1380 FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3])); 1381 set_64bit_val(qp_ctx, 40, 1382 FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) | 1383 FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1])); 1384 set_64bit_val(qp_ctx, 48, 1385 FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) | 1386 FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) | 1387 FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) | 1388 FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx)); 1389 qw7 |= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) | 1390 FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) | 1391 FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT, 1392 tcp->ignore_tcp_opt) | 1393 FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT, 1394 tcp->ignore_tcp_uns_opt) | 1395 FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) | 1396 FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) | 1397 FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale); 1398 set_64bit_val(qp_ctx, 72, 1399 FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) | 1400 FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age)); 1401 set_64bit_val(qp_ctx, 80, 1402 FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) | 1403 FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd)); 1404 set_64bit_val(qp_ctx, 88, 1405 FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) | 1406 FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd)); 1407 set_64bit_val(qp_ctx, 96, 1408 FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) | 1409 FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una)); 1410 set_64bit_val(qp_ctx, 104, 1411 FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) | 1412 FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var)); 1413 set_64bit_val(qp_ctx, 112, 1414 FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) | 1415 FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd)); 1416 set_64bit_val(qp_ctx, 120, 1417 FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) | 1418 FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2)); 1419 qw16 |= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) | 1420 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh); 1421 set_64bit_val(qp_ctx, 184, 1422 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) | 1423 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2])); 1424 set_64bit_val(qp_ctx, 192, 1425 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) | 1426 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0])); 1427 set_64bit_val(qp_ctx, 200, 1428 FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) | 1429 FIELD_PREP(IRDMAQPC_TLOW, iw->t_low)); 1430 set_64bit_val(qp_ctx, 208, 1431 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 1432 } 1433 1434 set_64bit_val(qp_ctx, 0, qw0); 1435 set_64bit_val(qp_ctx, 24, qw3); 1436 set_64bit_val(qp_ctx, 56, qw7); 1437 set_64bit_val(qp_ctx, 128, qw16); 1438 1439 print_hex_dump_debug("WQE: QP_HOST CTX", DUMP_PREFIX_OFFSET, 16, 8, 1440 qp_ctx, IRDMA_QP_CTX_SIZE, false); 1441 } 1442 1443 /** 1444 * irdma_sc_alloc_stag - mr stag alloc 1445 * @dev: sc device struct 1446 * @info: stag info 1447 * @scratch: u64 saved to be used during cqp completion 1448 * @post_sq: flag for cqp db to ring 1449 */ 1450 static int irdma_sc_alloc_stag(struct irdma_sc_dev *dev, 1451 struct irdma_allocate_stag_info *info, 1452 u64 scratch, bool post_sq) 1453 { 1454 __le64 *wqe; 1455 struct irdma_sc_cqp *cqp; 1456 u64 hdr; 1457 enum irdma_page_size page_size; 1458 1459 if (!info->total_len && !info->all_memory) 1460 return -EINVAL; 1461 1462 if (info->page_size == 0x40000000) 1463 page_size = IRDMA_PAGE_SIZE_1G; 1464 else if (info->page_size == 0x200000) 1465 page_size = IRDMA_PAGE_SIZE_2M; 1466 else 1467 page_size = IRDMA_PAGE_SIZE_4K; 1468 1469 cqp = dev->cqp; 1470 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1471 if (!wqe) 1472 return -ENOMEM; 1473 1474 set_64bit_val(wqe, 8, 1475 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) | 1476 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len)); 1477 set_64bit_val(wqe, 16, 1478 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx) | 1479 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); 1480 set_64bit_val(wqe, 40, 1481 FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index)); 1482 1483 if (info->chunk_size) 1484 set_64bit_val(wqe, 48, 1485 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx)); 1486 1487 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1488 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1489 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1490 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1491 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1492 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) | 1493 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1494 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1495 FIELD_PREP(IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN, 1496 info->remote_atomics_en) | 1497 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1498 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1499 1500 set_64bit_val(wqe, 24, hdr); 1501 1502 print_hex_dump_debug("WQE: ALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1503 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1504 if (post_sq) 1505 irdma_sc_cqp_post_sq(cqp); 1506 1507 return 0; 1508 } 1509 1510 /** 1511 * irdma_sc_mr_reg_non_shared - non-shared mr registration 1512 * @dev: sc device struct 1513 * @info: mr info 1514 * @scratch: u64 saved to be used during cqp completion 1515 * @post_sq: flag for cqp db to ring 1516 */ 1517 static int irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev, 1518 struct irdma_reg_ns_stag_info *info, 1519 u64 scratch, bool post_sq) 1520 { 1521 __le64 *wqe; 1522 u64 fbo; 1523 struct irdma_sc_cqp *cqp; 1524 u64 hdr; 1525 u32 pble_obj_cnt; 1526 bool remote_access; 1527 u8 addr_type; 1528 enum irdma_page_size page_size; 1529 1530 if (!info->total_len && !info->all_memory) 1531 return -EINVAL; 1532 1533 if (info->page_size == 0x40000000) 1534 page_size = IRDMA_PAGE_SIZE_1G; 1535 else if (info->page_size == 0x200000) 1536 page_size = IRDMA_PAGE_SIZE_2M; 1537 else if (info->page_size == 0x1000) 1538 page_size = IRDMA_PAGE_SIZE_4K; 1539 else 1540 return -EINVAL; 1541 1542 if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY | 1543 IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY)) 1544 remote_access = true; 1545 else 1546 remote_access = false; 1547 1548 pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 1549 if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt) 1550 return -EINVAL; 1551 1552 cqp = dev->cqp; 1553 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1554 if (!wqe) 1555 return -ENOMEM; 1556 fbo = info->va & (info->page_size - 1); 1557 1558 set_64bit_val(wqe, 0, 1559 (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ? 1560 info->va : fbo)); 1561 set_64bit_val(wqe, 8, 1562 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) | 1563 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1564 set_64bit_val(wqe, 16, 1565 FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) | 1566 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18) | 1567 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1568 if (!info->chunk_size) { 1569 set_64bit_val(wqe, 32, info->reg_addr_pa); 1570 set_64bit_val(wqe, 48, 0); 1571 } else { 1572 set_64bit_val(wqe, 32, 0); 1573 set_64bit_val(wqe, 48, 1574 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index)); 1575 } 1576 set_64bit_val(wqe, 40, info->hmc_fcn_index); 1577 set_64bit_val(wqe, 56, 0); 1578 1579 addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0; 1580 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) | 1581 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1582 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1583 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1584 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1585 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) | 1586 FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) | 1587 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1588 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1589 FIELD_PREP(IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN, 1590 info->remote_atomics_en) | 1591 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1592 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1593 1594 set_64bit_val(wqe, 24, hdr); 1595 1596 print_hex_dump_debug("WQE: MR_REG_NS WQE", DUMP_PREFIX_OFFSET, 16, 8, 1597 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1598 if (post_sq) 1599 irdma_sc_cqp_post_sq(cqp); 1600 1601 return 0; 1602 } 1603 1604 /** 1605 * irdma_sc_dealloc_stag - deallocate stag 1606 * @dev: sc device struct 1607 * @info: dealloc stag info 1608 * @scratch: u64 saved to be used during cqp completion 1609 * @post_sq: flag for cqp db to ring 1610 */ 1611 static int irdma_sc_dealloc_stag(struct irdma_sc_dev *dev, 1612 struct irdma_dealloc_stag_info *info, 1613 u64 scratch, bool post_sq) 1614 { 1615 u64 hdr; 1616 __le64 *wqe; 1617 struct irdma_sc_cqp *cqp; 1618 1619 cqp = dev->cqp; 1620 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1621 if (!wqe) 1622 return -ENOMEM; 1623 1624 set_64bit_val(wqe, 8, 1625 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1626 set_64bit_val(wqe, 16, 1627 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx) | 1628 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); 1629 1630 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) | 1631 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) | 1632 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1633 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1634 1635 set_64bit_val(wqe, 24, hdr); 1636 1637 print_hex_dump_debug("WQE: DEALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 1638 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1639 if (post_sq) 1640 irdma_sc_cqp_post_sq(cqp); 1641 1642 return 0; 1643 } 1644 1645 /** 1646 * irdma_sc_mw_alloc - mw allocate 1647 * @dev: sc device struct 1648 * @info: memory window allocation information 1649 * @scratch: u64 saved to be used during cqp completion 1650 * @post_sq: flag for cqp db to ring 1651 */ 1652 static int irdma_sc_mw_alloc(struct irdma_sc_dev *dev, 1653 struct irdma_mw_alloc_info *info, u64 scratch, 1654 bool post_sq) 1655 { 1656 u64 hdr; 1657 struct irdma_sc_cqp *cqp; 1658 __le64 *wqe; 1659 1660 cqp = dev->cqp; 1661 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1662 if (!wqe) 1663 return -ENOMEM; 1664 1665 set_64bit_val(wqe, 8, 1666 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1667 set_64bit_val(wqe, 16, 1668 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index) | 1669 FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); 1670 1671 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1672 FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) | 1673 FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY, 1674 info->mw1_bind_dont_vldt_key) | 1675 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1676 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1677 1678 set_64bit_val(wqe, 24, hdr); 1679 1680 print_hex_dump_debug("WQE: MW_ALLOC WQE", DUMP_PREFIX_OFFSET, 16, 8, 1681 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1682 if (post_sq) 1683 irdma_sc_cqp_post_sq(cqp); 1684 1685 return 0; 1686 } 1687 1688 /** 1689 * irdma_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp 1690 * @qp: sc qp struct 1691 * @info: fast mr info 1692 */ 1693 int irdma_sc_mr_fast_register(struct irdma_sc_qp *qp, 1694 struct irdma_fast_reg_stag_info *info) 1695 { 1696 u64 temp, hdr; 1697 __le64 *wqe; 1698 u32 wqe_idx; 1699 enum irdma_page_size page_size; 1700 struct irdma_post_sq_info sq_info = {}; 1701 1702 if (info->page_size == 0x40000000) 1703 page_size = IRDMA_PAGE_SIZE_1G; 1704 else if (info->page_size == 0x200000) 1705 page_size = IRDMA_PAGE_SIZE_2M; 1706 else 1707 page_size = IRDMA_PAGE_SIZE_4K; 1708 1709 sq_info.wr_id = info->wr_id; 1710 sq_info.signaled = info->signaled; 1711 1712 wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, 1713 IRDMA_QP_WQE_MIN_QUANTA, 0, &sq_info); 1714 if (!wqe) 1715 return -ENOMEM; 1716 1717 irdma_clr_wqes(&qp->qp_uk, wqe_idx); 1718 1719 ibdev_dbg(to_ibdev(qp->dev), 1720 "MR: wr_id[%llxh] wqe_idx[%04d] location[%p]\n", 1721 info->wr_id, wqe_idx, 1722 &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid); 1723 1724 set_64bit_val(wqe, 0, info->va); 1725 1726 temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI, 1727 info->first_pm_pbl_index >> 16); 1728 set_64bit_val(wqe, 8, 1729 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) | 1730 FIELD_PREP(IRDMAQPSQ_PBLADDR, info->reg_addr_pa >> IRDMA_HW_PAGE_SHIFT)); 1731 set_64bit_val(wqe, 16, 1732 info->total_len | 1733 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index)); 1734 1735 hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) | 1736 FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) | 1737 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) | 1738 FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) | 1739 FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) | 1740 FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) | 1741 IRDMAQPSQ_VABASEDTO | 1742 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | 1743 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 1744 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 1745 FIELD_PREP(IRDMAQPSQ_REMOTE_ATOMICS_EN, info->remote_atomics_en) | 1746 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1747 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1748 1749 set_64bit_val(wqe, 24, hdr); 1750 1751 print_hex_dump_debug("WQE: FAST_REG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1752 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1753 1754 irdma_uk_qp_post_wr(&qp->qp_uk); 1755 1756 return 0; 1757 } 1758 1759 /** 1760 * irdma_sc_gen_rts_ae - request AE generated after RTS 1761 * @qp: sc qp struct 1762 */ 1763 static void irdma_sc_gen_rts_ae(struct irdma_sc_qp *qp) 1764 { 1765 __le64 *wqe; 1766 u64 hdr; 1767 struct irdma_qp_uk *qp_uk; 1768 1769 qp_uk = &qp->qp_uk; 1770 1771 wqe = qp_uk->sq_base[1].elem; 1772 1773 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | 1774 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) | 1775 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1776 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1777 1778 set_64bit_val(wqe, 24, hdr); 1779 print_hex_dump_debug("QP: NOP W/LOCAL FENCE WQE", DUMP_PREFIX_OFFSET, 1780 16, 8, wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1781 1782 wqe = qp_uk->sq_base[2].elem; 1783 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) | 1784 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1785 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1786 1787 set_64bit_val(wqe, 24, hdr); 1788 print_hex_dump_debug("QP: CONN EST WQE", DUMP_PREFIX_OFFSET, 16, 8, 1789 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1790 } 1791 1792 /** 1793 * irdma_sc_send_lsmm - send last streaming mode message 1794 * @qp: sc qp struct 1795 * @lsmm_buf: buffer with lsmm message 1796 * @size: size of lsmm buffer 1797 * @stag: stag of lsmm buffer 1798 */ 1799 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size, 1800 irdma_stag stag) 1801 { 1802 __le64 *wqe; 1803 u64 hdr; 1804 struct irdma_qp_uk *qp_uk; 1805 1806 qp_uk = &qp->qp_uk; 1807 wqe = qp_uk->sq_base->elem; 1808 1809 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf); 1810 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1811 set_64bit_val(wqe, 8, 1812 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) | 1813 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag)); 1814 } else { 1815 set_64bit_val(wqe, 8, 1816 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) | 1817 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) | 1818 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1819 } 1820 set_64bit_val(wqe, 16, 0); 1821 1822 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) | 1823 FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) | 1824 FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) | 1825 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1826 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1827 1828 set_64bit_val(wqe, 24, hdr); 1829 1830 print_hex_dump_debug("WQE: SEND_LSMM WQE", DUMP_PREFIX_OFFSET, 16, 8, 1831 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1832 1833 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1834 irdma_sc_gen_rts_ae(qp); 1835 } 1836 1837 /** 1838 * irdma_sc_send_rtt - send last read0 or write0 1839 * @qp: sc qp struct 1840 * @read: Do read0 or write0 1841 */ 1842 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read) 1843 { 1844 __le64 *wqe; 1845 u64 hdr; 1846 struct irdma_qp_uk *qp_uk; 1847 1848 qp_uk = &qp->qp_uk; 1849 wqe = qp_uk->sq_base->elem; 1850 1851 set_64bit_val(wqe, 0, 0); 1852 set_64bit_val(wqe, 16, 0); 1853 if (read) { 1854 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1855 set_64bit_val(wqe, 8, 1856 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd)); 1857 } else { 1858 set_64bit_val(wqe, 8, 1859 (u64)0xabcd | FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1860 } 1861 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) | 1862 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) | 1863 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1864 1865 } else { 1866 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1867 set_64bit_val(wqe, 8, 0); 1868 } else { 1869 set_64bit_val(wqe, 8, 1870 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1871 } 1872 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) | 1873 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1874 } 1875 1876 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1877 1878 set_64bit_val(wqe, 24, hdr); 1879 1880 print_hex_dump_debug("WQE: RTR WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 1881 IRDMA_QP_WQE_MIN_SIZE, false); 1882 1883 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1884 irdma_sc_gen_rts_ae(qp); 1885 } 1886 1887 /** 1888 * irdma_iwarp_opcode - determine if incoming is rdma layer 1889 * @info: aeq info for the packet 1890 * @pkt: packet for error 1891 */ 1892 static u32 irdma_iwarp_opcode(struct irdma_aeqe_info *info, u8 *pkt) 1893 { 1894 __be16 *mpa; 1895 u32 opcode = 0xffffffff; 1896 1897 if (info->q2_data_written) { 1898 mpa = (__be16 *)pkt; 1899 opcode = ntohs(mpa[1]) & 0xf; 1900 } 1901 1902 return opcode; 1903 } 1904 1905 /** 1906 * irdma_locate_mpa - return pointer to mpa in the pkt 1907 * @pkt: packet with data 1908 */ 1909 static u8 *irdma_locate_mpa(u8 *pkt) 1910 { 1911 /* skip over ethernet header */ 1912 pkt += IRDMA_MAC_HLEN; 1913 1914 /* Skip over IP and TCP headers */ 1915 pkt += 4 * (pkt[0] & 0x0f); 1916 pkt += 4 * ((pkt[12] >> 4) & 0x0f); 1917 1918 return pkt; 1919 } 1920 1921 /** 1922 * irdma_bld_termhdr_ctrl - setup terminate hdr control fields 1923 * @qp: sc qp ptr for pkt 1924 * @hdr: term hdr 1925 * @opcode: flush opcode for termhdr 1926 * @layer_etype: error layer + error type 1927 * @err: error cod ein the header 1928 */ 1929 static void irdma_bld_termhdr_ctrl(struct irdma_sc_qp *qp, 1930 struct irdma_terminate_hdr *hdr, 1931 enum irdma_flush_opcode opcode, 1932 u8 layer_etype, u8 err) 1933 { 1934 qp->flush_code = opcode; 1935 hdr->layer_etype = layer_etype; 1936 hdr->error_code = err; 1937 } 1938 1939 /** 1940 * irdma_bld_termhdr_ddp_rdma - setup ddp and rdma hdrs in terminate hdr 1941 * @pkt: ptr to mpa in offending pkt 1942 * @hdr: term hdr 1943 * @copy_len: offending pkt length to be copied to term hdr 1944 * @is_tagged: DDP tagged or untagged 1945 */ 1946 static void irdma_bld_termhdr_ddp_rdma(u8 *pkt, struct irdma_terminate_hdr *hdr, 1947 int *copy_len, u8 *is_tagged) 1948 { 1949 u16 ddp_seg_len; 1950 1951 ddp_seg_len = ntohs(*(__be16 *)pkt); 1952 if (ddp_seg_len) { 1953 *copy_len = 2; 1954 hdr->hdrct = DDP_LEN_FLAG; 1955 if (pkt[2] & 0x80) { 1956 *is_tagged = 1; 1957 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) { 1958 *copy_len += TERM_DDP_LEN_TAGGED; 1959 hdr->hdrct |= DDP_HDR_FLAG; 1960 } 1961 } else { 1962 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) { 1963 *copy_len += TERM_DDP_LEN_UNTAGGED; 1964 hdr->hdrct |= DDP_HDR_FLAG; 1965 } 1966 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN) && 1967 ((pkt[3] & RDMA_OPCODE_M) == RDMA_READ_REQ_OPCODE)) { 1968 *copy_len += TERM_RDMA_LEN; 1969 hdr->hdrct |= RDMA_HDR_FLAG; 1970 } 1971 } 1972 } 1973 } 1974 1975 /** 1976 * irdma_bld_terminate_hdr - build terminate message header 1977 * @qp: qp associated with received terminate AE 1978 * @info: the struct contiaing AE information 1979 */ 1980 static int irdma_bld_terminate_hdr(struct irdma_sc_qp *qp, 1981 struct irdma_aeqe_info *info) 1982 { 1983 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 1984 int copy_len = 0; 1985 u8 is_tagged = 0; 1986 u32 opcode; 1987 struct irdma_terminate_hdr *termhdr; 1988 1989 termhdr = (struct irdma_terminate_hdr *)qp->q2_buf; 1990 memset(termhdr, 0, Q2_BAD_FRAME_OFFSET); 1991 1992 if (info->q2_data_written) { 1993 pkt = irdma_locate_mpa(pkt); 1994 irdma_bld_termhdr_ddp_rdma(pkt, termhdr, ©_len, &is_tagged); 1995 } 1996 1997 opcode = irdma_iwarp_opcode(info, pkt); 1998 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 1999 qp->sq_flush_code = info->sq; 2000 qp->rq_flush_code = info->rq; 2001 2002 switch (info->ae_id) { 2003 case IRDMA_AE_AMP_UNALLOCATED_STAG: 2004 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2005 if (opcode == IRDMA_OP_TYPE_RDMA_WRITE) 2006 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 2007 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2008 DDP_TAGGED_INV_STAG); 2009 else 2010 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2011 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2012 RDMAP_INV_STAG); 2013 break; 2014 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 2015 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2016 if (info->q2_data_written) 2017 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 2018 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2019 DDP_TAGGED_BOUNDS); 2020 else 2021 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2022 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2023 RDMAP_INV_BOUNDS); 2024 break; 2025 case IRDMA_AE_AMP_BAD_PD: 2026 switch (opcode) { 2027 case IRDMA_OP_TYPE_RDMA_WRITE: 2028 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 2029 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2030 DDP_TAGGED_UNASSOC_STAG); 2031 break; 2032 case IRDMA_OP_TYPE_SEND_INV: 2033 case IRDMA_OP_TYPE_SEND_SOL_INV: 2034 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2035 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2036 RDMAP_CANT_INV_STAG); 2037 break; 2038 default: 2039 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2040 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2041 RDMAP_UNASSOC_STAG); 2042 } 2043 break; 2044 case IRDMA_AE_AMP_INVALID_STAG: 2045 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2046 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2047 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2048 RDMAP_INV_STAG); 2049 break; 2050 case IRDMA_AE_AMP_BAD_QP: 2051 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_QP_OP_ERR, 2052 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2053 DDP_UNTAGGED_INV_QN); 2054 break; 2055 case IRDMA_AE_AMP_BAD_STAG_KEY: 2056 case IRDMA_AE_AMP_BAD_STAG_INDEX: 2057 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2058 switch (opcode) { 2059 case IRDMA_OP_TYPE_SEND_INV: 2060 case IRDMA_OP_TYPE_SEND_SOL_INV: 2061 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 2062 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2063 RDMAP_CANT_INV_STAG); 2064 break; 2065 default: 2066 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2067 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2068 RDMAP_INV_STAG); 2069 } 2070 break; 2071 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 2072 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 2073 case IRDMA_AE_PRIV_OPERATION_DENIED: 2074 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2075 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2076 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2077 RDMAP_ACCESS); 2078 break; 2079 case IRDMA_AE_AMP_TO_WRAP: 2080 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2081 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 2082 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 2083 RDMAP_TO_WRAP); 2084 break; 2085 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 2086 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2087 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC); 2088 break; 2089 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 2090 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 2091 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 2092 DDP_CATASTROPHIC_LOCAL); 2093 break; 2094 case IRDMA_AE_LCE_QP_CATASTROPHIC: 2095 case IRDMA_AE_DDP_NO_L_BIT: 2096 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 2097 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 2098 DDP_CATASTROPHIC_LOCAL); 2099 break; 2100 case IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN: 2101 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2102 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2103 DDP_UNTAGGED_INV_MSN_RANGE); 2104 break; 2105 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 2106 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 2107 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 2108 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2109 DDP_UNTAGGED_INV_TOO_LONG); 2110 break; 2111 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 2112 if (is_tagged) 2113 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2114 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 2115 DDP_TAGGED_INV_DDP_VER); 2116 else 2117 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2118 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2119 DDP_UNTAGGED_INV_DDP_VER); 2120 break; 2121 case IRDMA_AE_DDP_UBE_INVALID_MO: 2122 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2123 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2124 DDP_UNTAGGED_INV_MO); 2125 break; 2126 case IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: 2127 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 2128 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2129 DDP_UNTAGGED_INV_MSN_NO_BUF); 2130 break; 2131 case IRDMA_AE_DDP_UBE_INVALID_QN: 2132 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2133 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 2134 DDP_UNTAGGED_INV_QN); 2135 break; 2136 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 2137 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 2138 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2139 RDMAP_INV_RDMAP_VER); 2140 break; 2141 default: 2142 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 2143 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 2144 RDMAP_UNSPECIFIED); 2145 break; 2146 } 2147 2148 if (copy_len) 2149 memcpy(termhdr + 1, pkt, copy_len); 2150 2151 return sizeof(struct irdma_terminate_hdr) + copy_len; 2152 } 2153 2154 /** 2155 * irdma_terminate_send_fin() - Send fin for terminate message 2156 * @qp: qp associated with received terminate AE 2157 */ 2158 void irdma_terminate_send_fin(struct irdma_sc_qp *qp) 2159 { 2160 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 2161 IRDMAQP_TERM_SEND_FIN_ONLY, 0); 2162 } 2163 2164 /** 2165 * irdma_terminate_connection() - Bad AE and send terminate to remote QP 2166 * @qp: qp associated with received terminate AE 2167 * @info: the struct contiaing AE information 2168 */ 2169 void irdma_terminate_connection(struct irdma_sc_qp *qp, 2170 struct irdma_aeqe_info *info) 2171 { 2172 u8 termlen = 0; 2173 2174 if (qp->term_flags & IRDMA_TERM_SENT) 2175 return; 2176 2177 termlen = irdma_bld_terminate_hdr(qp, info); 2178 irdma_terminate_start_timer(qp); 2179 qp->term_flags |= IRDMA_TERM_SENT; 2180 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 2181 IRDMAQP_TERM_SEND_TERM_ONLY, termlen); 2182 } 2183 2184 /** 2185 * irdma_terminate_received - handle terminate received AE 2186 * @qp: qp associated with received terminate AE 2187 * @info: the struct contiaing AE information 2188 */ 2189 void irdma_terminate_received(struct irdma_sc_qp *qp, 2190 struct irdma_aeqe_info *info) 2191 { 2192 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 2193 __be32 *mpa; 2194 u8 ddp_ctl; 2195 u8 rdma_ctl; 2196 u16 aeq_id = 0; 2197 struct irdma_terminate_hdr *termhdr; 2198 2199 mpa = (__be32 *)irdma_locate_mpa(pkt); 2200 if (info->q2_data_written) { 2201 /* did not validate the frame - do it now */ 2202 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff; 2203 rdma_ctl = ntohl(mpa[0]) & 0xff; 2204 if ((ddp_ctl & 0xc0) != 0x40) 2205 aeq_id = IRDMA_AE_LCE_QP_CATASTROPHIC; 2206 else if ((ddp_ctl & 0x03) != 1) 2207 aeq_id = IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION; 2208 else if (ntohl(mpa[2]) != 2) 2209 aeq_id = IRDMA_AE_DDP_UBE_INVALID_QN; 2210 else if (ntohl(mpa[3]) != 1) 2211 aeq_id = IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN; 2212 else if (ntohl(mpa[4]) != 0) 2213 aeq_id = IRDMA_AE_DDP_UBE_INVALID_MO; 2214 else if ((rdma_ctl & 0xc0) != 0x40) 2215 aeq_id = IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION; 2216 2217 info->ae_id = aeq_id; 2218 if (info->ae_id) { 2219 /* Bad terminate recvd - send back a terminate */ 2220 irdma_terminate_connection(qp, info); 2221 return; 2222 } 2223 } 2224 2225 qp->term_flags |= IRDMA_TERM_RCVD; 2226 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 2227 termhdr = (struct irdma_terminate_hdr *)&mpa[5]; 2228 if (termhdr->layer_etype == RDMAP_REMOTE_PROT || 2229 termhdr->layer_etype == RDMAP_REMOTE_OP) { 2230 irdma_terminate_done(qp, 0); 2231 } else { 2232 irdma_terminate_start_timer(qp); 2233 irdma_terminate_send_fin(qp); 2234 } 2235 } 2236 2237 static int irdma_null_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri) 2238 { 2239 return 0; 2240 } 2241 2242 static void irdma_null_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri) 2243 { 2244 /* do nothing */ 2245 } 2246 2247 static void irdma_null_ws_reset(struct irdma_sc_vsi *vsi) 2248 { 2249 /* do nothing */ 2250 } 2251 2252 /** 2253 * irdma_sc_vsi_init - Init the vsi structure 2254 * @vsi: pointer to vsi structure to initialize 2255 * @info: the info used to initialize the vsi struct 2256 */ 2257 void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi, 2258 struct irdma_vsi_init_info *info) 2259 { 2260 int i; 2261 2262 vsi->dev = info->dev; 2263 vsi->back_vsi = info->back_vsi; 2264 vsi->register_qset = info->register_qset; 2265 vsi->unregister_qset = info->unregister_qset; 2266 vsi->mtu = info->params->mtu; 2267 vsi->exception_lan_q = info->exception_lan_q; 2268 vsi->vsi_idx = info->pf_data_vsi_num; 2269 2270 irdma_set_qos_info(vsi, info->params); 2271 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 2272 mutex_init(&vsi->qos[i].qos_mutex); 2273 INIT_LIST_HEAD(&vsi->qos[i].qplist); 2274 } 2275 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) { 2276 vsi->dev->ws_add = irdma_ws_add; 2277 vsi->dev->ws_remove = irdma_ws_remove; 2278 vsi->dev->ws_reset = irdma_ws_reset; 2279 } else { 2280 vsi->dev->ws_add = irdma_null_ws_add; 2281 vsi->dev->ws_remove = irdma_null_ws_remove; 2282 vsi->dev->ws_reset = irdma_null_ws_reset; 2283 } 2284 } 2285 2286 /** 2287 * irdma_get_stats_idx - Return stats index 2288 * @vsi: pointer to the vsi 2289 */ 2290 static u16 irdma_get_stats_idx(struct irdma_sc_vsi *vsi) 2291 { 2292 struct irdma_stats_inst_info stats_info = {}; 2293 struct irdma_sc_dev *dev = vsi->dev; 2294 u8 i; 2295 2296 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 2297 if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE, 2298 &stats_info)) 2299 return stats_info.stats_idx; 2300 } 2301 2302 for (i = 0; i < IRDMA_MAX_STATS_COUNT_GEN_1; i++) { 2303 if (!dev->stats_idx_array[i]) { 2304 dev->stats_idx_array[i] = true; 2305 return i; 2306 } 2307 } 2308 2309 return IRDMA_INVALID_STATS_IDX; 2310 } 2311 2312 /** 2313 * irdma_hw_stats_init_gen1 - Initialize stat reg table used for gen1 2314 * @vsi: vsi structure where hw_regs are set 2315 * 2316 * Populate the HW stats table 2317 */ 2318 static void irdma_hw_stats_init_gen1(struct irdma_sc_vsi *vsi) 2319 { 2320 struct irdma_sc_dev *dev = vsi->dev; 2321 const struct irdma_hw_stat_map *map; 2322 u64 *stat_reg = vsi->hw_stats_regs; 2323 u64 *regs = dev->hw_stats_regs; 2324 u16 i, stats_reg_set = vsi->stats_idx; 2325 2326 map = dev->hw_stats_map; 2327 2328 /* First 4 stat instances are reserved for port level statistics. */ 2329 stats_reg_set += vsi->stats_inst_alloc ? IRDMA_FIRST_NON_PF_STAT : 0; 2330 2331 for (i = 0; i < dev->hw_attrs.max_stat_idx; i++) { 2332 if (map[i].bitmask <= IRDMA_MAX_STATS_32) 2333 stat_reg[i] = regs[i] + stats_reg_set * sizeof(u32); 2334 else 2335 stat_reg[i] = regs[i] + stats_reg_set * sizeof(u64); 2336 } 2337 } 2338 2339 /** 2340 * irdma_vsi_stats_init - Initialize the vsi statistics 2341 * @vsi: pointer to the vsi structure 2342 * @info: The info structure used for initialization 2343 */ 2344 int irdma_vsi_stats_init(struct irdma_sc_vsi *vsi, 2345 struct irdma_vsi_stats_info *info) 2346 { 2347 struct irdma_dma_mem *stats_buff_mem; 2348 2349 vsi->pestat = info->pestat; 2350 vsi->pestat->hw = vsi->dev->hw; 2351 vsi->pestat->vsi = vsi; 2352 stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem; 2353 stats_buff_mem->size = ALIGN(IRDMA_GATHER_STATS_BUF_SIZE * 2, 1); 2354 stats_buff_mem->va = dma_alloc_coherent(vsi->pestat->hw->device, 2355 stats_buff_mem->size, 2356 &stats_buff_mem->pa, 2357 GFP_KERNEL); 2358 if (!stats_buff_mem->va) 2359 return -ENOMEM; 2360 2361 vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va; 2362 vsi->pestat->gather_info.last_gather_stats_va = 2363 (void *)((uintptr_t)stats_buff_mem->va + 2364 IRDMA_GATHER_STATS_BUF_SIZE); 2365 2366 if (vsi->dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3) 2367 irdma_hw_stats_start_timer(vsi); 2368 2369 /* when stat allocation is not required default to fcn_id. */ 2370 vsi->stats_idx = info->fcn_id; 2371 if (info->alloc_stats_inst) { 2372 u16 stats_idx = irdma_get_stats_idx(vsi); 2373 2374 if (stats_idx != IRDMA_INVALID_STATS_IDX) { 2375 vsi->stats_inst_alloc = true; 2376 vsi->stats_idx = stats_idx; 2377 vsi->pestat->gather_info.use_stats_inst = true; 2378 vsi->pestat->gather_info.stats_inst_index = stats_idx; 2379 } 2380 } 2381 2382 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 2383 irdma_hw_stats_init_gen1(vsi); 2384 2385 return 0; 2386 } 2387 2388 /** 2389 * irdma_vsi_stats_free - Free the vsi stats 2390 * @vsi: pointer to the vsi structure 2391 */ 2392 void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi) 2393 { 2394 struct irdma_stats_inst_info stats_info = {}; 2395 struct irdma_sc_dev *dev = vsi->dev; 2396 u16 stats_idx = vsi->stats_idx; 2397 2398 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 2399 if (vsi->stats_inst_alloc) { 2400 stats_info.stats_idx = vsi->stats_idx; 2401 irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE, 2402 &stats_info); 2403 } 2404 } else { 2405 if (vsi->stats_inst_alloc && 2406 stats_idx < vsi->dev->hw_attrs.max_stat_inst) 2407 vsi->dev->stats_idx_array[stats_idx] = false; 2408 } 2409 2410 if (!vsi->pestat) 2411 return; 2412 2413 if (dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3) 2414 irdma_hw_stats_stop_timer(vsi); 2415 dma_free_coherent(vsi->pestat->hw->device, 2416 vsi->pestat->gather_info.stats_buff_mem.size, 2417 vsi->pestat->gather_info.stats_buff_mem.va, 2418 vsi->pestat->gather_info.stats_buff_mem.pa); 2419 vsi->pestat->gather_info.stats_buff_mem.va = NULL; 2420 } 2421 2422 /** 2423 * irdma_get_encoded_wqe_size - given wq size, returns hardware encoded size 2424 * @wqsize: size of the wq (sq, rq) to encoded_size 2425 * @queue_type: queue type selected for the calculation algorithm 2426 */ 2427 u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type) 2428 { 2429 u8 encoded_size = 0; 2430 2431 if (queue_type == IRDMA_QUEUE_TYPE_SRQ) { 2432 /* Smallest SRQ size is 256B (8 quanta) that gets 2433 * encoded to 0. 2434 */ 2435 encoded_size = ilog2(wqsize) - 3; 2436 2437 return encoded_size; 2438 } 2439 /* cqp sq's hw coded value starts from 1 for size of 4 2440 * while it starts from 0 for qp' wq's. 2441 */ 2442 if (queue_type == IRDMA_QUEUE_TYPE_CQP) 2443 encoded_size = 1; 2444 wqsize >>= 2; 2445 while (wqsize >>= 1) 2446 encoded_size++; 2447 2448 return encoded_size; 2449 } 2450 2451 /** 2452 * irdma_sc_gather_stats - collect the statistics 2453 * @cqp: struct for cqp hw 2454 * @info: gather stats info structure 2455 * @scratch: u64 saved to be used during cqp completion 2456 */ 2457 static int irdma_sc_gather_stats(struct irdma_sc_cqp *cqp, 2458 struct irdma_stats_gather_info *info, 2459 u64 scratch) 2460 { 2461 __le64 *wqe; 2462 u64 temp; 2463 2464 if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE) 2465 return -ENOMEM; 2466 2467 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2468 if (!wqe) 2469 return -ENOMEM; 2470 2471 set_64bit_val(wqe, 40, 2472 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index)); 2473 set_64bit_val(wqe, 32, info->stats_buff_mem.pa); 2474 2475 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2476 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) | 2477 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, 2478 info->stats_inst_index) | 2479 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2480 info->use_hmc_fcn_index) | 2481 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS); 2482 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2483 2484 set_64bit_val(wqe, 24, temp); 2485 2486 print_hex_dump_debug("STATS: GATHER_STATS WQE", DUMP_PREFIX_OFFSET, 2487 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2488 2489 irdma_sc_cqp_post_sq(cqp); 2490 ibdev_dbg(to_ibdev(cqp->dev), 2491 "STATS: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 2492 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 2493 2494 return 0; 2495 } 2496 2497 /** 2498 * irdma_sc_manage_stats_inst - allocate or free stats instance 2499 * @cqp: struct for cqp hw 2500 * @info: stats info structure 2501 * @alloc: alloc vs. delete flag 2502 * @scratch: u64 saved to be used during cqp completion 2503 */ 2504 static int irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp, 2505 struct irdma_stats_inst_info *info, 2506 bool alloc, u64 scratch) 2507 { 2508 __le64 *wqe; 2509 u64 temp; 2510 2511 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2512 if (!wqe) 2513 return -ENOMEM; 2514 2515 set_64bit_val(wqe, 40, 2516 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id)); 2517 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2518 FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) | 2519 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2520 info->use_hmc_fcn_index) | 2521 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) | 2522 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS); 2523 2524 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2525 2526 set_64bit_val(wqe, 24, temp); 2527 2528 print_hex_dump_debug("WQE: MANAGE_STATS WQE", DUMP_PREFIX_OFFSET, 16, 2529 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2530 2531 irdma_sc_cqp_post_sq(cqp); 2532 return 0; 2533 } 2534 2535 /** 2536 * irdma_sc_set_up_map - set the up map table 2537 * @cqp: struct for cqp hw 2538 * @info: User priority map info 2539 * @scratch: u64 saved to be used during cqp completion 2540 */ 2541 static int irdma_sc_set_up_map(struct irdma_sc_cqp *cqp, 2542 struct irdma_up_info *info, u64 scratch) 2543 { 2544 __le64 *wqe; 2545 u64 temp = 0; 2546 int i; 2547 2548 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2549 if (!wqe) 2550 return -ENOMEM; 2551 2552 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) 2553 temp |= (u64)info->map[i] << (i * 8); 2554 2555 set_64bit_val(wqe, 0, temp); 2556 set_64bit_val(wqe, 40, 2557 FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) | 2558 FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx)); 2559 2560 temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) | 2561 FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) | 2562 FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE, 2563 info->use_cnp_up_override) | 2564 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP); 2565 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2566 2567 set_64bit_val(wqe, 24, temp); 2568 2569 print_hex_dump_debug("WQE: UPMAP WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 2570 IRDMA_CQP_WQE_SIZE * 8, false); 2571 irdma_sc_cqp_post_sq(cqp); 2572 2573 return 0; 2574 } 2575 2576 /** 2577 * irdma_sc_manage_ws_node - create/modify/destroy WS node 2578 * @cqp: struct for cqp hw 2579 * @info: node info structure 2580 * @node_op: 0 for add 1 for modify, 2 for delete 2581 * @scratch: u64 saved to be used during cqp completion 2582 */ 2583 static int irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp, 2584 struct irdma_ws_node_info *info, 2585 enum irdma_ws_node_op node_op, u64 scratch) 2586 { 2587 __le64 *wqe; 2588 u64 temp = 0; 2589 2590 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2591 if (!wqe) 2592 return -ENOMEM; 2593 2594 set_64bit_val(wqe, 32, 2595 FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) | 2596 FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight)); 2597 2598 temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) | 2599 FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) | 2600 FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) | 2601 FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) | 2602 FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) | 2603 FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) | 2604 FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) | 2605 FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) | 2606 FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id); 2607 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2608 2609 set_64bit_val(wqe, 24, temp); 2610 2611 print_hex_dump_debug("WQE: MANAGE_WS WQE", DUMP_PREFIX_OFFSET, 16, 8, 2612 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2613 irdma_sc_cqp_post_sq(cqp); 2614 2615 return 0; 2616 } 2617 2618 /** 2619 * irdma_sc_qp_flush_wqes - flush qp's wqe 2620 * @qp: sc qp 2621 * @info: dlush information 2622 * @scratch: u64 saved to be used during cqp completion 2623 */ 2624 int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp, 2625 struct irdma_qp_flush_info *info, u64 scratch) 2626 { 2627 u64 temp = 0; 2628 __le64 *wqe; 2629 struct irdma_sc_cqp *cqp; 2630 u64 hdr; 2631 bool flush_sq = false, flush_rq = false; 2632 2633 if (info->rq && !qp->flush_rq) 2634 flush_rq = true; 2635 if (info->sq && !qp->flush_sq) 2636 flush_sq = true; 2637 qp->flush_sq |= flush_sq; 2638 qp->flush_rq |= flush_rq; 2639 2640 if (!flush_sq && !flush_rq) { 2641 ibdev_dbg(to_ibdev(qp->dev), 2642 "CQP: Additional flush request ignored for qp %x\n", 2643 qp->qp_uk.qp_id); 2644 return -EALREADY; 2645 } 2646 2647 cqp = qp->pd->dev->cqp; 2648 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2649 if (!wqe) 2650 return -ENOMEM; 2651 2652 if (info->userflushcode) { 2653 if (flush_rq) 2654 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR, 2655 info->rq_minor_code) | 2656 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR, 2657 info->rq_major_code); 2658 if (flush_sq) 2659 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR, 2660 info->sq_minor_code) | 2661 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR, 2662 info->sq_major_code); 2663 } 2664 set_64bit_val(wqe, 16, temp); 2665 2666 temp = (info->generate_ae) ? 2667 info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2668 info->ae_src) : 0; 2669 set_64bit_val(wqe, 8, temp); 2670 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 2671 set_64bit_val(wqe, 40, 2672 FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_SQ_IDX, info->err_sq_idx)); 2673 set_64bit_val(wqe, 48, 2674 FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_RQ_IDX, info->err_rq_idx)); 2675 } 2676 2677 hdr = qp->qp_uk.qp_id | 2678 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) | 2679 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) | 2680 FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) | 2681 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) | 2682 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) | 2683 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2684 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 2685 hdr |= FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_VALID, info->err_sq_idx_valid) | 2686 FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_RQ_IDX_VALID, info->err_rq_idx_valid); 2687 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2688 2689 set_64bit_val(wqe, 24, hdr); 2690 2691 print_hex_dump_debug("WQE: QP_FLUSH WQE", DUMP_PREFIX_OFFSET, 16, 8, 2692 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2693 irdma_sc_cqp_post_sq(cqp); 2694 2695 return 0; 2696 } 2697 2698 /** 2699 * irdma_sc_gen_ae - generate AE, uses flush WQE CQP OP 2700 * @qp: sc qp 2701 * @info: gen ae information 2702 * @scratch: u64 saved to be used during cqp completion 2703 * @post_sq: flag for cqp db to ring 2704 */ 2705 static int irdma_sc_gen_ae(struct irdma_sc_qp *qp, 2706 struct irdma_gen_ae_info *info, u64 scratch, 2707 bool post_sq) 2708 { 2709 u64 temp; 2710 __le64 *wqe; 2711 struct irdma_sc_cqp *cqp; 2712 u64 hdr; 2713 2714 cqp = qp->pd->dev->cqp; 2715 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2716 if (!wqe) 2717 return -ENOMEM; 2718 2719 temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2720 info->ae_src); 2721 set_64bit_val(wqe, 8, temp); 2722 2723 hdr = qp->qp_uk.qp_id | FIELD_PREP(IRDMA_CQPSQ_OPCODE, 2724 IRDMA_CQP_OP_GEN_AE) | 2725 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) | 2726 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2727 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2728 2729 set_64bit_val(wqe, 24, hdr); 2730 2731 print_hex_dump_debug("WQE: GEN_AE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2732 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2733 if (post_sq) 2734 irdma_sc_cqp_post_sq(cqp); 2735 2736 return 0; 2737 } 2738 2739 /*** irdma_sc_qp_upload_context - upload qp's context 2740 * @dev: sc device struct 2741 * @info: upload context info ptr for return 2742 * @scratch: u64 saved to be used during cqp completion 2743 * @post_sq: flag for cqp db to ring 2744 */ 2745 static int irdma_sc_qp_upload_context(struct irdma_sc_dev *dev, 2746 struct irdma_upload_context_info *info, 2747 u64 scratch, bool post_sq) 2748 { 2749 __le64 *wqe; 2750 struct irdma_sc_cqp *cqp; 2751 u64 hdr; 2752 2753 cqp = dev->cqp; 2754 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2755 if (!wqe) 2756 return -ENOMEM; 2757 2758 set_64bit_val(wqe, 16, info->buf_pa); 2759 2760 hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) | 2761 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) | 2762 FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) | 2763 FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) | 2764 FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) | 2765 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2766 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2767 2768 set_64bit_val(wqe, 24, hdr); 2769 2770 print_hex_dump_debug("WQE: QP_UPLOAD_CTX WQE", DUMP_PREFIX_OFFSET, 16, 2771 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2772 if (post_sq) 2773 irdma_sc_cqp_post_sq(cqp); 2774 2775 return 0; 2776 } 2777 2778 /** 2779 * irdma_sc_manage_push_page - Handle push page 2780 * @cqp: struct for cqp hw 2781 * @info: push page info 2782 * @scratch: u64 saved to be used during cqp completion 2783 * @post_sq: flag for cqp db to ring 2784 */ 2785 static int irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp, 2786 struct irdma_cqp_manage_push_page_info *info, 2787 u64 scratch, bool post_sq) 2788 { 2789 __le64 *wqe; 2790 u64 hdr; 2791 2792 if (info->free_page && 2793 info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages) 2794 return -EINVAL; 2795 2796 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2797 if (!wqe) 2798 return -ENOMEM; 2799 2800 set_64bit_val(wqe, 16, info->qs_handle); 2801 hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) | 2802 FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) | 2803 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) | 2804 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 2805 FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page); 2806 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2807 2808 set_64bit_val(wqe, 24, hdr); 2809 2810 print_hex_dump_debug("WQE: MANAGE_PUSH_PAGES WQE", DUMP_PREFIX_OFFSET, 2811 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2812 if (post_sq) 2813 irdma_sc_cqp_post_sq(cqp); 2814 2815 return 0; 2816 } 2817 2818 /** 2819 * irdma_sc_suspend_qp - suspend qp for param change 2820 * @cqp: struct for cqp hw 2821 * @qp: sc qp struct 2822 * @scratch: u64 saved to be used during cqp completion 2823 */ 2824 static int irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp, 2825 u64 scratch) 2826 { 2827 u64 hdr; 2828 __le64 *wqe; 2829 2830 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2831 if (!wqe) 2832 return -ENOMEM; 2833 2834 hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) | 2835 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) | 2836 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2837 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2838 2839 set_64bit_val(wqe, 24, hdr); 2840 2841 print_hex_dump_debug("WQE: SUSPEND_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2842 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2843 irdma_sc_cqp_post_sq(cqp); 2844 2845 return 0; 2846 } 2847 2848 /** 2849 * irdma_sc_resume_qp - resume qp after suspend 2850 * @cqp: struct for cqp hw 2851 * @qp: sc qp struct 2852 * @scratch: u64 saved to be used during cqp completion 2853 */ 2854 static int irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp, 2855 u64 scratch) 2856 { 2857 u64 hdr; 2858 __le64 *wqe; 2859 2860 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2861 if (!wqe) 2862 return -ENOMEM; 2863 2864 set_64bit_val(wqe, 16, 2865 FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle)); 2866 2867 hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) | 2868 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) | 2869 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2870 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2871 2872 set_64bit_val(wqe, 24, hdr); 2873 2874 print_hex_dump_debug("WQE: RESUME_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2875 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2876 irdma_sc_cqp_post_sq(cqp); 2877 2878 return 0; 2879 } 2880 2881 /** 2882 * irdma_sc_cq_init - initialize completion q 2883 * @cq: cq struct 2884 * @info: cq initialization info 2885 */ 2886 int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info) 2887 { 2888 u32 pble_obj_cnt; 2889 2890 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 2891 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 2892 return -EINVAL; 2893 2894 cq->cq_pa = info->cq_base_pa; 2895 cq->dev = info->dev; 2896 cq->ceq_id = info->ceq_id; 2897 info->cq_uk_init_info.cqe_alloc_db = cq->dev->cq_arm_db; 2898 info->cq_uk_init_info.cq_ack_db = cq->dev->cq_ack_db; 2899 irdma_uk_cq_init(&cq->cq_uk, &info->cq_uk_init_info); 2900 2901 cq->virtual_map = info->virtual_map; 2902 cq->pbl_chunk_size = info->pbl_chunk_size; 2903 cq->ceqe_mask = info->ceqe_mask; 2904 cq->cq_type = (info->type) ? info->type : IRDMA_CQ_TYPE_IWARP; 2905 cq->shadow_area_pa = info->shadow_area_pa; 2906 cq->shadow_read_threshold = info->shadow_read_threshold; 2907 cq->ceq_id_valid = info->ceq_id_valid; 2908 cq->tph_en = info->tph_en; 2909 cq->tph_val = info->tph_val; 2910 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 2911 cq->vsi = info->vsi; 2912 2913 return 0; 2914 } 2915 2916 /** 2917 * irdma_sc_cq_create - create completion q 2918 * @cq: cq struct 2919 * @scratch: u64 saved to be used during cqp completion 2920 * @check_overflow: flag for overflow check 2921 * @post_sq: flag for cqp db to ring 2922 */ 2923 static int irdma_sc_cq_create(struct irdma_sc_cq *cq, u64 scratch, 2924 bool check_overflow, bool post_sq) 2925 { 2926 __le64 *wqe; 2927 struct irdma_sc_cqp *cqp; 2928 u64 hdr; 2929 2930 cqp = cq->dev->cqp; 2931 if (cq->cq_uk.cq_id >= cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt) 2932 return -EINVAL; 2933 2934 if (cq->ceq_id >= cq->dev->hmc_fpm_misc.max_ceqs) 2935 return -EINVAL; 2936 2937 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2938 if (!wqe) 2939 return -ENOMEM; 2940 2941 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 2942 set_64bit_val(wqe, 8, cq->cq_uk.cq_id); 2943 set_64bit_val(wqe, 16, 2944 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 2945 set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa)); 2946 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2947 set_64bit_val(wqe, 48, 2948 FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX, (cq->virtual_map ? cq->first_pm_pbl_idx : 0))); 2949 set_64bit_val(wqe, 56, 2950 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 2951 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 2952 2953 hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) | 2954 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 2955 IRDMA_CQPSQ_CQ_CEQID) | 2956 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 2957 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 2958 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) | 2959 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 2960 FIELD_PREP(IRDMA_CQPSQ_CQ_CQID_HIGH, cq->cq_uk.cq_id >> 22) | 2961 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQID_HIGH, 2962 (cq->ceq_id_valid ? cq->ceq_id : 0) >> 10) | 2963 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2964 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 2965 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2966 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 2967 cq->cq_uk.avoid_mem_cflct) | 2968 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2969 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2970 2971 set_64bit_val(wqe, 24, hdr); 2972 2973 print_hex_dump_debug("WQE: CQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2974 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2975 if (post_sq) 2976 irdma_sc_cqp_post_sq(cqp); 2977 2978 return 0; 2979 } 2980 2981 /** 2982 * irdma_sc_cq_destroy - destroy completion q 2983 * @cq: cq struct 2984 * @scratch: u64 saved to be used during cqp completion 2985 * @post_sq: flag for cqp db to ring 2986 */ 2987 int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq) 2988 { 2989 struct irdma_sc_cqp *cqp; 2990 __le64 *wqe; 2991 u64 hdr; 2992 2993 cqp = cq->dev->cqp; 2994 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2995 if (!wqe) 2996 return -ENOMEM; 2997 2998 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 2999 set_64bit_val(wqe, 8, cq->cq_uk.cq_id); 3000 set_64bit_val(wqe, 40, cq->shadow_area_pa); 3001 set_64bit_val(wqe, 48, 3002 (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); 3003 3004 hdr = cq->cq_uk.cq_id | 3005 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 3006 IRDMA_CQPSQ_CQ_CEQID) | 3007 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 3008 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 3009 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 3010 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 3011 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 3012 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 3013 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) | 3014 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3015 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3016 3017 set_64bit_val(wqe, 24, hdr); 3018 3019 print_hex_dump_debug("WQE: CQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 3020 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3021 if (post_sq) 3022 irdma_sc_cqp_post_sq(cqp); 3023 3024 return 0; 3025 } 3026 3027 /** 3028 * irdma_sc_cq_resize - set resized cq buffer info 3029 * @cq: resized cq 3030 * @info: resized cq buffer info 3031 */ 3032 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info) 3033 { 3034 cq->virtual_map = info->virtual_map; 3035 cq->cq_pa = info->cq_pa; 3036 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 3037 cq->pbl_chunk_size = info->pbl_chunk_size; 3038 irdma_uk_cq_resize(&cq->cq_uk, info->cq_base, info->cq_size); 3039 } 3040 3041 /** 3042 * irdma_sc_cq_modify - modify a Completion Queue 3043 * @cq: cq struct 3044 * @info: modification info struct 3045 * @scratch: u64 saved to be used during cqp completion 3046 * @post_sq: flag to post to sq 3047 */ 3048 static int irdma_sc_cq_modify(struct irdma_sc_cq *cq, 3049 struct irdma_modify_cq_info *info, u64 scratch, 3050 bool post_sq) 3051 { 3052 struct irdma_sc_cqp *cqp; 3053 __le64 *wqe; 3054 u64 hdr; 3055 u32 pble_obj_cnt; 3056 3057 pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 3058 if (info->cq_resize && info->virtual_map && 3059 info->first_pm_pbl_idx >= pble_obj_cnt) 3060 return -EINVAL; 3061 3062 cqp = cq->dev->cqp; 3063 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3064 if (!wqe) 3065 return -ENOMEM; 3066 3067 set_64bit_val(wqe, 0, info->cq_size); 3068 set_64bit_val(wqe, 8, cq->cq_uk.cq_id); 3069 set_64bit_val(wqe, 16, 3070 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold)); 3071 set_64bit_val(wqe, 32, info->cq_pa); 3072 set_64bit_val(wqe, 40, cq->shadow_area_pa); 3073 set_64bit_val(wqe, 48, info->first_pm_pbl_idx); 3074 set_64bit_val(wqe, 56, 3075 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 3076 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 3077 3078 hdr = cq->cq_uk.cq_id | 3079 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) | 3080 FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) | 3081 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) | 3082 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) | 3083 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) | 3084 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 3085 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 3086 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 3087 cq->cq_uk.avoid_mem_cflct) | 3088 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3089 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3090 3091 set_64bit_val(wqe, 24, hdr); 3092 3093 print_hex_dump_debug("WQE: CQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 3094 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3095 if (post_sq) 3096 irdma_sc_cqp_post_sq(cqp); 3097 3098 return 0; 3099 } 3100 3101 /** 3102 * irdma_sc_get_decoded_ird_size_gen_3 - get decoded IRD size for GEN 3 3103 * @ird_enc: IRD encoding 3104 * IRD size defaults to a value of 4 in case of invalid input. 3105 */ 3106 static u16 irdma_sc_get_decoded_ird_size_gen_3(u8 ird_enc) 3107 { 3108 switch (ird_enc) { 3109 case IRDMA_IRD_HW_SIZE_4096_GEN3: 3110 return 4096; 3111 case IRDMA_IRD_HW_SIZE_2048_GEN3: 3112 return 2048; 3113 case IRDMA_IRD_HW_SIZE_1024_GEN3: 3114 return 1024; 3115 case IRDMA_IRD_HW_SIZE_512_GEN3: 3116 return 512; 3117 case IRDMA_IRD_HW_SIZE_256_GEN3: 3118 return 256; 3119 case IRDMA_IRD_HW_SIZE_128_GEN3: 3120 return 128; 3121 case IRDMA_IRD_HW_SIZE_64_GEN3: 3122 return 64; 3123 case IRDMA_IRD_HW_SIZE_32_GEN3: 3124 return 32; 3125 case IRDMA_IRD_HW_SIZE_16_GEN3: 3126 return 16; 3127 case IRDMA_IRD_HW_SIZE_8_GEN3: 3128 return 8; 3129 case IRDMA_IRD_HW_SIZE_4_GEN3: 3130 return 4; 3131 default: 3132 return 4; 3133 } 3134 } 3135 3136 /** 3137 * irdma_check_cqp_progress - check cqp processing progress 3138 * @timeout: timeout info struct 3139 * @dev: sc device struct 3140 */ 3141 void irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout, struct irdma_sc_dev *dev) 3142 { 3143 u64 completed_ops = atomic64_read(&dev->cqp->completed_ops); 3144 3145 if (timeout->compl_cqp_cmds != completed_ops) { 3146 timeout->compl_cqp_cmds = completed_ops; 3147 timeout->count = 0; 3148 } else if (timeout->compl_cqp_cmds != dev->cqp->requested_ops) { 3149 timeout->count++; 3150 } 3151 } 3152 3153 /** 3154 * irdma_get_cqp_reg_info - get head and tail for cqp using registers 3155 * @cqp: struct for cqp hw 3156 * @val: cqp tail register value 3157 * @tail: wqtail register value 3158 * @error: cqp processing err 3159 */ 3160 static inline void irdma_get_cqp_reg_info(struct irdma_sc_cqp *cqp, u32 *val, 3161 u32 *tail, u32 *error) 3162 { 3163 *val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]); 3164 *tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, *val); 3165 *error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, *val); 3166 } 3167 3168 /** 3169 * irdma_sc_cqp_def_cmpl_ae_handler - remove completed requests from pending list 3170 * @dev: sc device struct 3171 * @info: AE entry info 3172 * @first: true if this is the first call to this handler for given AEQE 3173 * @scratch: (out) scratch entry pointer 3174 * @sw_def_info: (in/out) SW ticket value for this AE 3175 * 3176 * In case of AE_DEF_CMPL event, this function should be called in a loop 3177 * until it returns NULL-ptr via scratch. 3178 * For each call, it looks for a matching CQP request on pending list, 3179 * removes it from the list and returns the pointer to the associated scratch 3180 * entry. 3181 * If this is the first call to this function for given AEQE, sw_def_info 3182 * value is not used to find matching requests. Instead, it is populated 3183 * with the value from the first matching cqp_request on the list. 3184 * For subsequent calls, ooo_op->sw_def_info need to match the value passed 3185 * by a caller. 3186 * 3187 * Return: scratch entry pointer for cqp_request to be released or NULL 3188 * if no matching request is found. 3189 */ 3190 void irdma_sc_cqp_def_cmpl_ae_handler(struct irdma_sc_dev *dev, 3191 struct irdma_aeqe_info *info, 3192 bool first, u64 *scratch, 3193 u32 *sw_def_info) 3194 { 3195 struct irdma_ooo_cqp_op *ooo_op; 3196 unsigned long flags; 3197 3198 *scratch = 0; 3199 3200 spin_lock_irqsave(&dev->cqp->ooo_list_lock, flags); 3201 list_for_each_entry(ooo_op, &dev->cqp->ooo_pnd, list_entry) { 3202 if (ooo_op->deferred && 3203 ((first && ooo_op->def_info == info->def_info) || 3204 (!first && ooo_op->sw_def_info == *sw_def_info))) { 3205 *sw_def_info = ooo_op->sw_def_info; 3206 *scratch = ooo_op->scratch; 3207 3208 list_move(&ooo_op->list_entry, &dev->cqp->ooo_avail); 3209 atomic64_inc(&dev->cqp->completed_ops); 3210 3211 break; 3212 } 3213 } 3214 spin_unlock_irqrestore(&dev->cqp->ooo_list_lock, flags); 3215 3216 if (first && !*scratch) 3217 ibdev_dbg(to_ibdev(dev), 3218 "AEQ: deferred completion with unknown ticket: def_info 0x%x\n", 3219 info->def_info); 3220 } 3221 3222 /** 3223 * irdma_sc_cqp_cleanup_handler - remove requests from pending list 3224 * @dev: sc device struct 3225 * 3226 * This function should be called in a loop from irdma_cleanup_pending_cqp_op. 3227 * For each call, it returns first CQP request on pending list, removes it 3228 * from the list and returns the pointer to the associated scratch entry. 3229 * 3230 * Return: scratch entry pointer for cqp_request to be released or NULL 3231 * if pending list is empty. 3232 */ 3233 u64 irdma_sc_cqp_cleanup_handler(struct irdma_sc_dev *dev) 3234 { 3235 struct irdma_ooo_cqp_op *ooo_op; 3236 u64 scratch = 0; 3237 3238 list_for_each_entry(ooo_op, &dev->cqp->ooo_pnd, list_entry) { 3239 scratch = ooo_op->scratch; 3240 3241 list_del(&ooo_op->list_entry); 3242 list_add(&ooo_op->list_entry, &dev->cqp->ooo_avail); 3243 atomic64_inc(&dev->cqp->completed_ops); 3244 3245 break; 3246 } 3247 3248 return scratch; 3249 } 3250 3251 /** 3252 * irdma_cqp_poll_registers - poll cqp registers 3253 * @cqp: struct for cqp hw 3254 * @tail: wqtail register value 3255 * @count: how many times to try for completion 3256 */ 3257 static int irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp, u32 tail, 3258 u32 count) 3259 { 3260 u32 i = 0; 3261 u32 newtail, error, val; 3262 3263 while (i++ < count) { 3264 irdma_get_cqp_reg_info(cqp, &val, &newtail, &error); 3265 if (error) { 3266 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3267 ibdev_dbg(to_ibdev(cqp->dev), 3268 "CQP: CQPERRCODES error_code[x%08X]\n", 3269 error); 3270 return -EIO; 3271 } 3272 if (newtail != tail) { 3273 /* SUCCESS */ 3274 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 3275 atomic64_inc(&cqp->completed_ops); 3276 return 0; 3277 } 3278 udelay(cqp->dev->hw_attrs.max_sleep_count); 3279 } 3280 3281 return -ETIMEDOUT; 3282 } 3283 3284 /** 3285 * irdma_sc_decode_fpm_commit - decode a 64 bit value into count and base 3286 * @dev: sc device struct 3287 * @buf: pointer to commit buffer 3288 * @buf_idx: buffer index 3289 * @obj_info: object info pointer 3290 * @rsrc_idx: indexs of memory resource 3291 */ 3292 static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 *buf, 3293 u32 buf_idx, struct irdma_hmc_obj_info *obj_info, 3294 u32 rsrc_idx) 3295 { 3296 u64 temp; 3297 3298 get_64bit_val(buf, buf_idx, &temp); 3299 3300 switch (rsrc_idx) { 3301 case IRDMA_HMC_IW_QP: 3302 obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp); 3303 break; 3304 case IRDMA_HMC_IW_CQ: 3305 obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT); 3306 break; 3307 case IRDMA_HMC_IW_APBVT_ENTRY: 3308 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) 3309 obj_info[rsrc_idx].cnt = 1; 3310 else 3311 obj_info[rsrc_idx].cnt = 0; 3312 break; 3313 default: 3314 obj_info[rsrc_idx].cnt = (u32)temp; 3315 break; 3316 } 3317 3318 obj_info[rsrc_idx].base = (temp >> IRDMA_COMMIT_FPM_BASE_S) * 512; 3319 3320 return temp; 3321 } 3322 3323 /** 3324 * irdma_sc_parse_fpm_commit_buf - parse fpm commit buffer 3325 * @dev: pointer to dev struct 3326 * @buf: ptr to fpm commit buffer 3327 * @info: ptr to irdma_hmc_obj_info struct 3328 * @sd: number of SDs for HMC objects 3329 * 3330 * parses fpm commit info and copy base value 3331 * of hmc objects in hmc_info 3332 */ 3333 static void 3334 irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf, 3335 struct irdma_hmc_obj_info *info, u32 *sd) 3336 { 3337 u64 size; 3338 u32 i; 3339 u64 max_base = 0; 3340 u32 last_hmc_obj = 0; 3341 3342 irdma_sc_decode_fpm_commit(dev, buf, 0, info, 3343 IRDMA_HMC_IW_QP); 3344 irdma_sc_decode_fpm_commit(dev, buf, 8, info, 3345 IRDMA_HMC_IW_CQ); 3346 irdma_sc_decode_fpm_commit(dev, buf, 16, info, 3347 IRDMA_HMC_IW_SRQ); 3348 irdma_sc_decode_fpm_commit(dev, buf, 24, info, 3349 IRDMA_HMC_IW_HTE); 3350 irdma_sc_decode_fpm_commit(dev, buf, 32, info, 3351 IRDMA_HMC_IW_ARP); 3352 irdma_sc_decode_fpm_commit(dev, buf, 40, info, 3353 IRDMA_HMC_IW_APBVT_ENTRY); 3354 irdma_sc_decode_fpm_commit(dev, buf, 48, info, 3355 IRDMA_HMC_IW_MR); 3356 irdma_sc_decode_fpm_commit(dev, buf, 56, info, 3357 IRDMA_HMC_IW_XF); 3358 irdma_sc_decode_fpm_commit(dev, buf, 64, info, 3359 IRDMA_HMC_IW_XFFL); 3360 irdma_sc_decode_fpm_commit(dev, buf, 72, info, 3361 IRDMA_HMC_IW_Q1); 3362 irdma_sc_decode_fpm_commit(dev, buf, 80, info, 3363 IRDMA_HMC_IW_Q1FL); 3364 irdma_sc_decode_fpm_commit(dev, buf, 88, info, 3365 IRDMA_HMC_IW_TIMER); 3366 irdma_sc_decode_fpm_commit(dev, buf, 112, info, 3367 IRDMA_HMC_IW_PBLE); 3368 /* skipping RSVD. */ 3369 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 3370 irdma_sc_decode_fpm_commit(dev, buf, 96, info, 3371 IRDMA_HMC_IW_FSIMC); 3372 irdma_sc_decode_fpm_commit(dev, buf, 104, info, 3373 IRDMA_HMC_IW_FSIAV); 3374 irdma_sc_decode_fpm_commit(dev, buf, 128, info, 3375 IRDMA_HMC_IW_RRF); 3376 irdma_sc_decode_fpm_commit(dev, buf, 136, info, 3377 IRDMA_HMC_IW_RRFFL); 3378 irdma_sc_decode_fpm_commit(dev, buf, 144, info, 3379 IRDMA_HMC_IW_HDR); 3380 irdma_sc_decode_fpm_commit(dev, buf, 152, info, 3381 IRDMA_HMC_IW_MD); 3382 if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) { 3383 irdma_sc_decode_fpm_commit(dev, buf, 160, info, 3384 IRDMA_HMC_IW_OOISC); 3385 irdma_sc_decode_fpm_commit(dev, buf, 168, info, 3386 IRDMA_HMC_IW_OOISCFFL); 3387 } 3388 } 3389 3390 /* searching for the last object in HMC to find the size of the HMC area. */ 3391 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { 3392 if (info[i].base > max_base && info[i].cnt) { 3393 max_base = info[i].base; 3394 last_hmc_obj = i; 3395 } 3396 } 3397 3398 size = info[last_hmc_obj].cnt * info[last_hmc_obj].size + 3399 info[last_hmc_obj].base; 3400 3401 if (size & 0x1FFFFF) 3402 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */ 3403 else 3404 *sd = (u32)(size >> 21); 3405 3406 } 3407 3408 /** 3409 * irdma_sc_decode_fpm_query() - Decode a 64 bit value into max count and size 3410 * @buf: ptr to fpm query buffer 3411 * @buf_idx: index into buf 3412 * @obj_info: ptr to irdma_hmc_obj_info struct 3413 * @rsrc_idx: resource index into info 3414 * 3415 * Decode a 64 bit value from fpm query buffer into max count and size 3416 */ 3417 static u64 irdma_sc_decode_fpm_query(__le64 *buf, u32 buf_idx, 3418 struct irdma_hmc_obj_info *obj_info, 3419 u32 rsrc_idx) 3420 { 3421 u64 temp; 3422 u32 size; 3423 3424 get_64bit_val(buf, buf_idx, &temp); 3425 obj_info[rsrc_idx].max_cnt = (u32)temp; 3426 size = (u32)(temp >> 32); 3427 obj_info[rsrc_idx].size = BIT_ULL(size); 3428 3429 return temp; 3430 } 3431 3432 /** 3433 * irdma_sc_parse_fpm_query_buf() - parses fpm query buffer 3434 * @dev: ptr to shared code device 3435 * @buf: ptr to fpm query buffer 3436 * @hmc_info: ptr to irdma_hmc_obj_info struct 3437 * @hmc_fpm_misc: ptr to fpm data 3438 * 3439 * parses fpm query buffer and copy max_cnt and 3440 * size value of hmc objects in hmc_info 3441 */ 3442 static int irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf, 3443 struct irdma_hmc_info *hmc_info, 3444 struct irdma_hmc_fpm_misc *hmc_fpm_misc) 3445 { 3446 struct irdma_hmc_obj_info *obj_info; 3447 u8 ird_encoding; 3448 u64 temp; 3449 u32 size; 3450 u16 max_pe_sds; 3451 3452 obj_info = hmc_info->hmc_obj; 3453 3454 get_64bit_val(buf, 0, &temp); 3455 hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp); 3456 3457 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 3458 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS_GEN3, temp); 3459 else 3460 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp); 3461 3462 /* Reduce SD count for unprivleged functions by 1 to account for PBLE 3463 * backing page rounding 3464 */ 3465 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2 && 3466 (hmc_info->hmc_fn_id >= dev->hw_attrs.first_hw_vf_fpm_id || 3467 !dev->privileged)) 3468 max_pe_sds--; 3469 3470 hmc_fpm_misc->max_sds = max_pe_sds; 3471 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index; 3472 get_64bit_val(buf, 8, &temp); 3473 obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp); 3474 size = (u32)(temp >> 32); 3475 obj_info[IRDMA_HMC_IW_QP].size = BIT_ULL(size); 3476 3477 get_64bit_val(buf, 16, &temp); 3478 obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp); 3479 size = (u32)(temp >> 32); 3480 obj_info[IRDMA_HMC_IW_CQ].size = BIT_ULL(size); 3481 3482 irdma_sc_decode_fpm_query(buf, 24, obj_info, IRDMA_HMC_IW_SRQ); 3483 irdma_sc_decode_fpm_query(buf, 32, obj_info, IRDMA_HMC_IW_HTE); 3484 irdma_sc_decode_fpm_query(buf, 40, obj_info, IRDMA_HMC_IW_ARP); 3485 3486 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 3487 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 0; 3488 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 0; 3489 } else { 3490 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 8192; 3491 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 1; 3492 } 3493 3494 irdma_sc_decode_fpm_query(buf, 48, obj_info, IRDMA_HMC_IW_MR); 3495 irdma_sc_decode_fpm_query(buf, 56, obj_info, IRDMA_HMC_IW_XF); 3496 3497 get_64bit_val(buf, 64, &temp); 3498 obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp; 3499 obj_info[IRDMA_HMC_IW_XFFL].size = 4; 3500 hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp); 3501 if (obj_info[IRDMA_HMC_IW_XF].max_cnt && !hmc_fpm_misc->xf_block_size) 3502 return -EINVAL; 3503 3504 irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1); 3505 get_64bit_val(buf, 80, &temp); 3506 obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp; 3507 obj_info[IRDMA_HMC_IW_Q1FL].size = 4; 3508 3509 hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp); 3510 if (!hmc_fpm_misc->q1_block_size) 3511 return -EINVAL; 3512 3513 irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER); 3514 3515 get_64bit_val(buf, 112, &temp); 3516 obj_info[IRDMA_HMC_IW_PBLE].max_cnt = (u32)temp; 3517 obj_info[IRDMA_HMC_IW_PBLE].size = 8; 3518 3519 get_64bit_val(buf, 120, &temp); 3520 hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp); 3521 hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp); 3522 hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp); 3523 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, 3524 dev->feature_info[IRDMA_FTN_FLAGS])) { 3525 ird_encoding = (u8)FIELD_GET(IRDMA_QUERY_FPM_MAX_IRD, temp); 3526 hmc_fpm_misc->ird = 3527 irdma_sc_get_decoded_ird_size_gen_3(ird_encoding) / 2; 3528 dev->hw_attrs.max_hw_ird = hmc_fpm_misc->ird; 3529 dev->hw_attrs.max_hw_ord = hmc_fpm_misc->ird; 3530 } 3531 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 3532 return 0; 3533 irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC); 3534 irdma_sc_decode_fpm_query(buf, 104, obj_info, IRDMA_HMC_IW_FSIAV); 3535 irdma_sc_decode_fpm_query(buf, 128, obj_info, IRDMA_HMC_IW_RRF); 3536 3537 get_64bit_val(buf, 136, &temp); 3538 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp; 3539 obj_info[IRDMA_HMC_IW_RRFFL].size = 4; 3540 hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp); 3541 if (!hmc_fpm_misc->rrf_block_size && 3542 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt) 3543 return -EINVAL; 3544 3545 irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR); 3546 irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD); 3547 3548 if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) { 3549 irdma_sc_decode_fpm_query(buf, 160, obj_info, IRDMA_HMC_IW_OOISC); 3550 3551 get_64bit_val(buf, 168, &temp); 3552 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp; 3553 obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4; 3554 hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp); 3555 if (!hmc_fpm_misc->ooiscf_block_size && 3556 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt) 3557 return -EINVAL; 3558 } 3559 3560 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 3561 get_64bit_val(buf, 176, &temp); 3562 hmc_fpm_misc->loc_mem_pages = (u32)FIELD_GET(IRDMA_QUERY_FPM_LOC_MEM_PAGES, temp); 3563 if (!hmc_fpm_misc->loc_mem_pages) 3564 return -EINVAL; 3565 3566 get_64bit_val(buf, 184, &temp); 3567 if (temp) { 3568 hmc_fpm_misc->fw_scratch_buf0.size = temp; 3569 hmc_fpm_misc->fw_scratch_buf0.va = 3570 dma_alloc_coherent(dev->hw->device, 3571 hmc_fpm_misc->fw_scratch_buf0.size, 3572 &hmc_fpm_misc->fw_scratch_buf0.pa, 3573 GFP_KERNEL); 3574 3575 if (!hmc_fpm_misc->fw_scratch_buf0.va) { 3576 hmc_fpm_misc->fw_scratch_buf0.size = 0; 3577 return -ENOMEM; 3578 } 3579 } 3580 get_64bit_val(buf, 192, &temp); 3581 if (temp) { 3582 hmc_fpm_misc->fw_scratch_buf1.size = temp; 3583 hmc_fpm_misc->fw_scratch_buf1.va = 3584 dma_alloc_coherent(dev->hw->device, 3585 hmc_fpm_misc->fw_scratch_buf1.size, 3586 &hmc_fpm_misc->fw_scratch_buf1.pa, 3587 GFP_KERNEL); 3588 3589 if (!hmc_fpm_misc->fw_scratch_buf1.va) { 3590 hmc_fpm_misc->fw_scratch_buf1.size = 0; 3591 dma_free_coherent(dev->hw->device, 3592 hmc_fpm_misc->fw_scratch_buf0.size, 3593 hmc_fpm_misc->fw_scratch_buf0.va, 3594 hmc_fpm_misc->fw_scratch_buf0.pa); 3595 hmc_fpm_misc->fw_scratch_buf0.va = NULL; 3596 hmc_fpm_misc->fw_scratch_buf0.size = 0; 3597 return -ENOMEM; 3598 } 3599 } 3600 } 3601 3602 return 0; 3603 } 3604 3605 /** 3606 * irdma_sc_cqp_init - Initialize buffers for a control Queue Pair 3607 * @cqp: IWARP control queue pair pointer 3608 * @info: IWARP control queue pair init info pointer 3609 * 3610 * Initializes the object and context buffers for a control Queue Pair. 3611 */ 3612 int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp, 3613 struct irdma_cqp_init_info *info) 3614 { 3615 struct irdma_ooo_cqp_op *ooo_op; 3616 u32 num_ooo_ops; 3617 u8 hw_sq_size; 3618 3619 if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 || 3620 info->sq_size < IRDMA_CQP_SW_SQSIZE_4 || 3621 ((info->sq_size & (info->sq_size - 1)))) 3622 return -EINVAL; 3623 3624 hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size, 3625 IRDMA_QUEUE_TYPE_CQP); 3626 cqp->size = sizeof(*cqp); 3627 cqp->sq_size = info->sq_size; 3628 cqp->hw_sq_size = hw_sq_size; 3629 cqp->sq_base = info->sq; 3630 cqp->host_ctx = info->host_ctx; 3631 cqp->sq_pa = info->sq_pa; 3632 cqp->host_ctx_pa = info->host_ctx_pa; 3633 cqp->dev = info->dev; 3634 cqp->struct_ver = info->struct_ver; 3635 cqp->hw_maj_ver = info->hw_maj_ver; 3636 cqp->hw_min_ver = info->hw_min_ver; 3637 cqp->scratch_array = info->scratch_array; 3638 cqp->polarity = 0; 3639 cqp->en_datacenter_tcp = info->en_datacenter_tcp; 3640 cqp->ena_vf_count = info->ena_vf_count; 3641 cqp->hmc_profile = info->hmc_profile; 3642 cqp->ceqs_per_vf = info->ceqs_per_vf; 3643 cqp->disable_packed = info->disable_packed; 3644 cqp->rocev2_rto_policy = info->rocev2_rto_policy; 3645 cqp->protocol_used = info->protocol_used; 3646 memcpy(&cqp->dcqcn_params, &info->dcqcn_params, sizeof(cqp->dcqcn_params)); 3647 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 3648 cqp->ooisc_blksize = info->ooisc_blksize; 3649 cqp->rrsp_blksize = info->rrsp_blksize; 3650 cqp->q1_blksize = info->q1_blksize; 3651 cqp->xmit_blksize = info->xmit_blksize; 3652 cqp->blksizes_valid = info->blksizes_valid; 3653 cqp->ts_shift = info->ts_shift; 3654 cqp->ts_override = info->ts_override; 3655 cqp->en_fine_grained_timers = info->en_fine_grained_timers; 3656 cqp->pe_en_vf_cnt = info->pe_en_vf_cnt; 3657 cqp->ooo_op_array = info->ooo_op_array; 3658 /* initialize the OOO lists */ 3659 INIT_LIST_HEAD(&cqp->ooo_avail); 3660 INIT_LIST_HEAD(&cqp->ooo_pnd); 3661 if (cqp->ooo_op_array) { 3662 /* Populate avail list entries */ 3663 for (num_ooo_ops = 0, ooo_op = info->ooo_op_array; 3664 num_ooo_ops < cqp->sq_size; 3665 num_ooo_ops++, ooo_op++) 3666 list_add(&ooo_op->list_entry, &cqp->ooo_avail); 3667 } 3668 } 3669 info->dev->cqp = cqp; 3670 3671 IRDMA_RING_INIT(cqp->sq_ring, cqp->sq_size); 3672 cqp->last_def_cmpl_ticket = 0; 3673 cqp->sw_def_cmpl_ticket = 0; 3674 cqp->requested_ops = 0; 3675 atomic64_set(&cqp->completed_ops, 0); 3676 /* for the cqp commands backlog. */ 3677 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); 3678 3679 writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]); 3680 if (cqp->dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) { 3681 writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]); 3682 writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3683 } 3684 3685 ibdev_dbg(to_ibdev(cqp->dev), 3686 "WQE: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%p] cqp[%p] polarity[x%04x]\n", 3687 cqp->sq_size, cqp->hw_sq_size, cqp->sq_base, 3688 (u64 *)(uintptr_t)cqp->sq_pa, cqp, cqp->polarity); 3689 return 0; 3690 } 3691 3692 /** 3693 * irdma_sc_cqp_create - create cqp during bringup 3694 * @cqp: struct for cqp hw 3695 * @maj_err: If error, major err number 3696 * @min_err: If error, minor err number 3697 */ 3698 int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err) 3699 { 3700 u64 temp; 3701 u8 hw_rev; 3702 u32 cnt = 0, p1, p2, val = 0, err_code; 3703 int ret_code; 3704 3705 hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev; 3706 cqp->sdbuf.size = ALIGN(IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size, 3707 IRDMA_SD_BUF_ALIGNMENT); 3708 cqp->sdbuf.va = dma_alloc_coherent(cqp->dev->hw->device, 3709 cqp->sdbuf.size, &cqp->sdbuf.pa, 3710 GFP_KERNEL); 3711 if (!cqp->sdbuf.va) 3712 return -ENOMEM; 3713 3714 spin_lock_init(&cqp->dev->cqp_lock); 3715 spin_lock_init(&cqp->ooo_list_lock); 3716 3717 temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) | 3718 FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) | 3719 FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) | 3720 FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf); 3721 if (hw_rev >= IRDMA_GEN_2) { 3722 temp |= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY, 3723 cqp->rocev2_rto_policy) | 3724 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED, 3725 cqp->protocol_used); 3726 } 3727 if (hw_rev >= IRDMA_GEN_3) 3728 temp |= FIELD_PREP(IRDMA_CQPHC_EN_FINE_GRAINED_TIMERS, 3729 cqp->en_fine_grained_timers); 3730 3731 set_64bit_val(cqp->host_ctx, 0, temp); 3732 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa); 3733 3734 temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) | 3735 FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile); 3736 3737 if (hw_rev >= IRDMA_GEN_3) 3738 temp |= FIELD_PREP(IRDMA_CQPHC_OOISC_BLKSIZE, 3739 cqp->ooisc_blksize) | 3740 FIELD_PREP(IRDMA_CQPHC_RRSP_BLKSIZE, 3741 cqp->rrsp_blksize) | 3742 FIELD_PREP(IRDMA_CQPHC_Q1_BLKSIZE, cqp->q1_blksize) | 3743 FIELD_PREP(IRDMA_CQPHC_XMIT_BLKSIZE, 3744 cqp->xmit_blksize) | 3745 FIELD_PREP(IRDMA_CQPHC_BLKSIZES_VALID, 3746 cqp->blksizes_valid) | 3747 FIELD_PREP(IRDMA_CQPHC_TIMESTAMP_OVERRIDE, 3748 cqp->ts_override) | 3749 FIELD_PREP(IRDMA_CQPHC_TS_SHIFT, cqp->ts_shift); 3750 set_64bit_val(cqp->host_ctx, 16, temp); 3751 set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp); 3752 temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) | 3753 FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver); 3754 if (hw_rev >= IRDMA_GEN_2) { 3755 temp |= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) | 3756 FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor); 3757 } 3758 set_64bit_val(cqp->host_ctx, 32, temp); 3759 set_64bit_val(cqp->host_ctx, 40, 0); 3760 temp = 0; 3761 if (hw_rev >= IRDMA_GEN_2) { 3762 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) | 3763 FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) | 3764 FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor); 3765 } 3766 set_64bit_val(cqp->host_ctx, 48, temp); 3767 temp = 0; 3768 if (hw_rev >= IRDMA_GEN_2) { 3769 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) | 3770 FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) | 3771 FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) | 3772 FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod); 3773 } 3774 set_64bit_val(cqp->host_ctx, 56, temp); 3775 print_hex_dump_debug("WQE: CQP_HOST_CTX WQE", DUMP_PREFIX_OFFSET, 16, 3776 8, cqp->host_ctx, IRDMA_CQP_CTX_SIZE * 8, false); 3777 p1 = cqp->host_ctx_pa >> 32; 3778 p2 = (u32)cqp->host_ctx_pa; 3779 3780 writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3781 writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3782 3783 do { 3784 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3785 ret_code = -ETIMEDOUT; 3786 goto err; 3787 } 3788 udelay(cqp->dev->hw_attrs.max_sleep_count); 3789 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3790 } while (!val); 3791 3792 if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) { 3793 ret_code = -EOPNOTSUPP; 3794 goto err; 3795 } 3796 3797 cqp->process_cqp_sds = irdma_update_sds_noccq; 3798 return 0; 3799 3800 err: 3801 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3802 cqp->sdbuf.va, cqp->sdbuf.pa); 3803 cqp->sdbuf.va = NULL; 3804 err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3805 *min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code); 3806 *maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code); 3807 return ret_code; 3808 } 3809 3810 /** 3811 * irdma_sc_cqp_post_sq - post of cqp's sq 3812 * @cqp: struct for cqp hw 3813 */ 3814 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp) 3815 { 3816 writel(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db); 3817 3818 ibdev_dbg(to_ibdev(cqp->dev), 3819 "WQE: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 3820 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 3821 } 3822 3823 /** 3824 * irdma_sc_cqp_get_next_send_wqe_idx - get next wqe on cqp sq 3825 * and pass back index 3826 * @cqp: CQP HW structure 3827 * @scratch: private data for CQP WQE 3828 * @wqe_idx: WQE index of CQP SQ 3829 */ 3830 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch, 3831 u32 *wqe_idx) 3832 { 3833 __le64 *wqe = NULL; 3834 int ret_code; 3835 3836 if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) { 3837 ibdev_dbg(to_ibdev(cqp->dev), 3838 "WQE: CQP SQ is full, head 0x%x tail 0x%x size 0x%x\n", 3839 cqp->sq_ring.head, cqp->sq_ring.tail, 3840 cqp->sq_ring.size); 3841 return NULL; 3842 } 3843 IRDMA_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code); 3844 if (ret_code) 3845 return NULL; 3846 3847 cqp->requested_ops++; 3848 if (!*wqe_idx) 3849 cqp->polarity = !cqp->polarity; 3850 wqe = cqp->sq_base[*wqe_idx].elem; 3851 cqp->scratch_array[*wqe_idx] = scratch; 3852 IRDMA_CQP_INIT_WQE(wqe); 3853 3854 return wqe; 3855 } 3856 3857 /** 3858 * irdma_sc_cqp_destroy - destroy cqp during close 3859 * @cqp: struct for cqp hw 3860 */ 3861 int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp) 3862 { 3863 u32 cnt = 0, val; 3864 int ret_code = 0; 3865 3866 writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3867 writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3868 do { 3869 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3870 ret_code = -ETIMEDOUT; 3871 break; 3872 } 3873 udelay(cqp->dev->hw_attrs.max_sleep_count); 3874 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3875 } while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE)); 3876 3877 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3878 cqp->sdbuf.va, cqp->sdbuf.pa); 3879 cqp->sdbuf.va = NULL; 3880 return ret_code; 3881 } 3882 3883 /** 3884 * irdma_sc_ccq_arm - enable intr for control cq 3885 * @ccq: ccq sc struct 3886 */ 3887 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq) 3888 { 3889 unsigned long flags; 3890 u64 temp_val; 3891 u16 sw_cq_sel; 3892 u8 arm_next_se; 3893 u8 arm_seq_num; 3894 3895 spin_lock_irqsave(&ccq->dev->cqp_lock, flags); 3896 get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val); 3897 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 3898 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 3899 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 3900 arm_seq_num++; 3901 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 3902 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 3903 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 3904 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1); 3905 set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val); 3906 spin_unlock_irqrestore(&ccq->dev->cqp_lock, flags); 3907 3908 writel(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db); 3909 } 3910 3911 /** 3912 * irdma_sc_process_def_cmpl - process deferred or pending completion 3913 * @cqp: CQP sc struct 3914 * @info: CQP CQE info 3915 * @wqe_idx: CQP WQE descriptor index 3916 * @def_info: deferred op ticket value or out-of-order completion id 3917 * @def_cmpl: true for deferred completion, false for pending (RCA) 3918 */ 3919 static void irdma_sc_process_def_cmpl(struct irdma_sc_cqp *cqp, 3920 struct irdma_ccq_cqe_info *info, 3921 u32 wqe_idx, u32 def_info, bool def_cmpl) 3922 { 3923 struct irdma_ooo_cqp_op *ooo_op; 3924 unsigned long flags; 3925 3926 /* Deferred and out-of-order completions share the same list of pending 3927 * completions. Since the list can be also accessed from AE handler, 3928 * it must be protected by a lock. 3929 */ 3930 spin_lock_irqsave(&cqp->ooo_list_lock, flags); 3931 3932 /* For deferred completions bump up SW completion ticket value. */ 3933 if (def_cmpl) { 3934 cqp->last_def_cmpl_ticket = def_info; 3935 cqp->sw_def_cmpl_ticket++; 3936 } 3937 if (!list_empty(&cqp->ooo_avail)) { 3938 ooo_op = (struct irdma_ooo_cqp_op *) 3939 list_entry(cqp->ooo_avail.next, 3940 struct irdma_ooo_cqp_op, list_entry); 3941 3942 list_del(&ooo_op->list_entry); 3943 ooo_op->scratch = info->scratch; 3944 ooo_op->def_info = def_info; 3945 ooo_op->sw_def_info = cqp->sw_def_cmpl_ticket; 3946 ooo_op->deferred = def_cmpl; 3947 ooo_op->wqe_idx = wqe_idx; 3948 /* Pending completions must be chronologically ordered, 3949 * so adding at the end of list. 3950 */ 3951 list_add_tail(&ooo_op->list_entry, &cqp->ooo_pnd); 3952 } 3953 spin_unlock_irqrestore(&cqp->ooo_list_lock, flags); 3954 3955 info->pending = true; 3956 } 3957 3958 /** 3959 * irdma_sc_process_ooo_cmpl - process out-of-order (final) completion 3960 * @cqp: CQP sc struct 3961 * @info: CQP CQE info 3962 * @def_info: out-of-order completion id 3963 */ 3964 static void irdma_sc_process_ooo_cmpl(struct irdma_sc_cqp *cqp, 3965 struct irdma_ccq_cqe_info *info, 3966 u32 def_info) 3967 { 3968 struct irdma_ooo_cqp_op *ooo_op_tmp; 3969 struct irdma_ooo_cqp_op *ooo_op; 3970 unsigned long flags; 3971 3972 info->scratch = 0; 3973 3974 spin_lock_irqsave(&cqp->ooo_list_lock, flags); 3975 list_for_each_entry_safe(ooo_op, ooo_op_tmp, &cqp->ooo_pnd, 3976 list_entry) { 3977 if (!ooo_op->deferred && ooo_op->def_info == def_info) { 3978 list_del(&ooo_op->list_entry); 3979 info->scratch = ooo_op->scratch; 3980 list_add(&ooo_op->list_entry, &cqp->ooo_avail); 3981 break; 3982 } 3983 } 3984 spin_unlock_irqrestore(&cqp->ooo_list_lock, flags); 3985 3986 if (!info->scratch) 3987 ibdev_dbg(to_ibdev(cqp->dev), 3988 "CQP: DEBUG_FW_OOO out-of-order completion with unknown def_info = 0x%x\n", 3989 def_info); 3990 } 3991 3992 /** 3993 * irdma_sc_ccq_get_cqe_info - get ccq's cq entry 3994 * @ccq: ccq sc struct 3995 * @info: completion q entry to return 3996 */ 3997 int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq, 3998 struct irdma_ccq_cqe_info *info) 3999 { 4000 u32 def_info; 4001 bool def_cmpl = false; 4002 bool pend_cmpl = false; 4003 bool ooo_final_cmpl = false; 4004 u64 qp_ctx, temp, temp1; 4005 __le64 *cqe; 4006 struct irdma_sc_cqp *cqp; 4007 u32 wqe_idx; 4008 u32 error; 4009 u8 polarity; 4010 int ret_code = 0; 4011 unsigned long flags; 4012 4013 if (ccq->cq_uk.avoid_mem_cflct) 4014 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk); 4015 else 4016 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk); 4017 4018 get_64bit_val(cqe, 24, &temp); 4019 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp); 4020 if (polarity != ccq->cq_uk.polarity) 4021 return -ENOENT; 4022 4023 /* Ensure CEQE contents are read after valid bit is checked */ 4024 dma_rmb(); 4025 4026 get_64bit_val(cqe, 8, &qp_ctx); 4027 cqp = (struct irdma_sc_cqp *)(unsigned long)qp_ctx; 4028 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp); 4029 info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR; 4030 info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp); 4031 if (info->error) { 4032 info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp); 4033 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 4034 ibdev_dbg(to_ibdev(cqp->dev), 4035 "CQP: CQPERRCODES error_code[x%08X]\n", error); 4036 } 4037 4038 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp); 4039 info->scratch = cqp->scratch_array[wqe_idx]; 4040 4041 get_64bit_val(cqe, 16, &temp1); 4042 info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1); 4043 if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 4044 def_cmpl = info->maj_err_code == IRDMA_CQPSQ_MAJ_NO_ERROR && 4045 info->min_err_code == IRDMA_CQPSQ_MIN_DEF_CMPL; 4046 def_info = (u32)FIELD_GET(IRDMA_CCQ_DEFINFO, temp1); 4047 4048 pend_cmpl = info->maj_err_code == IRDMA_CQPSQ_MAJ_NO_ERROR && 4049 info->min_err_code == IRDMA_CQPSQ_MIN_OOO_CMPL; 4050 4051 ooo_final_cmpl = (bool)FIELD_GET(IRDMA_OOO_CMPL, temp); 4052 4053 if (def_cmpl || pend_cmpl || ooo_final_cmpl) { 4054 if (ooo_final_cmpl) 4055 irdma_sc_process_ooo_cmpl(cqp, info, def_info); 4056 else 4057 irdma_sc_process_def_cmpl(cqp, info, wqe_idx, 4058 def_info, def_cmpl); 4059 } 4060 } 4061 4062 get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1); 4063 info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1); 4064 info->cqp = cqp; 4065 4066 /* move the head for cq */ 4067 IRDMA_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code); 4068 if (!IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)) 4069 ccq->cq_uk.polarity ^= 1; 4070 4071 /* update cq tail in cq shadow memory also */ 4072 IRDMA_RING_MOVE_TAIL(ccq->cq_uk.cq_ring); 4073 set_64bit_val(ccq->cq_uk.shadow_area, 0, 4074 IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)); 4075 4076 dma_wmb(); /* make sure shadow area is updated before moving tail */ 4077 4078 spin_lock_irqsave(&cqp->dev->cqp_lock, flags); 4079 if (!ooo_final_cmpl) 4080 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 4081 spin_unlock_irqrestore(&cqp->dev->cqp_lock, flags); 4082 4083 /* Do not increment completed_ops counter on pending or deferred 4084 * completions. 4085 */ 4086 if (pend_cmpl || def_cmpl) 4087 return ret_code; 4088 atomic64_inc(&cqp->completed_ops); 4089 4090 return ret_code; 4091 } 4092 4093 /** 4094 * irdma_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ 4095 * @cqp: struct for cqp hw 4096 * @op_code: cqp opcode for completion 4097 * @compl_info: completion q entry to return 4098 */ 4099 int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code, 4100 struct irdma_ccq_cqe_info *compl_info) 4101 { 4102 struct irdma_ccq_cqe_info info = {}; 4103 struct irdma_sc_cq *ccq; 4104 int ret_code = 0; 4105 u32 cnt = 0; 4106 4107 ccq = cqp->dev->ccq; 4108 while (1) { 4109 if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count) 4110 return -ETIMEDOUT; 4111 4112 if (irdma_sc_ccq_get_cqe_info(ccq, &info)) { 4113 udelay(cqp->dev->hw_attrs.max_sleep_count); 4114 continue; 4115 } 4116 if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) { 4117 ret_code = -EIO; 4118 break; 4119 } 4120 /* make sure op code matches*/ 4121 if (op_code == info.op_code) 4122 break; 4123 ibdev_dbg(to_ibdev(cqp->dev), 4124 "WQE: opcode mismatch for my op code 0x%x, returned opcode %x\n", 4125 op_code, info.op_code); 4126 } 4127 4128 if (compl_info) 4129 memcpy(compl_info, &info, sizeof(*compl_info)); 4130 4131 return ret_code; 4132 } 4133 4134 /** 4135 * irdma_sc_manage_hmc_pm_func_table - manage of function table 4136 * @cqp: struct for cqp hw 4137 * @scratch: u64 saved to be used during cqp completion 4138 * @info: info for the manage function table operation 4139 * @post_sq: flag for cqp db to ring 4140 */ 4141 static int irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp, 4142 struct irdma_hmc_fcn_info *info, 4143 u64 scratch, bool post_sq) 4144 { 4145 __le64 *wqe; 4146 u64 hdr; 4147 4148 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4149 if (!wqe) 4150 return -ENOMEM; 4151 4152 set_64bit_val(wqe, 0, 0); 4153 set_64bit_val(wqe, 8, 0); 4154 set_64bit_val(wqe, 16, 0); 4155 set_64bit_val(wqe, 32, 0); 4156 set_64bit_val(wqe, 40, 0); 4157 set_64bit_val(wqe, 48, 0); 4158 set_64bit_val(wqe, 56, 0); 4159 4160 hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) | 4161 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 4162 IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) | 4163 FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) | 4164 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4165 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4166 4167 set_64bit_val(wqe, 24, hdr); 4168 4169 print_hex_dump_debug("WQE: MANAGE_HMC_PM_FUNC_TABLE WQE", 4170 DUMP_PREFIX_OFFSET, 16, 8, wqe, 4171 IRDMA_CQP_WQE_SIZE * 8, false); 4172 if (post_sq) 4173 irdma_sc_cqp_post_sq(cqp); 4174 4175 return 0; 4176 } 4177 4178 /** 4179 * irdma_sc_commit_fpm_val_done - wait for cqp eqe completion 4180 * for fpm commit 4181 * @cqp: struct for cqp hw 4182 */ 4183 static int irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp) 4184 { 4185 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL, 4186 NULL); 4187 } 4188 4189 /** 4190 * irdma_sc_commit_fpm_val - cqp wqe for commit fpm values 4191 * @cqp: struct for cqp hw 4192 * @scratch: u64 saved to be used during cqp completion 4193 * @hmc_fn_id: hmc function id 4194 * @commit_fpm_mem: Memory for fpm values 4195 * @post_sq: flag for cqp db to ring 4196 * @wait_type: poll ccq or cqp registers for cqp completion 4197 */ 4198 static int irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, 4199 u8 hmc_fn_id, 4200 struct irdma_dma_mem *commit_fpm_mem, 4201 bool post_sq, u8 wait_type) 4202 { 4203 __le64 *wqe; 4204 u64 hdr; 4205 u32 tail, val, error; 4206 int ret_code = 0; 4207 4208 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4209 if (!wqe) 4210 return -ENOMEM; 4211 4212 set_64bit_val(wqe, 16, hmc_fn_id); 4213 set_64bit_val(wqe, 32, commit_fpm_mem->pa); 4214 4215 hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) | 4216 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) | 4217 FIELD_PREP(IRDMA_CQPSQ_CFPM_FW_SCRATCH_BUF_PRESENT, 4218 cqp->dev->hmc_fpm_misc.fw_scratch_buf0.va != NULL) | 4219 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4220 4221 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4222 4223 set_64bit_val(wqe, 24, hdr); 4224 4225 print_hex_dump_debug("WQE: COMMIT_FPM_VAL WQE", DUMP_PREFIX_OFFSET, 4226 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4227 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4228 4229 if (post_sq) { 4230 irdma_sc_cqp_post_sq(cqp); 4231 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 4232 ret_code = irdma_cqp_poll_registers(cqp, tail, 4233 cqp->dev->hw_attrs.max_done_count); 4234 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 4235 ret_code = irdma_sc_commit_fpm_val_done(cqp); 4236 } 4237 4238 return ret_code; 4239 } 4240 4241 /** 4242 * irdma_sc_query_fpm_val_done - poll for cqp wqe completion for 4243 * query fpm 4244 * @cqp: struct for cqp hw 4245 */ 4246 static int irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp) 4247 { 4248 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL, 4249 NULL); 4250 } 4251 4252 /** 4253 * irdma_sc_query_fpm_val - cqp wqe query fpm values 4254 * @cqp: struct for cqp hw 4255 * @scratch: u64 saved to be used during cqp completion 4256 * @hmc_fn_id: hmc function id 4257 * @query_fpm_mem: memory for return fpm values 4258 * @post_sq: flag for cqp db to ring 4259 * @wait_type: poll ccq or cqp registers for cqp completion 4260 */ 4261 static int irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, 4262 u8 hmc_fn_id, 4263 struct irdma_dma_mem *query_fpm_mem, 4264 bool post_sq, u8 wait_type) 4265 { 4266 __le64 *wqe; 4267 u64 hdr; 4268 u32 tail, val, error; 4269 int ret_code = 0; 4270 4271 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4272 if (!wqe) 4273 return -ENOMEM; 4274 4275 set_64bit_val(wqe, 16, hmc_fn_id); 4276 set_64bit_val(wqe, 32, query_fpm_mem->pa); 4277 4278 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) | 4279 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4280 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4281 4282 set_64bit_val(wqe, 24, hdr); 4283 4284 print_hex_dump_debug("WQE: QUERY_FPM WQE", DUMP_PREFIX_OFFSET, 16, 8, 4285 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4286 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4287 4288 if (post_sq) { 4289 irdma_sc_cqp_post_sq(cqp); 4290 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 4291 ret_code = irdma_cqp_poll_registers(cqp, tail, 4292 cqp->dev->hw_attrs.max_done_count); 4293 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 4294 ret_code = irdma_sc_query_fpm_val_done(cqp); 4295 } 4296 4297 return ret_code; 4298 } 4299 4300 /** 4301 * irdma_sc_ceq_init - initialize ceq 4302 * @ceq: ceq sc structure 4303 * @info: ceq initialization info 4304 */ 4305 int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq, 4306 struct irdma_ceq_init_info *info) 4307 { 4308 u32 pble_obj_cnt; 4309 4310 if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size || 4311 info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size) 4312 return -EINVAL; 4313 4314 if (info->ceq_id >= info->dev->hmc_fpm_misc.max_ceqs) 4315 return -EINVAL; 4316 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4317 4318 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4319 return -EINVAL; 4320 4321 ceq->size = sizeof(*ceq); 4322 ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base; 4323 ceq->ceq_id = info->ceq_id; 4324 ceq->dev = info->dev; 4325 ceq->elem_cnt = info->elem_cnt; 4326 ceq->ceq_elem_pa = info->ceqe_pa; 4327 ceq->virtual_map = info->virtual_map; 4328 ceq->itr_no_expire = info->itr_no_expire; 4329 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0); 4330 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0); 4331 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL); 4332 ceq->tph_en = info->tph_en; 4333 ceq->tph_val = info->tph_val; 4334 ceq->vsi_idx = info->vsi_idx; 4335 ceq->polarity = 1; 4336 IRDMA_RING_INIT(ceq->ceq_ring, ceq->elem_cnt); 4337 ceq->dev->ceq[info->ceq_id] = ceq; 4338 4339 return 0; 4340 } 4341 4342 /** 4343 * irdma_sc_ceq_create - create ceq wqe 4344 * @ceq: ceq sc structure 4345 * @scratch: u64 saved to be used during cqp completion 4346 * @post_sq: flag for cqp db to ring 4347 */ 4348 4349 static int irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch, 4350 bool post_sq) 4351 { 4352 struct irdma_sc_cqp *cqp; 4353 __le64 *wqe; 4354 u64 hdr; 4355 4356 cqp = ceq->dev->cqp; 4357 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4358 if (!wqe) 4359 return -ENOMEM; 4360 set_64bit_val(wqe, 16, ceq->elem_cnt); 4361 set_64bit_val(wqe, 32, 4362 (ceq->virtual_map ? 0 : ceq->ceq_elem_pa)); 4363 set_64bit_val(wqe, 48, 4364 (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0)); 4365 set_64bit_val(wqe, 56, 4366 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) | 4367 FIELD_PREP(IRDMA_CQPSQ_PASID, ceq->pasid) | 4368 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi_idx)); 4369 hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) | 4370 FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID_HIGH, ceq->ceq_id >> 10) | 4371 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) | 4372 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 4373 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 4374 FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) | 4375 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 4376 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, ceq->pasid_valid) | 4377 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4378 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4379 4380 set_64bit_val(wqe, 24, hdr); 4381 4382 print_hex_dump_debug("WQE: CEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 4383 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4384 if (post_sq) 4385 irdma_sc_cqp_post_sq(cqp); 4386 4387 return 0; 4388 } 4389 4390 /** 4391 * irdma_sc_cceq_create_done - poll for control ceq wqe to complete 4392 * @ceq: ceq sc structure 4393 */ 4394 static int irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq) 4395 { 4396 struct irdma_sc_cqp *cqp; 4397 4398 cqp = ceq->dev->cqp; 4399 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CEQ, 4400 NULL); 4401 } 4402 4403 /** 4404 * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete 4405 * @ceq: ceq sc structure 4406 */ 4407 int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq) 4408 { 4409 struct irdma_sc_cqp *cqp; 4410 4411 cqp = ceq->dev->cqp; 4412 cqp->process_cqp_sds = irdma_update_sds_noccq; 4413 4414 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_DESTROY_CEQ, 4415 NULL); 4416 } 4417 4418 /** 4419 * irdma_sc_cceq_create - create cceq 4420 * @ceq: ceq sc structure 4421 * @scratch: u64 saved to be used during cqp completion 4422 */ 4423 int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch) 4424 { 4425 int ret_code; 4426 struct irdma_sc_dev *dev = ceq->dev; 4427 4428 dev->ccq->vsi_idx = ceq->vsi_idx; 4429 4430 ret_code = irdma_sc_ceq_create(ceq, scratch, true); 4431 if (!ret_code) 4432 return irdma_sc_cceq_create_done(ceq); 4433 4434 return ret_code; 4435 } 4436 4437 /** 4438 * irdma_sc_ceq_destroy - destroy ceq 4439 * @ceq: ceq sc structure 4440 * @scratch: u64 saved to be used during cqp completion 4441 * @post_sq: flag for cqp db to ring 4442 */ 4443 int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq) 4444 { 4445 struct irdma_sc_cqp *cqp; 4446 __le64 *wqe; 4447 u64 hdr; 4448 4449 cqp = ceq->dev->cqp; 4450 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4451 if (!wqe) 4452 return -ENOMEM; 4453 4454 set_64bit_val(wqe, 16, ceq->elem_cnt); 4455 set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx); 4456 set_64bit_val(wqe, 56, 4457 FIELD_PREP(IRDMA_CQPSQ_PASID, ceq->pasid)); 4458 hdr = ceq->ceq_id | 4459 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) | 4460 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 4461 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 4462 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 4463 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, ceq->pasid_valid) | 4464 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4465 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4466 4467 set_64bit_val(wqe, 24, hdr); 4468 4469 print_hex_dump_debug("WQE: CEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 4470 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4471 if (post_sq) 4472 irdma_sc_cqp_post_sq(cqp); 4473 4474 return 0; 4475 } 4476 4477 /** 4478 * irdma_sc_process_ceq - process ceq 4479 * @dev: sc device struct 4480 * @ceq: ceq sc structure 4481 * @cq_idx: Pointer to a CQ ID that will be populated. 4482 * 4483 * It is expected caller serializes this function with cleanup_ceqes() 4484 * because these functions manipulate the same ceq 4485 * 4486 * Return: True if cq_idx has been populated with a CQ ID. 4487 */ 4488 bool irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq, 4489 u32 *cq_idx) 4490 { 4491 u64 temp; 4492 __le64 *ceqe; 4493 u8 polarity; 4494 4495 do { 4496 ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq); 4497 get_64bit_val(ceqe, 0, &temp); 4498 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 4499 if (polarity != ceq->polarity) 4500 return false; 4501 4502 /* Truncate. Discard valid bit which is MSb of temp. */ 4503 *cq_idx = temp; 4504 if (*cq_idx >= dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt) 4505 *cq_idx = IRDMA_INVALID_CQ_IDX; 4506 4507 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); 4508 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) 4509 ceq->polarity ^= 1; 4510 } while (*cq_idx == IRDMA_INVALID_CQ_IDX); 4511 4512 return true; 4513 } 4514 4515 /** 4516 * irdma_sc_cleanup_ceqes - clear the valid ceqes ctx matching the cq 4517 * @cq: cq for which the ceqes need to be cleaned up 4518 * @ceq: ceq ptr 4519 * 4520 * The function is called after the cq is destroyed to cleanup 4521 * its pending ceqe entries. It is expected caller serializes this 4522 * function with process_ceq() in interrupt context. 4523 */ 4524 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq) 4525 { 4526 u8 ceq_polarity = ceq->polarity; 4527 __le64 *ceqe; 4528 u8 polarity; 4529 u32 cq_idx; 4530 u64 temp; 4531 int next; 4532 u32 i; 4533 4534 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, 0); 4535 4536 for (i = 1; i <= IRDMA_RING_SIZE(*ceq); i++) { 4537 ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next); 4538 4539 get_64bit_val(ceqe, 0, &temp); 4540 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 4541 if (polarity != ceq_polarity) 4542 return; 4543 4544 cq_idx = temp; 4545 if (cq_idx == cq->cq_uk.cq_id) 4546 set_64bit_val(ceqe, 0, (temp & IRDMA_CEQE_VALID) | 4547 IRDMA_INVALID_CQ_IDX); 4548 4549 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i); 4550 if (!next) 4551 ceq_polarity ^= 1; 4552 } 4553 } 4554 4555 /** 4556 * irdma_sc_aeq_init - initialize aeq 4557 * @aeq: aeq structure ptr 4558 * @info: aeq initialization info 4559 */ 4560 int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, 4561 struct irdma_aeq_init_info *info) 4562 { 4563 u32 pble_obj_cnt; 4564 4565 if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size || 4566 info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size) 4567 return -EINVAL; 4568 4569 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4570 4571 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4572 return -EINVAL; 4573 4574 aeq->size = sizeof(*aeq); 4575 aeq->polarity = 1; 4576 aeq->aeqe_base = (struct irdma_sc_aeqe *)info->aeqe_base; 4577 aeq->dev = info->dev; 4578 aeq->elem_cnt = info->elem_cnt; 4579 aeq->aeq_elem_pa = info->aeq_elem_pa; 4580 IRDMA_RING_INIT(aeq->aeq_ring, aeq->elem_cnt); 4581 aeq->virtual_map = info->virtual_map; 4582 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL); 4583 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0); 4584 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0); 4585 aeq->msix_idx = info->msix_idx; 4586 info->dev->aeq = aeq; 4587 4588 return 0; 4589 } 4590 4591 /** 4592 * irdma_sc_aeq_create - create aeq 4593 * @aeq: aeq structure ptr 4594 * @scratch: u64 saved to be used during cqp completion 4595 * @post_sq: flag for cqp db to ring 4596 */ 4597 static int irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, u64 scratch, 4598 bool post_sq) 4599 { 4600 __le64 *wqe; 4601 struct irdma_sc_cqp *cqp; 4602 u64 hdr; 4603 4604 cqp = aeq->dev->cqp; 4605 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4606 if (!wqe) 4607 return -ENOMEM; 4608 set_64bit_val(wqe, 16, aeq->elem_cnt); 4609 set_64bit_val(wqe, 32, 4610 (aeq->virtual_map ? 0 : aeq->aeq_elem_pa)); 4611 set_64bit_val(wqe, 48, 4612 (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0)); 4613 set_64bit_val(wqe, 56, 4614 FIELD_PREP(IRDMA_CQPSQ_PASID, aeq->pasid)); 4615 4616 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) | 4617 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 4618 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 4619 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, aeq->pasid_valid) | 4620 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4621 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4622 4623 set_64bit_val(wqe, 24, hdr); 4624 4625 print_hex_dump_debug("WQE: AEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 4626 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4627 if (post_sq) 4628 irdma_sc_cqp_post_sq(cqp); 4629 4630 return 0; 4631 } 4632 4633 /** 4634 * irdma_sc_aeq_destroy - destroy aeq during close 4635 * @aeq: aeq structure ptr 4636 * @scratch: u64 saved to be used during cqp completion 4637 * @post_sq: flag for cqp db to ring 4638 */ 4639 static int irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch, 4640 bool post_sq) 4641 { 4642 __le64 *wqe; 4643 struct irdma_sc_cqp *cqp; 4644 struct irdma_sc_dev *dev; 4645 u64 hdr; 4646 4647 dev = aeq->dev; 4648 4649 if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) 4650 writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 4651 4652 cqp = dev->cqp; 4653 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4654 if (!wqe) 4655 return -ENOMEM; 4656 set_64bit_val(wqe, 16, aeq->elem_cnt); 4657 set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx); 4658 set_64bit_val(wqe, 56, 4659 FIELD_PREP(IRDMA_CQPSQ_PASID, aeq->pasid)); 4660 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) | 4661 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 4662 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 4663 FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, aeq->pasid_valid) | 4664 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4665 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4666 4667 set_64bit_val(wqe, 24, hdr); 4668 4669 print_hex_dump_debug("WQE: AEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 4670 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4671 if (post_sq) 4672 irdma_sc_cqp_post_sq(cqp); 4673 return 0; 4674 } 4675 4676 /** 4677 * irdma_sc_get_next_aeqe - get next aeq entry 4678 * @aeq: aeq structure ptr 4679 * @info: aeqe info to be returned 4680 */ 4681 int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, 4682 struct irdma_aeqe_info *info) 4683 { 4684 u64 temp, compl_ctx; 4685 __le64 *aeqe; 4686 u8 ae_src; 4687 u8 polarity; 4688 4689 aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq); 4690 get_64bit_val(aeqe, 8, &temp); 4691 polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp); 4692 4693 if (aeq->polarity != polarity) 4694 return -ENOENT; 4695 4696 /* Ensure AEQE contents are read after valid bit is checked */ 4697 dma_rmb(); 4698 4699 get_64bit_val(aeqe, 0, &compl_ctx); 4700 4701 print_hex_dump_debug("WQE: AEQ_ENTRY WQE", DUMP_PREFIX_OFFSET, 16, 8, 4702 aeqe, 16, false); 4703 4704 if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 4705 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC_GEN_3, temp); 4706 info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX_GEN_3, 4707 temp); 4708 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_GEN_3, temp); 4709 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE_GEN_3, temp); 4710 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE_GEN_3, compl_ctx); 4711 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE_GEN_3, temp); 4712 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA_GEN_3, compl_ctx); 4713 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW_GEN_3, temp); 4714 info->compl_ctx = FIELD_GET(IRDMA_AEQE_CMPL_CTXT, compl_ctx); 4715 compl_ctx = FIELD_GET(IRDMA_AEQE_CMPL_CTXT, compl_ctx) << IRDMA_AEQE_CMPL_CTXT_S; 4716 } else { 4717 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp); 4718 info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp); 4719 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) | 4720 ((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18); 4721 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp); 4722 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp); 4723 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp); 4724 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp); 4725 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, 4726 temp); 4727 } 4728 4729 info->ae_src = ae_src; 4730 switch (info->ae_id) { 4731 case IRDMA_AE_SRQ_LIMIT: 4732 info->srq = true; 4733 /* [63:6] from CMPL_CTXT, [5:0] from WQDESCIDX. */ 4734 info->compl_ctx = compl_ctx; 4735 ae_src = IRDMA_AE_SOURCE_RSVD; 4736 break; 4737 case IRDMA_AE_PRIV_OPERATION_DENIED: 4738 case IRDMA_AE_AMP_INVALIDATE_TYPE1_MW: 4739 case IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW: 4740 case IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG: 4741 case IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH: 4742 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 4743 case IRDMA_AE_UDA_XMIT_BAD_PD: 4744 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 4745 case IRDMA_AE_BAD_CLOSE: 4746 case IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO: 4747 case IRDMA_AE_STAG_ZERO_INVALID: 4748 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 4749 case IRDMA_AE_IB_INVALID_REQUEST: 4750 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 4751 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 4752 case IRDMA_AE_IB_REMOTE_OP_ERROR: 4753 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 4754 case IRDMA_AE_DDP_UBE_INVALID_MO: 4755 case IRDMA_AE_DDP_UBE_INVALID_QN: 4756 case IRDMA_AE_DDP_NO_L_BIT: 4757 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 4758 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 4759 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 4760 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 4761 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 4762 case IRDMA_AE_INVALID_ARP_ENTRY: 4763 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 4764 case IRDMA_AE_STALE_ARP_ENTRY: 4765 case IRDMA_AE_INVALID_AH_ENTRY: 4766 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 4767 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 4768 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 4769 case IRDMA_AE_LLP_TOO_MANY_RNRS: 4770 case IRDMA_AE_REMOTE_QP_CATASTROPHIC: 4771 case IRDMA_AE_LOCAL_QP_CATASTROPHIC: 4772 case IRDMA_AE_RCE_QP_CATASTROPHIC: 4773 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 4774 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 4775 case IRDMA_AE_RESET_SENT: 4776 case IRDMA_AE_TERMINATE_SENT: 4777 case IRDMA_AE_RESET_NOT_SENT: 4778 case IRDMA_AE_LCE_QP_CATASTROPHIC: 4779 case IRDMA_AE_QP_SUSPEND_COMPLETE: 4780 case IRDMA_AE_UDA_L4LEN_INVALID: 4781 info->qp = true; 4782 info->compl_ctx = compl_ctx; 4783 break; 4784 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 4785 info->cq = true; 4786 info->compl_ctx = compl_ctx << 1; 4787 ae_src = IRDMA_AE_SOURCE_RSVD; 4788 break; 4789 case IRDMA_AE_CQP_DEFERRED_COMPLETE: 4790 info->def_info = info->wqe_idx; 4791 ae_src = IRDMA_AE_SOURCE_RSVD; 4792 break; 4793 case IRDMA_AE_ROCE_EMPTY_MCG: 4794 case IRDMA_AE_ROCE_BAD_MC_IP_ADDR: 4795 case IRDMA_AE_ROCE_BAD_MC_QPID: 4796 case IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH: 4797 fallthrough; 4798 case IRDMA_AE_LLP_CONNECTION_RESET: 4799 case IRDMA_AE_LLP_SYN_RECEIVED: 4800 case IRDMA_AE_LLP_FIN_RECEIVED: 4801 case IRDMA_AE_LLP_CLOSE_COMPLETE: 4802 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 4803 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 4804 ae_src = IRDMA_AE_SOURCE_RSVD; 4805 info->qp = true; 4806 info->compl_ctx = compl_ctx; 4807 break; 4808 default: 4809 break; 4810 } 4811 4812 switch (ae_src) { 4813 case IRDMA_AE_SOURCE_RQ: 4814 case IRDMA_AE_SOURCE_RQ_0011: 4815 info->qp = true; 4816 info->rq = true; 4817 info->compl_ctx = compl_ctx; 4818 info->err_rq_idx_valid = true; 4819 break; 4820 case IRDMA_AE_SOURCE_CQ: 4821 case IRDMA_AE_SOURCE_CQ_0110: 4822 case IRDMA_AE_SOURCE_CQ_1010: 4823 case IRDMA_AE_SOURCE_CQ_1110: 4824 info->cq = true; 4825 info->compl_ctx = compl_ctx << 1; 4826 break; 4827 case IRDMA_AE_SOURCE_SQ: 4828 case IRDMA_AE_SOURCE_SQ_0111: 4829 info->qp = true; 4830 info->sq = true; 4831 info->compl_ctx = compl_ctx; 4832 break; 4833 case IRDMA_AE_SOURCE_IN_RR_WR: 4834 info->qp = true; 4835 if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 4836 info->err_rq_idx_valid = true; 4837 info->compl_ctx = compl_ctx; 4838 info->in_rdrsp_wr = true; 4839 break; 4840 case IRDMA_AE_SOURCE_IN_RR_WR_1011: 4841 info->qp = true; 4842 if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 4843 info->sq = true; 4844 info->err_rq_idx_valid = true; 4845 } 4846 info->compl_ctx = compl_ctx; 4847 info->in_rdrsp_wr = true; 4848 break; 4849 case IRDMA_AE_SOURCE_OUT_RR: 4850 case IRDMA_AE_SOURCE_OUT_RR_1111: 4851 info->qp = true; 4852 info->compl_ctx = compl_ctx; 4853 info->out_rdrsp = true; 4854 break; 4855 case IRDMA_AE_SOURCE_RSVD: 4856 default: 4857 break; 4858 } 4859 4860 IRDMA_RING_MOVE_TAIL(aeq->aeq_ring); 4861 if (!IRDMA_RING_CURRENT_TAIL(aeq->aeq_ring)) 4862 aeq->polarity ^= 1; 4863 4864 return 0; 4865 } 4866 4867 /** 4868 * irdma_sc_repost_aeq_entries - repost completed aeq entries 4869 * @dev: sc device struct 4870 * @count: allocate count 4871 */ 4872 void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count) 4873 { 4874 writel(count, dev->hw_regs[IRDMA_AEQALLOC]); 4875 } 4876 4877 /** 4878 * irdma_sc_ccq_init - initialize control cq 4879 * @cq: sc's cq ctruct 4880 * @info: info for control cq initialization 4881 */ 4882 int irdma_sc_ccq_init(struct irdma_sc_cq *cq, struct irdma_ccq_init_info *info) 4883 { 4884 u32 pble_obj_cnt; 4885 4886 if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size || 4887 info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size) 4888 return -EINVAL; 4889 4890 if (info->ceq_id >= info->dev->hmc_fpm_misc.max_ceqs) 4891 return -EINVAL; 4892 4893 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4894 4895 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4896 return -EINVAL; 4897 4898 cq->cq_pa = info->cq_pa; 4899 cq->cq_uk.cq_base = info->cq_base; 4900 cq->shadow_area_pa = info->shadow_area_pa; 4901 cq->cq_uk.shadow_area = info->shadow_area; 4902 cq->shadow_read_threshold = info->shadow_read_threshold; 4903 cq->dev = info->dev; 4904 cq->ceq_id = info->ceq_id; 4905 cq->cq_uk.cq_size = info->num_elem; 4906 cq->cq_type = IRDMA_CQ_TYPE_CQP; 4907 cq->ceqe_mask = info->ceqe_mask; 4908 IRDMA_RING_INIT(cq->cq_uk.cq_ring, info->num_elem); 4909 cq->cq_uk.cq_id = 0; /* control cq is id 0 always */ 4910 cq->ceq_id_valid = info->ceq_id_valid; 4911 cq->tph_en = info->tph_en; 4912 cq->tph_val = info->tph_val; 4913 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct; 4914 cq->pbl_list = info->pbl_list; 4915 cq->virtual_map = info->virtual_map; 4916 cq->pbl_chunk_size = info->pbl_chunk_size; 4917 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 4918 cq->cq_uk.polarity = true; 4919 cq->vsi = info->vsi; 4920 cq->cq_uk.cq_ack_db = cq->dev->cq_ack_db; 4921 4922 /* Only applicable to CQs other than CCQ so initialize to zero */ 4923 cq->cq_uk.cqe_alloc_db = NULL; 4924 4925 info->dev->ccq = cq; 4926 return 0; 4927 } 4928 4929 /** 4930 * irdma_sc_ccq_create_done - poll cqp for ccq create 4931 * @ccq: ccq sc struct 4932 */ 4933 static inline int irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq) 4934 { 4935 struct irdma_sc_cqp *cqp; 4936 4937 cqp = ccq->dev->cqp; 4938 4939 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CQ, NULL); 4940 } 4941 4942 /** 4943 * irdma_sc_ccq_create - create control cq 4944 * @ccq: ccq sc struct 4945 * @scratch: u64 saved to be used during cqp completion 4946 * @check_overflow: overlow flag for ccq 4947 * @post_sq: flag for cqp db to ring 4948 */ 4949 int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch, 4950 bool check_overflow, bool post_sq) 4951 { 4952 int ret_code; 4953 4954 ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq); 4955 if (ret_code) 4956 return ret_code; 4957 4958 if (post_sq) { 4959 ret_code = irdma_sc_ccq_create_done(ccq); 4960 if (ret_code) 4961 return ret_code; 4962 } 4963 ccq->dev->cqp->process_cqp_sds = irdma_cqp_sds_cmd; 4964 4965 return 0; 4966 } 4967 4968 /** 4969 * irdma_sc_ccq_destroy - destroy ccq during close 4970 * @ccq: ccq sc struct 4971 * @scratch: u64 saved to be used during cqp completion 4972 * @post_sq: flag for cqp db to ring 4973 */ 4974 int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq) 4975 { 4976 struct irdma_sc_cqp *cqp; 4977 __le64 *wqe; 4978 u64 hdr; 4979 int ret_code = 0; 4980 u32 tail, val, error; 4981 4982 cqp = ccq->dev->cqp; 4983 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4984 if (!wqe) 4985 return -ENOMEM; 4986 4987 set_64bit_val(wqe, 0, ccq->cq_uk.cq_size); 4988 set_64bit_val(wqe, 8, ccq->cq_uk.cq_id); 4989 set_64bit_val(wqe, 40, ccq->shadow_area_pa); 4990 4991 hdr = ccq->cq_uk.cq_id | 4992 FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0), 4993 IRDMA_CQPSQ_CQ_CEQID) | 4994 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 4995 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) | 4996 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) | 4997 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) | 4998 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) | 4999 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 5000 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5001 5002 set_64bit_val(wqe, 24, hdr); 5003 5004 print_hex_dump_debug("WQE: CCQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 5005 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 5006 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5007 5008 if (post_sq) { 5009 irdma_sc_cqp_post_sq(cqp); 5010 ret_code = irdma_cqp_poll_registers(cqp, tail, 5011 cqp->dev->hw_attrs.max_done_count); 5012 } 5013 5014 cqp->process_cqp_sds = irdma_update_sds_noccq; 5015 5016 return ret_code; 5017 } 5018 5019 /** 5020 * irdma_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info 5021 * @dev : ptr to irdma_dev struct 5022 * @hmc_fn_id: hmc function id 5023 */ 5024 int irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u8 hmc_fn_id) 5025 { 5026 struct irdma_hmc_info *hmc_info; 5027 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5028 struct irdma_dma_mem query_fpm_mem; 5029 int ret_code = 0; 5030 u8 wait_type; 5031 5032 hmc_info = dev->hmc_info; 5033 hmc_fpm_misc = &dev->hmc_fpm_misc; 5034 query_fpm_mem.pa = dev->fpm_query_buf_pa; 5035 query_fpm_mem.va = dev->fpm_query_buf; 5036 hmc_info->hmc_fn_id = hmc_fn_id; 5037 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 5038 5039 ret_code = irdma_sc_query_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 5040 &query_fpm_mem, true, wait_type); 5041 if (ret_code) 5042 return ret_code; 5043 5044 /* parse the fpm_query_buf and fill hmc obj info */ 5045 ret_code = irdma_sc_parse_fpm_query_buf(dev, query_fpm_mem.va, hmc_info, 5046 hmc_fpm_misc); 5047 5048 print_hex_dump_debug("HMC: QUERY FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 5049 8, query_fpm_mem.va, IRDMA_QUERY_FPM_BUF_SIZE, 5050 false); 5051 return ret_code; 5052 } 5053 5054 /** 5055 * irdma_set_loc_mem() - set a local memory bit field 5056 * @buf: ptr to a buffer where local memory gets enabled 5057 */ 5058 static void irdma_set_loc_mem(__le64 *buf) 5059 { 5060 u64 loc_mem_en = BIT_ULL(ENABLE_LOC_MEM); 5061 u32 offset; 5062 u64 temp; 5063 5064 for (offset = 0; offset < IRDMA_COMMIT_FPM_BUF_SIZE; 5065 offset += sizeof(__le64)) { 5066 if (offset == IRDMA_PBLE_COMMIT_OFFSET || 5067 offset == IRDMA_SCRATCH_BUF0_COMMIT_OFFSET || 5068 offset == IRDMA_SCRATCH_BUF1_COMMIT_OFFSET) 5069 continue; 5070 get_64bit_val(buf, offset, &temp); 5071 if (temp) 5072 set_64bit_val(buf, offset, temp | loc_mem_en); 5073 } 5074 } 5075 5076 /** 5077 * irdma_sc_cfg_iw_fpm() - commits hmc obj cnt values using cqp 5078 * command and populates fpm base address in hmc_info 5079 * @dev : ptr to irdma_dev struct 5080 * @hmc_fn_id: hmc function id 5081 */ 5082 static int irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, u8 hmc_fn_id) 5083 { 5084 struct irdma_hmc_info *hmc_info; 5085 struct irdma_hmc_obj_info *obj_info; 5086 __le64 *buf; 5087 struct irdma_dma_mem commit_fpm_mem; 5088 int ret_code = 0; 5089 u8 wait_type; 5090 5091 hmc_info = dev->hmc_info; 5092 obj_info = hmc_info->hmc_obj; 5093 buf = dev->fpm_commit_buf; 5094 5095 set_64bit_val(buf, 0, (u64)obj_info[IRDMA_HMC_IW_QP].cnt); 5096 set_64bit_val(buf, 8, (u64)obj_info[IRDMA_HMC_IW_CQ].cnt); 5097 set_64bit_val(buf, 16, (u64)obj_info[IRDMA_HMC_IW_SRQ].cnt); 5098 set_64bit_val(buf, 24, (u64)obj_info[IRDMA_HMC_IW_HTE].cnt); 5099 set_64bit_val(buf, 32, (u64)obj_info[IRDMA_HMC_IW_ARP].cnt); 5100 set_64bit_val(buf, 40, (u64)0); /* RSVD */ 5101 set_64bit_val(buf, 48, (u64)obj_info[IRDMA_HMC_IW_MR].cnt); 5102 set_64bit_val(buf, 56, (u64)obj_info[IRDMA_HMC_IW_XF].cnt); 5103 set_64bit_val(buf, 64, (u64)obj_info[IRDMA_HMC_IW_XFFL].cnt); 5104 set_64bit_val(buf, 72, (u64)obj_info[IRDMA_HMC_IW_Q1].cnt); 5105 set_64bit_val(buf, 80, (u64)obj_info[IRDMA_HMC_IW_Q1FL].cnt); 5106 set_64bit_val(buf, 88, 5107 (u64)obj_info[IRDMA_HMC_IW_TIMER].cnt); 5108 set_64bit_val(buf, 96, 5109 (u64)obj_info[IRDMA_HMC_IW_FSIMC].cnt); 5110 set_64bit_val(buf, 104, 5111 (u64)obj_info[IRDMA_HMC_IW_FSIAV].cnt); 5112 set_64bit_val(buf, 112, 5113 (u64)obj_info[IRDMA_HMC_IW_PBLE].cnt); 5114 set_64bit_val(buf, 120, (u64)0); /* RSVD */ 5115 set_64bit_val(buf, 128, (u64)obj_info[IRDMA_HMC_IW_RRF].cnt); 5116 set_64bit_val(buf, 136, 5117 (u64)obj_info[IRDMA_HMC_IW_RRFFL].cnt); 5118 set_64bit_val(buf, 144, (u64)obj_info[IRDMA_HMC_IW_HDR].cnt); 5119 set_64bit_val(buf, 152, (u64)obj_info[IRDMA_HMC_IW_MD].cnt); 5120 set_64bit_val(buf, 160, 5121 (u64)obj_info[IRDMA_HMC_IW_OOISC].cnt); 5122 set_64bit_val(buf, 168, 5123 (u64)obj_info[IRDMA_HMC_IW_OOISCFFL].cnt); 5124 set_64bit_val(buf, 192, dev->hmc_fpm_misc.fw_scratch_buf0.pa); 5125 set_64bit_val(buf, 200, dev->hmc_fpm_misc.fw_scratch_buf1.pa); 5126 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3 && 5127 dev->hmc_fpm_misc.loc_mem_pages) 5128 irdma_set_loc_mem(buf); 5129 commit_fpm_mem.pa = dev->fpm_commit_buf_pa; 5130 commit_fpm_mem.va = dev->fpm_commit_buf; 5131 5132 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 5133 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 5134 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 5135 false); 5136 ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 5137 &commit_fpm_mem, true, wait_type); 5138 if (!ret_code) 5139 irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf, 5140 hmc_info->hmc_obj, 5141 &hmc_info->sd_table.sd_cnt); 5142 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 5143 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 5144 false); 5145 5146 return ret_code; 5147 } 5148 5149 /** 5150 * cqp_sds_wqe_fill - fill cqp wqe doe sd 5151 * @cqp: struct for cqp hw 5152 * @info: sd info for wqe 5153 * @scratch: u64 saved to be used during cqp completion 5154 */ 5155 static int cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp, 5156 struct irdma_update_sds_info *info, u64 scratch) 5157 { 5158 u64 data; 5159 u64 hdr; 5160 __le64 *wqe; 5161 int mem_entries, wqe_entries; 5162 struct irdma_dma_mem *sdbuf = &cqp->sdbuf; 5163 u64 offset = 0; 5164 u32 wqe_idx; 5165 5166 wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); 5167 if (!wqe) 5168 return -ENOMEM; 5169 5170 wqe_entries = (info->cnt > 3) ? 3 : info->cnt; 5171 mem_entries = info->cnt - wqe_entries; 5172 5173 if (mem_entries) { 5174 offset = wqe_idx * IRDMA_UPDATE_SD_BUFF_SIZE; 5175 memcpy(((char *)sdbuf->va + offset), &info->entry[3], mem_entries << 4); 5176 5177 data = (u64)sdbuf->pa + offset; 5178 } else { 5179 data = 0; 5180 } 5181 data |= FIELD_PREP(IRDMA_CQPSQ_UPESD_HMCFNID, info->hmc_fn_id); 5182 set_64bit_val(wqe, 16, data); 5183 5184 switch (wqe_entries) { 5185 case 3: 5186 set_64bit_val(wqe, 48, 5187 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) | 5188 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 5189 5190 set_64bit_val(wqe, 56, info->entry[2].data); 5191 fallthrough; 5192 case 2: 5193 set_64bit_val(wqe, 32, 5194 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) | 5195 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 5196 5197 set_64bit_val(wqe, 40, info->entry[1].data); 5198 fallthrough; 5199 case 1: 5200 set_64bit_val(wqe, 0, 5201 FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd)); 5202 5203 set_64bit_val(wqe, 8, info->entry[0].data); 5204 break; 5205 default: 5206 break; 5207 } 5208 5209 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) | 5210 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 5211 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries); 5212 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5213 5214 set_64bit_val(wqe, 24, hdr); 5215 5216 if (mem_entries) 5217 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE Buffer", 5218 DUMP_PREFIX_OFFSET, 16, 8, 5219 (char *)sdbuf->va + offset, 5220 mem_entries << 4, false); 5221 5222 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE", DUMP_PREFIX_OFFSET, 16, 5223 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 5224 5225 return 0; 5226 } 5227 5228 /** 5229 * irdma_update_pe_sds - cqp wqe for sd 5230 * @dev: ptr to irdma_dev struct 5231 * @info: sd info for sd's 5232 * @scratch: u64 saved to be used during cqp completion 5233 */ 5234 static int irdma_update_pe_sds(struct irdma_sc_dev *dev, 5235 struct irdma_update_sds_info *info, u64 scratch) 5236 { 5237 struct irdma_sc_cqp *cqp = dev->cqp; 5238 int ret_code; 5239 5240 ret_code = cqp_sds_wqe_fill(cqp, info, scratch); 5241 if (!ret_code) 5242 irdma_sc_cqp_post_sq(cqp); 5243 5244 return ret_code; 5245 } 5246 5247 /** 5248 * irdma_update_sds_noccq - update sd before ccq created 5249 * @dev: sc device struct 5250 * @info: sd info for sd's 5251 */ 5252 int irdma_update_sds_noccq(struct irdma_sc_dev *dev, 5253 struct irdma_update_sds_info *info) 5254 { 5255 u32 error, val, tail; 5256 struct irdma_sc_cqp *cqp = dev->cqp; 5257 int ret_code; 5258 5259 ret_code = cqp_sds_wqe_fill(cqp, info, 0); 5260 if (ret_code) 5261 return ret_code; 5262 5263 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5264 5265 irdma_sc_cqp_post_sq(cqp); 5266 return irdma_cqp_poll_registers(cqp, tail, 5267 cqp->dev->hw_attrs.max_done_count); 5268 } 5269 5270 /** 5271 * irdma_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages 5272 * @cqp: struct for cqp hw 5273 * @scratch: u64 saved to be used during cqp completion 5274 * @hmc_fn_id: hmc function id 5275 * @post_sq: flag for cqp db to ring 5276 * @poll_registers: flag to poll register for cqp completion 5277 */ 5278 int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, 5279 u8 hmc_fn_id, bool post_sq, 5280 bool poll_registers) 5281 { 5282 u64 hdr; 5283 __le64 *wqe; 5284 u32 tail, val, error; 5285 5286 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 5287 if (!wqe) 5288 return -ENOMEM; 5289 5290 set_64bit_val(wqe, 16, 5291 FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id)); 5292 5293 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 5294 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) | 5295 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 5296 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5297 5298 set_64bit_val(wqe, 24, hdr); 5299 5300 print_hex_dump_debug("WQE: SHMC_PAGES_ALLOCATED WQE", 5301 DUMP_PREFIX_OFFSET, 16, 8, wqe, 5302 IRDMA_CQP_WQE_SIZE * 8, false); 5303 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5304 5305 if (post_sq) { 5306 irdma_sc_cqp_post_sq(cqp); 5307 if (poll_registers) 5308 /* check for cqp sq tail update */ 5309 return irdma_cqp_poll_registers(cqp, tail, 5310 cqp->dev->hw_attrs.max_done_count); 5311 else 5312 return irdma_sc_poll_for_cqp_op_done(cqp, 5313 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED, 5314 NULL); 5315 } 5316 5317 return 0; 5318 } 5319 5320 /** 5321 * irdma_cqp_ring_full - check if cqp ring is full 5322 * @cqp: struct for cqp hw 5323 */ 5324 static bool irdma_cqp_ring_full(struct irdma_sc_cqp *cqp) 5325 { 5326 u64 in_flight = cqp->requested_ops - 5327 atomic64_read(&cqp->completed_ops); 5328 5329 return IRDMA_RING_FULL_ERR(cqp->sq_ring) || 5330 in_flight >= (cqp->sq_size - 1); 5331 } 5332 5333 /** 5334 * irdma_est_sd - returns approximate number of SDs for HMC 5335 * @dev: sc device struct 5336 * @hmc_info: hmc structure, size and count for HMC objects 5337 */ 5338 static u32 irdma_est_sd(struct irdma_sc_dev *dev, 5339 struct irdma_hmc_info *hmc_info) 5340 { 5341 struct irdma_hmc_obj_info *pble_info; 5342 int i; 5343 u64 size = 0; 5344 u64 sd; 5345 5346 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5347 if (i != IRDMA_HMC_IW_PBLE) 5348 size += round_up(hmc_info->hmc_obj[i].cnt * 5349 hmc_info->hmc_obj[i].size, 512); 5350 5351 pble_info = &hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE]; 5352 if (dev->privileged) 5353 size += round_up(pble_info->cnt * pble_info->size, 512); 5354 if (size & 0x1FFFFF) 5355 sd = (size >> 21) + 1; /* add 1 for remainder */ 5356 else 5357 sd = size >> 21; 5358 if (!dev->privileged && !dev->hmc_fpm_misc.loc_mem_pages) { 5359 /* 2MB alignment for VF PBLE HMC */ 5360 size = pble_info->cnt * pble_info->size; 5361 if (size & 0x1FFFFF) 5362 sd += (size >> 21) + 1; /* add 1 for remainder */ 5363 else 5364 sd += size >> 21; 5365 } 5366 if (sd > 0xFFFFFFFF) { 5367 ibdev_dbg(to_ibdev(dev), "HMC: sd overflow[%lld]\n", sd); 5368 sd = 0xFFFFFFFF - 1; 5369 } 5370 5371 return (u32)sd; 5372 } 5373 5374 /** 5375 * irdma_sc_query_rdma_features - query RDMA features and FW ver 5376 * @cqp: struct for cqp hw 5377 * @buf: buffer to hold query info 5378 * @scratch: u64 saved to be used during cqp completion 5379 */ 5380 static int irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp, 5381 struct irdma_dma_mem *buf, u64 scratch) 5382 { 5383 u32 tail, val, error; 5384 __le64 *wqe; 5385 int status; 5386 u64 temp; 5387 5388 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 5389 if (!wqe) 5390 return -ENOMEM; 5391 5392 temp = buf->pa; 5393 set_64bit_val(wqe, 32, temp); 5394 5395 temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID, 5396 cqp->polarity) | 5397 FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) | 5398 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES); 5399 dma_wmb(); /* make sure WQE is written before valid bit is set */ 5400 5401 set_64bit_val(wqe, 24, temp); 5402 5403 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 5404 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 5405 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 5406 5407 irdma_sc_cqp_post_sq(cqp); 5408 status = irdma_cqp_poll_registers(cqp, tail, 5409 cqp->dev->hw_attrs.max_done_count); 5410 if (error || status) 5411 status = -EINVAL; 5412 5413 return status; 5414 } 5415 5416 /** 5417 * irdma_get_rdma_features - get RDMA features 5418 * @dev: sc device struct 5419 */ 5420 int irdma_get_rdma_features(struct irdma_sc_dev *dev) 5421 { 5422 int ret_code; 5423 struct irdma_dma_mem feat_buf; 5424 u64 temp; 5425 u16 byte_idx, feat_type, feat_cnt, feat_idx; 5426 5427 feat_buf.size = ALIGN(IRDMA_FEATURE_BUF_SIZE, 5428 IRDMA_FEATURE_BUF_ALIGNMENT); 5429 feat_buf.va = dma_alloc_coherent(dev->hw->device, feat_buf.size, 5430 &feat_buf.pa, GFP_KERNEL); 5431 if (!feat_buf.va) 5432 return -ENOMEM; 5433 5434 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 5435 if (ret_code) 5436 goto exit; 5437 5438 get_64bit_val(feat_buf.va, 0, &temp); 5439 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 5440 if (feat_cnt < 2) { 5441 ret_code = -EINVAL; 5442 goto exit; 5443 } else if (feat_cnt > IRDMA_MAX_FEATURES) { 5444 ibdev_dbg(to_ibdev(dev), 5445 "DEV: feature buf size insufficient, retrying with larger buffer\n"); 5446 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 5447 feat_buf.pa); 5448 feat_buf.va = NULL; 5449 feat_buf.size = ALIGN(8 * feat_cnt, 5450 IRDMA_FEATURE_BUF_ALIGNMENT); 5451 feat_buf.va = dma_alloc_coherent(dev->hw->device, 5452 feat_buf.size, &feat_buf.pa, 5453 GFP_KERNEL); 5454 if (!feat_buf.va) 5455 return -ENOMEM; 5456 5457 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 5458 if (ret_code) 5459 goto exit; 5460 5461 get_64bit_val(feat_buf.va, 0, &temp); 5462 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 5463 if (feat_cnt < 2) { 5464 ret_code = -EINVAL; 5465 goto exit; 5466 } 5467 } 5468 5469 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 5470 16, 8, feat_buf.va, feat_cnt * 8, false); 5471 5472 for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, (u16)IRDMA_MAX_FEATURES); 5473 feat_idx++, byte_idx += 8) { 5474 get_64bit_val(feat_buf.va, byte_idx, &temp); 5475 feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp); 5476 if (feat_type >= IRDMA_MAX_FEATURES) { 5477 ibdev_dbg(to_ibdev(dev), 5478 "DEV: found unrecognized feature type %d\n", 5479 feat_type); 5480 continue; 5481 } 5482 dev->feature_info[feat_type] = temp; 5483 } 5484 5485 if (dev->feature_info[IRDMA_FTN_FLAGS] & IRDMA_ATOMICS_ALLOWED_BIT) 5486 dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_ATOMIC_OPS; 5487 5488 exit: 5489 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 5490 feat_buf.pa); 5491 feat_buf.va = NULL; 5492 return ret_code; 5493 } 5494 5495 static u32 irdma_q1_cnt(struct irdma_sc_dev *dev, 5496 struct irdma_hmc_info *hmc_info, u32 qpwanted) 5497 { 5498 u32 q1_cnt; 5499 5500 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 5501 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted); 5502 } else { 5503 if (dev->cqp->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) 5504 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted + 512); 5505 else 5506 q1_cnt = dev->hw_attrs.max_hw_ird * 2 * qpwanted; 5507 } 5508 5509 return q1_cnt; 5510 } 5511 5512 static void cfg_fpm_value_gen_1(struct irdma_sc_dev *dev, 5513 struct irdma_hmc_info *hmc_info, u32 qpwanted) 5514 { 5515 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = roundup_pow_of_two(qpwanted * dev->hw_attrs.max_hw_wqes); 5516 } 5517 5518 static void cfg_fpm_value_gen_2(struct irdma_sc_dev *dev, 5519 struct irdma_hmc_info *hmc_info, u32 qpwanted) 5520 { 5521 struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc; 5522 5523 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = 5524 4 * hmc_fpm_misc->xf_block_size * qpwanted; 5525 5526 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 5527 5528 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt) 5529 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 32 * qpwanted; 5530 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 5531 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = 5532 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 5533 hmc_fpm_misc->rrf_block_size; 5534 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt) 5535 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt = 32 * qpwanted; 5536 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt) 5537 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].cnt = 5538 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt / 5539 hmc_fpm_misc->ooiscf_block_size; 5540 } 5541 5542 /** 5543 * irdma_get_rsrc_mem_config - configure resources if local memory or host 5544 * @dev: sc device struct 5545 * @is_mrte_loc_mem: if true, MR's to be in local memory because sd=loc pages 5546 * 5547 * Only mr can be configured host or local memory if qp's are in local memory. 5548 * If qp is in local memory, then all resource object will be in local memory 5549 * except mr which can be either host or local memory. The only exception 5550 * is pble's which are always in host memory. 5551 */ 5552 static void irdma_get_rsrc_mem_config(struct irdma_sc_dev *dev, bool is_mrte_loc_mem) 5553 { 5554 struct irdma_hmc_info *hmc_info = dev->hmc_info; 5555 int i; 5556 5557 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5558 hmc_info->hmc_obj[i].mem_loc = IRDMA_LOC_MEM; 5559 5560 if (dev->feature_info[IRDMA_OBJ_1] && !is_mrte_loc_mem) { 5561 u8 mem_type; 5562 5563 mem_type = (u8)FIELD_GET(IRDMA_MR_MEM_LOC, dev->feature_info[IRDMA_OBJ_1]); 5564 5565 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc = 5566 (mem_type & IRDMA_OBJ_LOC_MEM_BIT) ? 5567 IRDMA_LOC_MEM : IRDMA_HOST_MEM; 5568 } else { 5569 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc = IRDMA_LOC_MEM; 5570 } 5571 5572 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].mem_loc = IRDMA_HOST_MEM; 5573 5574 ibdev_dbg(to_ibdev(dev), "HMC: INFO: mrte_mem_loc = %d pble = %d\n", 5575 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc, 5576 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].mem_loc); 5577 } 5578 5579 /** 5580 * irdma_cfg_sd_mem - allocate sd memory 5581 * @dev: sc device struct 5582 * @hmc_info: ptr to irdma_hmc_obj_info struct 5583 */ 5584 static int irdma_cfg_sd_mem(struct irdma_sc_dev *dev, 5585 struct irdma_hmc_info *hmc_info) 5586 { 5587 struct irdma_virt_mem virt_mem; 5588 u32 mem_size; 5589 5590 mem_size = sizeof(struct irdma_hmc_sd_entry) * hmc_info->sd_table.sd_cnt; 5591 virt_mem.size = mem_size; 5592 virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL); 5593 if (!virt_mem.va) 5594 return -ENOMEM; 5595 hmc_info->sd_table.sd_entry = virt_mem.va; 5596 5597 return 0; 5598 } 5599 5600 /** 5601 * irdma_get_objs_pages - get number of 2M pages needed 5602 * @dev: sc device struct 5603 * @hmc_info: pointer to the HMC configuration information struct 5604 * @mem_loc: pages for local or host memory 5605 */ 5606 static u32 irdma_get_objs_pages(struct irdma_sc_dev *dev, 5607 struct irdma_hmc_info *hmc_info, 5608 enum irdma_hmc_obj_mem mem_loc) 5609 { 5610 u64 size = 0; 5611 int i; 5612 5613 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { 5614 if (hmc_info->hmc_obj[i].mem_loc == mem_loc) { 5615 size += round_up(hmc_info->hmc_obj[i].cnt * 5616 hmc_info->hmc_obj[i].size, 512); 5617 } 5618 } 5619 5620 return DIV_ROUND_UP(size, IRDMA_HMC_PAGE_SIZE); 5621 } 5622 5623 /** 5624 * irdma_set_host_hmc_rsrc_gen_3 - calculate host hmc resources for gen 3 5625 * @dev: sc device struct 5626 */ 5627 static void irdma_set_host_hmc_rsrc_gen_3(struct irdma_sc_dev *dev) 5628 { 5629 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5630 struct irdma_hmc_info *hmc_info; 5631 enum irdma_hmc_obj_mem mrte_loc; 5632 u32 mrwanted, pblewanted; 5633 u32 avail_sds, mr_sds; 5634 5635 hmc_info = dev->hmc_info; 5636 hmc_fpm_misc = &dev->hmc_fpm_misc; 5637 avail_sds = hmc_fpm_misc->max_sds; 5638 mrte_loc = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc; 5639 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 5640 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; 5641 5642 if (mrte_loc == IRDMA_HOST_MEM && avail_sds > IRDMA_MIN_PBLE_PAGES) { 5643 mr_sds = avail_sds - IRDMA_MIN_PBLE_PAGES; 5644 mrwanted = min(mrwanted, mr_sds * MAX_MR_PER_SD); 5645 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; 5646 avail_sds -= DIV_ROUND_UP(mrwanted, MAX_MR_PER_SD); 5647 } 5648 5649 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS]) && 5650 pblewanted > avail_sds * MAX_PBLE_PER_SD) 5651 ibdev_dbg(to_ibdev(dev), 5652 "HMC: Warn: Resource version 2: pble wanted = 0x%x available = 0x%x\n", 5653 pblewanted, avail_sds * MAX_PBLE_PER_SD); 5654 5655 pblewanted = min(pblewanted, avail_sds * MAX_PBLE_PER_SD); 5656 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 5657 } 5658 5659 /** 5660 * irdma_verify_commit_fpm_gen_3 - verify query fpm values 5661 * @dev: sc device struct 5662 * @max_pages: max local memory available 5663 * @qpwanted: number of qp's wanted 5664 */ 5665 static int irdma_verify_commit_fpm_gen_3(struct irdma_sc_dev *dev, 5666 u32 max_pages, 5667 u32 qpwanted) 5668 { 5669 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5670 u32 rrf_cnt, xf_cnt, timer_cnt, pages_needed; 5671 struct irdma_hmc_info *hmc_info; 5672 u32 rrffl_cnt = 0; 5673 u32 xffl_cnt = 0; 5674 u32 q1fl_cnt; 5675 5676 hmc_info = dev->hmc_info; 5677 hmc_fpm_misc = &dev->hmc_fpm_misc; 5678 5679 rrf_cnt = roundup_pow_of_two(IRDMA_RRF_MULTIPLIER * qpwanted); 5680 5681 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 5682 rrffl_cnt = 5683 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 5684 hmc_fpm_misc->rrf_block_size; 5685 5686 xf_cnt = roundup_pow_of_two(IRDMA_XF_MULTIPLIER * qpwanted); 5687 5688 if (xf_cnt) 5689 xffl_cnt = xf_cnt / hmc_fpm_misc->xf_block_size; 5690 5691 timer_cnt = (round_up(qpwanted, 512) / 512 + 1) * 5692 hmc_fpm_misc->timer_bucket; 5693 5694 q1fl_cnt = hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 5695 5696 pages_needed = irdma_get_objs_pages(dev, hmc_info, IRDMA_LOC_MEM); 5697 if (pages_needed > max_pages) { 5698 ibdev_dbg(to_ibdev(dev), 5699 "HMC: FAIL: SW counts rrf_cnt = %u rrffl_cnt = %u timer_cnt = %u", 5700 rrf_cnt, rrffl_cnt, timer_cnt); 5701 ibdev_dbg(to_ibdev(dev), 5702 "HMC: FAIL: SW counts xf_cnt = %u xffl_cnt = %u q1fl_cnt = %u", 5703 xf_cnt, xffl_cnt, q1fl_cnt); 5704 5705 return -EINVAL; 5706 } 5707 5708 hmc_fpm_misc->max_sds -= pages_needed; 5709 hmc_fpm_misc->loc_mem_pages -= pages_needed; 5710 5711 return 0; 5712 } 5713 5714 /** 5715 * irdma_set_loc_hmc_rsrc_gen_3 - calculate hmc resources for gen 3 5716 * @dev: sc device struct 5717 * @max_pages: max local memory available 5718 * @qpwanted: number of qp's wanted 5719 */ 5720 static int irdma_set_loc_hmc_rsrc_gen_3(struct irdma_sc_dev *dev, 5721 u32 max_pages, 5722 u32 qpwanted) 5723 { 5724 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5725 u32 rrf_cnt, xf_cnt, timer_cnt, pages_needed; 5726 struct irdma_hmc_info *hmc_info; 5727 u32 ird, ord; 5728 5729 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5730 return irdma_verify_commit_fpm_gen_3(dev, max_pages, qpwanted); 5731 5732 hmc_info = dev->hmc_info; 5733 hmc_fpm_misc = &dev->hmc_fpm_misc; 5734 ird = dev->hw_attrs.max_hw_ird; 5735 ord = dev->hw_attrs.max_hw_ord; 5736 5737 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 5738 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; 5739 5740 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = 5741 min(hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, qpwanted * 2); 5742 5743 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = 5744 min(qpwanted * 8, hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); 5745 5746 rrf_cnt = roundup_pow_of_two(IRDMA_RRF_MULTIPLIER * qpwanted); 5747 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 5748 min(hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt, rrf_cnt); 5749 5750 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 5751 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = 5752 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 5753 hmc_fpm_misc->rrf_block_size; 5754 5755 xf_cnt = roundup_pow_of_two(IRDMA_XF_MULTIPLIER * qpwanted); 5756 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = 5757 min(hmc_info->hmc_obj[IRDMA_HMC_IW_XF].max_cnt, xf_cnt); 5758 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = 5759 xf_cnt / hmc_fpm_misc->xf_block_size; 5760 5761 timer_cnt = (round_up(qpwanted, 512) / 512 + 1) * 5762 hmc_fpm_misc->timer_bucket; 5763 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = 5764 min(timer_cnt, hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt); 5765 5766 do { 5767 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = roundup_pow_of_two(ird * 2 * qpwanted); 5768 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = 5769 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 5770 5771 pages_needed = irdma_get_objs_pages(dev, hmc_info, IRDMA_LOC_MEM); 5772 if (pages_needed <= max_pages) 5773 break; 5774 5775 ird /= 2; 5776 ord /= 2; 5777 } while (ird >= IRDMA_MIN_IRD); 5778 5779 if (ird < IRDMA_MIN_IRD) { 5780 ibdev_dbg(to_ibdev(dev), "HMC: FAIL: IRD=%u Q1 CNT = %u\n", 5781 ird, hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt); 5782 return -EINVAL; 5783 } 5784 5785 dev->hw_attrs.max_hw_ird = ird; 5786 dev->hw_attrs.max_hw_ord = ord; 5787 hmc_fpm_misc->max_sds -= pages_needed; 5788 5789 return 0; 5790 } 5791 5792 /** 5793 * cfg_fpm_value_gen_3 - configure fpm for gen 3 5794 * @dev: sc device struct 5795 * @hmc_info: ptr to irdma_hmc_obj_info struct 5796 * @hmc_fpm_misc: ptr to fpm data 5797 */ 5798 static int cfg_fpm_value_gen_3(struct irdma_sc_dev *dev, 5799 struct irdma_hmc_info *hmc_info, 5800 struct irdma_hmc_fpm_misc *hmc_fpm_misc) 5801 { 5802 enum irdma_hmc_obj_mem mrte_loc; 5803 u32 mrwanted, qpwanted; 5804 int i, ret_code = 0; 5805 u32 loc_mem_pages; 5806 bool is_mrte_loc_mem; 5807 5808 loc_mem_pages = hmc_fpm_misc->loc_mem_pages; 5809 is_mrte_loc_mem = hmc_fpm_misc->loc_mem_pages == hmc_fpm_misc->max_sds; 5810 5811 irdma_get_rsrc_mem_config(dev, is_mrte_loc_mem); 5812 mrte_loc = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc; 5813 5814 if (is_mrte_loc_mem) 5815 loc_mem_pages -= IRDMA_MIN_PBLE_PAGES; 5816 5817 ibdev_dbg(to_ibdev(dev), 5818 "HMC: mrte_loc %d loc_mem %u fpm max sds %u host_obj %d\n", 5819 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc, 5820 hmc_fpm_misc->loc_mem_pages, hmc_fpm_misc->max_sds, 5821 is_mrte_loc_mem); 5822 5823 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; 5824 qpwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt; 5825 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 5826 5827 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt = 0; 5828 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt = 0; 5829 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].max_cnt = 0; 5830 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt = 0; 5831 5832 if (!FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5833 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt = 5834 min(hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt, 5835 (u32)IRDMA_FSIAV_CNT_MAX); 5836 5837 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5838 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; 5839 5840 while (qpwanted >= IRDMA_MIN_QP_CNT) { 5841 if (!irdma_set_loc_hmc_rsrc_gen_3(dev, loc_mem_pages, qpwanted)) 5842 break; 5843 5844 if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5845 return -EINVAL; 5846 5847 qpwanted /= 2; 5848 if (mrte_loc == IRDMA_LOC_MEM) { 5849 mrwanted = qpwanted * IRDMA_MIN_MR_PER_QP; 5850 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = 5851 min(hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, mrwanted); 5852 } 5853 } 5854 5855 if (qpwanted < IRDMA_MIN_QP_CNT) { 5856 ibdev_dbg(to_ibdev(dev), 5857 "HMC: ERROR: could not allocate fpm resources\n"); 5858 return -EINVAL; 5859 } 5860 5861 irdma_set_host_hmc_rsrc_gen_3(dev); 5862 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); 5863 if (ret_code) { 5864 ibdev_dbg(to_ibdev(dev), 5865 "HMC: cfg_iw_fpm returned error_code[x%08X]\n", 5866 readl(dev->hw_regs[IRDMA_CQPERRCODES])); 5867 5868 return ret_code; 5869 } 5870 5871 return irdma_cfg_sd_mem(dev, hmc_info); 5872 } 5873 5874 /** 5875 * irdma_cfg_fpm_val - configure HMC objects 5876 * @dev: sc device struct 5877 * @qp_count: desired qp count 5878 */ 5879 int irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count) 5880 { 5881 u32 qpwanted, mrwanted, pblewanted; 5882 u32 powerof2, hte, i; 5883 u32 sd_needed; 5884 u32 sd_diff; 5885 u32 loop_count = 0; 5886 struct irdma_hmc_info *hmc_info; 5887 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5888 int ret_code = 0; 5889 u32 max_sds; 5890 5891 hmc_info = dev->hmc_info; 5892 hmc_fpm_misc = &dev->hmc_fpm_misc; 5893 5894 ret_code = irdma_sc_init_iw_hmc(dev, dev->hmc_fn_id); 5895 if (ret_code) { 5896 ibdev_dbg(to_ibdev(dev), 5897 "HMC: irdma_sc_init_iw_hmc returned error_code = %d\n", 5898 ret_code); 5899 return ret_code; 5900 } 5901 5902 max_sds = hmc_fpm_misc->max_sds; 5903 5904 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 5905 return cfg_fpm_value_gen_3(dev, hmc_info, hmc_fpm_misc); 5906 5907 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5908 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; 5909 sd_needed = irdma_est_sd(dev, hmc_info); 5910 ibdev_dbg(to_ibdev(dev), "HMC: sd count %u where max sd is %u\n", 5911 hmc_info->sd_table.sd_cnt, max_sds); 5912 5913 qpwanted = min(qp_count, hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt); 5914 5915 powerof2 = 1; 5916 while (powerof2 <= qpwanted) 5917 powerof2 *= 2; 5918 powerof2 /= 2; 5919 qpwanted = powerof2; 5920 5921 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; 5922 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; 5923 5924 ibdev_dbg(to_ibdev(dev), 5925 "HMC: req_qp=%d max_sd=%u, max_qp = %u, max_cq=%u, max_mr=%u, max_pble=%u, mc=%d, av=%u\n", 5926 qp_count, max_sds, 5927 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt, 5928 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt, 5929 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, 5930 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt, 5931 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt, 5932 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); 5933 5934 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt = 5935 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt; 5936 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = 5937 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt; 5938 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt = 5939 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt; 5940 hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1; 5941 5942 while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt) 5943 qpwanted /= 2; 5944 5945 do { 5946 ++loop_count; 5947 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; 5948 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = 5949 min(2 * qpwanted, hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt); 5950 hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].cnt = 0; /* Reserved */ 5951 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; 5952 5953 hte = round_up(qpwanted + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 512); 5954 powerof2 = 1; 5955 while (powerof2 < hte) 5956 powerof2 *= 2; 5957 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].cnt = 5958 powerof2 * hmc_fpm_misc->ht_multiplier; 5959 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 5960 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted); 5961 else 5962 cfg_fpm_value_gen_2(dev, hmc_info, qpwanted); 5963 5964 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = irdma_q1_cnt(dev, hmc_info, qpwanted); 5965 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = 5966 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size; 5967 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = 5968 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 5969 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = 5970 (round_up(qpwanted, 512) / 512 + 1) * hmc_fpm_misc->timer_bucket; 5971 5972 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 5973 sd_needed = irdma_est_sd(dev, hmc_info); 5974 ibdev_dbg(to_ibdev(dev), 5975 "HMC: sd_needed = %d, hmc_fpm_misc->max_sds=%d, mrwanted=%d, pblewanted=%d qpwanted=%d\n", 5976 sd_needed, hmc_fpm_misc->max_sds, mrwanted, 5977 pblewanted, qpwanted); 5978 5979 /* Do not reduce resources further. All objects fit with max SDs */ 5980 if (sd_needed <= hmc_fpm_misc->max_sds) 5981 break; 5982 5983 sd_diff = sd_needed - hmc_fpm_misc->max_sds; 5984 if (sd_diff > 128) { 5985 if (!(loop_count % 2) && qpwanted > 128) { 5986 qpwanted /= 2; 5987 } else { 5988 pblewanted /= 2; 5989 mrwanted /= 2; 5990 } 5991 continue; 5992 } 5993 5994 if (dev->cqp->hmc_profile != IRDMA_HMC_PROFILE_FAVOR_VF && 5995 pblewanted > (512 * FPM_MULTIPLIER * sd_diff)) { 5996 pblewanted -= 256 * FPM_MULTIPLIER * sd_diff; 5997 continue; 5998 } else if (pblewanted > (100 * FPM_MULTIPLIER)) { 5999 pblewanted -= 10 * FPM_MULTIPLIER; 6000 } else if (pblewanted > FPM_MULTIPLIER) { 6001 pblewanted -= FPM_MULTIPLIER; 6002 } else if (qpwanted <= 128) { 6003 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt > 256) 6004 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt /= 2; 6005 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 6006 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 6007 } 6008 if (mrwanted > FPM_MULTIPLIER) 6009 mrwanted -= FPM_MULTIPLIER; 6010 if (!(loop_count % 10) && qpwanted > 128) { 6011 qpwanted /= 2; 6012 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 6013 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 6014 } 6015 } while (loop_count < 2000); 6016 6017 if (sd_needed > hmc_fpm_misc->max_sds) { 6018 ibdev_dbg(to_ibdev(dev), 6019 "HMC: cfg_fpm failed loop_cnt=%u, sd_needed=%u, max sd count %u\n", 6020 loop_count, sd_needed, hmc_info->sd_table.sd_cnt); 6021 return -EINVAL; 6022 } 6023 6024 if (loop_count > 1 && sd_needed < max_sds) { 6025 pblewanted += (max_sds - sd_needed) * 256 * FPM_MULTIPLIER; 6026 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 6027 sd_needed = irdma_est_sd(dev, hmc_info); 6028 } 6029 6030 ibdev_dbg(to_ibdev(dev), 6031 "HMC: loop_cnt=%d, sd_needed=%d, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d, mc=%d, ah=%d, max sd count %d, first sd index %d\n", 6032 loop_count, sd_needed, 6033 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt, 6034 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 6035 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt, 6036 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt, 6037 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 6038 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt, 6039 hmc_info->sd_table.sd_cnt, hmc_info->first_sd_index); 6040 6041 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); 6042 if (ret_code) { 6043 ibdev_dbg(to_ibdev(dev), 6044 "HMC: cfg_iw_fpm returned error_code[x%08X]\n", 6045 readl(dev->hw_regs[IRDMA_CQPERRCODES])); 6046 return ret_code; 6047 } 6048 6049 return irdma_cfg_sd_mem(dev, hmc_info); 6050 } 6051 6052 /** 6053 * irdma_exec_cqp_cmd - execute cqp cmd when wqe are available 6054 * @dev: rdma device 6055 * @pcmdinfo: cqp command info 6056 */ 6057 static int irdma_exec_cqp_cmd(struct irdma_sc_dev *dev, 6058 struct cqp_cmds_info *pcmdinfo) 6059 { 6060 int status; 6061 struct irdma_dma_mem val_mem; 6062 bool alloc = false; 6063 6064 dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++; 6065 switch (pcmdinfo->cqp_cmd) { 6066 case IRDMA_OP_CEQ_DESTROY: 6067 status = irdma_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq, 6068 pcmdinfo->in.u.ceq_destroy.scratch, 6069 pcmdinfo->post_sq); 6070 break; 6071 case IRDMA_OP_AEQ_DESTROY: 6072 status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq, 6073 pcmdinfo->in.u.aeq_destroy.scratch, 6074 pcmdinfo->post_sq); 6075 6076 break; 6077 case IRDMA_OP_CEQ_CREATE: 6078 status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq, 6079 pcmdinfo->in.u.ceq_create.scratch, 6080 pcmdinfo->post_sq); 6081 break; 6082 case IRDMA_OP_AEQ_CREATE: 6083 status = irdma_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq, 6084 pcmdinfo->in.u.aeq_create.scratch, 6085 pcmdinfo->post_sq); 6086 break; 6087 case IRDMA_OP_QP_UPLOAD_CONTEXT: 6088 status = irdma_sc_qp_upload_context(pcmdinfo->in.u.qp_upload_context.dev, 6089 &pcmdinfo->in.u.qp_upload_context.info, 6090 pcmdinfo->in.u.qp_upload_context.scratch, 6091 pcmdinfo->post_sq); 6092 break; 6093 case IRDMA_OP_CQ_CREATE: 6094 status = irdma_sc_cq_create(pcmdinfo->in.u.cq_create.cq, 6095 pcmdinfo->in.u.cq_create.scratch, 6096 pcmdinfo->in.u.cq_create.check_overflow, 6097 pcmdinfo->post_sq); 6098 break; 6099 case IRDMA_OP_CQ_MODIFY: 6100 status = irdma_sc_cq_modify(pcmdinfo->in.u.cq_modify.cq, 6101 &pcmdinfo->in.u.cq_modify.info, 6102 pcmdinfo->in.u.cq_modify.scratch, 6103 pcmdinfo->post_sq); 6104 break; 6105 case IRDMA_OP_CQ_DESTROY: 6106 status = irdma_sc_cq_destroy(pcmdinfo->in.u.cq_destroy.cq, 6107 pcmdinfo->in.u.cq_destroy.scratch, 6108 pcmdinfo->post_sq); 6109 break; 6110 case IRDMA_OP_QP_FLUSH_WQES: 6111 status = irdma_sc_qp_flush_wqes(pcmdinfo->in.u.qp_flush_wqes.qp, 6112 &pcmdinfo->in.u.qp_flush_wqes.info, 6113 pcmdinfo->in.u.qp_flush_wqes.scratch); 6114 break; 6115 case IRDMA_OP_GEN_AE: 6116 status = irdma_sc_gen_ae(pcmdinfo->in.u.gen_ae.qp, 6117 &pcmdinfo->in.u.gen_ae.info, 6118 pcmdinfo->in.u.gen_ae.scratch, 6119 pcmdinfo->post_sq); 6120 break; 6121 case IRDMA_OP_MANAGE_PUSH_PAGE: 6122 status = irdma_sc_manage_push_page(pcmdinfo->in.u.manage_push_page.cqp, 6123 &pcmdinfo->in.u.manage_push_page.info, 6124 pcmdinfo->in.u.manage_push_page.scratch, 6125 pcmdinfo->post_sq); 6126 break; 6127 case IRDMA_OP_UPDATE_PE_SDS: 6128 status = irdma_update_pe_sds(pcmdinfo->in.u.update_pe_sds.dev, 6129 &pcmdinfo->in.u.update_pe_sds.info, 6130 pcmdinfo->in.u.update_pe_sds.scratch); 6131 break; 6132 case IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE: 6133 /* switch to calling through the call table */ 6134 status = 6135 irdma_sc_manage_hmc_pm_func_table(pcmdinfo->in.u.manage_hmc_pm.dev->cqp, 6136 &pcmdinfo->in.u.manage_hmc_pm.info, 6137 pcmdinfo->in.u.manage_hmc_pm.scratch, 6138 true); 6139 break; 6140 case IRDMA_OP_SUSPEND: 6141 status = irdma_sc_suspend_qp(pcmdinfo->in.u.suspend_resume.cqp, 6142 pcmdinfo->in.u.suspend_resume.qp, 6143 pcmdinfo->in.u.suspend_resume.scratch); 6144 break; 6145 case IRDMA_OP_RESUME: 6146 status = irdma_sc_resume_qp(pcmdinfo->in.u.suspend_resume.cqp, 6147 pcmdinfo->in.u.suspend_resume.qp, 6148 pcmdinfo->in.u.suspend_resume.scratch); 6149 break; 6150 case IRDMA_OP_QUERY_FPM_VAL: 6151 val_mem.pa = pcmdinfo->in.u.query_fpm_val.fpm_val_pa; 6152 val_mem.va = pcmdinfo->in.u.query_fpm_val.fpm_val_va; 6153 status = irdma_sc_query_fpm_val(pcmdinfo->in.u.query_fpm_val.cqp, 6154 pcmdinfo->in.u.query_fpm_val.scratch, 6155 pcmdinfo->in.u.query_fpm_val.hmc_fn_id, 6156 &val_mem, true, IRDMA_CQP_WAIT_EVENT); 6157 break; 6158 case IRDMA_OP_COMMIT_FPM_VAL: 6159 val_mem.pa = pcmdinfo->in.u.commit_fpm_val.fpm_val_pa; 6160 val_mem.va = pcmdinfo->in.u.commit_fpm_val.fpm_val_va; 6161 status = irdma_sc_commit_fpm_val(pcmdinfo->in.u.commit_fpm_val.cqp, 6162 pcmdinfo->in.u.commit_fpm_val.scratch, 6163 pcmdinfo->in.u.commit_fpm_val.hmc_fn_id, 6164 &val_mem, 6165 true, 6166 IRDMA_CQP_WAIT_EVENT); 6167 break; 6168 case IRDMA_OP_STATS_ALLOCATE: 6169 alloc = true; 6170 fallthrough; 6171 case IRDMA_OP_STATS_FREE: 6172 status = irdma_sc_manage_stats_inst(pcmdinfo->in.u.stats_manage.cqp, 6173 &pcmdinfo->in.u.stats_manage.info, 6174 alloc, 6175 pcmdinfo->in.u.stats_manage.scratch); 6176 break; 6177 case IRDMA_OP_STATS_GATHER: 6178 status = irdma_sc_gather_stats(pcmdinfo->in.u.stats_gather.cqp, 6179 &pcmdinfo->in.u.stats_gather.info, 6180 pcmdinfo->in.u.stats_gather.scratch); 6181 break; 6182 case IRDMA_OP_WS_MODIFY_NODE: 6183 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 6184 &pcmdinfo->in.u.ws_node.info, 6185 IRDMA_MODIFY_NODE, 6186 pcmdinfo->in.u.ws_node.scratch); 6187 break; 6188 case IRDMA_OP_WS_DELETE_NODE: 6189 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 6190 &pcmdinfo->in.u.ws_node.info, 6191 IRDMA_DEL_NODE, 6192 pcmdinfo->in.u.ws_node.scratch); 6193 break; 6194 case IRDMA_OP_WS_ADD_NODE: 6195 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 6196 &pcmdinfo->in.u.ws_node.info, 6197 IRDMA_ADD_NODE, 6198 pcmdinfo->in.u.ws_node.scratch); 6199 break; 6200 case IRDMA_OP_SET_UP_MAP: 6201 status = irdma_sc_set_up_map(pcmdinfo->in.u.up_map.cqp, 6202 &pcmdinfo->in.u.up_map.info, 6203 pcmdinfo->in.u.up_map.scratch); 6204 break; 6205 case IRDMA_OP_QUERY_RDMA_FEATURES: 6206 status = irdma_sc_query_rdma_features(pcmdinfo->in.u.query_rdma.cqp, 6207 &pcmdinfo->in.u.query_rdma.query_buff_mem, 6208 pcmdinfo->in.u.query_rdma.scratch); 6209 break; 6210 case IRDMA_OP_DELETE_ARP_CACHE_ENTRY: 6211 status = irdma_sc_del_arp_cache_entry(pcmdinfo->in.u.del_arp_cache_entry.cqp, 6212 pcmdinfo->in.u.del_arp_cache_entry.scratch, 6213 pcmdinfo->in.u.del_arp_cache_entry.arp_index, 6214 pcmdinfo->post_sq); 6215 break; 6216 case IRDMA_OP_MANAGE_APBVT_ENTRY: 6217 status = irdma_sc_manage_apbvt_entry(pcmdinfo->in.u.manage_apbvt_entry.cqp, 6218 &pcmdinfo->in.u.manage_apbvt_entry.info, 6219 pcmdinfo->in.u.manage_apbvt_entry.scratch, 6220 pcmdinfo->post_sq); 6221 break; 6222 case IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY: 6223 status = irdma_sc_manage_qhash_table_entry(pcmdinfo->in.u.manage_qhash_table_entry.cqp, 6224 &pcmdinfo->in.u.manage_qhash_table_entry.info, 6225 pcmdinfo->in.u.manage_qhash_table_entry.scratch, 6226 pcmdinfo->post_sq); 6227 break; 6228 case IRDMA_OP_QP_MODIFY: 6229 status = irdma_sc_qp_modify(pcmdinfo->in.u.qp_modify.qp, 6230 &pcmdinfo->in.u.qp_modify.info, 6231 pcmdinfo->in.u.qp_modify.scratch, 6232 pcmdinfo->post_sq); 6233 break; 6234 case IRDMA_OP_QP_CREATE: 6235 status = irdma_sc_qp_create(pcmdinfo->in.u.qp_create.qp, 6236 &pcmdinfo->in.u.qp_create.info, 6237 pcmdinfo->in.u.qp_create.scratch, 6238 pcmdinfo->post_sq); 6239 break; 6240 case IRDMA_OP_QP_DESTROY: 6241 status = irdma_sc_qp_destroy(pcmdinfo->in.u.qp_destroy.qp, 6242 pcmdinfo->in.u.qp_destroy.scratch, 6243 pcmdinfo->in.u.qp_destroy.remove_hash_idx, 6244 pcmdinfo->in.u.qp_destroy.ignore_mw_bnd, 6245 pcmdinfo->post_sq); 6246 break; 6247 case IRDMA_OP_ALLOC_STAG: 6248 status = irdma_sc_alloc_stag(pcmdinfo->in.u.alloc_stag.dev, 6249 &pcmdinfo->in.u.alloc_stag.info, 6250 pcmdinfo->in.u.alloc_stag.scratch, 6251 pcmdinfo->post_sq); 6252 break; 6253 case IRDMA_OP_MR_REG_NON_SHARED: 6254 status = irdma_sc_mr_reg_non_shared(pcmdinfo->in.u.mr_reg_non_shared.dev, 6255 &pcmdinfo->in.u.mr_reg_non_shared.info, 6256 pcmdinfo->in.u.mr_reg_non_shared.scratch, 6257 pcmdinfo->post_sq); 6258 break; 6259 case IRDMA_OP_DEALLOC_STAG: 6260 status = irdma_sc_dealloc_stag(pcmdinfo->in.u.dealloc_stag.dev, 6261 &pcmdinfo->in.u.dealloc_stag.info, 6262 pcmdinfo->in.u.dealloc_stag.scratch, 6263 pcmdinfo->post_sq); 6264 break; 6265 case IRDMA_OP_MW_ALLOC: 6266 status = irdma_sc_mw_alloc(pcmdinfo->in.u.mw_alloc.dev, 6267 &pcmdinfo->in.u.mw_alloc.info, 6268 pcmdinfo->in.u.mw_alloc.scratch, 6269 pcmdinfo->post_sq); 6270 break; 6271 case IRDMA_OP_ADD_ARP_CACHE_ENTRY: 6272 status = irdma_sc_add_arp_cache_entry(pcmdinfo->in.u.add_arp_cache_entry.cqp, 6273 &pcmdinfo->in.u.add_arp_cache_entry.info, 6274 pcmdinfo->in.u.add_arp_cache_entry.scratch, 6275 pcmdinfo->post_sq); 6276 break; 6277 case IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY: 6278 status = irdma_sc_alloc_local_mac_entry(pcmdinfo->in.u.alloc_local_mac_entry.cqp, 6279 pcmdinfo->in.u.alloc_local_mac_entry.scratch, 6280 pcmdinfo->post_sq); 6281 break; 6282 case IRDMA_OP_ADD_LOCAL_MAC_ENTRY: 6283 status = irdma_sc_add_local_mac_entry(pcmdinfo->in.u.add_local_mac_entry.cqp, 6284 &pcmdinfo->in.u.add_local_mac_entry.info, 6285 pcmdinfo->in.u.add_local_mac_entry.scratch, 6286 pcmdinfo->post_sq); 6287 break; 6288 case IRDMA_OP_DELETE_LOCAL_MAC_ENTRY: 6289 status = irdma_sc_del_local_mac_entry(pcmdinfo->in.u.del_local_mac_entry.cqp, 6290 pcmdinfo->in.u.del_local_mac_entry.scratch, 6291 pcmdinfo->in.u.del_local_mac_entry.entry_idx, 6292 pcmdinfo->in.u.del_local_mac_entry.ignore_ref_count, 6293 pcmdinfo->post_sq); 6294 break; 6295 case IRDMA_OP_AH_CREATE: 6296 status = irdma_sc_create_ah(pcmdinfo->in.u.ah_create.cqp, 6297 &pcmdinfo->in.u.ah_create.info, 6298 pcmdinfo->in.u.ah_create.scratch); 6299 break; 6300 case IRDMA_OP_AH_DESTROY: 6301 status = irdma_sc_destroy_ah(pcmdinfo->in.u.ah_destroy.cqp, 6302 &pcmdinfo->in.u.ah_destroy.info, 6303 pcmdinfo->in.u.ah_destroy.scratch); 6304 break; 6305 case IRDMA_OP_MC_CREATE: 6306 status = irdma_sc_create_mcast_grp(pcmdinfo->in.u.mc_create.cqp, 6307 &pcmdinfo->in.u.mc_create.info, 6308 pcmdinfo->in.u.mc_create.scratch); 6309 break; 6310 case IRDMA_OP_MC_DESTROY: 6311 status = irdma_sc_destroy_mcast_grp(pcmdinfo->in.u.mc_destroy.cqp, 6312 &pcmdinfo->in.u.mc_destroy.info, 6313 pcmdinfo->in.u.mc_destroy.scratch); 6314 break; 6315 case IRDMA_OP_MC_MODIFY: 6316 status = irdma_sc_modify_mcast_grp(pcmdinfo->in.u.mc_modify.cqp, 6317 &pcmdinfo->in.u.mc_modify.info, 6318 pcmdinfo->in.u.mc_modify.scratch); 6319 break; 6320 case IRDMA_OP_SRQ_CREATE: 6321 status = irdma_sc_srq_create(pcmdinfo->in.u.srq_create.srq, 6322 pcmdinfo->in.u.srq_create.scratch, 6323 pcmdinfo->post_sq); 6324 break; 6325 case IRDMA_OP_SRQ_MODIFY: 6326 status = irdma_sc_srq_modify(pcmdinfo->in.u.srq_modify.srq, 6327 &pcmdinfo->in.u.srq_modify.info, 6328 pcmdinfo->in.u.srq_modify.scratch, 6329 pcmdinfo->post_sq); 6330 break; 6331 case IRDMA_OP_SRQ_DESTROY: 6332 status = irdma_sc_srq_destroy(pcmdinfo->in.u.srq_destroy.srq, 6333 pcmdinfo->in.u.srq_destroy.scratch, 6334 pcmdinfo->post_sq); 6335 break; 6336 default: 6337 status = -EOPNOTSUPP; 6338 break; 6339 } 6340 6341 return status; 6342 } 6343 6344 /** 6345 * irdma_process_cqp_cmd - process all cqp commands 6346 * @dev: sc device struct 6347 * @pcmdinfo: cqp command info 6348 */ 6349 int irdma_process_cqp_cmd(struct irdma_sc_dev *dev, 6350 struct cqp_cmds_info *pcmdinfo) 6351 { 6352 int status = 0; 6353 unsigned long flags; 6354 6355 spin_lock_irqsave(&dev->cqp_lock, flags); 6356 if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp)) 6357 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 6358 else 6359 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head); 6360 spin_unlock_irqrestore(&dev->cqp_lock, flags); 6361 return status; 6362 } 6363 6364 /** 6365 * irdma_process_bh - called from tasklet for cqp list 6366 * @dev: sc device struct 6367 */ 6368 int irdma_process_bh(struct irdma_sc_dev *dev) 6369 { 6370 int status = 0; 6371 struct cqp_cmds_info *pcmdinfo; 6372 unsigned long flags; 6373 6374 spin_lock_irqsave(&dev->cqp_lock, flags); 6375 while (!list_empty(&dev->cqp_cmd_head) && 6376 !irdma_cqp_ring_full(dev->cqp)) { 6377 pcmdinfo = (struct cqp_cmds_info *)irdma_remove_cqp_head(dev); 6378 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 6379 if (status) 6380 break; 6381 } 6382 spin_unlock_irqrestore(&dev->cqp_lock, flags); 6383 return status; 6384 } 6385 6386 /** 6387 * irdma_cfg_aeq- Configure AEQ interrupt 6388 * @dev: pointer to the device structure 6389 * @idx: vector index 6390 * @enable: True to enable, False disables 6391 */ 6392 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable) 6393 { 6394 u32 reg_val; 6395 6396 reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) | 6397 FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) | 6398 FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, 3); 6399 writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 6400 } 6401 6402 /** 6403 * sc_vsi_update_stats - Update statistics 6404 * @vsi: sc_vsi instance to update 6405 */ 6406 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi) 6407 { 6408 struct irdma_dev_hw_stats *hw_stats = &vsi->pestat->hw_stats; 6409 struct irdma_gather_stats *gather_stats = 6410 vsi->pestat->gather_info.gather_stats_va; 6411 struct irdma_gather_stats *last_gather_stats = 6412 vsi->pestat->gather_info.last_gather_stats_va; 6413 const struct irdma_hw_stat_map *map = vsi->dev->hw_stats_map; 6414 u16 max_stat_idx = vsi->dev->hw_attrs.max_stat_idx; 6415 u16 i; 6416 6417 if (vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { 6418 for (i = 0; i < max_stat_idx; i++) { 6419 u16 idx = map[i].byteoff / sizeof(u64); 6420 6421 hw_stats->stats_val[i] = gather_stats->val[idx]; 6422 } 6423 return; 6424 } 6425 6426 irdma_update_stats(hw_stats, gather_stats, last_gather_stats, 6427 map, max_stat_idx); 6428 } 6429 6430 /** 6431 * irdma_wait_pe_ready - Check if firmware is ready 6432 * @dev: provides access to registers 6433 */ 6434 static int irdma_wait_pe_ready(struct irdma_sc_dev *dev) 6435 { 6436 u32 statuscpu0; 6437 u32 statuscpu1; 6438 u32 statuscpu2; 6439 u32 retrycount = 0; 6440 6441 do { 6442 statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]); 6443 statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]); 6444 statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]); 6445 if (statuscpu0 == 0x80 && statuscpu1 == 0x80 && 6446 statuscpu2 == 0x80) 6447 return 0; 6448 mdelay(1000); 6449 } while (retrycount++ < dev->hw_attrs.max_pe_ready_count); 6450 return -1; 6451 } 6452 6453 static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev) 6454 { 6455 switch (dev->hw_attrs.uk_attrs.hw_rev) { 6456 case IRDMA_GEN_1: 6457 i40iw_init_hw(dev); 6458 break; 6459 case IRDMA_GEN_2: 6460 icrdma_init_hw(dev); 6461 break; 6462 case IRDMA_GEN_3: 6463 case IRDMA_GEN_4: 6464 ig3rdma_init_hw(dev); 6465 break; 6466 } 6467 } 6468 6469 /** 6470 * irdma_sc_dev_init - Initialize control part of device 6471 * @ver: version 6472 * @dev: Device pointer 6473 * @info: Device init info 6474 */ 6475 int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev, 6476 struct irdma_device_init_info *info) 6477 { 6478 u32 val; 6479 int ret_code = 0; 6480 u8 db_size; 6481 6482 spin_lock_init(&dev->puda_cq_lock); 6483 dev->ilq_cq = NULL; 6484 dev->ieq_cq = NULL; 6485 INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */ 6486 mutex_init(&dev->ws_mutex); 6487 dev->hmc_fn_id = info->hmc_fn_id; 6488 dev->fpm_query_buf_pa = info->fpm_query_buf_pa; 6489 dev->fpm_query_buf = info->fpm_query_buf; 6490 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa; 6491 dev->fpm_commit_buf = info->fpm_commit_buf; 6492 dev->hw = info->hw; 6493 dev->hw->hw_addr = info->bar0; 6494 dev->protocol_used = info->protocol_used; 6495 /* Setup the hardware limits, hmc may limit further */ 6496 dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID; 6497 dev->hw_attrs.min_hw_srq_id = IRDMA_MIN_IW_SRQ_ID; 6498 dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES; 6499 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 6500 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES_GEN_3; 6501 else 6502 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES; 6503 dev->hw_attrs.min_hw_ceq_size = IRDMA_MIN_CEQ_ENTRIES; 6504 dev->hw_attrs.max_hw_ceq_size = IRDMA_MAX_CEQ_ENTRIES; 6505 dev->hw_attrs.uk_attrs.min_hw_cq_size = IRDMA_MIN_CQ_SIZE; 6506 dev->hw_attrs.uk_attrs.max_hw_cq_size = IRDMA_MAX_CQ_SIZE; 6507 dev->hw_attrs.uk_attrs.max_hw_wq_frags = IRDMA_MAX_WQ_FRAGMENT_COUNT; 6508 dev->hw_attrs.uk_attrs.max_hw_read_sges = IRDMA_MAX_SGE_RD; 6509 dev->hw_attrs.max_hw_outbound_msg_size = IRDMA_MAX_OUTBOUND_MSG_SIZE; 6510 dev->hw_attrs.max_mr_size = IRDMA_MAX_MR_SIZE; 6511 dev->hw_attrs.max_hw_inbound_msg_size = IRDMA_MAX_INBOUND_MSG_SIZE; 6512 dev->hw_attrs.max_hw_device_pages = IRDMA_MAX_PUSH_PAGE_COUNT; 6513 dev->hw_attrs.uk_attrs.max_hw_inline = IRDMA_MAX_INLINE_DATA_SIZE; 6514 dev->hw_attrs.max_hw_wqes = IRDMA_MAX_WQ_ENTRIES; 6515 dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(IRDMA_MAX_QUANTA_PER_WR); 6516 6517 dev->hw_attrs.uk_attrs.max_hw_rq_quanta = IRDMA_QP_SW_MAX_RQ_QUANTA; 6518 dev->hw_attrs.uk_attrs.max_hw_wq_quanta = IRDMA_QP_SW_MAX_WQ_QUANTA; 6519 dev->hw_attrs.max_hw_pds = IRDMA_MAX_PDS; 6520 dev->hw_attrs.max_hw_ena_vf_count = IRDMA_MAX_PE_ENA_VF_COUNT; 6521 6522 dev->hw_attrs.max_pe_ready_count = 14; 6523 dev->hw_attrs.max_done_count = IRDMA_DONE_COUNT; 6524 dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT; 6525 dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS; 6526 6527 if (!dev->privileged) { 6528 ret_code = irdma_vchnl_req_get_hmc_fcn(dev); 6529 if (ret_code) { 6530 ibdev_dbg(to_ibdev(dev), 6531 "DEV: Get HMC function ret = %d\n", 6532 ret_code); 6533 6534 return ret_code; 6535 } 6536 } 6537 6538 irdma_sc_init_hw(dev); 6539 6540 if (dev->privileged) { 6541 if (irdma_wait_pe_ready(dev)) 6542 return -ETIMEDOUT; 6543 6544 val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]); 6545 db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val); 6546 if (db_size != IRDMA_PE_DB_SIZE_4M && 6547 db_size != IRDMA_PE_DB_SIZE_8M) { 6548 ibdev_dbg(to_ibdev(dev), 6549 "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n", 6550 val, db_size); 6551 return -ENODEV; 6552 } 6553 } else { 6554 ret_code = irdma_vchnl_req_get_reg_layout(dev); 6555 if (ret_code) 6556 ibdev_dbg(to_ibdev(dev), 6557 "DEV: Get Register layout failed ret = %d\n", 6558 ret_code); 6559 } 6560 6561 return ret_code; 6562 } 6563 6564 /** 6565 * irdma_stat_val - Extract HW counter value from statistics buffer 6566 * @stats_val: pointer to statistics buffer 6567 * @byteoff: byte offset of counter value in the buffer (8B-aligned) 6568 * @bitoff: bit offset of counter value within 8B entry 6569 * @bitmask: maximum counter value (e.g. 0xffffff for 24-bit counter) 6570 */ 6571 static inline u64 irdma_stat_val(const u64 *stats_val, u16 byteoff, u8 bitoff, 6572 u64 bitmask) 6573 { 6574 u16 idx = byteoff / sizeof(*stats_val); 6575 6576 return (stats_val[idx] >> bitoff) & bitmask; 6577 } 6578 6579 /** 6580 * irdma_stat_delta - Calculate counter delta 6581 * @new_val: updated counter value 6582 * @old_val: last counter value 6583 * @max_val: maximum counter value (e.g. 0xffffff for 24-bit counter) 6584 */ 6585 static inline u64 irdma_stat_delta(u64 new_val, u64 old_val, u64 max_val) 6586 { 6587 if (new_val >= old_val) 6588 return new_val - old_val; 6589 6590 /* roll-over case */ 6591 return max_val - old_val + new_val + 1; 6592 } 6593 6594 /** 6595 * irdma_update_stats - Update statistics 6596 * @hw_stats: hw_stats instance to update 6597 * @gather_stats: updated stat counters 6598 * @last_gather_stats: last stat counters 6599 * @map: HW stat map (hw_stats => gather_stats) 6600 * @max_stat_idx: number of HW stats 6601 */ 6602 void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats, 6603 struct irdma_gather_stats *gather_stats, 6604 struct irdma_gather_stats *last_gather_stats, 6605 const struct irdma_hw_stat_map *map, u16 max_stat_idx) 6606 { 6607 u64 *stats_val = hw_stats->stats_val; 6608 u16 i; 6609 6610 for (i = 0; i < max_stat_idx; i++) { 6611 u64 new_val = irdma_stat_val(gather_stats->val, map[i].byteoff, 6612 map[i].bitoff, map[i].bitmask); 6613 u64 last_val = irdma_stat_val(last_gather_stats->val, 6614 map[i].byteoff, map[i].bitoff, 6615 map[i].bitmask); 6616 6617 stats_val[i] += 6618 irdma_stat_delta(new_val, last_val, map[i].bitmask); 6619 } 6620 6621 memcpy(last_gather_stats, gather_stats, sizeof(*last_gather_stats)); 6622 } 6623