1*8d765af5SAbhijit Gangurde /* SPDX-License-Identifier: GPL-2.0 */ 2*8d765af5SAbhijit Gangurde /* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ 3*8d765af5SAbhijit Gangurde 4*8d765af5SAbhijit Gangurde #ifndef _IONIC_LIF_CFG_H_ 5*8d765af5SAbhijit Gangurde 6*8d765af5SAbhijit Gangurde #define IONIC_VERSION(a, b) (((a) << 16) + ((b) << 8)) 7*8d765af5SAbhijit Gangurde #define IONIC_PAGE_SIZE_SUPPORTED 0x40201000 /* 4kb, 2Mb, 1Gb */ 8*8d765af5SAbhijit Gangurde 9*8d765af5SAbhijit Gangurde #define IONIC_EXPDB_64B_WQE BIT(0) 10*8d765af5SAbhijit Gangurde #define IONIC_EXPDB_128B_WQE BIT(1) 11*8d765af5SAbhijit Gangurde #define IONIC_EXPDB_256B_WQE BIT(2) 12*8d765af5SAbhijit Gangurde #define IONIC_EXPDB_512B_WQE BIT(3) 13*8d765af5SAbhijit Gangurde 14*8d765af5SAbhijit Gangurde struct ionic_lif_cfg { 15*8d765af5SAbhijit Gangurde struct device *hwdev; 16*8d765af5SAbhijit Gangurde struct ionic_lif *lif; 17*8d765af5SAbhijit Gangurde 18*8d765af5SAbhijit Gangurde int lif_index; 19*8d765af5SAbhijit Gangurde int lif_hw_index; 20*8d765af5SAbhijit Gangurde 21*8d765af5SAbhijit Gangurde u32 dbid; 22*8d765af5SAbhijit Gangurde int dbid_count; 23*8d765af5SAbhijit Gangurde u64 __iomem *dbpage; 24*8d765af5SAbhijit Gangurde struct ionic_intr __iomem *intr_ctrl; 25*8d765af5SAbhijit Gangurde phys_addr_t db_phys; 26*8d765af5SAbhijit Gangurde 27*8d765af5SAbhijit Gangurde u64 page_size_supported; 28*8d765af5SAbhijit Gangurde u32 npts_per_lif; 29*8d765af5SAbhijit Gangurde u32 nmrs_per_lif; 30*8d765af5SAbhijit Gangurde u32 nahs_per_lif; 31*8d765af5SAbhijit Gangurde 32*8d765af5SAbhijit Gangurde u32 aq_base; 33*8d765af5SAbhijit Gangurde u32 cq_base; 34*8d765af5SAbhijit Gangurde u32 eq_base; 35*8d765af5SAbhijit Gangurde 36*8d765af5SAbhijit Gangurde int aq_count; 37*8d765af5SAbhijit Gangurde int eq_count; 38*8d765af5SAbhijit Gangurde int cq_count; 39*8d765af5SAbhijit Gangurde int qp_count; 40*8d765af5SAbhijit Gangurde 41*8d765af5SAbhijit Gangurde u16 stats_type; 42*8d765af5SAbhijit Gangurde u8 aq_qtype; 43*8d765af5SAbhijit Gangurde u8 sq_qtype; 44*8d765af5SAbhijit Gangurde u8 rq_qtype; 45*8d765af5SAbhijit Gangurde u8 cq_qtype; 46*8d765af5SAbhijit Gangurde u8 eq_qtype; 47*8d765af5SAbhijit Gangurde 48*8d765af5SAbhijit Gangurde u8 udma_count; 49*8d765af5SAbhijit Gangurde u8 udma_qgrp_shift; 50*8d765af5SAbhijit Gangurde 51*8d765af5SAbhijit Gangurde u8 rdma_version; 52*8d765af5SAbhijit Gangurde u8 qp_opcodes; 53*8d765af5SAbhijit Gangurde u8 admin_opcodes; 54*8d765af5SAbhijit Gangurde 55*8d765af5SAbhijit Gangurde u8 max_stride; 56*8d765af5SAbhijit Gangurde bool sq_expdb; 57*8d765af5SAbhijit Gangurde bool rq_expdb; 58*8d765af5SAbhijit Gangurde u8 expdb_mask; 59*8d765af5SAbhijit Gangurde }; 60*8d765af5SAbhijit Gangurde 61*8d765af5SAbhijit Gangurde void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg); 62*8d765af5SAbhijit Gangurde struct net_device *ionic_lif_netdev(struct ionic_lif *lif); 63*8d765af5SAbhijit Gangurde 64*8d765af5SAbhijit Gangurde #endif /* _IONIC_LIF_CFG_H_ */ 65