1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ 3 4 #include <linux/kernel.h> 5 6 #include <ionic.h> 7 #include <ionic_lif.h> 8 9 #include "ionic_lif_cfg.h" 10 11 #define IONIC_MIN_RDMA_VERSION 0 12 #define IONIC_MAX_RDMA_VERSION 2 13 14 static u8 ionic_get_expdb(struct ionic_lif *lif) 15 { 16 u8 expdb_support = 0; 17 18 if (lif->ionic->idev.phy_cmb_expdb64_pages) 19 expdb_support |= IONIC_EXPDB_64B_WQE; 20 if (lif->ionic->idev.phy_cmb_expdb128_pages) 21 expdb_support |= IONIC_EXPDB_128B_WQE; 22 if (lif->ionic->idev.phy_cmb_expdb256_pages) 23 expdb_support |= IONIC_EXPDB_256B_WQE; 24 if (lif->ionic->idev.phy_cmb_expdb512_pages) 25 expdb_support |= IONIC_EXPDB_512B_WQE; 26 27 return expdb_support; 28 } 29 30 void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg) 31 { 32 union ionic_lif_identity *ident = &lif->ionic->ident.lif; 33 34 cfg->lif = lif; 35 cfg->hwdev = &lif->ionic->pdev->dev; 36 cfg->lif_index = lif->index; 37 cfg->lif_hw_index = lif->hw_index; 38 39 cfg->dbid = lif->kern_pid; 40 cfg->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 41 cfg->dbpage = lif->kern_dbpage; 42 cfg->intr_ctrl = lif->ionic->idev.intr_ctrl; 43 44 cfg->db_phys = lif->ionic->bars[IONIC_PCI_BAR_DBELL].bus_addr; 45 46 if (IONIC_VERSION(ident->rdma.version, ident->rdma.minor_version) >= 47 IONIC_VERSION(2, 1)) 48 cfg->page_size_supported = 49 le64_to_cpu(ident->rdma.page_size_cap); 50 else 51 cfg->page_size_supported = IONIC_PAGE_SIZE_SUPPORTED; 52 53 cfg->rdma_version = ident->rdma.version; 54 cfg->qp_opcodes = ident->rdma.qp_opcodes; 55 cfg->admin_opcodes = ident->rdma.admin_opcodes; 56 57 cfg->stats_type = le16_to_cpu(ident->rdma.stats_type); 58 cfg->npts_per_lif = le32_to_cpu(ident->rdma.npts_per_lif); 59 cfg->nmrs_per_lif = le32_to_cpu(ident->rdma.nmrs_per_lif); 60 cfg->nahs_per_lif = le32_to_cpu(ident->rdma.nahs_per_lif); 61 62 cfg->aq_base = le32_to_cpu(ident->rdma.aq_qtype.qid_base); 63 cfg->cq_base = le32_to_cpu(ident->rdma.cq_qtype.qid_base); 64 cfg->eq_base = le32_to_cpu(ident->rdma.eq_qtype.qid_base); 65 66 /* 67 * ionic_create_rdma_admin() may reduce aq_count or eq_count if 68 * it is unable to allocate all that were requested. 69 * aq_count is tunable; see ionic_aq_count 70 * eq_count is tunable; see ionic_eq_count 71 */ 72 cfg->aq_count = le32_to_cpu(ident->rdma.aq_qtype.qid_count); 73 cfg->eq_count = le32_to_cpu(ident->rdma.eq_qtype.qid_count); 74 cfg->cq_count = le32_to_cpu(ident->rdma.cq_qtype.qid_count); 75 cfg->qp_count = le32_to_cpu(ident->rdma.sq_qtype.qid_count); 76 cfg->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 77 78 cfg->aq_qtype = ident->rdma.aq_qtype.qtype; 79 cfg->sq_qtype = ident->rdma.sq_qtype.qtype; 80 cfg->rq_qtype = ident->rdma.rq_qtype.qtype; 81 cfg->cq_qtype = ident->rdma.cq_qtype.qtype; 82 cfg->eq_qtype = ident->rdma.eq_qtype.qtype; 83 cfg->udma_qgrp_shift = ident->rdma.udma_shift; 84 cfg->udma_count = 2; 85 86 cfg->max_stride = ident->rdma.max_stride; 87 cfg->expdb_mask = ionic_get_expdb(lif); 88 89 cfg->sq_expdb = 90 !!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_EXPDB); 91 cfg->rq_expdb = 92 !!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_EXPDB); 93 } 94 95 struct net_device *ionic_lif_netdev(struct ionic_lif *lif) 96 { 97 struct net_device *netdev = lif->netdev; 98 99 dev_hold(netdev); 100 return netdev; 101 } 102 103 void ionic_lif_fw_version(struct ionic_lif *lif, char *str, size_t len) 104 { 105 strscpy(str, lif->ionic->idev.dev_info.fw_version, len); 106 } 107 108 u8 ionic_lif_asic_rev(struct ionic_lif *lif) 109 { 110 return lif->ionic->idev.dev_info.asic_rev; 111 } 112