1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ 3 4 #ifndef _IONIC_IBDEV_H_ 5 #define _IONIC_IBDEV_H_ 6 7 #include <rdma/ib_umem.h> 8 #include <rdma/ib_verbs.h> 9 10 #include <ionic_api.h> 11 #include <ionic_regs.h> 12 13 #include "ionic_fw.h" 14 #include "ionic_queue.h" 15 #include "ionic_res.h" 16 17 #include "ionic_lif_cfg.h" 18 19 /* Config knobs */ 20 #define IONIC_EQ_DEPTH 511 21 #define IONIC_EQ_COUNT 32 22 #define IONIC_AQ_DEPTH 63 23 #define IONIC_AQ_COUNT 4 24 #define IONIC_EQ_ISR_BUDGET 10 25 #define IONIC_EQ_WORK_BUDGET 1000 26 #define IONIC_MAX_PD 1024 27 28 #define IONIC_CQ_GRACE 100 29 30 struct ionic_aq; 31 struct ionic_cq; 32 struct ionic_eq; 33 struct ionic_vcq; 34 35 enum ionic_admin_state { 36 IONIC_ADMIN_ACTIVE, /* submitting admin commands to queue */ 37 IONIC_ADMIN_PAUSED, /* not submitting, but may complete normally */ 38 IONIC_ADMIN_KILLED, /* not submitting, locally completed */ 39 }; 40 41 enum ionic_admin_flags { 42 IONIC_ADMIN_F_BUSYWAIT = BIT(0), /* Don't sleep */ 43 IONIC_ADMIN_F_TEARDOWN = BIT(1), /* In destroy path */ 44 IONIC_ADMIN_F_INTERRUPT = BIT(2), /* Interruptible w/timeout */ 45 }; 46 47 struct ionic_qdesc { 48 __aligned_u64 addr; 49 __u32 size; 50 __u16 mask; 51 __u8 depth_log2; 52 __u8 stride_log2; 53 }; 54 55 enum ionic_mmap_flag { 56 IONIC_MMAP_WC = BIT(0), 57 }; 58 59 struct ionic_mmap_entry { 60 struct rdma_user_mmap_entry rdma_entry; 61 unsigned long size; 62 unsigned long pfn; 63 u8 mmap_flags; 64 }; 65 66 struct ionic_ibdev { 67 struct ib_device ibdev; 68 69 struct ionic_lif_cfg lif_cfg; 70 71 struct xarray qp_tbl; 72 struct xarray cq_tbl; 73 74 struct ionic_resid_bits inuse_dbid; 75 struct ionic_resid_bits inuse_pdid; 76 struct ionic_resid_bits inuse_ahid; 77 struct ionic_resid_bits inuse_mrid; 78 struct ionic_resid_bits inuse_qpid; 79 struct ionic_resid_bits inuse_cqid; 80 81 u8 half_cqid_udma_shift; 82 u8 half_qpid_udma_shift; 83 u8 next_qpid_udma_idx; 84 u8 next_mrkey; 85 86 struct work_struct reset_work; 87 bool reset_posted; 88 u32 reset_cnt; 89 90 struct delayed_work admin_dwork; 91 struct ionic_aq **aq_vec; 92 atomic_t admin_state; 93 94 struct ionic_eq **eq_vec; 95 }; 96 97 struct ionic_eq { 98 struct ionic_ibdev *dev; 99 100 u32 eqid; 101 u32 intr; 102 103 struct ionic_queue q; 104 105 bool armed; 106 bool enable; 107 108 struct work_struct work; 109 110 int irq; 111 char name[32]; 112 }; 113 114 struct ionic_admin_wr { 115 struct completion work; 116 struct list_head aq_ent; 117 struct ionic_v1_admin_wqe wqe; 118 struct ionic_v1_cqe cqe; 119 struct ionic_aq *aq; 120 int status; 121 }; 122 123 struct ionic_admin_wr_q { 124 struct ionic_admin_wr *wr; 125 int wqe_strides; 126 }; 127 128 struct ionic_aq { 129 struct ionic_ibdev *dev; 130 struct ionic_vcq *vcq; 131 132 struct work_struct work; 133 134 atomic_t admin_state; 135 unsigned long stamp; 136 bool armed; 137 138 u32 aqid; 139 u32 cqid; 140 141 spinlock_t lock; /* for posting */ 142 struct ionic_queue q; 143 struct ionic_admin_wr_q *q_wr; 144 struct list_head wr_prod; 145 struct list_head wr_post; 146 }; 147 148 struct ionic_ctx { 149 struct ib_ucontext ibctx; 150 u32 dbid; 151 struct rdma_user_mmap_entry *mmap_dbell; 152 }; 153 154 struct ionic_tbl_buf { 155 u32 tbl_limit; 156 u32 tbl_pages; 157 size_t tbl_size; 158 __le64 *tbl_buf; 159 dma_addr_t tbl_dma; 160 u8 page_size_log2; 161 }; 162 163 struct ionic_cq { 164 struct ionic_vcq *vcq; 165 166 u32 cqid; 167 u32 eqid; 168 169 spinlock_t lock; /* for polling */ 170 struct list_head poll_sq; 171 bool flush; 172 struct list_head flush_sq; 173 struct list_head flush_rq; 174 struct list_head ibkill_flush_ent; 175 176 struct ionic_queue q; 177 bool color; 178 int credit; 179 u16 arm_any_prod; 180 u16 arm_sol_prod; 181 182 struct kref cq_kref; 183 struct completion cq_rel_comp; 184 185 /* infrequently accessed, keep at end */ 186 struct ib_umem *umem; 187 }; 188 189 struct ionic_vcq { 190 struct ib_cq ibcq; 191 struct ionic_cq cq[2]; 192 u8 udma_mask; 193 u8 poll_idx; 194 }; 195 196 static inline struct ionic_ibdev *to_ionic_ibdev(struct ib_device *ibdev) 197 { 198 return container_of(ibdev, struct ionic_ibdev, ibdev); 199 } 200 201 static inline void ionic_cq_complete(struct kref *kref) 202 { 203 struct ionic_cq *cq = container_of(kref, struct ionic_cq, cq_kref); 204 205 complete(&cq->cq_rel_comp); 206 } 207 208 /* ionic_admin.c */ 209 extern struct workqueue_struct *ionic_evt_workq; 210 void ionic_admin_post(struct ionic_ibdev *dev, struct ionic_admin_wr *wr); 211 int ionic_admin_wait(struct ionic_ibdev *dev, struct ionic_admin_wr *wr, 212 enum ionic_admin_flags); 213 214 int ionic_rdma_reset_devcmd(struct ionic_ibdev *dev); 215 216 int ionic_create_rdma_admin(struct ionic_ibdev *dev); 217 void ionic_destroy_rdma_admin(struct ionic_ibdev *dev); 218 void ionic_kill_rdma_admin(struct ionic_ibdev *dev, bool fatal_path); 219 220 /* ionic_controlpath.c */ 221 int ionic_create_cq_common(struct ionic_vcq *vcq, 222 struct ionic_tbl_buf *buf, 223 const struct ib_cq_init_attr *attr, 224 struct ionic_ctx *ctx, 225 struct ib_udata *udata, 226 struct ionic_qdesc *req_cq, 227 __u32 *resp_cqid, 228 int udma_idx); 229 void ionic_destroy_cq_common(struct ionic_ibdev *dev, struct ionic_cq *cq); 230 231 /* ionic_pgtbl.c */ 232 int ionic_pgtbl_page(struct ionic_tbl_buf *buf, u64 dma); 233 int ionic_pgtbl_init(struct ionic_ibdev *dev, 234 struct ionic_tbl_buf *buf, 235 struct ib_umem *umem, 236 dma_addr_t dma, 237 int limit, 238 u64 page_size); 239 void ionic_pgtbl_unbuf(struct ionic_ibdev *dev, struct ionic_tbl_buf *buf); 240 #endif /* _IONIC_IBDEV_H_ */ 241