1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ 3 4 #ifndef _IONIC_FW_H_ 5 #define _IONIC_FW_H_ 6 7 #include <linux/kernel.h> 8 9 /* completion queue v1 cqe */ 10 struct ionic_v1_cqe { 11 union { 12 struct { 13 __be16 cmd_idx; 14 __u8 cmd_op; 15 __u8 rsvd[17]; 16 __le16 old_sq_cindex; 17 __le16 old_rq_cq_cindex; 18 } admin; 19 struct { 20 __u64 wqe_id; 21 __be32 src_qpn_op; 22 __u8 src_mac[6]; 23 __be16 vlan_tag; 24 __be32 imm_data_rkey; 25 } recv; 26 struct { 27 __u8 rsvd[4]; 28 __be32 msg_msn; 29 __u8 rsvd2[8]; 30 __u64 npg_wqe_id; 31 } send; 32 }; 33 __be32 status_length; 34 __be32 qid_type_flags; 35 }; 36 37 /* bits for cqe qid_type_flags */ 38 enum ionic_v1_cqe_qtf_bits { 39 IONIC_V1_CQE_COLOR = BIT(0), 40 IONIC_V1_CQE_ERROR = BIT(1), 41 IONIC_V1_CQE_TYPE_SHIFT = 5, 42 IONIC_V1_CQE_TYPE_MASK = 0x7, 43 IONIC_V1_CQE_QID_SHIFT = 8, 44 45 IONIC_V1_CQE_TYPE_ADMIN = 0, 46 IONIC_V1_CQE_TYPE_RECV = 1, 47 IONIC_V1_CQE_TYPE_SEND_MSN = 2, 48 IONIC_V1_CQE_TYPE_SEND_NPG = 3, 49 }; 50 51 static inline bool ionic_v1_cqe_color(struct ionic_v1_cqe *cqe) 52 { 53 return cqe->qid_type_flags & cpu_to_be32(IONIC_V1_CQE_COLOR); 54 } 55 56 static inline bool ionic_v1_cqe_error(struct ionic_v1_cqe *cqe) 57 { 58 return cqe->qid_type_flags & cpu_to_be32(IONIC_V1_CQE_ERROR); 59 } 60 61 static inline void ionic_v1_cqe_clean(struct ionic_v1_cqe *cqe) 62 { 63 cqe->qid_type_flags |= cpu_to_be32(~0u << IONIC_V1_CQE_QID_SHIFT); 64 } 65 66 static inline u32 ionic_v1_cqe_qtf(struct ionic_v1_cqe *cqe) 67 { 68 return be32_to_cpu(cqe->qid_type_flags); 69 } 70 71 static inline u8 ionic_v1_cqe_qtf_type(u32 qtf) 72 { 73 return (qtf >> IONIC_V1_CQE_TYPE_SHIFT) & IONIC_V1_CQE_TYPE_MASK; 74 } 75 76 static inline u32 ionic_v1_cqe_qtf_qid(u32 qtf) 77 { 78 return qtf >> IONIC_V1_CQE_QID_SHIFT; 79 } 80 81 #define ADMIN_WQE_STRIDE 64 82 #define ADMIN_WQE_HDR_LEN 4 83 84 /* admin queue v1 wqe */ 85 struct ionic_v1_admin_wqe { 86 __u8 op; 87 __u8 rsvd; 88 __le16 len; 89 90 union { 91 } cmd; 92 }; 93 94 /* admin queue v1 cqe status */ 95 enum ionic_v1_admin_status { 96 IONIC_V1_ASTS_OK, 97 IONIC_V1_ASTS_BAD_CMD, 98 IONIC_V1_ASTS_BAD_INDEX, 99 IONIC_V1_ASTS_BAD_STATE, 100 IONIC_V1_ASTS_BAD_TYPE, 101 IONIC_V1_ASTS_BAD_ATTR, 102 IONIC_V1_ASTS_MSG_TOO_BIG, 103 }; 104 105 /* event queue v1 eqe */ 106 struct ionic_v1_eqe { 107 __be32 evt; 108 }; 109 110 /* bits for cqe queue_type_flags */ 111 enum ionic_v1_eqe_evt_bits { 112 IONIC_V1_EQE_COLOR = BIT(0), 113 IONIC_V1_EQE_TYPE_SHIFT = 1, 114 IONIC_V1_EQE_TYPE_MASK = 0x7, 115 IONIC_V1_EQE_CODE_SHIFT = 4, 116 IONIC_V1_EQE_CODE_MASK = 0xf, 117 IONIC_V1_EQE_QID_SHIFT = 8, 118 119 /* cq events */ 120 IONIC_V1_EQE_TYPE_CQ = 0, 121 /* cq normal events */ 122 IONIC_V1_EQE_CQ_NOTIFY = 0, 123 /* cq error events */ 124 IONIC_V1_EQE_CQ_ERR = 8, 125 126 /* qp and srq events */ 127 IONIC_V1_EQE_TYPE_QP = 1, 128 /* qp normal events */ 129 IONIC_V1_EQE_SRQ_LEVEL = 0, 130 IONIC_V1_EQE_SQ_DRAIN = 1, 131 IONIC_V1_EQE_QP_COMM_EST = 2, 132 IONIC_V1_EQE_QP_LAST_WQE = 3, 133 /* qp error events */ 134 IONIC_V1_EQE_QP_ERR = 8, 135 IONIC_V1_EQE_QP_ERR_REQUEST = 9, 136 IONIC_V1_EQE_QP_ERR_ACCESS = 10, 137 }; 138 139 static inline bool ionic_v1_eqe_color(struct ionic_v1_eqe *eqe) 140 { 141 return eqe->evt & cpu_to_be32(IONIC_V1_EQE_COLOR); 142 } 143 144 static inline u32 ionic_v1_eqe_evt(struct ionic_v1_eqe *eqe) 145 { 146 return be32_to_cpu(eqe->evt); 147 } 148 149 static inline u8 ionic_v1_eqe_evt_type(u32 evt) 150 { 151 return (evt >> IONIC_V1_EQE_TYPE_SHIFT) & IONIC_V1_EQE_TYPE_MASK; 152 } 153 154 static inline u8 ionic_v1_eqe_evt_code(u32 evt) 155 { 156 return (evt >> IONIC_V1_EQE_CODE_SHIFT) & IONIC_V1_EQE_CODE_MASK; 157 } 158 159 static inline u32 ionic_v1_eqe_evt_qid(u32 evt) 160 { 161 return evt >> IONIC_V1_EQE_QID_SHIFT; 162 } 163 164 #endif /* _IONIC_FW_H_ */ 165