1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ 3 4 #ifndef _IONIC_FW_H_ 5 #define _IONIC_FW_H_ 6 7 #include <linux/kernel.h> 8 #include <rdma/ib_verbs.h> 9 10 /* common for ib spec */ 11 12 #define IONIC_EXP_DBELL_SZ 8 13 14 enum ionic_mrid_bits { 15 IONIC_MRID_INDEX_SHIFT = 8, 16 }; 17 18 static inline u32 ionic_mrid(u32 index, u8 key) 19 { 20 return (index << IONIC_MRID_INDEX_SHIFT) | key; 21 } 22 23 static inline u32 ionic_mrid_index(u32 lrkey) 24 { 25 return lrkey >> IONIC_MRID_INDEX_SHIFT; 26 } 27 28 /* common to all versions */ 29 30 /* wqe scatter gather element */ 31 struct ionic_sge { 32 __be64 va; 33 __be32 len; 34 __be32 lkey; 35 }; 36 37 /* admin queue mr type */ 38 enum ionic_mr_flags { 39 /* bits that determine mr access */ 40 IONIC_MRF_LOCAL_WRITE = BIT(0), 41 IONIC_MRF_REMOTE_WRITE = BIT(1), 42 IONIC_MRF_REMOTE_READ = BIT(2), 43 IONIC_MRF_REMOTE_ATOMIC = BIT(3), 44 IONIC_MRF_MW_BIND = BIT(4), 45 IONIC_MRF_ZERO_BASED = BIT(5), 46 IONIC_MRF_ON_DEMAND = BIT(6), 47 IONIC_MRF_PB = BIT(7), 48 IONIC_MRF_ACCESS_MASK = BIT(12) - 1, 49 50 /* bits that determine mr type */ 51 IONIC_MRF_UKEY_EN = BIT(13), 52 IONIC_MRF_IS_MW = BIT(14), 53 IONIC_MRF_INV_EN = BIT(15), 54 55 /* base flags combinations for mr types */ 56 IONIC_MRF_USER_MR = 0, 57 IONIC_MRF_PHYS_MR = (IONIC_MRF_UKEY_EN | 58 IONIC_MRF_INV_EN), 59 IONIC_MRF_MW_1 = (IONIC_MRF_UKEY_EN | 60 IONIC_MRF_IS_MW), 61 IONIC_MRF_MW_2 = (IONIC_MRF_UKEY_EN | 62 IONIC_MRF_IS_MW | 63 IONIC_MRF_INV_EN), 64 }; 65 66 static inline int to_ionic_mr_flags(int access) 67 { 68 int flags = 0; 69 70 if (access & IB_ACCESS_LOCAL_WRITE) 71 flags |= IONIC_MRF_LOCAL_WRITE; 72 73 if (access & IB_ACCESS_REMOTE_READ) 74 flags |= IONIC_MRF_REMOTE_READ; 75 76 if (access & IB_ACCESS_REMOTE_WRITE) 77 flags |= IONIC_MRF_REMOTE_WRITE; 78 79 if (access & IB_ACCESS_REMOTE_ATOMIC) 80 flags |= IONIC_MRF_REMOTE_ATOMIC; 81 82 if (access & IB_ACCESS_MW_BIND) 83 flags |= IONIC_MRF_MW_BIND; 84 85 if (access & IB_ZERO_BASED) 86 flags |= IONIC_MRF_ZERO_BASED; 87 88 return flags; 89 } 90 91 enum ionic_qp_flags { 92 /* bits that determine qp access */ 93 IONIC_QPF_REMOTE_WRITE = BIT(0), 94 IONIC_QPF_REMOTE_READ = BIT(1), 95 IONIC_QPF_REMOTE_ATOMIC = BIT(2), 96 97 /* bits that determine other qp behavior */ 98 IONIC_QPF_SQ_PB = BIT(6), 99 IONIC_QPF_RQ_PB = BIT(7), 100 IONIC_QPF_SQ_SPEC = BIT(8), 101 IONIC_QPF_RQ_SPEC = BIT(9), 102 IONIC_QPF_REMOTE_PRIVILEGED = BIT(10), 103 IONIC_QPF_SQ_DRAINING = BIT(11), 104 IONIC_QPF_SQD_NOTIFY = BIT(12), 105 IONIC_QPF_SQ_CMB = BIT(13), 106 IONIC_QPF_RQ_CMB = BIT(14), 107 IONIC_QPF_PRIVILEGED = BIT(15), 108 }; 109 110 static inline int from_ionic_qp_flags(int flags) 111 { 112 int access_flags = 0; 113 114 if (flags & IONIC_QPF_REMOTE_WRITE) 115 access_flags |= IB_ACCESS_REMOTE_WRITE; 116 117 if (flags & IONIC_QPF_REMOTE_READ) 118 access_flags |= IB_ACCESS_REMOTE_READ; 119 120 if (flags & IONIC_QPF_REMOTE_ATOMIC) 121 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 122 123 return access_flags; 124 } 125 126 static inline int to_ionic_qp_flags(int access, bool sqd_notify, 127 bool sq_is_cmb, bool rq_is_cmb, 128 bool sq_spec, bool rq_spec, 129 bool privileged, bool remote_privileged) 130 { 131 int flags = 0; 132 133 if (access & IB_ACCESS_REMOTE_WRITE) 134 flags |= IONIC_QPF_REMOTE_WRITE; 135 136 if (access & IB_ACCESS_REMOTE_READ) 137 flags |= IONIC_QPF_REMOTE_READ; 138 139 if (access & IB_ACCESS_REMOTE_ATOMIC) 140 flags |= IONIC_QPF_REMOTE_ATOMIC; 141 142 if (sqd_notify) 143 flags |= IONIC_QPF_SQD_NOTIFY; 144 145 if (sq_is_cmb) 146 flags |= IONIC_QPF_SQ_CMB; 147 148 if (rq_is_cmb) 149 flags |= IONIC_QPF_RQ_CMB; 150 151 if (sq_spec) 152 flags |= IONIC_QPF_SQ_SPEC; 153 154 if (rq_spec) 155 flags |= IONIC_QPF_RQ_SPEC; 156 157 if (privileged) 158 flags |= IONIC_QPF_PRIVILEGED; 159 160 if (remote_privileged) 161 flags |= IONIC_QPF_REMOTE_PRIVILEGED; 162 163 return flags; 164 } 165 166 /* admin queue qp type */ 167 enum ionic_qp_type { 168 IONIC_QPT_RC, 169 IONIC_QPT_UC, 170 IONIC_QPT_RD, 171 IONIC_QPT_UD, 172 IONIC_QPT_SRQ, 173 IONIC_QPT_XRC_INI, 174 IONIC_QPT_XRC_TGT, 175 IONIC_QPT_XRC_SRQ, 176 }; 177 178 static inline int to_ionic_qp_type(enum ib_qp_type type) 179 { 180 switch (type) { 181 case IB_QPT_GSI: 182 case IB_QPT_UD: 183 return IONIC_QPT_UD; 184 case IB_QPT_RC: 185 return IONIC_QPT_RC; 186 case IB_QPT_UC: 187 return IONIC_QPT_UC; 188 case IB_QPT_XRC_INI: 189 return IONIC_QPT_XRC_INI; 190 case IB_QPT_XRC_TGT: 191 return IONIC_QPT_XRC_TGT; 192 default: 193 return -EINVAL; 194 } 195 } 196 197 /* admin queue qp state */ 198 enum ionic_qp_state { 199 IONIC_QPS_RESET, 200 IONIC_QPS_INIT, 201 IONIC_QPS_RTR, 202 IONIC_QPS_RTS, 203 IONIC_QPS_SQD, 204 IONIC_QPS_SQE, 205 IONIC_QPS_ERR, 206 }; 207 208 static inline int from_ionic_qp_state(enum ionic_qp_state state) 209 { 210 switch (state) { 211 case IONIC_QPS_RESET: 212 return IB_QPS_RESET; 213 case IONIC_QPS_INIT: 214 return IB_QPS_INIT; 215 case IONIC_QPS_RTR: 216 return IB_QPS_RTR; 217 case IONIC_QPS_RTS: 218 return IB_QPS_RTS; 219 case IONIC_QPS_SQD: 220 return IB_QPS_SQD; 221 case IONIC_QPS_SQE: 222 return IB_QPS_SQE; 223 case IONIC_QPS_ERR: 224 return IB_QPS_ERR; 225 default: 226 return -EINVAL; 227 } 228 } 229 230 static inline int to_ionic_qp_state(enum ib_qp_state state) 231 { 232 switch (state) { 233 case IB_QPS_RESET: 234 return IONIC_QPS_RESET; 235 case IB_QPS_INIT: 236 return IONIC_QPS_INIT; 237 case IB_QPS_RTR: 238 return IONIC_QPS_RTR; 239 case IB_QPS_RTS: 240 return IONIC_QPS_RTS; 241 case IB_QPS_SQD: 242 return IONIC_QPS_SQD; 243 case IB_QPS_SQE: 244 return IONIC_QPS_SQE; 245 case IB_QPS_ERR: 246 return IONIC_QPS_ERR; 247 default: 248 return 0; 249 } 250 } 251 252 static inline int to_ionic_qp_modify_state(enum ib_qp_state to_state, 253 enum ib_qp_state from_state) 254 { 255 return to_ionic_qp_state(to_state) | 256 (to_ionic_qp_state(from_state) << 4); 257 } 258 259 /* fw abi v1 */ 260 261 /* data payload part of v1 wqe */ 262 union ionic_v1_pld { 263 struct ionic_sge sgl[2]; 264 __be32 spec32[8]; 265 __be16 spec16[16]; 266 __u8 data[32]; 267 }; 268 269 /* completion queue v1 cqe */ 270 struct ionic_v1_cqe { 271 union { 272 struct { 273 __be16 cmd_idx; 274 __u8 cmd_op; 275 __u8 rsvd[17]; 276 __le16 old_sq_cindex; 277 __le16 old_rq_cq_cindex; 278 } admin; 279 struct { 280 __u64 wqe_id; 281 __be32 src_qpn_op; 282 __u8 src_mac[6]; 283 __be16 vlan_tag; 284 __be32 imm_data_rkey; 285 } recv; 286 struct { 287 __u8 rsvd[4]; 288 __be32 msg_msn; 289 __u8 rsvd2[8]; 290 __u64 npg_wqe_id; 291 } send; 292 }; 293 __be32 status_length; 294 __be32 qid_type_flags; 295 }; 296 297 /* bits for cqe qid_type_flags */ 298 enum ionic_v1_cqe_qtf_bits { 299 IONIC_V1_CQE_COLOR = BIT(0), 300 IONIC_V1_CQE_ERROR = BIT(1), 301 IONIC_V1_CQE_TYPE_SHIFT = 5, 302 IONIC_V1_CQE_TYPE_MASK = 0x7, 303 IONIC_V1_CQE_QID_SHIFT = 8, 304 305 IONIC_V1_CQE_TYPE_ADMIN = 0, 306 IONIC_V1_CQE_TYPE_RECV = 1, 307 IONIC_V1_CQE_TYPE_SEND_MSN = 2, 308 IONIC_V1_CQE_TYPE_SEND_NPG = 3, 309 }; 310 311 static inline bool ionic_v1_cqe_color(struct ionic_v1_cqe *cqe) 312 { 313 return cqe->qid_type_flags & cpu_to_be32(IONIC_V1_CQE_COLOR); 314 } 315 316 static inline bool ionic_v1_cqe_error(struct ionic_v1_cqe *cqe) 317 { 318 return cqe->qid_type_flags & cpu_to_be32(IONIC_V1_CQE_ERROR); 319 } 320 321 static inline void ionic_v1_cqe_clean(struct ionic_v1_cqe *cqe) 322 { 323 cqe->qid_type_flags |= cpu_to_be32(~0u << IONIC_V1_CQE_QID_SHIFT); 324 } 325 326 static inline u32 ionic_v1_cqe_qtf(struct ionic_v1_cqe *cqe) 327 { 328 return be32_to_cpu(cqe->qid_type_flags); 329 } 330 331 static inline u8 ionic_v1_cqe_qtf_type(u32 qtf) 332 { 333 return (qtf >> IONIC_V1_CQE_TYPE_SHIFT) & IONIC_V1_CQE_TYPE_MASK; 334 } 335 336 static inline u32 ionic_v1_cqe_qtf_qid(u32 qtf) 337 { 338 return qtf >> IONIC_V1_CQE_QID_SHIFT; 339 } 340 341 /* v1 base wqe header */ 342 struct ionic_v1_base_hdr { 343 __u64 wqe_id; 344 __u8 op; 345 __u8 num_sge_key; 346 __be16 flags; 347 __be32 imm_data_key; 348 }; 349 350 /* v1 receive wqe body */ 351 struct ionic_v1_recv_bdy { 352 __u8 rsvd[16]; 353 union ionic_v1_pld pld; 354 }; 355 356 /* v1 send/rdma wqe body (common, has sgl) */ 357 struct ionic_v1_common_bdy { 358 union { 359 struct { 360 __be32 ah_id; 361 __be32 dest_qpn; 362 __be32 dest_qkey; 363 } send; 364 struct { 365 __be32 remote_va_high; 366 __be32 remote_va_low; 367 __be32 remote_rkey; 368 } rdma; 369 }; 370 __be32 length; 371 union ionic_v1_pld pld; 372 }; 373 374 /* v1 atomic wqe body */ 375 struct ionic_v1_atomic_bdy { 376 __be32 remote_va_high; 377 __be32 remote_va_low; 378 __be32 remote_rkey; 379 __be32 swap_add_high; 380 __be32 swap_add_low; 381 __be32 compare_high; 382 __be32 compare_low; 383 __u8 rsvd[4]; 384 struct ionic_sge sge; 385 }; 386 387 /* v1 reg mr wqe body */ 388 struct ionic_v1_reg_mr_bdy { 389 __be64 va; 390 __be64 length; 391 __be64 offset; 392 __be64 dma_addr; 393 __be32 map_count; 394 __be16 flags; 395 __u8 dir_size_log2; 396 __u8 page_size_log2; 397 __u8 rsvd[8]; 398 }; 399 400 /* v1 bind mw wqe body */ 401 struct ionic_v1_bind_mw_bdy { 402 __be64 va; 403 __be64 length; 404 __be32 lkey; 405 __be16 flags; 406 __u8 rsvd[26]; 407 }; 408 409 /* v1 send/recv wqe */ 410 struct ionic_v1_wqe { 411 struct ionic_v1_base_hdr base; 412 union { 413 struct ionic_v1_recv_bdy recv; 414 struct ionic_v1_common_bdy common; 415 struct ionic_v1_atomic_bdy atomic; 416 struct ionic_v1_reg_mr_bdy reg_mr; 417 struct ionic_v1_bind_mw_bdy bind_mw; 418 }; 419 }; 420 421 /* queue pair v1 send opcodes */ 422 enum ionic_v1_op { 423 IONIC_V1_OP_SEND, 424 IONIC_V1_OP_SEND_INV, 425 IONIC_V1_OP_SEND_IMM, 426 IONIC_V1_OP_RDMA_READ, 427 IONIC_V1_OP_RDMA_WRITE, 428 IONIC_V1_OP_RDMA_WRITE_IMM, 429 IONIC_V1_OP_ATOMIC_CS, 430 IONIC_V1_OP_ATOMIC_FA, 431 IONIC_V1_OP_REG_MR, 432 IONIC_V1_OP_LOCAL_INV, 433 IONIC_V1_OP_BIND_MW, 434 435 /* flags */ 436 IONIC_V1_FLAG_FENCE = BIT(0), 437 IONIC_V1_FLAG_SOL = BIT(1), 438 IONIC_V1_FLAG_INL = BIT(2), 439 IONIC_V1_FLAG_SIG = BIT(3), 440 441 /* flags last four bits for sgl spec format */ 442 IONIC_V1_FLAG_SPEC32 = (1u << 12), 443 IONIC_V1_FLAG_SPEC16 = (2u << 12), 444 IONIC_V1_SPEC_FIRST_SGE = 2, 445 }; 446 447 static inline size_t ionic_v1_send_wqe_min_size(int min_sge, int min_data, 448 int spec, bool expdb) 449 { 450 size_t sz_wqe, sz_sgl, sz_data; 451 452 if (spec > IONIC_V1_SPEC_FIRST_SGE) 453 min_sge += IONIC_V1_SPEC_FIRST_SGE; 454 455 if (expdb) { 456 min_sge += 1; 457 min_data += IONIC_EXP_DBELL_SZ; 458 } 459 460 sz_wqe = sizeof(struct ionic_v1_wqe); 461 sz_sgl = offsetof(struct ionic_v1_wqe, common.pld.sgl[min_sge]); 462 sz_data = offsetof(struct ionic_v1_wqe, common.pld.data[min_data]); 463 464 if (sz_sgl > sz_wqe) 465 sz_wqe = sz_sgl; 466 467 if (sz_data > sz_wqe) 468 sz_wqe = sz_data; 469 470 return sz_wqe; 471 } 472 473 static inline int ionic_v1_send_wqe_max_sge(u8 stride_log2, int spec, 474 bool expdb) 475 { 476 struct ionic_sge *sge = (void *)(1ull << stride_log2); 477 struct ionic_v1_wqe *wqe = (void *)0; 478 int num_sge = 0; 479 480 if (expdb) 481 sge -= 1; 482 483 if (spec > IONIC_V1_SPEC_FIRST_SGE) 484 num_sge = IONIC_V1_SPEC_FIRST_SGE; 485 486 num_sge = sge - &wqe->common.pld.sgl[num_sge]; 487 488 if (spec && num_sge > spec) 489 num_sge = spec; 490 491 return num_sge; 492 } 493 494 static inline int ionic_v1_send_wqe_max_data(u8 stride_log2, bool expdb) 495 { 496 struct ionic_v1_wqe *wqe = (void *)0; 497 __u8 *data = (void *)(1ull << stride_log2); 498 499 if (expdb) 500 data -= IONIC_EXP_DBELL_SZ; 501 502 return data - wqe->common.pld.data; 503 } 504 505 static inline size_t ionic_v1_recv_wqe_min_size(int min_sge, int spec, 506 bool expdb) 507 { 508 size_t sz_wqe, sz_sgl; 509 510 if (spec > IONIC_V1_SPEC_FIRST_SGE) 511 min_sge += IONIC_V1_SPEC_FIRST_SGE; 512 513 if (expdb) 514 min_sge += 1; 515 516 sz_wqe = sizeof(struct ionic_v1_wqe); 517 sz_sgl = offsetof(struct ionic_v1_wqe, recv.pld.sgl[min_sge]); 518 519 if (sz_sgl > sz_wqe) 520 sz_wqe = sz_sgl; 521 522 return sz_wqe; 523 } 524 525 static inline int ionic_v1_recv_wqe_max_sge(u8 stride_log2, int spec, 526 bool expdb) 527 { 528 struct ionic_sge *sge = (void *)(1ull << stride_log2); 529 struct ionic_v1_wqe *wqe = (void *)0; 530 int num_sge = 0; 531 532 if (expdb) 533 sge -= 1; 534 535 if (spec > IONIC_V1_SPEC_FIRST_SGE) 536 num_sge = IONIC_V1_SPEC_FIRST_SGE; 537 538 num_sge = sge - &wqe->recv.pld.sgl[num_sge]; 539 540 if (spec && num_sge > spec) 541 num_sge = spec; 542 543 return num_sge; 544 } 545 546 static inline int ionic_v1_use_spec_sge(int min_sge, int spec) 547 { 548 if (!spec || min_sge > spec) 549 return 0; 550 551 if (min_sge <= IONIC_V1_SPEC_FIRST_SGE) 552 return IONIC_V1_SPEC_FIRST_SGE; 553 554 return spec; 555 } 556 557 struct ionic_admin_create_ah { 558 __le64 dma_addr; 559 __le32 length; 560 __le32 pd_id; 561 __le32 id_ver; 562 __le16 dbid_flags; 563 __u8 csum_profile; 564 __u8 crypto; 565 } __packed; 566 567 #define IONIC_ADMIN_CREATE_AH_IN_V1_LEN 24 568 static_assert(sizeof(struct ionic_admin_create_ah) == 569 IONIC_ADMIN_CREATE_AH_IN_V1_LEN); 570 571 struct ionic_admin_destroy_ah { 572 __le32 ah_id; 573 } __packed; 574 575 #define IONIC_ADMIN_DESTROY_AH_IN_V1_LEN 4 576 static_assert(sizeof(struct ionic_admin_destroy_ah) == 577 IONIC_ADMIN_DESTROY_AH_IN_V1_LEN); 578 579 struct ionic_admin_query_ah { 580 __le64 dma_addr; 581 } __packed; 582 583 #define IONIC_ADMIN_QUERY_AH_IN_V1_LEN 8 584 static_assert(sizeof(struct ionic_admin_query_ah) == 585 IONIC_ADMIN_QUERY_AH_IN_V1_LEN); 586 587 struct ionic_admin_create_mr { 588 __le64 va; 589 __le64 length; 590 __le32 pd_id; 591 __le32 id_ver; 592 __le32 tbl_index; 593 __le32 map_count; 594 __le64 dma_addr; 595 __le16 dbid_flags; 596 __u8 pt_type; 597 __u8 dir_size_log2; 598 __u8 page_size_log2; 599 } __packed; 600 601 #define IONIC_ADMIN_CREATE_MR_IN_V1_LEN 45 602 static_assert(sizeof(struct ionic_admin_create_mr) == 603 IONIC_ADMIN_CREATE_MR_IN_V1_LEN); 604 605 struct ionic_admin_destroy_mr { 606 __le32 mr_id; 607 } __packed; 608 609 #define IONIC_ADMIN_DESTROY_MR_IN_V1_LEN 4 610 static_assert(sizeof(struct ionic_admin_destroy_mr) == 611 IONIC_ADMIN_DESTROY_MR_IN_V1_LEN); 612 613 struct ionic_admin_create_cq { 614 __le32 eq_id; 615 __u8 depth_log2; 616 __u8 stride_log2; 617 __u8 dir_size_log2_rsvd; 618 __u8 page_size_log2; 619 __le32 cq_flags; 620 __le32 id_ver; 621 __le32 tbl_index; 622 __le32 map_count; 623 __le64 dma_addr; 624 __le16 dbid_flags; 625 } __packed; 626 627 #define IONIC_ADMIN_CREATE_CQ_IN_V1_LEN 34 628 static_assert(sizeof(struct ionic_admin_create_cq) == 629 IONIC_ADMIN_CREATE_CQ_IN_V1_LEN); 630 631 struct ionic_admin_destroy_cq { 632 __le32 cq_id; 633 } __packed; 634 635 #define IONIC_ADMIN_DESTROY_CQ_IN_V1_LEN 4 636 static_assert(sizeof(struct ionic_admin_destroy_cq) == 637 IONIC_ADMIN_DESTROY_CQ_IN_V1_LEN); 638 639 struct ionic_admin_create_qp { 640 __le32 pd_id; 641 __be32 priv_flags; 642 __le32 sq_cq_id; 643 __u8 sq_depth_log2; 644 __u8 sq_stride_log2; 645 __u8 sq_dir_size_log2_rsvd; 646 __u8 sq_page_size_log2; 647 __le32 sq_tbl_index_xrcd_id; 648 __le32 sq_map_count; 649 __le64 sq_dma_addr; 650 __le32 rq_cq_id; 651 __u8 rq_depth_log2; 652 __u8 rq_stride_log2; 653 __u8 rq_dir_size_log2_rsvd; 654 __u8 rq_page_size_log2; 655 __le32 rq_tbl_index_srq_id; 656 __le32 rq_map_count; 657 __le64 rq_dma_addr; 658 __le32 id_ver; 659 __le16 dbid_flags; 660 __u8 type_state; 661 __u8 rsvd; 662 } __packed; 663 664 #define IONIC_ADMIN_CREATE_QP_IN_V1_LEN 64 665 static_assert(sizeof(struct ionic_admin_create_qp) == 666 IONIC_ADMIN_CREATE_QP_IN_V1_LEN); 667 668 struct ionic_admin_destroy_qp { 669 __le32 qp_id; 670 } __packed; 671 672 #define IONIC_ADMIN_DESTROY_QP_IN_V1_LEN 4 673 static_assert(sizeof(struct ionic_admin_destroy_qp) == 674 IONIC_ADMIN_DESTROY_QP_IN_V1_LEN); 675 676 struct ionic_admin_mod_qp { 677 __be32 attr_mask; 678 __u8 dcqcn_profile; 679 __u8 tfp_csum_profile; 680 __be16 access_flags; 681 __le32 rq_psn; 682 __le32 sq_psn; 683 __le32 qkey_dest_qpn; 684 __le32 rate_limit_kbps; 685 __u8 pmtu; 686 __u8 retry; 687 __u8 rnr_timer; 688 __u8 retry_timeout; 689 __u8 rsq_depth; 690 __u8 rrq_depth; 691 __le16 pkey_id; 692 __le32 ah_id_len; 693 __u8 en_pcp; 694 __u8 ip_dscp; 695 __u8 rsvd2; 696 __u8 type_state; 697 union { 698 struct { 699 __le16 rsvd1; 700 }; 701 __le32 rrq_index; 702 }; 703 __le32 rsq_index; 704 __le64 dma_addr; 705 __le32 id_ver; 706 } __packed; 707 708 #define IONIC_ADMIN_MODIFY_QP_IN_V1_LEN 60 709 static_assert(sizeof(struct ionic_admin_mod_qp) == 710 IONIC_ADMIN_MODIFY_QP_IN_V1_LEN); 711 712 struct ionic_admin_query_qp { 713 __le64 hdr_dma_addr; 714 __le64 sq_dma_addr; 715 __le64 rq_dma_addr; 716 __le32 ah_id; 717 __le32 id_ver; 718 __le16 dbid_flags; 719 } __packed; 720 721 #define IONIC_ADMIN_QUERY_QP_IN_V1_LEN 34 722 static_assert(sizeof(struct ionic_admin_query_qp) == 723 IONIC_ADMIN_QUERY_QP_IN_V1_LEN); 724 725 #define ADMIN_WQE_STRIDE 64 726 #define ADMIN_WQE_HDR_LEN 4 727 728 /* admin queue v1 wqe */ 729 struct ionic_v1_admin_wqe { 730 __u8 op; 731 __u8 rsvd; 732 __le16 len; 733 734 union { 735 struct ionic_admin_create_ah create_ah; 736 struct ionic_admin_destroy_ah destroy_ah; 737 struct ionic_admin_query_ah query_ah; 738 struct ionic_admin_create_mr create_mr; 739 struct ionic_admin_destroy_mr destroy_mr; 740 struct ionic_admin_create_cq create_cq; 741 struct ionic_admin_destroy_cq destroy_cq; 742 struct ionic_admin_create_qp create_qp; 743 struct ionic_admin_destroy_qp destroy_qp; 744 struct ionic_admin_mod_qp mod_qp; 745 struct ionic_admin_query_qp query_qp; 746 } cmd; 747 }; 748 749 /* side data for query qp */ 750 struct ionic_v1_admin_query_qp_sq { 751 __u8 rnr_timer; 752 __u8 retry_timeout; 753 __be16 access_perms_flags; 754 __be16 rsvd; 755 __be16 pkey_id; 756 __be32 qkey_dest_qpn; 757 __be32 rate_limit_kbps; 758 __be32 rq_psn; 759 }; 760 761 struct ionic_v1_admin_query_qp_rq { 762 __u8 state_pmtu; 763 __u8 retry_rnrtry; 764 __u8 rrq_depth; 765 __u8 rsq_depth; 766 __be32 sq_psn; 767 __be16 access_perms_flags; 768 __be16 rsvd; 769 }; 770 771 /* admin queue v1 opcodes */ 772 enum ionic_v1_admin_op { 773 IONIC_V1_ADMIN_NOOP, 774 IONIC_V1_ADMIN_CREATE_CQ, 775 IONIC_V1_ADMIN_CREATE_QP, 776 IONIC_V1_ADMIN_CREATE_MR, 777 IONIC_V1_ADMIN_STATS_HDRS, 778 IONIC_V1_ADMIN_STATS_VALS, 779 IONIC_V1_ADMIN_DESTROY_MR, 780 IONIC_V1_ADMIN_RSVD_7, /* RESIZE_CQ */ 781 IONIC_V1_ADMIN_DESTROY_CQ, 782 IONIC_V1_ADMIN_MODIFY_QP, 783 IONIC_V1_ADMIN_QUERY_QP, 784 IONIC_V1_ADMIN_DESTROY_QP, 785 IONIC_V1_ADMIN_DEBUG, 786 IONIC_V1_ADMIN_CREATE_AH, 787 IONIC_V1_ADMIN_QUERY_AH, 788 IONIC_V1_ADMIN_MODIFY_DCQCN, 789 IONIC_V1_ADMIN_DESTROY_AH, 790 IONIC_V1_ADMIN_QP_STATS_HDRS, 791 IONIC_V1_ADMIN_QP_STATS_VALS, 792 IONIC_V1_ADMIN_OPCODES_MAX, 793 }; 794 795 /* admin queue v1 cqe status */ 796 enum ionic_v1_admin_status { 797 IONIC_V1_ASTS_OK, 798 IONIC_V1_ASTS_BAD_CMD, 799 IONIC_V1_ASTS_BAD_INDEX, 800 IONIC_V1_ASTS_BAD_STATE, 801 IONIC_V1_ASTS_BAD_TYPE, 802 IONIC_V1_ASTS_BAD_ATTR, 803 IONIC_V1_ASTS_MSG_TOO_BIG, 804 }; 805 806 /* event queue v1 eqe */ 807 struct ionic_v1_eqe { 808 __be32 evt; 809 }; 810 811 /* bits for cqe queue_type_flags */ 812 enum ionic_v1_eqe_evt_bits { 813 IONIC_V1_EQE_COLOR = BIT(0), 814 IONIC_V1_EQE_TYPE_SHIFT = 1, 815 IONIC_V1_EQE_TYPE_MASK = 0x7, 816 IONIC_V1_EQE_CODE_SHIFT = 4, 817 IONIC_V1_EQE_CODE_MASK = 0xf, 818 IONIC_V1_EQE_QID_SHIFT = 8, 819 820 /* cq events */ 821 IONIC_V1_EQE_TYPE_CQ = 0, 822 /* cq normal events */ 823 IONIC_V1_EQE_CQ_NOTIFY = 0, 824 /* cq error events */ 825 IONIC_V1_EQE_CQ_ERR = 8, 826 827 /* qp and srq events */ 828 IONIC_V1_EQE_TYPE_QP = 1, 829 /* qp normal events */ 830 IONIC_V1_EQE_SRQ_LEVEL = 0, 831 IONIC_V1_EQE_SQ_DRAIN = 1, 832 IONIC_V1_EQE_QP_COMM_EST = 2, 833 IONIC_V1_EQE_QP_LAST_WQE = 3, 834 /* qp error events */ 835 IONIC_V1_EQE_QP_ERR = 8, 836 IONIC_V1_EQE_QP_ERR_REQUEST = 9, 837 IONIC_V1_EQE_QP_ERR_ACCESS = 10, 838 }; 839 840 enum ionic_tfp_csum_profiles { 841 IONIC_TFP_CSUM_PROF_ETH_IPV4_UDP = 0, 842 IONIC_TFP_CSUM_PROF_ETH_QTAG_IPV4_UDP = 1, 843 IONIC_TFP_CSUM_PROF_ETH_IPV6_UDP = 2, 844 IONIC_TFP_CSUM_PROF_ETH_QTAG_IPV6_UDP = 3, 845 IONIC_TFP_CSUM_PROF_IPV4_UDP_VXLAN_ETH_QTAG_IPV4_UDP = 4, 846 IONIC_TFP_CSUM_PROF_IPV4_UDP_VXLAN_ETH_QTAG_IPV6_UDP = 5, 847 IONIC_TFP_CSUM_PROF_QTAG_IPV4_UDP_VXLAN_ETH_QTAG_IPV4_UDP = 6, 848 IONIC_TFP_CSUM_PROF_QTAG_IPV4_UDP_VXLAN_ETH_QTAG_IPV6_UDP = 7, 849 IONIC_TFP_CSUM_PROF_ETH_QTAG_IPV4_UDP_ESP_IPV4_UDP = 8, 850 IONIC_TFP_CSUM_PROF_ETH_QTAG_IPV4_ESP_UDP = 9, 851 IONIC_TFP_CSUM_PROF_ETH_QTAG_IPV4_UDP_ESP_UDP = 10, 852 IONIC_TFP_CSUM_PROF_ETH_QTAG_IPV6_ESP_UDP = 11, 853 IONIC_TFP_CSUM_PROF_ETH_QTAG_IPV4_UDP_CSUM = 12, 854 }; 855 856 static inline bool ionic_v1_eqe_color(struct ionic_v1_eqe *eqe) 857 { 858 return eqe->evt & cpu_to_be32(IONIC_V1_EQE_COLOR); 859 } 860 861 static inline u32 ionic_v1_eqe_evt(struct ionic_v1_eqe *eqe) 862 { 863 return be32_to_cpu(eqe->evt); 864 } 865 866 static inline u8 ionic_v1_eqe_evt_type(u32 evt) 867 { 868 return (evt >> IONIC_V1_EQE_TYPE_SHIFT) & IONIC_V1_EQE_TYPE_MASK; 869 } 870 871 static inline u8 ionic_v1_eqe_evt_code(u32 evt) 872 { 873 return (evt >> IONIC_V1_EQE_CODE_SHIFT) & IONIC_V1_EQE_CODE_MASK; 874 } 875 876 static inline u32 ionic_v1_eqe_evt_qid(u32 evt) 877 { 878 return evt >> IONIC_V1_EQE_QID_SHIFT; 879 } 880 881 #endif /* _IONIC_FW_H_ */ 882