xref: /linux/drivers/infiniband/hw/hns/hns_roce_hw_v2.h (revision 39f75da7bcc829ddc4d40bb60d0e95520de7898b)
1 /*
2  * Copyright (c) 2016-2017 Hisilicon Limited.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef _HNS_ROCE_HW_V2_H
34 #define _HNS_ROCE_HW_V2_H
35 
36 #include <linux/bitops.h>
37 
38 #define HNS_ROCE_VF_QPC_BT_NUM			256
39 #define HNS_ROCE_VF_SCCC_BT_NUM			64
40 #define HNS_ROCE_VF_SRQC_BT_NUM			64
41 #define HNS_ROCE_VF_CQC_BT_NUM			64
42 #define HNS_ROCE_VF_MPT_BT_NUM			64
43 #define HNS_ROCE_VF_SMAC_NUM			32
44 #define HNS_ROCE_VF_SL_NUM			8
45 #define HNS_ROCE_VF_GMV_BT_NUM			256
46 
47 #define HNS_ROCE_V2_MAX_QP_NUM			0x1000
48 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM		0x200
49 #define HNS_ROCE_V2_MAX_WQE_NUM			0x8000
50 #define	HNS_ROCE_V2_MAX_SRQ			0x100000
51 #define HNS_ROCE_V2_MAX_SRQ_WR			0x8000
52 #define HNS_ROCE_V2_MAX_SRQ_SGE			64
53 #define HNS_ROCE_V2_MAX_CQ_NUM			0x100000
54 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM		0x100
55 #define HNS_ROCE_V2_MAX_SRQ_NUM			0x100000
56 #define HNS_ROCE_V2_MAX_CQE_NUM			0x400000
57 #define HNS_ROCE_V2_MAX_SRQWQE_NUM		0x8000
58 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM		64
59 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM		64
60 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM		0x200000
61 #define HNS_ROCE_V2_MAX_SQ_INLINE		0x20
62 #define HNS_ROCE_V3_MAX_SQ_INLINE		0x400
63 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ		32
64 #define HNS_ROCE_V2_UAR_NUM			256
65 #define HNS_ROCE_V2_PHY_UAR_NUM			1
66 #define HNS_ROCE_V2_MAX_IRQ_NUM			65
67 #define HNS_ROCE_V2_COMP_VEC_NUM		63
68 #define HNS_ROCE_V2_AEQE_VEC_NUM		1
69 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM		1
70 #define HNS_ROCE_V2_MAX_MTPT_NUM		0x100000
71 #define HNS_ROCE_V2_MAX_MTT_SEGS		0x1000000
72 #define HNS_ROCE_V2_MAX_CQE_SEGS		0x1000000
73 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS		0x1000000
74 #define HNS_ROCE_V2_MAX_IDX_SEGS		0x1000000
75 #define HNS_ROCE_V2_MAX_PD_NUM			0x1000000
76 #define HNS_ROCE_V2_MAX_XRCD_NUM		0x1000000
77 #define HNS_ROCE_V2_RSV_XRCD_NUM		0
78 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA		128
79 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA		128
80 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ		64
81 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ		16
82 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ		64
83 #define HNS_ROCE_V2_IRRL_ENTRY_SZ		64
84 #define HNS_ROCE_V2_TRRL_ENTRY_SZ		48
85 #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ	100
86 #define HNS_ROCE_V2_CQC_ENTRY_SZ		64
87 #define HNS_ROCE_V2_SRQC_ENTRY_SZ		64
88 #define HNS_ROCE_V2_MTPT_ENTRY_SZ		64
89 #define HNS_ROCE_V2_MTT_ENTRY_SZ		64
90 #define HNS_ROCE_V2_IDX_ENTRY_SZ		4
91 
92 #define HNS_ROCE_V2_SCCC_SZ			32
93 #define HNS_ROCE_V3_SCCC_SZ			64
94 #define HNS_ROCE_V3_GMV_ENTRY_SZ		32
95 
96 #define HNS_ROCE_V2_EXT_LLM_ENTRY_SZ		8
97 #define HNS_ROCE_V2_EXT_LLM_MAX_DEPTH		4096
98 
99 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ		PAGE_SIZE
100 #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ		PAGE_SIZE
101 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED		0xFFFFF000
102 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM		2
103 #define HNS_ROCE_INVALID_LKEY			0x0
104 #define HNS_ROCE_INVALID_SGE_LENGTH		0x80000000
105 #define HNS_ROCE_CMQ_TX_TIMEOUT			30000
106 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE	2
107 #define HNS_ROCE_V2_RSV_QPS			8
108 
109 #define HNS_ROCE_V2_HW_RST_TIMEOUT		1000
110 #define HNS_ROCE_V2_HW_RST_UNINT_DELAY		100
111 
112 #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT	20
113 
114 #define HNS_ROCE_CONTEXT_HOP_NUM		1
115 #define HNS_ROCE_SCCC_HOP_NUM			1
116 #define HNS_ROCE_MTT_HOP_NUM			1
117 #define HNS_ROCE_CQE_HOP_NUM			1
118 #define HNS_ROCE_SRQWQE_HOP_NUM			1
119 #define HNS_ROCE_PBL_HOP_NUM			2
120 #define HNS_ROCE_EQE_HOP_NUM			2
121 #define HNS_ROCE_IDX_HOP_NUM			1
122 #define HNS_ROCE_SQWQE_HOP_NUM			2
123 #define HNS_ROCE_EXT_SGE_HOP_NUM		1
124 #define HNS_ROCE_RQWQE_HOP_NUM			2
125 
126 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K	6
127 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K		2
128 #define HNS_ROCE_V2_GID_INDEX_NUM		16
129 
130 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE		(1 << 18)
131 
132 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT	0
133 #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT	1
134 #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT		2
135 #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT	3
136 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT		4
137 #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT	5
138 
139 #define HNS_ROCE_CMD_FLAG_IN		BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
140 #define HNS_ROCE_CMD_FLAG_OUT		BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
141 #define HNS_ROCE_CMD_FLAG_NEXT		BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
142 #define HNS_ROCE_CMD_FLAG_WR		BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
143 #define HNS_ROCE_CMD_FLAG_NO_INTR	BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
144 #define HNS_ROCE_CMD_FLAG_ERR_INTR	BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
145 
146 #define HNS_ROCE_CMQ_DESC_NUM_S		3
147 
148 #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT		5
149 
150 #define HNS_ROCE_CONG_SIZE 64
151 
152 #define check_whether_last_step(hop_num, step_idx) \
153 	((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
154 	(step_idx == 1 && hop_num == 1) || \
155 	(step_idx == 2 && hop_num == 2))
156 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT	0
157 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL	BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
158 
159 #define CMD_CSQ_DESC_NUM		1024
160 #define CMD_CRQ_DESC_NUM		1024
161 
162 enum {
163 	NO_ARMED = 0x0,
164 	REG_NXT_CEQE = 0x2,
165 	REG_NXT_SE_CEQE = 0x3
166 };
167 
168 enum {
169 	CQE_SIZE_32B = 0x0,
170 	CQE_SIZE_64B = 0x1
171 };
172 
173 #define V2_CQ_DB_REQ_NOT_SOL			0
174 #define V2_CQ_DB_REQ_NOT			1
175 
176 #define V2_CQ_STATE_VALID			1
177 #define V2_QKEY_VAL				0x80010000
178 
179 #define	GID_LEN_V2				16
180 
181 enum {
182 	HNS_ROCE_V2_WQE_OP_SEND				= 0x0,
183 	HNS_ROCE_V2_WQE_OP_SEND_WITH_INV		= 0x1,
184 	HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM		= 0x2,
185 	HNS_ROCE_V2_WQE_OP_RDMA_WRITE			= 0x3,
186 	HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM		= 0x4,
187 	HNS_ROCE_V2_WQE_OP_RDMA_READ			= 0x5,
188 	HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP		= 0x6,
189 	HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD		= 0x7,
190 	HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP	= 0x8,
191 	HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD	= 0x9,
192 	HNS_ROCE_V2_WQE_OP_FAST_REG_PMR			= 0xa,
193 	HNS_ROCE_V2_WQE_OP_LOCAL_INV			= 0xb,
194 	HNS_ROCE_V2_WQE_OP_BIND_MW			= 0xc,
195 	HNS_ROCE_V2_WQE_OP_MASK				= 0x1f,
196 };
197 
198 enum {
199 	/* rq operations */
200 	HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
201 	HNS_ROCE_V2_OPCODE_SEND = 0x1,
202 	HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
203 	HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
204 };
205 
206 enum {
207 	HNS_ROCE_V2_SQ_DB,
208 	HNS_ROCE_V2_RQ_DB,
209 	HNS_ROCE_V2_SRQ_DB,
210 	HNS_ROCE_V2_CQ_DB,
211 	HNS_ROCE_V2_CQ_DB_NOTIFY
212 };
213 
214 enum {
215 	HNS_ROCE_CQE_V2_SUCCESS				= 0x00,
216 	HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR		= 0x01,
217 	HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR			= 0x02,
218 	HNS_ROCE_CQE_V2_LOCAL_PROT_ERR			= 0x04,
219 	HNS_ROCE_CQE_V2_WR_FLUSH_ERR			= 0x05,
220 	HNS_ROCE_CQE_V2_MW_BIND_ERR			= 0x06,
221 	HNS_ROCE_CQE_V2_BAD_RESP_ERR			= 0x10,
222 	HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR		= 0x11,
223 	HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR		= 0x12,
224 	HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR		= 0x13,
225 	HNS_ROCE_CQE_V2_REMOTE_OP_ERR			= 0x14,
226 	HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR		= 0x15,
227 	HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR		= 0x16,
228 	HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR		= 0x22,
229 	HNS_ROCE_CQE_V2_GENERAL_ERR			= 0x23,
230 
231 	HNS_ROCE_V2_CQE_STATUS_MASK			= 0xff,
232 };
233 
234 /* CMQ command */
235 enum hns_roce_opcode_type {
236 	HNS_QUERY_FW_VER				= 0x0001,
237 	HNS_ROCE_OPC_QUERY_HW_VER			= 0x8000,
238 	HNS_ROCE_OPC_CFG_GLOBAL_PARAM			= 0x8001,
239 	HNS_ROCE_OPC_ALLOC_PF_RES			= 0x8004,
240 	HNS_ROCE_OPC_QUERY_PF_RES			= 0x8400,
241 	HNS_ROCE_OPC_ALLOC_VF_RES			= 0x8401,
242 	HNS_ROCE_OPC_CFG_EXT_LLM			= 0x8403,
243 	HNS_ROCE_OPC_QUERY_PF_TIMER_RES			= 0x8406,
244 	HNS_ROCE_OPC_QUERY_FUNC_INFO			= 0x8407,
245 	HNS_ROCE_OPC_QUERY_PF_CAPS_NUM                  = 0x8408,
246 	HNS_ROCE_OPC_CFG_ENTRY_SIZE			= 0x8409,
247 	HNS_ROCE_OPC_CFG_SGID_TB			= 0x8500,
248 	HNS_ROCE_OPC_CFG_SMAC_TB			= 0x8501,
249 	HNS_ROCE_OPC_POST_MB				= 0x8504,
250 	HNS_ROCE_OPC_QUERY_MB_ST			= 0x8505,
251 	HNS_ROCE_OPC_CFG_BT_ATTR			= 0x8506,
252 	HNS_ROCE_OPC_FUNC_CLEAR				= 0x8508,
253 	HNS_ROCE_OPC_CLR_SCCC				= 0x8509,
254 	HNS_ROCE_OPC_QUERY_SCCC				= 0x850a,
255 	HNS_ROCE_OPC_RESET_SCCC				= 0x850b,
256 	HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO		= 0x850d,
257 	HNS_ROCE_OPC_QUERY_VF_RES			= 0x850e,
258 	HNS_ROCE_OPC_CFG_GMV_TBL			= 0x850f,
259 	HNS_ROCE_OPC_CFG_GMV_BT				= 0x8510,
260 	HNS_ROCE_OPC_EXT_CFG				= 0x8512,
261 	HNS_SWITCH_PARAMETER_CFG			= 0x1033,
262 };
263 
264 enum {
265 	TYPE_CRQ,
266 	TYPE_CSQ,
267 };
268 
269 enum hns_roce_cmd_return_status {
270 	CMD_EXEC_SUCCESS,
271 	CMD_NO_AUTH,
272 	CMD_NOT_EXIST,
273 	CMD_CRQ_FULL,
274 	CMD_NEXT_ERR,
275 	CMD_NOT_EXEC,
276 	CMD_PARA_ERR,
277 	CMD_RESULT_ERR,
278 	CMD_TIMEOUT,
279 	CMD_HILINK_ERR,
280 	CMD_INFO_ILLEGAL,
281 	CMD_INVALID,
282 	CMD_ROH_CHECK_FAIL,
283 	CMD_OTHER_ERR = 0xff
284 };
285 
286 enum hns_roce_sgid_type {
287 	GID_TYPE_FLAG_ROCE_V1 = 0,
288 	GID_TYPE_FLAG_ROCE_V2_IPV4,
289 	GID_TYPE_FLAG_ROCE_V2_IPV6,
290 };
291 
292 struct hns_roce_v2_cq_context {
293 	__le32 byte_4_pg_ceqn;
294 	__le32 byte_8_cqn;
295 	__le32 cqe_cur_blk_addr;
296 	__le32 byte_16_hop_addr;
297 	__le32 cqe_nxt_blk_addr;
298 	__le32 byte_24_pgsz_addr;
299 	__le32 byte_28_cq_pi;
300 	__le32 byte_32_cq_ci;
301 	__le32 cqe_ba;
302 	__le32 byte_40_cqe_ba;
303 	__le32 byte_44_db_record;
304 	__le32 db_record_addr;
305 	__le32 byte_52_cqe_cnt;
306 	__le32 byte_56_cqe_period_maxcnt;
307 	__le32 cqe_report_timer;
308 	__le32 byte_64_se_cqe_idx;
309 };
310 
311 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
312 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL	0x0
313 
314 #define	V2_CQC_BYTE_4_ARM_ST_S 6
315 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
316 
317 #define	V2_CQC_BYTE_4_CEQN_S 15
318 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
319 
320 #define	V2_CQC_BYTE_8_CQN_S 0
321 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
322 
323 #define	V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
324 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
325 
326 #define	V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
327 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
328 
329 #define	V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
330 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
331 
332 #define	V2_CQC_BYTE_52_CQE_CNT_S 0
333 #define	V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
334 
335 #define	V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
336 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
337 
338 #define	V2_CQC_BYTE_56_CQ_PERIOD_S 16
339 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
340 
341 #define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l)
342 
343 #define CQC_CQ_ST CQC_FIELD_LOC(1, 0)
344 #define CQC_POLL CQC_FIELD_LOC(2, 2)
345 #define CQC_SE CQC_FIELD_LOC(3, 3)
346 #define CQC_OVER_IGNORE CQC_FIELD_LOC(4, 4)
347 #define CQC_ARM_ST CQC_FIELD_LOC(7, 6)
348 #define CQC_SHIFT CQC_FIELD_LOC(12, 8)
349 #define CQC_CMD_SN CQC_FIELD_LOC(14, 13)
350 #define CQC_CEQN CQC_FIELD_LOC(23, 15)
351 #define CQC_CQN CQC_FIELD_LOC(55, 32)
352 #define CQC_POE_EN CQC_FIELD_LOC(56, 56)
353 #define CQC_POE_NUM CQC_FIELD_LOC(58, 57)
354 #define CQC_CQE_SIZE CQC_FIELD_LOC(60, 59)
355 #define CQC_CQ_CNT_MODE CQC_FIELD_LOC(61, 61)
356 #define CQC_STASH CQC_FIELD_LOC(63, 63)
357 #define CQC_CQE_CUR_BLK_ADDR_L CQC_FIELD_LOC(95, 64)
358 #define CQC_CQE_CUR_BLK_ADDR_H CQC_FIELD_LOC(115, 96)
359 #define CQC_POE_QID CQC_FIELD_LOC(125, 116)
360 #define CQC_CQE_HOP_NUM CQC_FIELD_LOC(127, 126)
361 #define CQC_CQE_NEX_BLK_ADDR_L CQC_FIELD_LOC(159, 128)
362 #define CQC_CQE_NEX_BLK_ADDR_H CQC_FIELD_LOC(179, 160)
363 #define CQC_CQE_BAR_PG_SZ CQC_FIELD_LOC(187, 184)
364 #define CQC_CQE_BUF_PG_SZ CQC_FIELD_LOC(191, 188)
365 #define CQC_CQ_PRODUCER_IDX CQC_FIELD_LOC(215, 192)
366 #define CQC_CQ_CONSUMER_IDX CQC_FIELD_LOC(247, 224)
367 #define CQC_CQE_BA_L CQC_FIELD_LOC(287, 256)
368 #define CQC_CQE_BA_H CQC_FIELD_LOC(316, 288)
369 #define CQC_POE_QID_H_0 CQC_FIELD_LOC(319, 317)
370 #define CQC_DB_RECORD_EN CQC_FIELD_LOC(320, 320)
371 #define CQC_CQE_DB_RECORD_ADDR_L CQC_FIELD_LOC(351, 321)
372 #define CQC_CQE_DB_RECORD_ADDR_H CQC_FIELD_LOC(383, 352)
373 #define CQC_CQE_CNT CQC_FIELD_LOC(407, 384)
374 #define CQC_CQ_MAX_CNT CQC_FIELD_LOC(431, 416)
375 #define CQC_CQ_PERIOD CQC_FIELD_LOC(447, 432)
376 #define CQC_CQE_REPORT_TIMER CQC_FIELD_LOC(471, 448)
377 #define CQC_WR_CQE_IDX CQC_FIELD_LOC(479, 472)
378 #define CQC_SE_CQE_IDX CQC_FIELD_LOC(503, 480)
379 #define CQC_POE_QID_H_1 CQC_FIELD_LOC(511, 511)
380 
381 struct hns_roce_srq_context {
382 	__le32 data[16];
383 };
384 
385 #define SRQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_srq_context, h, l)
386 
387 #define SRQC_SRQ_ST SRQC_FIELD_LOC(1, 0)
388 #define SRQC_WQE_HOP_NUM SRQC_FIELD_LOC(3, 2)
389 #define SRQC_SHIFT SRQC_FIELD_LOC(7, 4)
390 #define SRQC_SRQN SRQC_FIELD_LOC(31, 8)
391 #define SRQC_LIMIT_WL SRQC_FIELD_LOC(47, 32)
392 #define SRQC_RSV0 SRQC_FIELD_LOC(63, 48)
393 #define SRQC_XRCD SRQC_FIELD_LOC(87, 64)
394 #define SRQC_RSV1 SRQC_FIELD_LOC(95, 88)
395 #define SRQC_PRODUCER_IDX SRQC_FIELD_LOC(111, 96)
396 #define SRQC_CONSUMER_IDX SRQC_FIELD_LOC(127, 112)
397 #define SRQC_WQE_BT_BA_L SRQC_FIELD_LOC(159, 128)
398 #define SRQC_WQE_BT_BA_H SRQC_FIELD_LOC(188, 160)
399 #define SRQC_RSV2 SRQC_FIELD_LOC(190, 189)
400 #define SRQC_SRQ_TYPE SRQC_FIELD_LOC(191, 191)
401 #define SRQC_PD SRQC_FIELD_LOC(215, 192)
402 #define SRQC_RQWS SRQC_FIELD_LOC(219, 216)
403 #define SRQC_RSV3 SRQC_FIELD_LOC(223, 220)
404 #define SRQC_IDX_BT_BA_L SRQC_FIELD_LOC(255, 224)
405 #define SRQC_IDX_BT_BA_H SRQC_FIELD_LOC(284, 256)
406 #define SRQC_RSV4 SRQC_FIELD_LOC(287, 285)
407 #define SRQC_IDX_CUR_BLK_ADDR_L SRQC_FIELD_LOC(319, 288)
408 #define SRQC_IDX_CUR_BLK_ADDR_H SRQC_FIELD_LOC(339, 320)
409 #define SRQC_RSV5 SRQC_FIELD_LOC(341, 340)
410 #define SRQC_IDX_HOP_NUM SRQC_FIELD_LOC(343, 342)
411 #define SRQC_IDX_BA_PG_SZ SRQC_FIELD_LOC(347, 344)
412 #define SRQC_IDX_BUF_PG_SZ SRQC_FIELD_LOC(351, 348)
413 #define SRQC_IDX_NXT_BLK_ADDR_L SRQC_FIELD_LOC(383, 352)
414 #define SRQC_IDX_NXT_BLK_ADDR_H SRQC_FIELD_LOC(403, 384)
415 #define SRQC_RSV6 SRQC_FIELD_LOC(415, 404)
416 #define SRQC_XRC_CQN SRQC_FIELD_LOC(439, 416)
417 #define SRQC_WQE_BA_PG_SZ SRQC_FIELD_LOC(443, 440)
418 #define SRQC_WQE_BUF_PG_SZ SRQC_FIELD_LOC(447, 444)
419 #define SRQC_DB_RECORD_EN SRQC_FIELD_LOC(448, 448)
420 #define SRQC_DB_RECORD_ADDR_L SRQC_FIELD_LOC(479, 449)
421 #define SRQC_DB_RECORD_ADDR_H SRQC_FIELD_LOC(511, 480)
422 
423 enum {
424 	V2_MPT_ST_VALID = 0x1,
425 	V2_MPT_ST_FREE	= 0x2,
426 };
427 
428 enum hns_roce_v2_qp_state {
429 	HNS_ROCE_QP_ST_RST,
430 	HNS_ROCE_QP_ST_INIT,
431 	HNS_ROCE_QP_ST_RTR,
432 	HNS_ROCE_QP_ST_RTS,
433 	HNS_ROCE_QP_ST_SQD,
434 	HNS_ROCE_QP_ST_SQER,
435 	HNS_ROCE_QP_ST_ERR,
436 	HNS_ROCE_QP_ST_SQ_DRAINING,
437 	HNS_ROCE_QP_NUM_ST
438 };
439 
440 struct hns_roce_v2_qp_context_ex {
441 	__le32 data[64];
442 };
443 struct hns_roce_v2_qp_context {
444 	__le32 byte_4_sqpn_tst;
445 	__le32 wqe_sge_ba;
446 	__le32 byte_12_sq_hop;
447 	__le32 byte_16_buf_ba_pg_sz;
448 	__le32 byte_20_smac_sgid_idx;
449 	__le32 byte_24_mtu_tc;
450 	__le32 byte_28_at_fl;
451 	u8 dgid[GID_LEN_V2];
452 	__le32 dmac;
453 	__le32 byte_52_udpspn_dmac;
454 	__le32 byte_56_dqpn_err;
455 	__le32 byte_60_qpst_tempid;
456 	__le32 qkey_xrcd;
457 	__le32 byte_68_rq_db;
458 	__le32 rq_db_record_addr;
459 	__le32 byte_76_srqn_op_en;
460 	__le32 byte_80_rnr_rx_cqn;
461 	__le32 byte_84_rq_ci_pi;
462 	__le32 rq_cur_blk_addr;
463 	__le32 byte_92_srq_info;
464 	__le32 byte_96_rx_reqmsn;
465 	__le32 rq_nxt_blk_addr;
466 	__le32 byte_104_rq_sge;
467 	__le32 byte_108_rx_reqepsn;
468 	__le32 rq_rnr_timer;
469 	__le32 rx_msg_len;
470 	__le32 rx_rkey_pkt_info;
471 	__le64 rx_va;
472 	__le32 byte_132_trrl;
473 	__le32 trrl_ba;
474 	__le32 byte_140_raq;
475 	__le32 byte_144_raq;
476 	__le32 byte_148_raq;
477 	__le32 byte_152_raq;
478 	__le32 byte_156_raq;
479 	__le32 byte_160_sq_ci_pi;
480 	__le32 sq_cur_blk_addr;
481 	__le32 byte_168_irrl_idx;
482 	__le32 byte_172_sq_psn;
483 	__le32 byte_176_msg_pktn;
484 	__le32 sq_cur_sge_blk_addr;
485 	__le32 byte_184_irrl_idx;
486 	__le32 cur_sge_offset;
487 	__le32 byte_192_ext_sge;
488 	__le32 byte_196_sq_psn;
489 	__le32 byte_200_sq_max;
490 	__le32 irrl_ba;
491 	__le32 byte_208_irrl;
492 	__le32 byte_212_lsn;
493 	__le32 sq_timer;
494 	__le32 byte_220_retry_psn_msn;
495 	__le32 byte_224_retry_msg;
496 	__le32 rx_sq_cur_blk_addr;
497 	__le32 byte_232_irrl_sge;
498 	__le32 irrl_cur_sge_offset;
499 	__le32 byte_240_irrl_tail;
500 	__le32 byte_244_rnr_rxack;
501 	__le32 byte_248_ack_psn;
502 	__le32 byte_252_err_txcqn;
503 	__le32 byte_256_sqflush_rqcqe;
504 
505 	struct hns_roce_v2_qp_context_ex ext;
506 };
507 
508 #define QPC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context, h, l)
509 
510 #define QPC_TST QPC_FIELD_LOC(2, 0)
511 #define QPC_SGE_SHIFT QPC_FIELD_LOC(7, 3)
512 #define QPC_CNP_TIMER QPC_FIELD_LOC(31, 8)
513 #define QPC_WQE_SGE_BA_L QPC_FIELD_LOC(63, 32)
514 #define QPC_WQE_SGE_BA_H QPC_FIELD_LOC(92, 64)
515 #define QPC_SQ_HOP_NUM QPC_FIELD_LOC(94, 93)
516 #define QPC_CIRE_EN QPC_FIELD_LOC(95, 95)
517 #define QPC_WQE_SGE_BA_PG_SZ QPC_FIELD_LOC(99, 96)
518 #define QPC_WQE_SGE_BUF_PG_SZ QPC_FIELD_LOC(103, 100)
519 #define QPC_PD QPC_FIELD_LOC(127, 104)
520 #define QPC_RQ_HOP_NUM QPC_FIELD_LOC(129, 128)
521 #define QPC_SGE_HOP_NUM QPC_FIELD_LOC(131, 130)
522 #define QPC_RQWS QPC_FIELD_LOC(135, 132)
523 #define QPC_SQ_SHIFT QPC_FIELD_LOC(139, 136)
524 #define QPC_RQ_SHIFT QPC_FIELD_LOC(143, 140)
525 #define QPC_GMV_IDX QPC_FIELD_LOC(159, 144)
526 #define QPC_HOPLIMIT QPC_FIELD_LOC(167, 160)
527 #define QPC_TC QPC_FIELD_LOC(175, 168)
528 #define QPC_VLAN_ID QPC_FIELD_LOC(187, 176)
529 #define QPC_MTU QPC_FIELD_LOC(191, 188)
530 #define QPC_FL QPC_FIELD_LOC(211, 192)
531 #define QPC_SL QPC_FIELD_LOC(215, 212)
532 #define QPC_CNP_TX_FLAG QPC_FIELD_LOC(216, 216)
533 #define QPC_CE_FLAG QPC_FIELD_LOC(217, 217)
534 #define QPC_LBI QPC_FIELD_LOC(218, 218)
535 #define QPC_AT QPC_FIELD_LOC(223, 219)
536 #define QPC_DGID QPC_FIELD_LOC(351, 224)
537 #define QPC_DMAC_L QPC_FIELD_LOC(383, 352)
538 #define QPC_DMAC_H QPC_FIELD_LOC(399, 384)
539 #define QPC_UDPSPN QPC_FIELD_LOC(415, 400)
540 #define QPC_DQPN QPC_FIELD_LOC(439, 416)
541 #define QPC_SQ_TX_ERR QPC_FIELD_LOC(440, 440)
542 #define QPC_SQ_RX_ERR QPC_FIELD_LOC(441, 441)
543 #define QPC_RQ_TX_ERR QPC_FIELD_LOC(442, 442)
544 #define QPC_RQ_RX_ERR QPC_FIELD_LOC(443, 443)
545 #define QPC_LP_PKTN_INI QPC_FIELD_LOC(447, 444)
546 #define QPC_CONG_ALGO_TMPL_ID QPC_FIELD_LOC(455, 448)
547 #define QPC_SCC_TOKEN QPC_FIELD_LOC(474, 456)
548 #define QPC_SQ_DB_DOING QPC_FIELD_LOC(475, 475)
549 #define QPC_RQ_DB_DOING QPC_FIELD_LOC(476, 476)
550 #define QPC_QP_ST QPC_FIELD_LOC(479, 477)
551 #define QPC_QKEY_XRCD QPC_FIELD_LOC(511, 480)
552 #define QPC_RQ_RECORD_EN QPC_FIELD_LOC(512, 512)
553 #define QPC_RQ_DB_RECORD_ADDR_L QPC_FIELD_LOC(543, 513)
554 #define QPC_RQ_DB_RECORD_ADDR_H QPC_FIELD_LOC(575, 544)
555 #define QPC_SRQN QPC_FIELD_LOC(599, 576)
556 #define QPC_SRQ_EN QPC_FIELD_LOC(600, 600)
557 #define QPC_RRE QPC_FIELD_LOC(601, 601)
558 #define QPC_RWE QPC_FIELD_LOC(602, 602)
559 #define QPC_ATE QPC_FIELD_LOC(603, 603)
560 #define QPC_RQIE QPC_FIELD_LOC(604, 604)
561 #define QPC_EXT_ATE QPC_FIELD_LOC(605, 605)
562 #define QPC_RQ_VLAN_EN QPC_FIELD_LOC(606, 606)
563 #define QPC_RQ_RTY_TX_ERR QPC_FIELD_LOC(607, 607)
564 #define QPC_RX_CQN QPC_FIELD_LOC(631, 608)
565 #define QPC_XRC_QP_TYPE QPC_FIELD_LOC(632, 632)
566 #define QPC_RSV3 QPC_FIELD_LOC(634, 633)
567 #define QPC_MIN_RNR_TIME QPC_FIELD_LOC(639, 635)
568 #define QPC_RQ_PRODUCER_IDX QPC_FIELD_LOC(655, 640)
569 #define QPC_RQ_CONSUMER_IDX QPC_FIELD_LOC(671, 656)
570 #define QPC_RQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(703, 672)
571 #define QPC_RQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(723, 704)
572 #define QPC_SRQ_INFO QPC_FIELD_LOC(735, 724)
573 #define QPC_RX_REQ_MSN QPC_FIELD_LOC(759, 736)
574 #define QPC_REDUCE_CODE QPC_FIELD_LOC(766, 760)
575 #define QPC_RX_XRC_PKT_CQE_FLG QPC_FIELD_LOC(767, 767)
576 #define QPC_RQ_NXT_BLK_ADDR_L QPC_FIELD_LOC(799, 768)
577 #define QPC_RQ_NXT_BLK_ADDR_H QPC_FIELD_LOC(819, 800)
578 #define QPC_REDUCE_EN QPC_FIELD_LOC(820, 820)
579 #define QPC_FLUSH_EN QPC_FIELD_LOC(821, 821)
580 #define QPC_AW_EN QPC_FIELD_LOC(822, 822)
581 #define QPC_WN_EN QPC_FIELD_LOC(823, 823)
582 #define QPC_RQ_CUR_WQE_SGE_NUM QPC_FIELD_LOC(831, 824)
583 #define QPC_INV_CREDIT QPC_FIELD_LOC(832, 832)
584 #define QPC_LAST_WRITE_TYPE QPC_FIELD_LOC(834, 833)
585 #define QPC_RX_REQ_PSN_ERR QPC_FIELD_LOC(835, 835)
586 #define QPC_RX_REQ_LAST_OPTYPE QPC_FIELD_LOC(838, 836)
587 #define QPC_RX_REQ_RNR QPC_FIELD_LOC(839, 839)
588 #define QPC_RX_REQ_EPSN QPC_FIELD_LOC(863, 840)
589 #define QPC_RQ_RNR_TIMER QPC_FIELD_LOC(895, 864)
590 #define QPC_RX_MSG_LEN QPC_FIELD_LOC(927, 896)
591 #define QPC_RX_RKEY_PKT_INFO QPC_FIELD_LOC(959, 928)
592 #define QPC_RX_VA QPC_FIELD_LOC(1023, 960)
593 #define QPC_TRRL_HEAD_MAX QPC_FIELD_LOC(1031, 1024)
594 #define QPC_TRRL_TAIL_MAX QPC_FIELD_LOC(1039, 1032)
595 #define QPC_TRRL_BA_L QPC_FIELD_LOC(1055, 1040)
596 #define QPC_TRRL_BA_M QPC_FIELD_LOC(1087, 1056)
597 #define QPC_TRRL_BA_H QPC_FIELD_LOC(1099, 1088)
598 #define QPC_RR_MAX QPC_FIELD_LOC(1102, 1100)
599 #define QPC_RQ_RTY_WAIT_DO QPC_FIELD_LOC(1103, 1103)
600 #define QPC_RAQ_TRRL_HEAD QPC_FIELD_LOC(1111, 1104)
601 #define QPC_RAQ_TRRL_TAIL QPC_FIELD_LOC(1119, 1112)
602 #define QPC_RAQ_RTY_INI_PSN QPC_FIELD_LOC(1143, 1120)
603 #define QPC_CIRE_SLV_RQ_EN QPC_FIELD_LOC(1144, 1144)
604 #define QPC_RAQ_CREDIT QPC_FIELD_LOC(1149, 1145)
605 #define QPC_RQ_DB_IN_EXT QPC_FIELD_LOC(1150, 1150)
606 #define QPC_RESP_RTY_FLG QPC_FIELD_LOC(1151, 1151)
607 #define QPC_RAQ_MSN QPC_FIELD_LOC(1175, 1152)
608 #define QPC_RAQ_SYNDROME QPC_FIELD_LOC(1183, 1176)
609 #define QPC_RAQ_PSN QPC_FIELD_LOC(1207, 1184)
610 #define QPC_RAQ_TRRL_RTY_HEAD QPC_FIELD_LOC(1215, 1208)
611 #define QPC_RAQ_USE_PKTN QPC_FIELD_LOC(1239, 1216)
612 #define QPC_RQ_SCC_TOKEN QPC_FIELD_LOC(1245, 1240)
613 #define QPC_RVD10 QPC_FIELD_LOC(1247, 1246)
614 #define QPC_SQ_PRODUCER_IDX QPC_FIELD_LOC(1263, 1248)
615 #define QPC_SQ_CONSUMER_IDX QPC_FIELD_LOC(1279, 1264)
616 #define QPC_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1311, 1280)
617 #define QPC_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1331, 1312)
618 #define QPC_MSG_RTY_LP_FLG QPC_FIELD_LOC(1332, 1332)
619 #define QPC_SQ_INVLD_FLG QPC_FIELD_LOC(1333, 1333)
620 #define QPC_LP_SGEN_INI QPC_FIELD_LOC(1335, 1334)
621 #define QPC_SQ_VLAN_EN QPC_FIELD_LOC(1336, 1336)
622 #define QPC_POLL_DB_WAIT_DO QPC_FIELD_LOC(1337, 1337)
623 #define QPC_SCC_TOKEN_FORBID_SQ_DEQ QPC_FIELD_LOC(1338, 1338)
624 #define QPC_WAIT_ACK_TIMEOUT QPC_FIELD_LOC(1339, 1339)
625 #define QPC_IRRL_IDX_LSB QPC_FIELD_LOC(1343, 1340)
626 #define QPC_ACK_REQ_FREQ QPC_FIELD_LOC(1349, 1344)
627 #define QPC_MSG_RNR_FLG QPC_FIELD_LOC(1350, 1350)
628 #define QPC_FRE QPC_FIELD_LOC(1351, 1351)
629 #define QPC_SQ_CUR_PSN QPC_FIELD_LOC(1375, 1352)
630 #define QPC_MSG_USE_PKTN QPC_FIELD_LOC(1399, 1376)
631 #define QPC_IRRL_HEAD_PRE QPC_FIELD_LOC(1407, 1400)
632 #define QPC_SQ_CUR_SGE_BLK_ADDR_L QPC_FIELD_LOC(1439, 1408)
633 #define QPC_SQ_CUR_SGE_BLK_ADDR_H QPC_FIELD_LOC(1459, 1440)
634 #define QPC_IRRL_IDX_MSB QPC_FIELD_LOC(1471, 1460)
635 #define QPC_CUR_SGE_OFFSET QPC_FIELD_LOC(1503, 1472)
636 #define QPC_CUR_SGE_IDX QPC_FIELD_LOC(1527, 1504)
637 #define QPC_EXT_SGE_NUM_LEFT QPC_FIELD_LOC(1535, 1528)
638 #define QPC_OWNER_MODE QPC_FIELD_LOC(1536, 1536)
639 #define QPC_CIRE_SLV_SQ_EN QPC_FIELD_LOC(1537, 1537)
640 #define QPC_CIRE_DOING QPC_FIELD_LOC(1538, 1538)
641 #define QPC_CIRE_RESULT QPC_FIELD_LOC(1539, 1539)
642 #define QPC_OWNER_DB_WAIT_DO QPC_FIELD_LOC(1540, 1540)
643 #define QPC_SQ_WQE_INVLD QPC_FIELD_LOC(1541, 1541)
644 #define QPC_DCA_MODE QPC_FIELD_LOC(1542, 1542)
645 #define QPC_RTY_OWNER_NOCHK QPC_FIELD_LOC(1543, 1543)
646 #define QPC_V2_IRRL_HEAD QPC_FIELD_LOC(1543, 1536)
647 #define QPC_SQ_MAX_PSN QPC_FIELD_LOC(1567, 1544)
648 #define QPC_SQ_MAX_IDX QPC_FIELD_LOC(1583, 1568)
649 #define QPC_LCL_OPERATED_CNT QPC_FIELD_LOC(1599, 1584)
650 #define QPC_IRRL_BA_L QPC_FIELD_LOC(1631, 1600)
651 #define QPC_IRRL_BA_H QPC_FIELD_LOC(1657, 1632)
652 #define QPC_PKT_RNR_FLG QPC_FIELD_LOC(1658, 1658)
653 #define QPC_PKT_RTY_FLG QPC_FIELD_LOC(1659, 1659)
654 #define QPC_RMT_E2E QPC_FIELD_LOC(1660, 1660)
655 #define QPC_SR_MAX QPC_FIELD_LOC(1663, 1661)
656 #define QPC_LSN QPC_FIELD_LOC(1687, 1664)
657 #define QPC_RETRY_NUM_INIT QPC_FIELD_LOC(1690, 1688)
658 #define QPC_CHECK_FLG QPC_FIELD_LOC(1692, 1691)
659 #define QPC_RETRY_CNT QPC_FIELD_LOC(1695, 1693)
660 #define QPC_SQ_TIMER QPC_FIELD_LOC(1727, 1696)
661 #define QPC_RETRY_MSG_MSN QPC_FIELD_LOC(1743, 1728)
662 #define QPC_RETRY_MSG_PSN_L QPC_FIELD_LOC(1759, 1744)
663 #define QPC_RETRY_MSG_PSN_H QPC_FIELD_LOC(1767, 1760)
664 #define QPC_RETRY_MSG_FPKT_PSN QPC_FIELD_LOC(1791, 1768)
665 #define QPC_RX_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1823, 1792)
666 #define QPC_RX_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1843, 1824)
667 #define QPC_IRRL_SGE_IDX QPC_FIELD_LOC(1851, 1844)
668 #define QPC_LSAN_EN QPC_FIELD_LOC(1852, 1852)
669 #define QPC_SO_LP_VLD QPC_FIELD_LOC(1853, 1853)
670 #define QPC_FENCE_LP_VLD QPC_FIELD_LOC(1854, 1854)
671 #define QPC_IRRL_LP_VLD QPC_FIELD_LOC(1855, 1855)
672 #define QPC_IRRL_CUR_SGE_OFFSET QPC_FIELD_LOC(1887, 1856)
673 #define QPC_IRRL_TAIL_REAL QPC_FIELD_LOC(1895, 1888)
674 #define QPC_IRRL_TAIL_RD QPC_FIELD_LOC(1903, 1896)
675 #define QPC_RX_ACK_MSN QPC_FIELD_LOC(1919, 1904)
676 #define QPC_RX_ACK_EPSN QPC_FIELD_LOC(1943, 1920)
677 #define QPC_RNR_NUM_INIT QPC_FIELD_LOC(1946, 1944)
678 #define QPC_RNR_CNT QPC_FIELD_LOC(1949, 1947)
679 #define QPC_LCL_OP_FLG QPC_FIELD_LOC(1950, 1950)
680 #define QPC_IRRL_RD_FLG QPC_FIELD_LOC(1951, 1951)
681 #define QPC_IRRL_PSN QPC_FIELD_LOC(1975, 1952)
682 #define QPC_ACK_PSN_ERR QPC_FIELD_LOC(1976, 1976)
683 #define QPC_ACK_LAST_OPTYPE QPC_FIELD_LOC(1978, 1977)
684 #define QPC_IRRL_PSN_VLD QPC_FIELD_LOC(1979, 1979)
685 #define QPC_RNR_RETRY_FLAG QPC_FIELD_LOC(1980, 1980)
686 #define QPC_SQ_RTY_TX_ERR QPC_FIELD_LOC(1981, 1981)
687 #define QPC_LAST_IND QPC_FIELD_LOC(1982, 1982)
688 #define QPC_CQ_ERR_IND QPC_FIELD_LOC(1983, 1983)
689 #define QPC_TX_CQN QPC_FIELD_LOC(2007, 1984)
690 #define QPC_SIG_TYPE QPC_FIELD_LOC(2008, 2008)
691 #define QPC_ERR_TYPE QPC_FIELD_LOC(2015, 2009)
692 #define QPC_RQ_CQE_IDX QPC_FIELD_LOC(2031, 2016)
693 #define QPC_SQ_FLUSH_IDX QPC_FIELD_LOC(2047, 2032)
694 
695 #define RETRY_MSG_PSN_SHIFT 16
696 
697 #define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l)
698 
699 #define QPCEX_CONG_ALG_SEL QPCEX_FIELD_LOC(0, 0)
700 #define QPCEX_CONG_ALG_SUB_SEL QPCEX_FIELD_LOC(1, 1)
701 #define QPCEX_DIP_CTX_IDX_VLD QPCEX_FIELD_LOC(2, 2)
702 #define QPCEX_DIP_CTX_IDX QPCEX_FIELD_LOC(22, 3)
703 #define QPCEX_SQ_RQ_NOT_FORBID_EN QPCEX_FIELD_LOC(23, 23)
704 #define QPCEX_STASH QPCEX_FIELD_LOC(82, 82)
705 
706 #define	V2_QP_RWE_S 1 /* rdma write enable */
707 #define	V2_QP_RRE_S 2 /* rdma read enable */
708 #define	V2_QP_ATE_S 3 /* rdma atomic enable */
709 
710 struct hns_roce_v2_cqe {
711 	__le32	byte_4;
712 	union {
713 		__le32 rkey;
714 		__le32 immtdata;
715 	};
716 	__le32	byte_12;
717 	__le32	byte_16;
718 	__le32	byte_cnt;
719 	u8	smac[4];
720 	__le32	byte_28;
721 	__le32	byte_32;
722 	__le32	rsv[8];
723 };
724 
725 #define CQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cqe, h, l)
726 
727 #define CQE_OPCODE CQE_FIELD_LOC(4, 0)
728 #define CQE_RQ_INLINE CQE_FIELD_LOC(5, 5)
729 #define CQE_S_R CQE_FIELD_LOC(6, 6)
730 #define CQE_OWNER CQE_FIELD_LOC(7, 7)
731 #define CQE_STATUS CQE_FIELD_LOC(15, 8)
732 #define CQE_WQE_IDX CQE_FIELD_LOC(31, 16)
733 #define CQE_RKEY_IMMTDATA CQE_FIELD_LOC(63, 32)
734 #define CQE_XRC_SRQN CQE_FIELD_LOC(87, 64)
735 #define CQE_RSV0 CQE_FIELD_LOC(95, 88)
736 #define CQE_LCL_QPN CQE_FIELD_LOC(119, 96)
737 #define CQE_SUB_STATUS CQE_FIELD_LOC(127, 120)
738 #define CQE_BYTE_CNT CQE_FIELD_LOC(159, 128)
739 #define CQE_SMAC CQE_FIELD_LOC(207, 160)
740 #define CQE_PORT_TYPE CQE_FIELD_LOC(209, 208)
741 #define CQE_VID CQE_FIELD_LOC(221, 210)
742 #define CQE_VID_VLD CQE_FIELD_LOC(222, 222)
743 #define CQE_RSV2 CQE_FIELD_LOC(223, 223)
744 #define CQE_RMT_QPN CQE_FIELD_LOC(247, 224)
745 #define CQE_SL CQE_FIELD_LOC(250, 248)
746 #define CQE_PORTN CQE_FIELD_LOC(253, 251)
747 #define CQE_GRH CQE_FIELD_LOC(254, 254)
748 #define CQE_LPK CQE_FIELD_LOC(255, 255)
749 #define CQE_RSV3 CQE_FIELD_LOC(511, 256)
750 
751 struct hns_roce_v2_mpt_entry {
752 	__le32	byte_4_pd_hop_st;
753 	__le32	byte_8_mw_cnt_en;
754 	__le32	byte_12_mw_pa;
755 	__le32	bound_lkey;
756 	__le32	len_l;
757 	__le32	len_h;
758 	__le32	lkey;
759 	__le32	va_l;
760 	__le32	va_h;
761 	__le32	pbl_size;
762 	__le32	pbl_ba_l;
763 	__le32	byte_48_mode_ba;
764 	__le32	pa0_l;
765 	__le32	byte_56_pa0_h;
766 	__le32	pa1_l;
767 	__le32	byte_64_buf_pa1;
768 };
769 
770 #define MPT_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_mpt_entry, h, l)
771 
772 #define MPT_ST MPT_FIELD_LOC(1, 0)
773 #define MPT_PBL_HOP_NUM MPT_FIELD_LOC(3, 2)
774 #define MPT_PBL_BA_PG_SZ MPT_FIELD_LOC(7, 4)
775 #define MPT_PD MPT_FIELD_LOC(31, 8)
776 #define MPT_RA_EN MPT_FIELD_LOC(32, 32)
777 #define MPT_R_INV_EN MPT_FIELD_LOC(33, 33)
778 #define MPT_L_INV_EN MPT_FIELD_LOC(34, 34)
779 #define MPT_BIND_EN MPT_FIELD_LOC(35, 35)
780 #define MPT_ATOMIC_EN MPT_FIELD_LOC(36, 36)
781 #define MPT_RR_EN MPT_FIELD_LOC(37, 37)
782 #define MPT_RW_EN MPT_FIELD_LOC(38, 38)
783 #define MPT_LW_EN MPT_FIELD_LOC(39, 39)
784 #define MPT_MW_CNT MPT_FIELD_LOC(63, 40)
785 #define MPT_FRE MPT_FIELD_LOC(64, 64)
786 #define MPT_PA MPT_FIELD_LOC(65, 65)
787 #define MPT_ZBVA MPT_FIELD_LOC(66, 66)
788 #define MPT_SHARE MPT_FIELD_LOC(67, 67)
789 #define MPT_MR_MW MPT_FIELD_LOC(68, 68)
790 #define MPT_BPD MPT_FIELD_LOC(69, 69)
791 #define MPT_BQP MPT_FIELD_LOC(70, 70)
792 #define MPT_INNER_PA_VLD MPT_FIELD_LOC(71, 71)
793 #define MPT_MW_BIND_QPN MPT_FIELD_LOC(95, 72)
794 #define MPT_BOUND_LKEY MPT_FIELD_LOC(127, 96)
795 #define MPT_LEN MPT_FIELD_LOC(191, 128)
796 #define MPT_LKEY MPT_FIELD_LOC(223, 192)
797 #define MPT_VA MPT_FIELD_LOC(287, 224)
798 #define MPT_PBL_SIZE MPT_FIELD_LOC(319, 288)
799 #define MPT_PBL_BA MPT_FIELD_LOC(380, 320)
800 #define MPT_BLK_MODE MPT_FIELD_LOC(381, 381)
801 #define MPT_RSV0 MPT_FIELD_LOC(383, 382)
802 #define MPT_PA0 MPT_FIELD_LOC(441, 384)
803 #define MPT_BOUND_VA MPT_FIELD_LOC(447, 442)
804 #define MPT_PA1 MPT_FIELD_LOC(505, 448)
805 #define MPT_PERSIST_EN MPT_FIELD_LOC(506, 506)
806 #define MPT_RSV2 MPT_FIELD_LOC(507, 507)
807 #define MPT_PBL_BUF_PG_SZ MPT_FIELD_LOC(511, 508)
808 
809 #define V2_MPT_BYTE_4_MPT_ST_S 0
810 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
811 
812 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
813 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
814 
815 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
816 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
817 
818 #define V2_MPT_BYTE_4_PD_S 8
819 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
820 
821 #define V2_MPT_BYTE_8_RA_EN_S 0
822 
823 #define V2_MPT_BYTE_8_R_INV_EN_S 1
824 
825 #define V2_MPT_BYTE_8_L_INV_EN_S 2
826 
827 #define V2_MPT_BYTE_8_BIND_EN_S 3
828 
829 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4
830 
831 #define V2_MPT_BYTE_8_RR_EN_S 5
832 
833 #define V2_MPT_BYTE_8_RW_EN_S 6
834 
835 #define V2_MPT_BYTE_8_LW_EN_S 7
836 
837 #define V2_MPT_BYTE_8_MW_CNT_S 8
838 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
839 
840 #define V2_MPT_BYTE_12_FRE_S 0
841 
842 #define V2_MPT_BYTE_12_PA_S 1
843 
844 #define V2_MPT_BYTE_12_MR_MW_S 4
845 
846 #define V2_MPT_BYTE_12_BPD_S 5
847 
848 #define V2_MPT_BYTE_12_BQP_S 6
849 
850 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
851 
852 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
853 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
854 
855 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
856 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
857 
858 #define V2_MPT_BYTE_48_BLK_MODE_S 29
859 
860 #define V2_MPT_BYTE_56_PA0_H_S 0
861 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
862 
863 #define V2_MPT_BYTE_64_PA1_H_S 0
864 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
865 
866 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
867 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
868 
869 struct hns_roce_v2_db {
870 	__le32	data[2];
871 };
872 
873 #define DB_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_db, h, l)
874 
875 #define DB_TAG DB_FIELD_LOC(23, 0)
876 #define DB_CMD DB_FIELD_LOC(27, 24)
877 #define DB_FLAG DB_FIELD_LOC(31, 31)
878 #define DB_PI DB_FIELD_LOC(47, 32)
879 #define DB_SL DB_FIELD_LOC(50, 48)
880 #define DB_CQ_CI DB_FIELD_LOC(55, 32)
881 #define DB_CQ_NOTIFY DB_FIELD_LOC(56, 56)
882 #define DB_CQ_CMD_SN DB_FIELD_LOC(58, 57)
883 #define EQ_DB_TAG DB_FIELD_LOC(7, 0)
884 #define EQ_DB_CMD DB_FIELD_LOC(17, 16)
885 #define EQ_DB_CI DB_FIELD_LOC(55, 32)
886 
887 #define V2_DB_PRODUCER_IDX_S 0
888 #define V2_DB_PRODUCER_IDX_M GENMASK(15, 0)
889 
890 #define V2_CQ_DB_CONS_IDX_S 0
891 #define V2_CQ_DB_CONS_IDX_M GENMASK(23, 0)
892 
893 struct hns_roce_v2_ud_send_wqe {
894 	__le32	byte_4;
895 	__le32	msg_len;
896 	__le32	immtdata;
897 	__le32	byte_16;
898 	__le32	byte_20;
899 	__le32	byte_24;
900 	__le32	qkey;
901 	__le32	byte_32;
902 	__le32	byte_36;
903 	__le32	byte_40;
904 	u8	dmac[ETH_ALEN];
905 	u8	sgid_index;
906 	u8	smac_index;
907 	u8	dgid[GID_LEN_V2];
908 };
909 
910 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
911 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
912 
913 #define	V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
914 
915 #define	V2_UD_SEND_WQE_BYTE_4_CQE_S 8
916 
917 #define	V2_UD_SEND_WQE_BYTE_4_SE_S 11
918 
919 #define	V2_UD_SEND_WQE_BYTE_16_PD_S 0
920 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
921 
922 #define	V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
923 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
924 
925 #define	V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
926 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
927 
928 #define	V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
929 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
930 
931 #define	V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
932 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
933 
934 #define	V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
935 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
936 
937 #define	V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
938 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
939 
940 #define	V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
941 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
942 
943 #define	V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
944 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
945 
946 #define	V2_UD_SEND_WQE_BYTE_40_SL_S 20
947 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
948 
949 #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
950 
951 #define	V2_UD_SEND_WQE_BYTE_40_LBI_S 31
952 
953 struct hns_roce_v2_rc_send_wqe {
954 	__le32		byte_4;
955 	__le32		msg_len;
956 	union {
957 		__le32  inv_key;
958 		__le32  immtdata;
959 	};
960 	__le32		byte_16;
961 	__le32		byte_20;
962 	__le32		rkey;
963 	__le64		va;
964 };
965 
966 #define	V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
967 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
968 
969 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5
970 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5)
971 
972 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13
973 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13)
974 
975 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15
976 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15)
977 
978 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
979 
980 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
981 
982 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
983 
984 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10
985 
986 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11
987 
988 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
989 
990 #define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31
991 
992 #define	V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
993 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
994 
995 #define	V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
996 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
997 
998 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
999 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1000 
1001 #define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31
1002 
1003 struct hns_roce_wqe_frmr_seg {
1004 	__le32	pbl_size;
1005 	__le32	byte_40;
1006 };
1007 
1008 #define FRMR_WQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_wqe_frmr_seg, h, l)
1009 
1010 #define FRMR_PBL_SIZE FRMR_WQE_FIELD_LOC(31, 0)
1011 #define FRMR_BLOCK_SIZE FRMR_WQE_FIELD_LOC(35, 32)
1012 #define FRMR_PBL_BUF_PG_SZ FRMR_WQE_FIELD_LOC(39, 36)
1013 #define FRMR_BLK_MODE FRMR_WQE_FIELD_LOC(40, 40)
1014 #define FRMR_ZBVA FRMR_WQE_FIELD_LOC(41, 41)
1015 #define FRMR_BIND_EN FRMR_WQE_FIELD_LOC(42, 42)
1016 #define FRMR_ATOMIC FRMR_WQE_FIELD_LOC(43, 43)
1017 #define FRMR_RR FRMR_WQE_FIELD_LOC(44, 44)
1018 #define FRMR_RW FRMR_WQE_FIELD_LOC(45, 45)
1019 #define FRMR_LW FRMR_WQE_FIELD_LOC(46, 46)
1020 
1021 struct hns_roce_v2_wqe_data_seg {
1022 	__le32    len;
1023 	__le32    lkey;
1024 	__le64    addr;
1025 };
1026 
1027 struct hns_roce_query_version {
1028 	__le16 rocee_vendor_id;
1029 	__le16 rocee_hw_version;
1030 	__le32 rsv[5];
1031 };
1032 
1033 struct hns_roce_query_fw_info {
1034 	__le32 fw_ver;
1035 	__le32 rsv[5];
1036 };
1037 
1038 struct hns_roce_func_clear {
1039 	__le32 rst_funcid_en;
1040 	__le32 func_done;
1041 	__le32 rsv[4];
1042 };
1043 
1044 #define FUNC_CLEAR_RST_FUN_DONE_S 0
1045 /* Each physical function manages up to 248 virtual functions, it takes up to
1046  * 100ms for each function to execute clear. If an abnormal reset occurs, it is
1047  * executed twice at most, so it takes up to 249 * 2 * 100ms.
1048  */
1049 #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS	(249 * 2 * 100)
1050 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL	40
1051 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT	20
1052 
1053 /* Fields of HNS_ROCE_OPC_EXT_CFG */
1054 #define EXT_CFG_VF_ID CMQ_REQ_FIELD_LOC(31, 0)
1055 #define EXT_CFG_QP_PI_IDX CMQ_REQ_FIELD_LOC(45, 32)
1056 #define EXT_CFG_QP_PI_NUM CMQ_REQ_FIELD_LOC(63, 48)
1057 #define EXT_CFG_QP_NUM CMQ_REQ_FIELD_LOC(87, 64)
1058 #define EXT_CFG_QP_IDX CMQ_REQ_FIELD_LOC(119, 96)
1059 #define EXT_CFG_LLM_IDX CMQ_REQ_FIELD_LOC(139, 128)
1060 #define EXT_CFG_LLM_NUM CMQ_REQ_FIELD_LOC(156, 144)
1061 
1062 #define CFG_LLM_A_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1063 #define CFG_LLM_A_BA_H CMQ_REQ_FIELD_LOC(63, 32)
1064 #define CFG_LLM_A_DEPTH CMQ_REQ_FIELD_LOC(76, 64)
1065 #define CFG_LLM_A_PGSZ CMQ_REQ_FIELD_LOC(83, 80)
1066 #define CFG_LLM_A_INIT_EN CMQ_REQ_FIELD_LOC(84, 84)
1067 #define CFG_LLM_A_HEAD_BA_L CMQ_REQ_FIELD_LOC(127, 96)
1068 #define CFG_LLM_A_HEAD_BA_H CMQ_REQ_FIELD_LOC(147, 128)
1069 #define CFG_LLM_A_HEAD_NXTPTR CMQ_REQ_FIELD_LOC(159, 148)
1070 #define CFG_LLM_A_HEAD_PTR CMQ_REQ_FIELD_LOC(171, 160)
1071 #define CFG_LLM_B_TAIL_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1072 #define CFG_LLM_B_TAIL_BA_H CMQ_REQ_FIELD_LOC(63, 32)
1073 #define CFG_LLM_B_TAIL_PTR CMQ_REQ_FIELD_LOC(75, 64)
1074 
1075 /* Fields of HNS_ROCE_OPC_CFG_GLOBAL_PARAM */
1076 #define CFG_GLOBAL_PARAM_1US_CYCLES CMQ_REQ_FIELD_LOC(9, 0)
1077 #define CFG_GLOBAL_PARAM_UDP_PORT CMQ_REQ_FIELD_LOC(31, 16)
1078 
1079 /*
1080  * Fields of HNS_ROCE_OPC_QUERY_PF_RES, HNS_ROCE_OPC_QUERY_VF_RES
1081  * and HNS_ROCE_OPC_ALLOC_VF_RES
1082  */
1083 #define FUNC_RES_A_VF_ID CMQ_REQ_FIELD_LOC(7, 0)
1084 #define FUNC_RES_A_QPC_BT_IDX CMQ_REQ_FIELD_LOC(42, 32)
1085 #define FUNC_RES_A_QPC_BT_NUM CMQ_REQ_FIELD_LOC(59, 48)
1086 #define FUNC_RES_A_SRQC_BT_IDX CMQ_REQ_FIELD_LOC(72, 64)
1087 #define FUNC_RES_A_SRQC_BT_NUM CMQ_REQ_FIELD_LOC(89, 80)
1088 #define FUNC_RES_A_CQC_BT_IDX CMQ_REQ_FIELD_LOC(104, 96)
1089 #define FUNC_RES_A_CQC_BT_NUM CMQ_REQ_FIELD_LOC(121, 112)
1090 #define FUNC_RES_A_MPT_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
1091 #define FUNC_RES_A_MPT_BT_NUM CMQ_REQ_FIELD_LOC(153, 144)
1092 #define FUNC_RES_A_EQC_BT_IDX CMQ_REQ_FIELD_LOC(168, 160)
1093 #define FUNC_RES_A_EQC_BT_NUM CMQ_REQ_FIELD_LOC(185, 176)
1094 #define FUNC_RES_B_SMAC_IDX CMQ_REQ_FIELD_LOC(39, 32)
1095 #define FUNC_RES_B_SMAC_NUM CMQ_REQ_FIELD_LOC(48, 40)
1096 #define FUNC_RES_B_SGID_IDX CMQ_REQ_FIELD_LOC(71, 64)
1097 #define FUNC_RES_B_SGID_NUM CMQ_REQ_FIELD_LOC(80, 72)
1098 #define FUNC_RES_B_QID_IDX CMQ_REQ_FIELD_LOC(105, 96)
1099 #define FUNC_RES_B_QID_NUM CMQ_REQ_FIELD_LOC(122, 112)
1100 #define FUNC_RES_V_QID_NUM CMQ_REQ_FIELD_LOC(115, 112)
1101 
1102 #define FUNC_RES_B_SCCC_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
1103 #define FUNC_RES_B_SCCC_BT_NUM CMQ_REQ_FIELD_LOC(145, 137)
1104 #define FUNC_RES_B_GMV_BT_IDX CMQ_REQ_FIELD_LOC(167, 160)
1105 #define FUNC_RES_B_GMV_BT_NUM CMQ_REQ_FIELD_LOC(176, 168)
1106 #define FUNC_RES_V_GMV_BT_NUM CMQ_REQ_FIELD_LOC(184, 176)
1107 
1108 /* Fields of HNS_ROCE_OPC_QUERY_PF_TIMER_RES */
1109 #define PF_TIMER_RES_QPC_ITEM_IDX CMQ_REQ_FIELD_LOC(43, 32)
1110 #define PF_TIMER_RES_QPC_ITEM_NUM CMQ_REQ_FIELD_LOC(60, 48)
1111 #define PF_TIMER_RES_CQC_ITEM_IDX CMQ_REQ_FIELD_LOC(74, 64)
1112 #define PF_TIMER_RES_CQC_ITEM_NUM CMQ_REQ_FIELD_LOC(91, 80)
1113 
1114 struct hns_roce_vf_switch {
1115 	__le32 rocee_sel;
1116 	__le32 fun_id;
1117 	__le32 cfg;
1118 	__le32 resv1;
1119 	__le32 resv2;
1120 	__le32 resv3;
1121 };
1122 
1123 #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1124 #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1125 
1126 #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1127 #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1128 #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1129 
1130 struct hns_roce_post_mbox {
1131 	__le32	in_param_l;
1132 	__le32	in_param_h;
1133 	__le32	out_param_l;
1134 	__le32	out_param_h;
1135 	__le32	cmd_tag;
1136 	__le32	token_event_en;
1137 };
1138 
1139 struct hns_roce_mbox_status {
1140 	__le32	mb_status_hw_run;
1141 	__le32	rsv[5];
1142 };
1143 
1144 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1145 
1146 #define MB_ST_HW_RUN_M BIT(31)
1147 #define MB_ST_COMPLETE_M GENMASK(7, 0)
1148 
1149 #define MB_ST_COMPLETE_SUCC 1
1150 
1151 /* Fields of HNS_ROCE_OPC_CFG_BT_ATTR */
1152 #define CFG_BT_ATTR_QPC_BA_PGSZ CMQ_REQ_FIELD_LOC(3, 0)
1153 #define CFG_BT_ATTR_QPC_BUF_PGSZ CMQ_REQ_FIELD_LOC(7, 4)
1154 #define CFG_BT_ATTR_QPC_HOPNUM CMQ_REQ_FIELD_LOC(9, 8)
1155 #define CFG_BT_ATTR_SRQC_BA_PGSZ CMQ_REQ_FIELD_LOC(35, 32)
1156 #define CFG_BT_ATTR_SRQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(39, 36)
1157 #define CFG_BT_ATTR_SRQC_HOPNUM CMQ_REQ_FIELD_LOC(41, 40)
1158 #define CFG_BT_ATTR_CQC_BA_PGSZ CMQ_REQ_FIELD_LOC(67, 64)
1159 #define CFG_BT_ATTR_CQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(71, 68)
1160 #define CFG_BT_ATTR_CQC_HOPNUM CMQ_REQ_FIELD_LOC(73, 72)
1161 #define CFG_BT_ATTR_MPT_BA_PGSZ CMQ_REQ_FIELD_LOC(99, 96)
1162 #define CFG_BT_ATTR_MPT_BUF_PGSZ CMQ_REQ_FIELD_LOC(103, 100)
1163 #define CFG_BT_ATTR_MPT_HOPNUM CMQ_REQ_FIELD_LOC(105, 104)
1164 #define CFG_BT_ATTR_SCCC_BA_PGSZ CMQ_REQ_FIELD_LOC(131, 128)
1165 #define CFG_BT_ATTR_SCCC_BUF_PGSZ CMQ_REQ_FIELD_LOC(135, 132)
1166 #define CFG_BT_ATTR_SCCC_HOPNUM CMQ_REQ_FIELD_LOC(137, 136)
1167 
1168 /* Fields of HNS_ROCE_OPC_CFG_ENTRY_SIZE */
1169 #define CFG_HEM_ENTRY_SIZE_TYPE CMQ_REQ_FIELD_LOC(31, 0)
1170 enum {
1171 	HNS_ROCE_CFG_QPC_SIZE = BIT(0),
1172 	HNS_ROCE_CFG_SCCC_SIZE = BIT(1),
1173 };
1174 
1175 #define CFG_HEM_ENTRY_SIZE_VALUE CMQ_REQ_FIELD_LOC(191, 160)
1176 
1177 /* Fields of HNS_ROCE_OPC_CFG_GMV_BT */
1178 #define CFG_GMV_BT_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1179 #define CFG_GMV_BT_BA_H CMQ_REQ_FIELD_LOC(51, 32)
1180 #define CFG_GMV_BT_IDX CMQ_REQ_FIELD_LOC(95, 64)
1181 
1182 struct hns_roce_cfg_sgid_tb {
1183 	__le32	table_idx_rsv;
1184 	__le32	vf_sgid_l;
1185 	__le32	vf_sgid_ml;
1186 	__le32	vf_sgid_mh;
1187 	__le32	vf_sgid_h;
1188 	__le32	vf_sgid_type_rsv;
1189 };
1190 
1191 #define CFG_SGID_TB_TABLE_IDX_S 0
1192 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1193 
1194 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1195 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1196 
1197 struct hns_roce_cfg_smac_tb {
1198 	__le32	tb_idx_rsv;
1199 	__le32	vf_smac_l;
1200 	__le32	vf_smac_h_rsv;
1201 	__le32	rsv[3];
1202 };
1203 #define CFG_SMAC_TB_IDX_S 0
1204 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1205 
1206 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1207 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1208 
1209 struct hns_roce_cfg_gmv_tb_a {
1210 	__le32 vf_sgid_l;
1211 	__le32 vf_sgid_ml;
1212 	__le32 vf_sgid_mh;
1213 	__le32 vf_sgid_h;
1214 	__le32 vf_sgid_type_vlan;
1215 	__le32 resv;
1216 };
1217 
1218 #define CFG_GMV_TB_SGID_IDX_S 0
1219 #define CFG_GMV_TB_SGID_IDX_M GENMASK(7, 0)
1220 
1221 #define CFG_GMV_TB_VF_SGID_TYPE_S 0
1222 #define CFG_GMV_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1223 
1224 #define CFG_GMV_TB_VF_VLAN_EN_S 2
1225 
1226 #define CFG_GMV_TB_VF_VLAN_ID_S 16
1227 #define CFG_GMV_TB_VF_VLAN_ID_M GENMASK(27, 16)
1228 
1229 struct hns_roce_cfg_gmv_tb_b {
1230 	__le32	vf_smac_l;
1231 	__le32	vf_smac_h;
1232 	__le32	table_idx_rsv;
1233 	__le32	resv[3];
1234 };
1235 
1236 #define CFG_GMV_TB_SMAC_H_S 0
1237 #define CFG_GMV_TB_SMAC_H_M GENMASK(15, 0)
1238 
1239 #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5
1240 struct hns_roce_query_pf_caps_a {
1241 	u8 number_ports;
1242 	u8 local_ca_ack_delay;
1243 	__le16 max_sq_sg;
1244 	__le16 max_sq_inline;
1245 	__le16 max_rq_sg;
1246 	__le32 max_extend_sg;
1247 	__le16 num_qpc_timer;
1248 	__le16 num_cqc_timer;
1249 	__le16 max_srq_sges;
1250 	u8 num_aeq_vectors;
1251 	u8 num_other_vectors;
1252 	u8 max_sq_desc_sz;
1253 	u8 max_rq_desc_sz;
1254 	u8 max_srq_desc_sz;
1255 	u8 cqe_sz;
1256 };
1257 
1258 struct hns_roce_query_pf_caps_b {
1259 	u8 mtpt_entry_sz;
1260 	u8 irrl_entry_sz;
1261 	u8 trrl_entry_sz;
1262 	u8 cqc_entry_sz;
1263 	u8 srqc_entry_sz;
1264 	u8 idx_entry_sz;
1265 	u8 sccc_sz;
1266 	u8 max_mtu;
1267 	__le16 qpc_sz;
1268 	__le16 qpc_timer_entry_sz;
1269 	__le16 cqc_timer_entry_sz;
1270 	u8 min_cqes;
1271 	u8 min_wqes;
1272 	__le32 page_size_cap;
1273 	u8 pkey_table_len;
1274 	u8 phy_num_uars;
1275 	u8 ctx_hop_num;
1276 	u8 pbl_hop_num;
1277 };
1278 
1279 struct hns_roce_query_pf_caps_c {
1280 	__le32 cap_flags_num_pds;
1281 	__le32 max_gid_num_cqs;
1282 	__le32 cq_depth;
1283 	__le32 num_mrws;
1284 	__le32 ord_num_qps;
1285 	__le16 sq_depth;
1286 	__le16 rq_depth;
1287 };
1288 
1289 #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0
1290 #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)
1291 
1292 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20
1293 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)
1294 
1295 #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0
1296 #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)
1297 
1298 #define V2_QUERY_PF_CAPS_C_MAX_GID_S 20
1299 #define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20)
1300 
1301 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0
1302 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)
1303 
1304 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0
1305 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)
1306 
1307 #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0
1308 #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)
1309 
1310 #define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20
1311 #define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20)
1312 
1313 struct hns_roce_query_pf_caps_d {
1314 	__le32 wq_hop_num_max_srqs;
1315 	__le16 srq_depth;
1316 	__le16 cap_flags_ex;
1317 	__le32 num_ceqs_ceq_depth;
1318 	__le32 arm_st_aeq_depth;
1319 	__le32 num_uars_rsv_pds;
1320 	__le32 rsv_uars_rsv_qps;
1321 };
1322 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0
1323 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)
1324 
1325 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20
1326 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20)
1327 
1328 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22
1329 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)
1330 
1331 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24
1332 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24)
1333 
1334 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_S 26
1335 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_M GENMASK(29, 26)
1336 
1337 struct hns_roce_congestion_algorithm {
1338 	u8 alg_sel;
1339 	u8 alg_sub_sel;
1340 	u8 dip_vld;
1341 	u8 wnd_mode_sel;
1342 };
1343 
1344 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0
1345 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)
1346 
1347 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22
1348 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)
1349 
1350 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0
1351 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)
1352 
1353 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22
1354 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)
1355 
1356 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24
1357 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24)
1358 
1359 #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0
1360 #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)
1361 
1362 #define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20
1363 #define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20)
1364 
1365 #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0
1366 #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)
1367 
1368 #define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20
1369 #define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20)
1370 
1371 struct hns_roce_query_pf_caps_e {
1372 	__le32 chunk_size_shift_rsv_mrws;
1373 	__le32 rsv_cqs;
1374 	__le32 rsv_srqs;
1375 	__le32 rsv_lkey;
1376 	__le16 ceq_max_cnt;
1377 	__le16 ceq_period;
1378 	__le16 aeq_max_cnt;
1379 	__le16 aeq_period;
1380 };
1381 
1382 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0
1383 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)
1384 
1385 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20
1386 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)
1387 
1388 #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0
1389 #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)
1390 
1391 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0
1392 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)
1393 
1394 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0
1395 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)
1396 
1397 struct hns_roce_cmq_req {
1398 	__le32 data[6];
1399 };
1400 
1401 #define CMQ_REQ_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cmq_req, h, l)
1402 
1403 struct hns_roce_cmq_desc {
1404 	__le16 opcode;
1405 	__le16 flag;
1406 	__le16 retval;
1407 	__le16 rsv;
1408 	union {
1409 		__le32 data[6];
1410 		struct {
1411 			__le32 own_func_num;
1412 			__le32 own_mac_id;
1413 			__le32 rsv[4];
1414 		} func_info;
1415 	};
1416 
1417 };
1418 
1419 struct hns_roce_v2_cmq_ring {
1420 	dma_addr_t desc_dma_addr;
1421 	struct hns_roce_cmq_desc *desc;
1422 	u32 head;
1423 	u16 buf_size;
1424 	u16 desc_num;
1425 	u8 flag;
1426 	spinlock_t lock; /* command queue lock */
1427 };
1428 
1429 struct hns_roce_v2_cmq {
1430 	struct hns_roce_v2_cmq_ring csq;
1431 	u16 tx_timeout;
1432 };
1433 
1434 struct hns_roce_link_table {
1435 	struct hns_roce_buf_list table;
1436 	struct hns_roce_buf *buf;
1437 };
1438 
1439 #define HNS_ROCE_EXT_LLM_ENTRY(addr, id) (((id) << (64 - 12)) | ((addr) >> 12))
1440 #define HNS_ROCE_EXT_LLM_MIN_PAGES(que_num) ((que_num) * 4 + 2)
1441 
1442 struct hns_roce_v2_priv {
1443 	struct hnae3_handle *handle;
1444 	struct hns_roce_v2_cmq cmq;
1445 	struct hns_roce_link_table ext_llm;
1446 };
1447 
1448 struct hns_roce_dip {
1449 	u8 dgid[GID_LEN_V2];
1450 	u8 dip_idx;
1451 	struct list_head node;	/* all dips are on a list */
1452 };
1453 
1454 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM	0x0
1455 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL	0x0
1456 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM	0x0
1457 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL	0x0
1458 
1459 #define HNS_ROCE_V2_EQ_STATE_INVALID		0
1460 #define HNS_ROCE_V2_EQ_STATE_VALID		1
1461 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW		2
1462 #define HNS_ROCE_V2_EQ_STATE_FAILURE		3
1463 
1464 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0		0
1465 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1		1
1466 
1467 #define HNS_ROCE_V2_EQ_COALESCE_0		0
1468 #define HNS_ROCE_V2_EQ_COALESCE_1		1
1469 
1470 #define HNS_ROCE_V2_EQ_FIRED			0
1471 #define HNS_ROCE_V2_EQ_ARMED			1
1472 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED		3
1473 
1474 #define HNS_ROCE_EQ_INIT_EQE_CNT		0
1475 #define HNS_ROCE_EQ_INIT_PROD_IDX		0
1476 #define HNS_ROCE_EQ_INIT_REPORT_TIMER		0
1477 #define HNS_ROCE_EQ_INIT_MSI_IDX		0
1478 #define HNS_ROCE_EQ_INIT_CONS_IDX		0
1479 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA		0
1480 
1481 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S		31
1482 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S		31
1483 
1484 #define HNS_ROCE_V2_COMP_EQE_NUM		0x1000
1485 #define HNS_ROCE_V2_ASYNC_EQE_NUM		0x1000
1486 
1487 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S	0
1488 #define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S		1
1489 
1490 #define HNS_ROCE_EQ_DB_CMD_AEQ			0x0
1491 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED		0x1
1492 #define HNS_ROCE_EQ_DB_CMD_CEQ			0x2
1493 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED		0x3
1494 
1495 #define EQ_ENABLE				1
1496 #define EQ_DISABLE				0
1497 
1498 #define EQ_REG_OFFSET				0x4
1499 
1500 #define HNS_ROCE_INT_NAME_LEN			32
1501 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1502 
1503 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1504 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1505 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1506 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1507 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1508 
1509 struct hns_roce_eq_context {
1510 	__le32	data[16];
1511 };
1512 
1513 #define EQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_eq_context, h, l)
1514 
1515 #define EQC_EQ_ST EQC_FIELD_LOC(1, 0)
1516 #define EQC_EQE_HOP_NUM EQC_FIELD_LOC(3, 2)
1517 #define EQC_OVER_IGNORE EQC_FIELD_LOC(4, 4)
1518 #define EQC_COALESCE EQC_FIELD_LOC(5, 5)
1519 #define EQC_ARM_ST EQC_FIELD_LOC(7, 6)
1520 #define EQC_EQN EQC_FIELD_LOC(15, 8)
1521 #define EQC_EQE_CNT EQC_FIELD_LOC(31, 16)
1522 #define EQC_EQE_BA_PG_SZ EQC_FIELD_LOC(35, 32)
1523 #define EQC_EQE_BUF_PG_SZ EQC_FIELD_LOC(39, 36)
1524 #define EQC_EQ_PROD_INDX EQC_FIELD_LOC(63, 40)
1525 #define EQC_EQ_MAX_CNT EQC_FIELD_LOC(79, 64)
1526 #define EQC_EQ_PERIOD EQC_FIELD_LOC(95, 80)
1527 #define EQC_EQE_REPORT_TIMER EQC_FIELD_LOC(127, 96)
1528 #define EQC_EQE_BA_L EQC_FIELD_LOC(159, 128)
1529 #define EQC_EQE_BA_H EQC_FIELD_LOC(188, 160)
1530 #define EQC_SHIFT EQC_FIELD_LOC(199, 192)
1531 #define EQC_MSI_INDX EQC_FIELD_LOC(207, 200)
1532 #define EQC_CUR_EQE_BA_L EQC_FIELD_LOC(223, 208)
1533 #define EQC_CUR_EQE_BA_M EQC_FIELD_LOC(255, 224)
1534 #define EQC_CUR_EQE_BA_H EQC_FIELD_LOC(259, 256)
1535 #define EQC_EQ_CONS_INDX EQC_FIELD_LOC(287, 264)
1536 #define EQC_NEX_EQE_BA_L EQC_FIELD_LOC(319, 288)
1537 #define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320)
1538 #define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340)
1539 
1540 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1541 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1542 
1543 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1544 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1545 
1546 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1547 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1548 
1549 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1550 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1551 
1552 #define MAX_SERVICE_LEVEL 0x7
1553 
1554 struct hns_roce_wqe_atomic_seg {
1555 	__le64          fetchadd_swap_data;
1556 	__le64          cmp_data;
1557 };
1558 
1559 struct hns_roce_sccc_clr {
1560 	__le32 qpn;
1561 	__le32 rsv[5];
1562 };
1563 
1564 struct hns_roce_sccc_clr_done {
1565 	__le32 clr_done;
1566 	__le32 rsv[5];
1567 };
1568 
1569 int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
1570 			       int *buffer);
1571 
1572 static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
1573 				    void __iomem *dest)
1574 {
1575 	struct hns_roce_v2_priv *priv = hr_dev->priv;
1576 	struct hnae3_handle *handle = priv->handle;
1577 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1578 
1579 	if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
1580 		hns_roce_write64_k(val, dest);
1581 }
1582 
1583 #endif
1584