1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <linux/types.h> 38 #include <net/addrconf.h> 39 #include <rdma/ib_addr.h> 40 #include <rdma/ib_umem.h> 41 42 #include "hnae3.h" 43 #include "hns_roce_common.h" 44 #include "hns_roce_device.h" 45 #include "hns_roce_cmd.h" 46 #include "hns_roce_hem.h" 47 #include "hns_roce_hw_v2.h" 48 49 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 50 struct ib_sge *sg) 51 { 52 dseg->lkey = cpu_to_le32(sg->lkey); 53 dseg->addr = cpu_to_le64(sg->addr); 54 dseg->len = cpu_to_le32(sg->length); 55 } 56 57 static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 58 unsigned int *sge_ind) 59 { 60 struct hns_roce_v2_wqe_data_seg *dseg; 61 struct ib_sge *sg; 62 int num_in_wqe = 0; 63 int extend_sge_num; 64 int fi_sge_num; 65 int se_sge_num; 66 int shift; 67 int i; 68 69 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) 70 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; 71 extend_sge_num = wr->num_sge - num_in_wqe; 72 sg = wr->sg_list + num_in_wqe; 73 shift = qp->hr_buf.page_shift; 74 75 /* 76 * Check whether wr->num_sge sges are in the same page. If not, we 77 * should calculate how many sges in the first page and the second 78 * page. 79 */ 80 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1)); 81 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) - 82 (uintptr_t)dseg) / 83 sizeof(struct hns_roce_v2_wqe_data_seg); 84 if (extend_sge_num > fi_sge_num) { 85 se_sge_num = extend_sge_num - fi_sge_num; 86 for (i = 0; i < fi_sge_num; i++) { 87 set_data_seg_v2(dseg++, sg + i); 88 (*sge_ind)++; 89 } 90 dseg = get_send_extend_sge(qp, 91 (*sge_ind) & (qp->sge.sge_cnt - 1)); 92 for (i = 0; i < se_sge_num; i++) { 93 set_data_seg_v2(dseg++, sg + fi_sge_num + i); 94 (*sge_ind)++; 95 } 96 } else { 97 for (i = 0; i < extend_sge_num; i++) { 98 set_data_seg_v2(dseg++, sg + i); 99 (*sge_ind)++; 100 } 101 } 102 } 103 104 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 105 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 106 void *wqe, unsigned int *sge_ind, 107 const struct ib_send_wr **bad_wr) 108 { 109 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 110 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 111 struct hns_roce_qp *qp = to_hr_qp(ibqp); 112 int i; 113 114 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) { 115 if (le32_to_cpu(rc_sq_wqe->msg_len) > 116 hr_dev->caps.max_sq_inline) { 117 *bad_wr = wr; 118 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal", 119 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline); 120 return -EINVAL; 121 } 122 123 if (wr->opcode == IB_WR_RDMA_READ) { 124 dev_err(hr_dev->dev, "Not support inline data!\n"); 125 return -EINVAL; 126 } 127 128 for (i = 0; i < wr->num_sge; i++) { 129 memcpy(wqe, ((void *)wr->sg_list[i].addr), 130 wr->sg_list[i].length); 131 wqe += wr->sg_list[i].length; 132 } 133 134 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 135 1); 136 } else { 137 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) { 138 for (i = 0; i < wr->num_sge; i++) { 139 if (likely(wr->sg_list[i].length)) { 140 set_data_seg_v2(dseg, wr->sg_list + i); 141 dseg++; 142 } 143 } 144 } else { 145 roce_set_field(rc_sq_wqe->byte_20, 146 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 147 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 148 (*sge_ind) & (qp->sge.sge_cnt - 1)); 149 150 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) { 151 if (likely(wr->sg_list[i].length)) { 152 set_data_seg_v2(dseg, wr->sg_list + i); 153 dseg++; 154 } 155 } 156 157 set_extend_sge(qp, wr, sge_ind); 158 } 159 160 roce_set_field(rc_sq_wqe->byte_16, 161 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 162 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge); 163 } 164 165 return 0; 166 } 167 168 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 169 const struct ib_qp_attr *attr, 170 int attr_mask, enum ib_qp_state cur_state, 171 enum ib_qp_state new_state); 172 173 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 174 const struct ib_send_wr *wr, 175 const struct ib_send_wr **bad_wr) 176 { 177 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 178 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 179 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe; 180 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe; 181 struct hns_roce_qp *qp = to_hr_qp(ibqp); 182 struct device *dev = hr_dev->dev; 183 struct hns_roce_v2_db sq_db; 184 struct ib_qp_attr attr; 185 unsigned int sge_ind = 0; 186 unsigned int owner_bit; 187 unsigned long flags; 188 unsigned int ind; 189 void *wqe = NULL; 190 bool loopback; 191 int attr_mask; 192 u32 tmp_len; 193 int ret = 0; 194 u8 *smac; 195 int nreq; 196 int i; 197 198 if (unlikely(ibqp->qp_type != IB_QPT_RC && 199 ibqp->qp_type != IB_QPT_GSI && 200 ibqp->qp_type != IB_QPT_UD)) { 201 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type); 202 *bad_wr = wr; 203 return -EOPNOTSUPP; 204 } 205 206 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT || 207 qp->state == IB_QPS_RTR)) { 208 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state); 209 *bad_wr = wr; 210 return -EINVAL; 211 } 212 213 spin_lock_irqsave(&qp->sq.lock, flags); 214 ind = qp->sq_next_wqe; 215 sge_ind = qp->next_sge; 216 217 for (nreq = 0; wr; ++nreq, wr = wr->next) { 218 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 219 ret = -ENOMEM; 220 *bad_wr = wr; 221 goto out; 222 } 223 224 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 225 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n", 226 wr->num_sge, qp->sq.max_gs); 227 ret = -EINVAL; 228 *bad_wr = wr; 229 goto out; 230 } 231 232 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 233 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = 234 wr->wr_id; 235 236 owner_bit = 237 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 238 tmp_len = 0; 239 240 /* Corresponding to the QP type, wqe process separately */ 241 if (ibqp->qp_type == IB_QPT_GSI) { 242 ud_sq_wqe = wqe; 243 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); 244 245 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, 246 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); 247 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, 248 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); 249 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, 250 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); 251 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, 252 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); 253 roce_set_field(ud_sq_wqe->byte_48, 254 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, 255 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, 256 ah->av.mac[4]); 257 roce_set_field(ud_sq_wqe->byte_48, 258 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, 259 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, 260 ah->av.mac[5]); 261 262 /* MAC loopback */ 263 smac = (u8 *)hr_dev->dev_addr[qp->port]; 264 loopback = ether_addr_equal_unaligned(ah->av.mac, 265 smac) ? 1 : 0; 266 267 roce_set_bit(ud_sq_wqe->byte_40, 268 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); 269 270 roce_set_field(ud_sq_wqe->byte_4, 271 V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 272 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, 273 HNS_ROCE_V2_WQE_OP_SEND); 274 275 for (i = 0; i < wr->num_sge; i++) 276 tmp_len += wr->sg_list[i].length; 277 278 ud_sq_wqe->msg_len = 279 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len); 280 281 switch (wr->opcode) { 282 case IB_WR_SEND_WITH_IMM: 283 case IB_WR_RDMA_WRITE_WITH_IMM: 284 ud_sq_wqe->immtdata = 285 cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 286 break; 287 default: 288 ud_sq_wqe->immtdata = 0; 289 break; 290 } 291 292 /* Set sig attr */ 293 roce_set_bit(ud_sq_wqe->byte_4, 294 V2_UD_SEND_WQE_BYTE_4_CQE_S, 295 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 296 297 /* Set se attr */ 298 roce_set_bit(ud_sq_wqe->byte_4, 299 V2_UD_SEND_WQE_BYTE_4_SE_S, 300 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 301 302 roce_set_bit(ud_sq_wqe->byte_4, 303 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 304 305 roce_set_field(ud_sq_wqe->byte_16, 306 V2_UD_SEND_WQE_BYTE_16_PD_M, 307 V2_UD_SEND_WQE_BYTE_16_PD_S, 308 to_hr_pd(ibqp->pd)->pdn); 309 310 roce_set_field(ud_sq_wqe->byte_16, 311 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 312 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, 313 wr->num_sge); 314 315 roce_set_field(ud_sq_wqe->byte_20, 316 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 317 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 318 sge_ind & (qp->sge.sge_cnt - 1)); 319 320 roce_set_field(ud_sq_wqe->byte_24, 321 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 322 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); 323 ud_sq_wqe->qkey = 324 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 325 qp->qkey : ud_wr(wr)->remote_qkey); 326 roce_set_field(ud_sq_wqe->byte_32, 327 V2_UD_SEND_WQE_BYTE_32_DQPN_M, 328 V2_UD_SEND_WQE_BYTE_32_DQPN_S, 329 ud_wr(wr)->remote_qpn); 330 331 roce_set_field(ud_sq_wqe->byte_36, 332 V2_UD_SEND_WQE_BYTE_36_VLAN_M, 333 V2_UD_SEND_WQE_BYTE_36_VLAN_S, 334 le16_to_cpu(ah->av.vlan)); 335 roce_set_field(ud_sq_wqe->byte_36, 336 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 337 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, 338 ah->av.hop_limit); 339 roce_set_field(ud_sq_wqe->byte_36, 340 V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 341 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, 342 ah->av.sl_tclass_flowlabel >> 343 HNS_ROCE_TCLASS_SHIFT); 344 roce_set_field(ud_sq_wqe->byte_40, 345 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 346 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, 347 ah->av.sl_tclass_flowlabel & 348 HNS_ROCE_FLOW_LABEL_MASK); 349 roce_set_field(ud_sq_wqe->byte_40, 350 V2_UD_SEND_WQE_BYTE_40_SL_M, 351 V2_UD_SEND_WQE_BYTE_40_SL_S, 352 le32_to_cpu(ah->av.sl_tclass_flowlabel) >> 353 HNS_ROCE_SL_SHIFT); 354 roce_set_field(ud_sq_wqe->byte_40, 355 V2_UD_SEND_WQE_BYTE_40_PORTN_M, 356 V2_UD_SEND_WQE_BYTE_40_PORTN_S, 357 qp->port); 358 359 roce_set_field(ud_sq_wqe->byte_48, 360 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, 361 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, 362 hns_get_gid_index(hr_dev, qp->phy_port, 363 ah->av.gid_index)); 364 365 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], 366 GID_LEN_V2); 367 368 set_extend_sge(qp, wr, &sge_ind); 369 ind++; 370 } else if (ibqp->qp_type == IB_QPT_RC) { 371 rc_sq_wqe = wqe; 372 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); 373 for (i = 0; i < wr->num_sge; i++) 374 tmp_len += wr->sg_list[i].length; 375 376 rc_sq_wqe->msg_len = 377 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len); 378 379 switch (wr->opcode) { 380 case IB_WR_SEND_WITH_IMM: 381 case IB_WR_RDMA_WRITE_WITH_IMM: 382 rc_sq_wqe->immtdata = 383 cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 384 break; 385 case IB_WR_SEND_WITH_INV: 386 rc_sq_wqe->inv_key = 387 cpu_to_le32(wr->ex.invalidate_rkey); 388 break; 389 default: 390 rc_sq_wqe->immtdata = 0; 391 break; 392 } 393 394 roce_set_bit(rc_sq_wqe->byte_4, 395 V2_RC_SEND_WQE_BYTE_4_FENCE_S, 396 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 397 398 roce_set_bit(rc_sq_wqe->byte_4, 399 V2_RC_SEND_WQE_BYTE_4_SE_S, 400 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 401 402 roce_set_bit(rc_sq_wqe->byte_4, 403 V2_RC_SEND_WQE_BYTE_4_CQE_S, 404 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 405 406 roce_set_bit(rc_sq_wqe->byte_4, 407 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 408 409 switch (wr->opcode) { 410 case IB_WR_RDMA_READ: 411 roce_set_field(rc_sq_wqe->byte_4, 412 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 413 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 414 HNS_ROCE_V2_WQE_OP_RDMA_READ); 415 rc_sq_wqe->rkey = 416 cpu_to_le32(rdma_wr(wr)->rkey); 417 rc_sq_wqe->va = 418 cpu_to_le64(rdma_wr(wr)->remote_addr); 419 break; 420 case IB_WR_RDMA_WRITE: 421 roce_set_field(rc_sq_wqe->byte_4, 422 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 423 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 424 HNS_ROCE_V2_WQE_OP_RDMA_WRITE); 425 rc_sq_wqe->rkey = 426 cpu_to_le32(rdma_wr(wr)->rkey); 427 rc_sq_wqe->va = 428 cpu_to_le64(rdma_wr(wr)->remote_addr); 429 break; 430 case IB_WR_RDMA_WRITE_WITH_IMM: 431 roce_set_field(rc_sq_wqe->byte_4, 432 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 433 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 434 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM); 435 rc_sq_wqe->rkey = 436 cpu_to_le32(rdma_wr(wr)->rkey); 437 rc_sq_wqe->va = 438 cpu_to_le64(rdma_wr(wr)->remote_addr); 439 break; 440 case IB_WR_SEND: 441 roce_set_field(rc_sq_wqe->byte_4, 442 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 443 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 444 HNS_ROCE_V2_WQE_OP_SEND); 445 break; 446 case IB_WR_SEND_WITH_INV: 447 roce_set_field(rc_sq_wqe->byte_4, 448 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 449 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 450 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV); 451 break; 452 case IB_WR_SEND_WITH_IMM: 453 roce_set_field(rc_sq_wqe->byte_4, 454 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 455 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 456 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM); 457 break; 458 case IB_WR_LOCAL_INV: 459 roce_set_field(rc_sq_wqe->byte_4, 460 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 461 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 462 HNS_ROCE_V2_WQE_OP_LOCAL_INV); 463 break; 464 case IB_WR_ATOMIC_CMP_AND_SWP: 465 roce_set_field(rc_sq_wqe->byte_4, 466 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 467 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 468 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP); 469 break; 470 case IB_WR_ATOMIC_FETCH_AND_ADD: 471 roce_set_field(rc_sq_wqe->byte_4, 472 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 473 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 474 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD); 475 break; 476 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 477 roce_set_field(rc_sq_wqe->byte_4, 478 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 479 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 480 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP); 481 break; 482 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 483 roce_set_field(rc_sq_wqe->byte_4, 484 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 485 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 486 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD); 487 break; 488 default: 489 roce_set_field(rc_sq_wqe->byte_4, 490 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 491 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 492 HNS_ROCE_V2_WQE_OP_MASK); 493 break; 494 } 495 496 wqe += sizeof(struct hns_roce_v2_rc_send_wqe); 497 498 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe, 499 &sge_ind, bad_wr); 500 if (ret) 501 goto out; 502 ind++; 503 } else { 504 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type); 505 spin_unlock_irqrestore(&qp->sq.lock, flags); 506 *bad_wr = wr; 507 return -EOPNOTSUPP; 508 } 509 } 510 511 out: 512 if (likely(nreq)) { 513 qp->sq.head += nreq; 514 /* Memory barrier */ 515 wmb(); 516 517 sq_db.byte_4 = 0; 518 sq_db.parameter = 0; 519 520 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 521 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 522 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 523 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 524 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, 525 V2_DB_PARAMETER_IDX_S, 526 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)); 527 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 528 V2_DB_PARAMETER_SL_S, qp->sl); 529 530 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l); 531 532 qp->sq_next_wqe = ind; 533 qp->next_sge = sge_ind; 534 535 if (qp->state == IB_QPS_ERR) { 536 attr_mask = IB_QP_STATE; 537 attr.qp_state = IB_QPS_ERR; 538 539 ret = hns_roce_v2_modify_qp(&qp->ibqp, &attr, attr_mask, 540 qp->state, IB_QPS_ERR); 541 if (ret) { 542 spin_unlock_irqrestore(&qp->sq.lock, flags); 543 *bad_wr = wr; 544 return ret; 545 } 546 } 547 } 548 549 spin_unlock_irqrestore(&qp->sq.lock, flags); 550 551 return ret; 552 } 553 554 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 555 const struct ib_recv_wr *wr, 556 const struct ib_recv_wr **bad_wr) 557 { 558 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 559 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 560 struct hns_roce_v2_wqe_data_seg *dseg; 561 struct hns_roce_rinl_sge *sge_list; 562 struct device *dev = hr_dev->dev; 563 struct ib_qp_attr attr; 564 unsigned long flags; 565 void *wqe = NULL; 566 int attr_mask; 567 int ret = 0; 568 int nreq; 569 int ind; 570 int i; 571 572 spin_lock_irqsave(&hr_qp->rq.lock, flags); 573 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1); 574 575 if (hr_qp->state == IB_QPS_RESET) { 576 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 577 *bad_wr = wr; 578 return -EINVAL; 579 } 580 581 for (nreq = 0; wr; ++nreq, wr = wr->next) { 582 if (hns_roce_wq_overflow(&hr_qp->rq, nreq, 583 hr_qp->ibqp.recv_cq)) { 584 ret = -ENOMEM; 585 *bad_wr = wr; 586 goto out; 587 } 588 589 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) { 590 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n", 591 wr->num_sge, hr_qp->rq.max_gs); 592 ret = -EINVAL; 593 *bad_wr = wr; 594 goto out; 595 } 596 597 wqe = get_recv_wqe(hr_qp, ind); 598 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 599 for (i = 0; i < wr->num_sge; i++) { 600 if (!wr->sg_list[i].length) 601 continue; 602 set_data_seg_v2(dseg, wr->sg_list + i); 603 dseg++; 604 } 605 606 if (i < hr_qp->rq.max_gs) { 607 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 608 dseg->addr = 0; 609 } 610 611 /* rq support inline data */ 612 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 613 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list; 614 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt = 615 (u32)wr->num_sge; 616 for (i = 0; i < wr->num_sge; i++) { 617 sge_list[i].addr = 618 (void *)(u64)wr->sg_list[i].addr; 619 sge_list[i].len = wr->sg_list[i].length; 620 } 621 } 622 623 hr_qp->rq.wrid[ind] = wr->wr_id; 624 625 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1); 626 } 627 628 out: 629 if (likely(nreq)) { 630 hr_qp->rq.head += nreq; 631 /* Memory barrier */ 632 wmb(); 633 634 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; 635 636 if (hr_qp->state == IB_QPS_ERR) { 637 attr_mask = IB_QP_STATE; 638 attr.qp_state = IB_QPS_ERR; 639 640 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, 641 attr_mask, hr_qp->state, 642 IB_QPS_ERR); 643 if (ret) { 644 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 645 *bad_wr = wr; 646 return ret; 647 } 648 } 649 } 650 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 651 652 return ret; 653 } 654 655 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) 656 { 657 int ntu = ring->next_to_use; 658 int ntc = ring->next_to_clean; 659 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 660 661 return ring->desc_num - used - 1; 662 } 663 664 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 665 struct hns_roce_v2_cmq_ring *ring) 666 { 667 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 668 669 ring->desc = kzalloc(size, GFP_KERNEL); 670 if (!ring->desc) 671 return -ENOMEM; 672 673 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 674 DMA_BIDIRECTIONAL); 675 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 676 ring->desc_dma_addr = 0; 677 kfree(ring->desc); 678 ring->desc = NULL; 679 return -ENOMEM; 680 } 681 682 return 0; 683 } 684 685 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 686 struct hns_roce_v2_cmq_ring *ring) 687 { 688 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 689 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 690 DMA_BIDIRECTIONAL); 691 692 ring->desc_dma_addr = 0; 693 kfree(ring->desc); 694 } 695 696 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 697 { 698 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 699 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 700 &priv->cmq.csq : &priv->cmq.crq; 701 702 ring->flag = ring_type; 703 ring->next_to_clean = 0; 704 ring->next_to_use = 0; 705 706 return hns_roce_alloc_cmq_desc(hr_dev, ring); 707 } 708 709 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 710 { 711 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 712 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 713 &priv->cmq.csq : &priv->cmq.crq; 714 dma_addr_t dma = ring->desc_dma_addr; 715 716 if (ring_type == TYPE_CSQ) { 717 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 718 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 719 upper_32_bits(dma)); 720 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 721 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 722 HNS_ROCE_CMQ_ENABLE); 723 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 724 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 725 } else { 726 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 727 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 728 upper_32_bits(dma)); 729 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 730 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 731 HNS_ROCE_CMQ_ENABLE); 732 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 733 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 734 } 735 } 736 737 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 738 { 739 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 740 int ret; 741 742 /* Setup the queue entries for command queue */ 743 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM; 744 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM; 745 746 /* Setup the lock for command queue */ 747 spin_lock_init(&priv->cmq.csq.lock); 748 spin_lock_init(&priv->cmq.crq.lock); 749 750 /* Setup Tx write back timeout */ 751 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 752 753 /* Init CSQ */ 754 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 755 if (ret) { 756 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 757 return ret; 758 } 759 760 /* Init CRQ */ 761 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 762 if (ret) { 763 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 764 goto err_crq; 765 } 766 767 /* Init CSQ REG */ 768 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 769 770 /* Init CRQ REG */ 771 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 772 773 return 0; 774 775 err_crq: 776 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 777 778 return ret; 779 } 780 781 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 782 { 783 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 784 785 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 786 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 787 } 788 789 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 790 enum hns_roce_opcode_type opcode, 791 bool is_read) 792 { 793 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 794 desc->opcode = cpu_to_le16(opcode); 795 desc->flag = 796 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 797 if (is_read) 798 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 799 else 800 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 801 } 802 803 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 804 { 805 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 806 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 807 808 return head == priv->cmq.csq.next_to_use; 809 } 810 811 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) 812 { 813 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 814 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 815 struct hns_roce_cmq_desc *desc; 816 u16 ntc = csq->next_to_clean; 817 u32 head; 818 int clean = 0; 819 820 desc = &csq->desc[ntc]; 821 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 822 while (head != ntc) { 823 memset(desc, 0, sizeof(*desc)); 824 ntc++; 825 if (ntc == csq->desc_num) 826 ntc = 0; 827 desc = &csq->desc[ntc]; 828 clean++; 829 } 830 csq->next_to_clean = ntc; 831 832 return clean; 833 } 834 835 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 836 struct hns_roce_cmq_desc *desc, int num) 837 { 838 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 839 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 840 struct hns_roce_cmq_desc *desc_to_use; 841 bool complete = false; 842 u32 timeout = 0; 843 int handle = 0; 844 u16 desc_ret; 845 int ret = 0; 846 int ntc; 847 848 if (hr_dev->is_reset) 849 return 0; 850 851 spin_lock_bh(&csq->lock); 852 853 if (num > hns_roce_cmq_space(csq)) { 854 spin_unlock_bh(&csq->lock); 855 return -EBUSY; 856 } 857 858 /* 859 * Record the location of desc in the cmq for this time 860 * which will be use for hardware to write back 861 */ 862 ntc = csq->next_to_use; 863 864 while (handle < num) { 865 desc_to_use = &csq->desc[csq->next_to_use]; 866 *desc_to_use = desc[handle]; 867 dev_dbg(hr_dev->dev, "set cmq desc:\n"); 868 csq->next_to_use++; 869 if (csq->next_to_use == csq->desc_num) 870 csq->next_to_use = 0; 871 handle++; 872 } 873 874 /* Write to hardware */ 875 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); 876 877 /* 878 * If the command is sync, wait for the firmware to write back, 879 * if multi descriptors to be sent, use the first one to check 880 */ 881 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 882 do { 883 if (hns_roce_cmq_csq_done(hr_dev)) 884 break; 885 udelay(1); 886 timeout++; 887 } while (timeout < priv->cmq.tx_timeout); 888 } 889 890 if (hns_roce_cmq_csq_done(hr_dev)) { 891 complete = true; 892 handle = 0; 893 while (handle < num) { 894 /* get the result of hardware write back */ 895 desc_to_use = &csq->desc[ntc]; 896 desc[handle] = *desc_to_use; 897 dev_dbg(hr_dev->dev, "Get cmq desc:\n"); 898 desc_ret = desc[handle].retval; 899 if (desc_ret == CMD_EXEC_SUCCESS) 900 ret = 0; 901 else 902 ret = -EIO; 903 priv->cmq.last_status = desc_ret; 904 ntc++; 905 handle++; 906 if (ntc == csq->desc_num) 907 ntc = 0; 908 } 909 } 910 911 if (!complete) 912 ret = -EAGAIN; 913 914 /* clean the command send queue */ 915 handle = hns_roce_cmq_csq_clean(hr_dev); 916 if (handle != num) 917 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", 918 handle, num); 919 920 spin_unlock_bh(&csq->lock); 921 922 return ret; 923 } 924 925 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 926 { 927 struct hns_roce_query_version *resp; 928 struct hns_roce_cmq_desc desc; 929 int ret; 930 931 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 932 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 933 if (ret) 934 return ret; 935 936 resp = (struct hns_roce_query_version *)desc.data; 937 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version); 938 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id); 939 940 return 0; 941 } 942 943 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 944 { 945 struct hns_roce_cfg_global_param *req; 946 struct hns_roce_cmq_desc desc; 947 948 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 949 false); 950 951 req = (struct hns_roce_cfg_global_param *)desc.data; 952 memset(req, 0, sizeof(*req)); 953 roce_set_field(req->time_cfg_udp_port, 954 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 955 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 956 roce_set_field(req->time_cfg_udp_port, 957 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 958 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); 959 960 return hns_roce_cmq_send(hr_dev, &desc, 1); 961 } 962 963 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 964 { 965 struct hns_roce_cmq_desc desc[2]; 966 struct hns_roce_pf_res_a *req_a; 967 struct hns_roce_pf_res_b *req_b; 968 int ret; 969 int i; 970 971 for (i = 0; i < 2; i++) { 972 hns_roce_cmq_setup_basic_desc(&desc[i], 973 HNS_ROCE_OPC_QUERY_PF_RES, true); 974 975 if (i == 0) 976 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 977 else 978 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 979 } 980 981 ret = hns_roce_cmq_send(hr_dev, desc, 2); 982 if (ret) 983 return ret; 984 985 req_a = (struct hns_roce_pf_res_a *)desc[0].data; 986 req_b = (struct hns_roce_pf_res_b *)desc[1].data; 987 988 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num, 989 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 990 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 991 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num, 992 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 993 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 994 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num, 995 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 996 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 997 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num, 998 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 999 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 1000 1001 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num, 1002 PF_RES_DATA_3_PF_SL_NUM_M, 1003 PF_RES_DATA_3_PF_SL_NUM_S); 1004 1005 return 0; 1006 } 1007 1008 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1009 { 1010 struct hns_roce_cmq_desc desc[2]; 1011 struct hns_roce_vf_res_a *req_a; 1012 struct hns_roce_vf_res_b *req_b; 1013 int i; 1014 1015 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 1016 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 1017 memset(req_a, 0, sizeof(*req_a)); 1018 memset(req_b, 0, sizeof(*req_b)); 1019 for (i = 0; i < 2; i++) { 1020 hns_roce_cmq_setup_basic_desc(&desc[i], 1021 HNS_ROCE_OPC_ALLOC_VF_RES, false); 1022 1023 if (i == 0) 1024 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1025 else 1026 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1027 1028 if (i == 0) { 1029 roce_set_field(req_a->vf_qpc_bt_idx_num, 1030 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 1031 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 1032 roce_set_field(req_a->vf_qpc_bt_idx_num, 1033 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 1034 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, 1035 HNS_ROCE_VF_QPC_BT_NUM); 1036 1037 roce_set_field(req_a->vf_srqc_bt_idx_num, 1038 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 1039 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 1040 roce_set_field(req_a->vf_srqc_bt_idx_num, 1041 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 1042 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 1043 HNS_ROCE_VF_SRQC_BT_NUM); 1044 1045 roce_set_field(req_a->vf_cqc_bt_idx_num, 1046 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 1047 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 1048 roce_set_field(req_a->vf_cqc_bt_idx_num, 1049 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 1050 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, 1051 HNS_ROCE_VF_CQC_BT_NUM); 1052 1053 roce_set_field(req_a->vf_mpt_bt_idx_num, 1054 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 1055 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 1056 roce_set_field(req_a->vf_mpt_bt_idx_num, 1057 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 1058 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, 1059 HNS_ROCE_VF_MPT_BT_NUM); 1060 1061 roce_set_field(req_a->vf_eqc_bt_idx_num, 1062 VF_RES_A_DATA_5_VF_EQC_IDX_M, 1063 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 1064 roce_set_field(req_a->vf_eqc_bt_idx_num, 1065 VF_RES_A_DATA_5_VF_EQC_NUM_M, 1066 VF_RES_A_DATA_5_VF_EQC_NUM_S, 1067 HNS_ROCE_VF_EQC_NUM); 1068 } else { 1069 roce_set_field(req_b->vf_smac_idx_num, 1070 VF_RES_B_DATA_1_VF_SMAC_IDX_M, 1071 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 1072 roce_set_field(req_b->vf_smac_idx_num, 1073 VF_RES_B_DATA_1_VF_SMAC_NUM_M, 1074 VF_RES_B_DATA_1_VF_SMAC_NUM_S, 1075 HNS_ROCE_VF_SMAC_NUM); 1076 1077 roce_set_field(req_b->vf_sgid_idx_num, 1078 VF_RES_B_DATA_2_VF_SGID_IDX_M, 1079 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 1080 roce_set_field(req_b->vf_sgid_idx_num, 1081 VF_RES_B_DATA_2_VF_SGID_NUM_M, 1082 VF_RES_B_DATA_2_VF_SGID_NUM_S, 1083 HNS_ROCE_VF_SGID_NUM); 1084 1085 roce_set_field(req_b->vf_qid_idx_sl_num, 1086 VF_RES_B_DATA_3_VF_QID_IDX_M, 1087 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 1088 roce_set_field(req_b->vf_qid_idx_sl_num, 1089 VF_RES_B_DATA_3_VF_SL_NUM_M, 1090 VF_RES_B_DATA_3_VF_SL_NUM_S, 1091 HNS_ROCE_VF_SL_NUM); 1092 } 1093 } 1094 1095 return hns_roce_cmq_send(hr_dev, desc, 2); 1096 } 1097 1098 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1099 { 1100 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 1101 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 1102 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 1103 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 1104 struct hns_roce_cfg_bt_attr *req; 1105 struct hns_roce_cmq_desc desc; 1106 1107 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1108 req = (struct hns_roce_cfg_bt_attr *)desc.data; 1109 memset(req, 0, sizeof(*req)); 1110 1111 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1112 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1113 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1114 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1115 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1116 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1117 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1118 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1119 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1120 1121 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1122 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1123 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1124 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1125 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1126 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1127 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1128 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1129 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1130 1131 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1132 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1133 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1134 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1135 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1136 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1137 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1138 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1139 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1140 1141 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1142 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1143 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1144 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1145 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1146 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1147 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1148 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1149 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1150 1151 return hns_roce_cmq_send(hr_dev, &desc, 1); 1152 } 1153 1154 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 1155 { 1156 struct hns_roce_caps *caps = &hr_dev->caps; 1157 int ret; 1158 1159 ret = hns_roce_cmq_query_hw_info(hr_dev); 1160 if (ret) { 1161 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 1162 ret); 1163 return ret; 1164 } 1165 1166 ret = hns_roce_config_global_param(hr_dev); 1167 if (ret) { 1168 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 1169 ret); 1170 return ret; 1171 } 1172 1173 /* Get pf resource owned by every pf */ 1174 ret = hns_roce_query_pf_resource(hr_dev); 1175 if (ret) { 1176 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 1177 ret); 1178 return ret; 1179 } 1180 1181 ret = hns_roce_alloc_vf_resource(hr_dev); 1182 if (ret) { 1183 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 1184 ret); 1185 return ret; 1186 } 1187 1188 hr_dev->vendor_part_id = 0; 1189 hr_dev->sys_image_guid = 0; 1190 1191 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1192 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1193 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1194 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1195 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1196 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1197 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1198 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1199 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1200 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1201 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1202 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1203 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1204 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1205 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1206 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1207 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1208 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1209 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1210 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1211 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1212 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; 1213 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1214 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ; 1215 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1216 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1217 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1218 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; 1219 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1220 caps->reserved_lkey = 0; 1221 caps->reserved_pds = 0; 1222 caps->reserved_mrws = 1; 1223 caps->reserved_uars = 0; 1224 caps->reserved_cqs = 0; 1225 1226 caps->qpc_ba_pg_sz = 0; 1227 caps->qpc_buf_pg_sz = 0; 1228 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1229 caps->srqc_ba_pg_sz = 0; 1230 caps->srqc_buf_pg_sz = 0; 1231 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0; 1232 caps->cqc_ba_pg_sz = 0; 1233 caps->cqc_buf_pg_sz = 0; 1234 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1235 caps->mpt_ba_pg_sz = 0; 1236 caps->mpt_buf_pg_sz = 0; 1237 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1238 caps->pbl_ba_pg_sz = 0; 1239 caps->pbl_buf_pg_sz = 0; 1240 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 1241 caps->mtt_ba_pg_sz = 0; 1242 caps->mtt_buf_pg_sz = 0; 1243 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1244 caps->cqe_ba_pg_sz = 0; 1245 caps->cqe_buf_pg_sz = 0; 1246 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1247 caps->eqe_ba_pg_sz = 0; 1248 caps->eqe_buf_pg_sz = 0; 1249 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 1250 caps->tsq_buf_pg_sz = 0; 1251 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1252 1253 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1254 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1255 HNS_ROCE_CAP_FLAG_RQ_INLINE | 1256 HNS_ROCE_CAP_FLAG_RECORD_DB | 1257 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; 1258 caps->pkey_table_len[0] = 1; 1259 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1260 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1261 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1262 caps->local_ca_ack_delay = 0; 1263 caps->max_mtu = IB_MTU_4096; 1264 1265 ret = hns_roce_v2_set_bt(hr_dev); 1266 if (ret) 1267 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", 1268 ret); 1269 1270 return ret; 1271 } 1272 1273 static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev, 1274 enum hns_roce_link_table_type type) 1275 { 1276 struct hns_roce_cmq_desc desc[2]; 1277 struct hns_roce_cfg_llm_a *req_a = 1278 (struct hns_roce_cfg_llm_a *)desc[0].data; 1279 struct hns_roce_cfg_llm_b *req_b = 1280 (struct hns_roce_cfg_llm_b *)desc[1].data; 1281 struct hns_roce_v2_priv *priv = hr_dev->priv; 1282 struct hns_roce_link_table *link_tbl; 1283 struct hns_roce_link_table_entry *entry; 1284 enum hns_roce_opcode_type opcode; 1285 u32 page_num; 1286 int i; 1287 1288 switch (type) { 1289 case TSQ_LINK_TABLE: 1290 link_tbl = &priv->tsq; 1291 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 1292 break; 1293 case TPQ_LINK_TABLE: 1294 link_tbl = &priv->tpq; 1295 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM; 1296 break; 1297 default: 1298 return -EINVAL; 1299 } 1300 1301 page_num = link_tbl->npages; 1302 entry = link_tbl->table.buf; 1303 memset(req_a, 0, sizeof(*req_a)); 1304 memset(req_b, 0, sizeof(*req_b)); 1305 1306 for (i = 0; i < 2; i++) { 1307 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false); 1308 1309 if (i == 0) 1310 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1311 else 1312 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1313 1314 if (i == 0) { 1315 req_a->base_addr_l = link_tbl->table.map & 0xffffffff; 1316 req_a->base_addr_h = (link_tbl->table.map >> 32) & 1317 0xffffffff; 1318 roce_set_field(req_a->depth_pgsz_init_en, 1319 CFG_LLM_QUE_DEPTH_M, 1320 CFG_LLM_QUE_DEPTH_S, 1321 link_tbl->npages); 1322 roce_set_field(req_a->depth_pgsz_init_en, 1323 CFG_LLM_QUE_PGSZ_M, 1324 CFG_LLM_QUE_PGSZ_S, 1325 link_tbl->pg_sz); 1326 req_a->head_ba_l = entry[0].blk_ba0; 1327 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr; 1328 roce_set_field(req_a->head_ptr, 1329 CFG_LLM_HEAD_PTR_M, 1330 CFG_LLM_HEAD_PTR_S, 0); 1331 } else { 1332 req_b->tail_ba_l = entry[page_num - 1].blk_ba0; 1333 roce_set_field(req_b->tail_ba_h, 1334 CFG_LLM_TAIL_BA_H_M, 1335 CFG_LLM_TAIL_BA_H_S, 1336 entry[page_num - 1].blk_ba1_nxt_ptr & 1337 HNS_ROCE_LINK_TABLE_BA1_M); 1338 roce_set_field(req_b->tail_ptr, 1339 CFG_LLM_TAIL_PTR_M, 1340 CFG_LLM_TAIL_PTR_S, 1341 (entry[page_num - 2].blk_ba1_nxt_ptr & 1342 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >> 1343 HNS_ROCE_LINK_TABLE_NXT_PTR_S); 1344 } 1345 } 1346 roce_set_field(req_a->depth_pgsz_init_en, 1347 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1); 1348 1349 return hns_roce_cmq_send(hr_dev, desc, 2); 1350 } 1351 1352 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev, 1353 enum hns_roce_link_table_type type) 1354 { 1355 struct hns_roce_v2_priv *priv = hr_dev->priv; 1356 struct hns_roce_link_table *link_tbl; 1357 struct hns_roce_link_table_entry *entry; 1358 struct device *dev = hr_dev->dev; 1359 u32 buf_chk_sz; 1360 dma_addr_t t; 1361 int func_num = 1; 1362 int pg_num_a; 1363 int pg_num_b; 1364 int pg_num; 1365 int size; 1366 int i; 1367 1368 switch (type) { 1369 case TSQ_LINK_TABLE: 1370 link_tbl = &priv->tsq; 1371 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT); 1372 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz; 1373 pg_num_b = hr_dev->caps.sl_num * 4 + 2; 1374 break; 1375 case TPQ_LINK_TABLE: 1376 link_tbl = &priv->tpq; 1377 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT); 1378 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz; 1379 pg_num_b = 2 * 4 * func_num + 2; 1380 break; 1381 default: 1382 return -EINVAL; 1383 } 1384 1385 pg_num = max(pg_num_a, pg_num_b); 1386 size = pg_num * sizeof(struct hns_roce_link_table_entry); 1387 1388 link_tbl->table.buf = dma_alloc_coherent(dev, size, 1389 &link_tbl->table.map, 1390 GFP_KERNEL); 1391 if (!link_tbl->table.buf) 1392 goto out; 1393 1394 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list), 1395 GFP_KERNEL); 1396 if (!link_tbl->pg_list) 1397 goto err_kcalloc_failed; 1398 1399 entry = link_tbl->table.buf; 1400 for (i = 0; i < pg_num; ++i) { 1401 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz, 1402 &t, GFP_KERNEL); 1403 if (!link_tbl->pg_list[i].buf) 1404 goto err_alloc_buf_failed; 1405 1406 link_tbl->pg_list[i].map = t; 1407 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz); 1408 1409 entry[i].blk_ba0 = (t >> 12) & 0xffffffff; 1410 roce_set_field(entry[i].blk_ba1_nxt_ptr, 1411 HNS_ROCE_LINK_TABLE_BA1_M, 1412 HNS_ROCE_LINK_TABLE_BA1_S, 1413 t >> 44); 1414 1415 if (i < (pg_num - 1)) 1416 roce_set_field(entry[i].blk_ba1_nxt_ptr, 1417 HNS_ROCE_LINK_TABLE_NXT_PTR_M, 1418 HNS_ROCE_LINK_TABLE_NXT_PTR_S, 1419 i + 1); 1420 } 1421 link_tbl->npages = pg_num; 1422 link_tbl->pg_sz = buf_chk_sz; 1423 1424 return hns_roce_config_link_table(hr_dev, type); 1425 1426 err_alloc_buf_failed: 1427 for (i -= 1; i >= 0; i--) 1428 dma_free_coherent(dev, buf_chk_sz, 1429 link_tbl->pg_list[i].buf, 1430 link_tbl->pg_list[i].map); 1431 kfree(link_tbl->pg_list); 1432 1433 err_kcalloc_failed: 1434 dma_free_coherent(dev, size, link_tbl->table.buf, 1435 link_tbl->table.map); 1436 1437 out: 1438 return -ENOMEM; 1439 } 1440 1441 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev, 1442 struct hns_roce_link_table *link_tbl) 1443 { 1444 struct device *dev = hr_dev->dev; 1445 int size; 1446 int i; 1447 1448 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry); 1449 1450 for (i = 0; i < link_tbl->npages; ++i) 1451 if (link_tbl->pg_list[i].buf) 1452 dma_free_coherent(dev, link_tbl->pg_sz, 1453 link_tbl->pg_list[i].buf, 1454 link_tbl->pg_list[i].map); 1455 kfree(link_tbl->pg_list); 1456 1457 dma_free_coherent(dev, size, link_tbl->table.buf, 1458 link_tbl->table.map); 1459 } 1460 1461 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 1462 { 1463 struct hns_roce_v2_priv *priv = hr_dev->priv; 1464 int ret; 1465 1466 /* TSQ includes SQ doorbell and ack doorbell */ 1467 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE); 1468 if (ret) { 1469 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret); 1470 return ret; 1471 } 1472 1473 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE); 1474 if (ret) { 1475 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret); 1476 goto err_tpq_init_failed; 1477 } 1478 1479 return 0; 1480 1481 err_tpq_init_failed: 1482 hns_roce_free_link_table(hr_dev, &priv->tsq); 1483 1484 return ret; 1485 } 1486 1487 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 1488 { 1489 struct hns_roce_v2_priv *priv = hr_dev->priv; 1490 1491 hns_roce_free_link_table(hr_dev, &priv->tpq); 1492 hns_roce_free_link_table(hr_dev, &priv->tsq); 1493 } 1494 1495 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 1496 { 1497 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1498 1499 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 1500 } 1501 1502 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 1503 { 1504 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1505 1506 return status & HNS_ROCE_HW_MB_STATUS_MASK; 1507 } 1508 1509 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 1510 u64 out_param, u32 in_modifier, u8 op_modifier, 1511 u16 op, u16 token, int event) 1512 { 1513 struct device *dev = hr_dev->dev; 1514 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + 1515 ROCEE_VF_MB_CFG0_REG); 1516 unsigned long end; 1517 u32 val0 = 0; 1518 u32 val1 = 0; 1519 1520 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 1521 while (hns_roce_v2_cmd_pending(hr_dev)) { 1522 if (time_after(jiffies, end)) { 1523 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 1524 (int)end); 1525 return -EAGAIN; 1526 } 1527 cond_resched(); 1528 } 1529 1530 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK, 1531 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier); 1532 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK, 1533 HNS_ROCE_VF_MB4_CMD_SHIFT, op); 1534 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK, 1535 HNS_ROCE_VF_MB5_EVENT_SHIFT, event); 1536 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK, 1537 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token); 1538 1539 writeq(in_param, hcr + 0); 1540 writeq(out_param, hcr + 2); 1541 1542 /* Memory barrier */ 1543 wmb(); 1544 1545 writel(val0, hcr + 4); 1546 writel(val1, hcr + 5); 1547 1548 mmiowb(); 1549 1550 return 0; 1551 } 1552 1553 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 1554 unsigned long timeout) 1555 { 1556 struct device *dev = hr_dev->dev; 1557 unsigned long end = 0; 1558 u32 status; 1559 1560 end = msecs_to_jiffies(timeout) + jiffies; 1561 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 1562 cond_resched(); 1563 1564 if (hns_roce_v2_cmd_pending(hr_dev)) { 1565 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 1566 return -ETIMEDOUT; 1567 } 1568 1569 status = hns_roce_v2_cmd_complete(hr_dev); 1570 if (status != 0x1) { 1571 dev_err(dev, "mailbox status 0x%x!\n", status); 1572 return -EBUSY; 1573 } 1574 1575 return 0; 1576 } 1577 1578 static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev, 1579 int gid_index, const union ib_gid *gid, 1580 enum hns_roce_sgid_type sgid_type) 1581 { 1582 struct hns_roce_cmq_desc desc; 1583 struct hns_roce_cfg_sgid_tb *sgid_tb = 1584 (struct hns_roce_cfg_sgid_tb *)desc.data; 1585 u32 *p; 1586 1587 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 1588 1589 roce_set_field(sgid_tb->table_idx_rsv, 1590 CFG_SGID_TB_TABLE_IDX_M, 1591 CFG_SGID_TB_TABLE_IDX_S, gid_index); 1592 roce_set_field(sgid_tb->vf_sgid_type_rsv, 1593 CFG_SGID_TB_VF_SGID_TYPE_M, 1594 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 1595 1596 p = (u32 *)&gid->raw[0]; 1597 sgid_tb->vf_sgid_l = cpu_to_le32(*p); 1598 1599 p = (u32 *)&gid->raw[4]; 1600 sgid_tb->vf_sgid_ml = cpu_to_le32(*p); 1601 1602 p = (u32 *)&gid->raw[8]; 1603 sgid_tb->vf_sgid_mh = cpu_to_le32(*p); 1604 1605 p = (u32 *)&gid->raw[0xc]; 1606 sgid_tb->vf_sgid_h = cpu_to_le32(*p); 1607 1608 return hns_roce_cmq_send(hr_dev, &desc, 1); 1609 } 1610 1611 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 1612 int gid_index, const union ib_gid *gid, 1613 const struct ib_gid_attr *attr) 1614 { 1615 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 1616 int ret; 1617 1618 if (!gid || !attr) 1619 return -EINVAL; 1620 1621 if (attr->gid_type == IB_GID_TYPE_ROCE) 1622 sgid_type = GID_TYPE_FLAG_ROCE_V1; 1623 1624 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 1625 if (ipv6_addr_v4mapped((void *)gid)) 1626 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 1627 else 1628 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 1629 } 1630 1631 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type); 1632 if (ret) 1633 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret); 1634 1635 return ret; 1636 } 1637 1638 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 1639 u8 *addr) 1640 { 1641 struct hns_roce_cmq_desc desc; 1642 struct hns_roce_cfg_smac_tb *smac_tb = 1643 (struct hns_roce_cfg_smac_tb *)desc.data; 1644 u16 reg_smac_h; 1645 u32 reg_smac_l; 1646 1647 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 1648 1649 reg_smac_l = *(u32 *)(&addr[0]); 1650 reg_smac_h = *(u16 *)(&addr[4]); 1651 1652 memset(smac_tb, 0, sizeof(*smac_tb)); 1653 roce_set_field(smac_tb->tb_idx_rsv, 1654 CFG_SMAC_TB_IDX_M, 1655 CFG_SMAC_TB_IDX_S, phy_port); 1656 roce_set_field(smac_tb->vf_smac_h_rsv, 1657 CFG_SMAC_TB_VF_SMAC_H_M, 1658 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 1659 smac_tb->vf_smac_l = reg_smac_l; 1660 1661 return hns_roce_cmq_send(hr_dev, &desc, 1); 1662 } 1663 1664 static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, 1665 unsigned long mtpt_idx) 1666 { 1667 struct hns_roce_v2_mpt_entry *mpt_entry; 1668 struct scatterlist *sg; 1669 u64 page_addr; 1670 u64 *pages; 1671 int i, j; 1672 int len; 1673 int entry; 1674 1675 mpt_entry = mb_buf; 1676 memset(mpt_entry, 0, sizeof(*mpt_entry)); 1677 1678 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 1679 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 1680 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 1681 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == 1682 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); 1683 roce_set_field(mpt_entry->byte_4_pd_hop_st, 1684 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 1685 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 1686 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 1687 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1688 V2_MPT_BYTE_4_PD_S, mr->pd); 1689 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st); 1690 1691 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); 1692 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 1693 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0); 1694 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, 1695 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); 1696 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 0); 1697 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1698 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1699 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1700 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1701 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1702 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1703 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en); 1704 1705 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 1706 mr->type == MR_TYPE_MR ? 0 : 1); 1707 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S, 1708 1); 1709 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa); 1710 1711 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 1712 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 1713 mpt_entry->lkey = cpu_to_le32(mr->key); 1714 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 1715 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 1716 1717 if (mr->type == MR_TYPE_DMA) 1718 return 0; 1719 1720 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1721 1722 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1723 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 1724 V2_MPT_BYTE_48_PBL_BA_H_S, 1725 upper_32_bits(mr->pbl_ba >> 3)); 1726 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba); 1727 1728 pages = (u64 *)__get_free_page(GFP_KERNEL); 1729 if (!pages) 1730 return -ENOMEM; 1731 1732 i = 0; 1733 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) { 1734 len = sg_dma_len(sg) >> PAGE_SHIFT; 1735 for (j = 0; j < len; ++j) { 1736 page_addr = sg_dma_address(sg) + 1737 (j << mr->umem->page_shift); 1738 pages[i] = page_addr >> 6; 1739 1740 /* Record the first 2 entry directly to MTPT table */ 1741 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) 1742 goto found; 1743 i++; 1744 } 1745 } 1746 1747 found: 1748 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 1749 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 1750 V2_MPT_BYTE_56_PA0_H_S, 1751 upper_32_bits(pages[0])); 1752 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h); 1753 1754 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 1755 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 1756 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 1757 1758 free_page((unsigned long)pages); 1759 1760 roce_set_field(mpt_entry->byte_64_buf_pa1, 1761 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 1762 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 1763 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 1764 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1); 1765 1766 return 0; 1767 } 1768 1769 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 1770 struct hns_roce_mr *mr, int flags, 1771 u32 pdn, int mr_access_flags, u64 iova, 1772 u64 size, void *mb_buf) 1773 { 1774 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 1775 1776 if (flags & IB_MR_REREG_PD) { 1777 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1778 V2_MPT_BYTE_4_PD_S, pdn); 1779 mr->pd = pdn; 1780 } 1781 1782 if (flags & IB_MR_REREG_ACCESS) { 1783 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1784 V2_MPT_BYTE_8_BIND_EN_S, 1785 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 1786 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1787 V2_MPT_BYTE_8_ATOMIC_EN_S, 1788 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0)); 1789 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1790 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1791 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1792 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1793 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1794 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1795 } 1796 1797 if (flags & IB_MR_REREG_TRANS) { 1798 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); 1799 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); 1800 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); 1801 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); 1802 1803 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1804 mpt_entry->pbl_ba_l = 1805 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1806 roce_set_field(mpt_entry->byte_48_mode_ba, 1807 V2_MPT_BYTE_48_PBL_BA_H_M, 1808 V2_MPT_BYTE_48_PBL_BA_H_S, 1809 upper_32_bits(mr->pbl_ba >> 3)); 1810 mpt_entry->byte_48_mode_ba = 1811 cpu_to_le32(mpt_entry->byte_48_mode_ba); 1812 1813 mr->iova = iova; 1814 mr->size = size; 1815 } 1816 1817 return 0; 1818 } 1819 1820 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1821 { 1822 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf, 1823 n * HNS_ROCE_V2_CQE_ENTRY_SIZE); 1824 } 1825 1826 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1827 { 1828 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 1829 1830 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 1831 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 1832 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL; 1833 } 1834 1835 static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq) 1836 { 1837 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 1838 } 1839 1840 static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) 1841 { 1842 *hr_cq->set_ci_db = cons_index & 0xffffff; 1843 } 1844 1845 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1846 struct hns_roce_srq *srq) 1847 { 1848 struct hns_roce_v2_cqe *cqe, *dest; 1849 u32 prod_index; 1850 int nfreed = 0; 1851 u8 owner_bit; 1852 1853 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 1854 ++prod_index) { 1855 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe) 1856 break; 1857 } 1858 1859 /* 1860 * Now backwards through the CQ, removing CQ entries 1861 * that match our QP by overwriting them with next entries. 1862 */ 1863 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 1864 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 1865 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 1866 V2_CQE_BYTE_16_LCL_QPN_S) & 1867 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 1868 /* In v1 engine, not support SRQ */ 1869 ++nfreed; 1870 } else if (nfreed) { 1871 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 1872 hr_cq->ib_cq.cqe); 1873 owner_bit = roce_get_bit(dest->byte_4, 1874 V2_CQE_BYTE_4_OWNER_S); 1875 memcpy(dest, cqe, sizeof(*cqe)); 1876 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 1877 owner_bit); 1878 } 1879 } 1880 1881 if (nfreed) { 1882 hr_cq->cons_index += nfreed; 1883 /* 1884 * Make sure update of buffer contents is done before 1885 * updating consumer index. 1886 */ 1887 wmb(); 1888 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 1889 } 1890 } 1891 1892 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1893 struct hns_roce_srq *srq) 1894 { 1895 spin_lock_irq(&hr_cq->lock); 1896 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 1897 spin_unlock_irq(&hr_cq->lock); 1898 } 1899 1900 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 1901 struct hns_roce_cq *hr_cq, void *mb_buf, 1902 u64 *mtts, dma_addr_t dma_handle, int nent, 1903 u32 vector) 1904 { 1905 struct hns_roce_v2_cq_context *cq_context; 1906 1907 cq_context = mb_buf; 1908 memset(cq_context, 0, sizeof(*cq_context)); 1909 1910 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 1911 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 1912 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 1913 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 1914 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 1915 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent)); 1916 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 1917 V2_CQC_BYTE_4_CEQN_S, vector); 1918 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn); 1919 1920 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 1921 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 1922 1923 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 1924 cq_context->cqe_cur_blk_addr = 1925 cpu_to_le32(cq_context->cqe_cur_blk_addr); 1926 1927 roce_set_field(cq_context->byte_16_hop_addr, 1928 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 1929 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 1930 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT))); 1931 roce_set_field(cq_context->byte_16_hop_addr, 1932 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 1933 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 1934 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 1935 1936 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT); 1937 roce_set_field(cq_context->byte_24_pgsz_addr, 1938 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 1939 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 1940 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT))); 1941 roce_set_field(cq_context->byte_24_pgsz_addr, 1942 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 1943 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 1944 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET); 1945 roce_set_field(cq_context->byte_24_pgsz_addr, 1946 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 1947 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 1948 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET); 1949 1950 cq_context->cqe_ba = (u32)(dma_handle >> 3); 1951 1952 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 1953 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 1954 1955 if (hr_cq->db_en) 1956 roce_set_bit(cq_context->byte_44_db_record, 1957 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1); 1958 1959 roce_set_field(cq_context->byte_44_db_record, 1960 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 1961 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 1962 ((u32)hr_cq->db.dma) >> 1); 1963 cq_context->db_record_addr = hr_cq->db.dma >> 32; 1964 1965 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1966 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 1967 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 1968 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 1969 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1970 V2_CQC_BYTE_56_CQ_PERIOD_M, 1971 V2_CQC_BYTE_56_CQ_PERIOD_S, 1972 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 1973 } 1974 1975 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 1976 enum ib_cq_notify_flags flags) 1977 { 1978 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 1979 u32 notification_flag; 1980 u32 doorbell[2]; 1981 1982 doorbell[0] = 0; 1983 doorbell[1] = 0; 1984 1985 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 1986 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 1987 /* 1988 * flags = 0; Notification Flag = 1, next 1989 * flags = 1; Notification Flag = 0, solocited 1990 */ 1991 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 1992 hr_cq->cqn); 1993 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 1994 HNS_ROCE_V2_CQ_DB_NTR); 1995 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 1996 V2_CQ_DB_PARAMETER_CONS_IDX_S, 1997 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1)); 1998 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 1999 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 2000 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 2001 notification_flag); 2002 2003 hns_roce_write64_k(doorbell, hr_cq->cq_db_l); 2004 2005 return 0; 2006 } 2007 2008 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 2009 struct hns_roce_qp **cur_qp, 2010 struct ib_wc *wc) 2011 { 2012 struct hns_roce_rinl_sge *sge_list; 2013 u32 wr_num, wr_cnt, sge_num; 2014 u32 sge_cnt, data_len, size; 2015 void *wqe_buf; 2016 2017 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 2018 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 2019 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 2020 2021 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 2022 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 2023 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt); 2024 data_len = wc->byte_len; 2025 2026 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 2027 size = min(sge_list[sge_cnt].len, data_len); 2028 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 2029 2030 data_len -= size; 2031 wqe_buf += size; 2032 } 2033 2034 if (data_len) { 2035 wc->status = IB_WC_LOC_LEN_ERR; 2036 return -EAGAIN; 2037 } 2038 2039 return 0; 2040 } 2041 2042 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 2043 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 2044 { 2045 struct hns_roce_dev *hr_dev; 2046 struct hns_roce_v2_cqe *cqe; 2047 struct hns_roce_qp *hr_qp; 2048 struct hns_roce_wq *wq; 2049 struct ib_qp_attr attr; 2050 int attr_mask; 2051 int is_send; 2052 u16 wqe_ctr; 2053 u32 opcode; 2054 u32 status; 2055 int qpn; 2056 int ret; 2057 2058 /* Find cqe according to consumer index */ 2059 cqe = next_cqe_sw_v2(hr_cq); 2060 if (!cqe) 2061 return -EAGAIN; 2062 2063 ++hr_cq->cons_index; 2064 /* Memory barrier */ 2065 rmb(); 2066 2067 /* 0->SQ, 1->RQ */ 2068 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 2069 2070 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 2071 V2_CQE_BYTE_16_LCL_QPN_S); 2072 2073 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 2074 hr_dev = to_hr_dev(hr_cq->ib_cq.device); 2075 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 2076 if (unlikely(!hr_qp)) { 2077 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n", 2078 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK)); 2079 return -EINVAL; 2080 } 2081 *cur_qp = hr_qp; 2082 } 2083 2084 wc->qp = &(*cur_qp)->ibqp; 2085 wc->vendor_err = 0; 2086 2087 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 2088 V2_CQE_BYTE_4_STATUS_S); 2089 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) { 2090 case HNS_ROCE_CQE_V2_SUCCESS: 2091 wc->status = IB_WC_SUCCESS; 2092 break; 2093 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR: 2094 wc->status = IB_WC_LOC_LEN_ERR; 2095 break; 2096 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR: 2097 wc->status = IB_WC_LOC_QP_OP_ERR; 2098 break; 2099 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR: 2100 wc->status = IB_WC_LOC_PROT_ERR; 2101 break; 2102 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR: 2103 wc->status = IB_WC_WR_FLUSH_ERR; 2104 break; 2105 case HNS_ROCE_CQE_V2_MW_BIND_ERR: 2106 wc->status = IB_WC_MW_BIND_ERR; 2107 break; 2108 case HNS_ROCE_CQE_V2_BAD_RESP_ERR: 2109 wc->status = IB_WC_BAD_RESP_ERR; 2110 break; 2111 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR: 2112 wc->status = IB_WC_LOC_ACCESS_ERR; 2113 break; 2114 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR: 2115 wc->status = IB_WC_REM_INV_REQ_ERR; 2116 break; 2117 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR: 2118 wc->status = IB_WC_REM_ACCESS_ERR; 2119 break; 2120 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR: 2121 wc->status = IB_WC_REM_OP_ERR; 2122 break; 2123 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR: 2124 wc->status = IB_WC_RETRY_EXC_ERR; 2125 break; 2126 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR: 2127 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 2128 break; 2129 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR: 2130 wc->status = IB_WC_REM_ABORT_ERR; 2131 break; 2132 default: 2133 wc->status = IB_WC_GENERAL_ERR; 2134 break; 2135 } 2136 2137 /* flush cqe if wc status is error, excluding flush error */ 2138 if ((wc->status != IB_WC_SUCCESS) && 2139 (wc->status != IB_WC_WR_FLUSH_ERR)) { 2140 attr_mask = IB_QP_STATE; 2141 attr.qp_state = IB_QPS_ERR; 2142 return hns_roce_v2_modify_qp(&(*cur_qp)->ibqp, 2143 &attr, attr_mask, 2144 (*cur_qp)->state, IB_QPS_ERR); 2145 } 2146 2147 if (wc->status == IB_WC_WR_FLUSH_ERR) 2148 return 0; 2149 2150 if (is_send) { 2151 wc->wc_flags = 0; 2152 /* SQ corresponding to CQE */ 2153 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 2154 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 2155 case HNS_ROCE_SQ_OPCODE_SEND: 2156 wc->opcode = IB_WC_SEND; 2157 break; 2158 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV: 2159 wc->opcode = IB_WC_SEND; 2160 break; 2161 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM: 2162 wc->opcode = IB_WC_SEND; 2163 wc->wc_flags |= IB_WC_WITH_IMM; 2164 break; 2165 case HNS_ROCE_SQ_OPCODE_RDMA_READ: 2166 wc->opcode = IB_WC_RDMA_READ; 2167 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 2168 break; 2169 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE: 2170 wc->opcode = IB_WC_RDMA_WRITE; 2171 break; 2172 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM: 2173 wc->opcode = IB_WC_RDMA_WRITE; 2174 wc->wc_flags |= IB_WC_WITH_IMM; 2175 break; 2176 case HNS_ROCE_SQ_OPCODE_LOCAL_INV: 2177 wc->opcode = IB_WC_LOCAL_INV; 2178 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2179 break; 2180 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP: 2181 wc->opcode = IB_WC_COMP_SWAP; 2182 wc->byte_len = 8; 2183 break; 2184 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD: 2185 wc->opcode = IB_WC_FETCH_ADD; 2186 wc->byte_len = 8; 2187 break; 2188 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP: 2189 wc->opcode = IB_WC_MASKED_COMP_SWAP; 2190 wc->byte_len = 8; 2191 break; 2192 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD: 2193 wc->opcode = IB_WC_MASKED_FETCH_ADD; 2194 wc->byte_len = 8; 2195 break; 2196 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR: 2197 wc->opcode = IB_WC_REG_MR; 2198 break; 2199 case HNS_ROCE_SQ_OPCODE_BIND_MW: 2200 wc->opcode = IB_WC_REG_MR; 2201 break; 2202 default: 2203 wc->status = IB_WC_GENERAL_ERR; 2204 break; 2205 } 2206 2207 wq = &(*cur_qp)->sq; 2208 if ((*cur_qp)->sq_signal_bits) { 2209 /* 2210 * If sg_signal_bit is 1, 2211 * firstly tail pointer updated to wqe 2212 * which current cqe correspond to 2213 */ 2214 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 2215 V2_CQE_BYTE_4_WQE_INDX_M, 2216 V2_CQE_BYTE_4_WQE_INDX_S); 2217 wq->tail += (wqe_ctr - (u16)wq->tail) & 2218 (wq->wqe_cnt - 1); 2219 } 2220 2221 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 2222 ++wq->tail; 2223 } else { 2224 /* RQ correspond to CQE */ 2225 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 2226 2227 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 2228 V2_CQE_BYTE_4_OPCODE_S); 2229 switch (opcode & 0x1f) { 2230 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 2231 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 2232 wc->wc_flags = IB_WC_WITH_IMM; 2233 wc->ex.imm_data = 2234 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 2235 break; 2236 case HNS_ROCE_V2_OPCODE_SEND: 2237 wc->opcode = IB_WC_RECV; 2238 wc->wc_flags = 0; 2239 break; 2240 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 2241 wc->opcode = IB_WC_RECV; 2242 wc->wc_flags = IB_WC_WITH_IMM; 2243 wc->ex.imm_data = 2244 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 2245 break; 2246 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 2247 wc->opcode = IB_WC_RECV; 2248 wc->wc_flags = IB_WC_WITH_INVALIDATE; 2249 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 2250 break; 2251 default: 2252 wc->status = IB_WC_GENERAL_ERR; 2253 break; 2254 } 2255 2256 if ((wc->qp->qp_type == IB_QPT_RC || 2257 wc->qp->qp_type == IB_QPT_UC) && 2258 (opcode == HNS_ROCE_V2_OPCODE_SEND || 2259 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 2260 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 2261 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 2262 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 2263 if (ret) 2264 return -EAGAIN; 2265 } 2266 2267 /* Update tail pointer, record wr_id */ 2268 wq = &(*cur_qp)->rq; 2269 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 2270 ++wq->tail; 2271 2272 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 2273 V2_CQE_BYTE_32_SL_S); 2274 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 2275 V2_CQE_BYTE_32_RMT_QPN_M, 2276 V2_CQE_BYTE_32_RMT_QPN_S); 2277 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 2278 V2_CQE_BYTE_32_GRH_S) ? 2279 IB_WC_GRH : 0); 2280 wc->port_num = roce_get_field(cqe->byte_32, 2281 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 2282 wc->pkey_index = 0; 2283 memcpy(wc->smac, cqe->smac, 4); 2284 wc->smac[4] = roce_get_field(cqe->byte_28, 2285 V2_CQE_BYTE_28_SMAC_4_M, 2286 V2_CQE_BYTE_28_SMAC_4_S); 2287 wc->smac[5] = roce_get_field(cqe->byte_28, 2288 V2_CQE_BYTE_28_SMAC_5_M, 2289 V2_CQE_BYTE_28_SMAC_5_S); 2290 wc->vlan_id = 0xffff; 2291 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 2292 wc->network_hdr_type = roce_get_field(cqe->byte_28, 2293 V2_CQE_BYTE_28_PORT_TYPE_M, 2294 V2_CQE_BYTE_28_PORT_TYPE_S); 2295 } 2296 2297 return 0; 2298 } 2299 2300 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 2301 struct ib_wc *wc) 2302 { 2303 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 2304 struct hns_roce_qp *cur_qp = NULL; 2305 unsigned long flags; 2306 int npolled; 2307 2308 spin_lock_irqsave(&hr_cq->lock, flags); 2309 2310 for (npolled = 0; npolled < num_entries; ++npolled) { 2311 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 2312 break; 2313 } 2314 2315 if (npolled) { 2316 /* Memory barrier */ 2317 wmb(); 2318 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 2319 } 2320 2321 spin_unlock_irqrestore(&hr_cq->lock, flags); 2322 2323 return npolled; 2324 } 2325 2326 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 2327 struct hns_roce_hem_table *table, int obj, 2328 int step_idx) 2329 { 2330 struct device *dev = hr_dev->dev; 2331 struct hns_roce_cmd_mailbox *mailbox; 2332 struct hns_roce_hem_iter iter; 2333 struct hns_roce_hem_mhop mhop; 2334 struct hns_roce_hem *hem; 2335 unsigned long mhop_obj = obj; 2336 int i, j, k; 2337 int ret = 0; 2338 u64 hem_idx = 0; 2339 u64 l1_idx = 0; 2340 u64 bt_ba = 0; 2341 u32 chunk_ba_num; 2342 u32 hop_num; 2343 u16 op = 0xff; 2344 2345 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 2346 return 0; 2347 2348 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 2349 i = mhop.l0_idx; 2350 j = mhop.l1_idx; 2351 k = mhop.l2_idx; 2352 hop_num = mhop.hop_num; 2353 chunk_ba_num = mhop.bt_chunk_size / 8; 2354 2355 if (hop_num == 2) { 2356 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 2357 k; 2358 l1_idx = i * chunk_ba_num + j; 2359 } else if (hop_num == 1) { 2360 hem_idx = i * chunk_ba_num + j; 2361 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 2362 hem_idx = i; 2363 } 2364 2365 switch (table->type) { 2366 case HEM_TYPE_QPC: 2367 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 2368 break; 2369 case HEM_TYPE_MTPT: 2370 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 2371 break; 2372 case HEM_TYPE_CQC: 2373 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 2374 break; 2375 case HEM_TYPE_SRQC: 2376 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 2377 break; 2378 default: 2379 dev_warn(dev, "Table %d not to be written by mailbox!\n", 2380 table->type); 2381 return 0; 2382 } 2383 op += step_idx; 2384 2385 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2386 if (IS_ERR(mailbox)) 2387 return PTR_ERR(mailbox); 2388 2389 if (check_whether_last_step(hop_num, step_idx)) { 2390 hem = table->hem[hem_idx]; 2391 for (hns_roce_hem_first(hem, &iter); 2392 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 2393 bt_ba = hns_roce_hem_addr(&iter); 2394 2395 /* configure the ba, tag, and op */ 2396 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, 2397 obj, 0, op, 2398 HNS_ROCE_CMD_TIMEOUT_MSECS); 2399 } 2400 } else { 2401 if (step_idx == 0) 2402 bt_ba = table->bt_l0_dma_addr[i]; 2403 else if (step_idx == 1 && hop_num == 2) 2404 bt_ba = table->bt_l1_dma_addr[l1_idx]; 2405 2406 /* configure the ba, tag, and op */ 2407 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 2408 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 2409 } 2410 2411 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2412 return ret; 2413 } 2414 2415 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 2416 struct hns_roce_hem_table *table, int obj, 2417 int step_idx) 2418 { 2419 struct device *dev = hr_dev->dev; 2420 struct hns_roce_cmd_mailbox *mailbox; 2421 int ret = 0; 2422 u16 op = 0xff; 2423 2424 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 2425 return 0; 2426 2427 switch (table->type) { 2428 case HEM_TYPE_QPC: 2429 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 2430 break; 2431 case HEM_TYPE_MTPT: 2432 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 2433 break; 2434 case HEM_TYPE_CQC: 2435 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 2436 break; 2437 case HEM_TYPE_SRQC: 2438 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 2439 break; 2440 default: 2441 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", 2442 table->type); 2443 return 0; 2444 } 2445 op += step_idx; 2446 2447 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2448 if (IS_ERR(mailbox)) 2449 return PTR_ERR(mailbox); 2450 2451 /* configure the tag and op */ 2452 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 2453 HNS_ROCE_CMD_TIMEOUT_MSECS); 2454 2455 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2456 return ret; 2457 } 2458 2459 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 2460 struct hns_roce_mtt *mtt, 2461 enum ib_qp_state cur_state, 2462 enum ib_qp_state new_state, 2463 struct hns_roce_v2_qp_context *context, 2464 struct hns_roce_qp *hr_qp) 2465 { 2466 struct hns_roce_cmd_mailbox *mailbox; 2467 int ret; 2468 2469 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2470 if (IS_ERR(mailbox)) 2471 return PTR_ERR(mailbox); 2472 2473 memcpy(mailbox->buf, context, sizeof(*context) * 2); 2474 2475 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 2476 HNS_ROCE_CMD_MODIFY_QPC, 2477 HNS_ROCE_CMD_TIMEOUT_MSECS); 2478 2479 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2480 2481 return ret; 2482 } 2483 2484 static void set_access_flags(struct hns_roce_qp *hr_qp, 2485 struct hns_roce_v2_qp_context *context, 2486 struct hns_roce_v2_qp_context *qpc_mask, 2487 const struct ib_qp_attr *attr, int attr_mask) 2488 { 2489 u8 dest_rd_atomic; 2490 u32 access_flags; 2491 2492 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 2493 attr->max_dest_rd_atomic : hr_qp->resp_depth; 2494 2495 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 2496 attr->qp_access_flags : hr_qp->atomic_rd_en; 2497 2498 if (!dest_rd_atomic) 2499 access_flags &= IB_ACCESS_REMOTE_WRITE; 2500 2501 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2502 !!(access_flags & IB_ACCESS_REMOTE_READ)); 2503 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 2504 2505 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2506 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 2507 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 2508 2509 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2510 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2511 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 2512 } 2513 2514 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 2515 const struct ib_qp_attr *attr, 2516 int attr_mask, 2517 struct hns_roce_v2_qp_context *context, 2518 struct hns_roce_v2_qp_context *qpc_mask) 2519 { 2520 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2521 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2522 2523 /* 2524 * In v2 engine, software pass context and context mask to hardware 2525 * when modifying qp. If software need modify some fields in context, 2526 * we should set all bits of the relevant fields in context mask to 2527 * 0 at the same time, else set them to 0x1. 2528 */ 2529 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2530 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2531 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2532 V2_QPC_BYTE_4_TST_S, 0); 2533 2534 if (ibqp->qp_type == IB_QPT_GSI) 2535 roce_set_field(context->byte_4_sqpn_tst, 2536 V2_QPC_BYTE_4_SGE_SHIFT_M, 2537 V2_QPC_BYTE_4_SGE_SHIFT_S, 2538 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2539 else 2540 roce_set_field(context->byte_4_sqpn_tst, 2541 V2_QPC_BYTE_4_SGE_SHIFT_M, 2542 V2_QPC_BYTE_4_SGE_SHIFT_S, 2543 hr_qp->sq.max_gs > 2 ? 2544 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2545 2546 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2547 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2548 2549 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2550 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2551 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2552 V2_QPC_BYTE_4_SQPN_S, 0); 2553 2554 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2555 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2556 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2557 V2_QPC_BYTE_16_PD_S, 0); 2558 2559 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2560 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 2561 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2562 V2_QPC_BYTE_20_RQWS_S, 0); 2563 2564 roce_set_field(context->byte_20_smac_sgid_idx, 2565 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2566 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2567 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2568 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2569 2570 roce_set_field(context->byte_20_smac_sgid_idx, 2571 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2572 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2573 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2574 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2575 2576 /* No VLAN need to set 0xFFF */ 2577 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 2578 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); 2579 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 2580 V2_QPC_BYTE_24_VLAN_ID_S, 0); 2581 2582 /* 2583 * Set some fields in context to zero, Because the default values 2584 * of all fields in context are zero, we need not set them to 0 again. 2585 * but we should set the relevant fields of context mask to 0. 2586 */ 2587 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0); 2588 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0); 2589 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0); 2590 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0); 2591 2592 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M, 2593 V2_QPC_BYTE_60_MAPID_S, 0); 2594 2595 roce_set_bit(qpc_mask->byte_60_qpst_mapid, 2596 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0); 2597 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S, 2598 0); 2599 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S, 2600 0); 2601 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S, 2602 0); 2603 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S, 2604 0); 2605 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S, 2606 0); 2607 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0); 2608 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0); 2609 2610 if (attr_mask & IB_QP_QKEY) { 2611 context->qkey_xrcd = attr->qkey; 2612 qpc_mask->qkey_xrcd = 0; 2613 hr_qp->qkey = attr->qkey; 2614 } 2615 2616 if (hr_qp->rdb_en) { 2617 roce_set_bit(context->byte_68_rq_db, 2618 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); 2619 roce_set_bit(qpc_mask->byte_68_rq_db, 2620 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0); 2621 } 2622 2623 roce_set_field(context->byte_68_rq_db, 2624 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 2625 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 2626 ((u32)hr_qp->rdb.dma) >> 1); 2627 roce_set_field(qpc_mask->byte_68_rq_db, 2628 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 2629 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0); 2630 context->rq_db_record_addr = hr_qp->rdb.dma >> 32; 2631 qpc_mask->rq_db_record_addr = 0; 2632 2633 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 2634 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); 2635 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0); 2636 2637 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2638 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2639 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2640 V2_QPC_BYTE_80_RX_CQN_S, 0); 2641 if (ibqp->srq) { 2642 roce_set_field(context->byte_76_srqn_op_en, 2643 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2644 to_hr_srq(ibqp->srq)->srqn); 2645 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2646 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2647 roce_set_bit(context->byte_76_srqn_op_en, 2648 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2649 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2650 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2651 } 2652 2653 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2654 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2655 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 2656 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2657 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 2658 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 2659 2660 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M, 2661 V2_QPC_BYTE_92_SRQ_INFO_S, 0); 2662 2663 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 2664 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 2665 2666 roce_set_field(qpc_mask->byte_104_rq_sge, 2667 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M, 2668 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0); 2669 2670 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2671 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 2672 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2673 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 2674 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 2675 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2676 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0); 2677 2678 qpc_mask->rq_rnr_timer = 0; 2679 qpc_mask->rx_msg_len = 0; 2680 qpc_mask->rx_rkey_pkt_info = 0; 2681 qpc_mask->rx_va = 0; 2682 2683 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 2684 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 2685 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 2686 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 2687 2688 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0); 2689 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M, 2690 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0); 2691 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M, 2692 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0); 2693 2694 roce_set_field(qpc_mask->byte_144_raq, 2695 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M, 2696 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0); 2697 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S, 2698 0); 2699 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M, 2700 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0); 2701 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0); 2702 2703 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M, 2704 V2_QPC_BYTE_148_RQ_MSN_S, 0); 2705 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M, 2706 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0); 2707 2708 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2709 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 2710 roce_set_field(qpc_mask->byte_152_raq, 2711 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M, 2712 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0); 2713 2714 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M, 2715 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0); 2716 2717 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2718 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 2719 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 2720 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2721 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M, 2722 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0); 2723 2724 roce_set_field(context->byte_168_irrl_idx, 2725 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2726 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2727 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2728 roce_set_field(qpc_mask->byte_168_irrl_idx, 2729 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2730 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2731 2732 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2733 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0); 2734 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2735 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0); 2736 roce_set_field(qpc_mask->byte_168_irrl_idx, 2737 V2_QPC_BYTE_168_IRRL_IDX_LSB_M, 2738 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0); 2739 2740 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2741 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); 2742 roce_set_field(qpc_mask->byte_172_sq_psn, 2743 V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2744 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0); 2745 2746 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S, 2747 0); 2748 2749 roce_set_field(qpc_mask->byte_176_msg_pktn, 2750 V2_QPC_BYTE_176_MSG_USE_PKTN_M, 2751 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0); 2752 roce_set_field(qpc_mask->byte_176_msg_pktn, 2753 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M, 2754 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0); 2755 2756 roce_set_field(qpc_mask->byte_184_irrl_idx, 2757 V2_QPC_BYTE_184_IRRL_IDX_MSB_M, 2758 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0); 2759 2760 qpc_mask->cur_sge_offset = 0; 2761 2762 roce_set_field(qpc_mask->byte_192_ext_sge, 2763 V2_QPC_BYTE_192_CUR_SGE_IDX_M, 2764 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0); 2765 roce_set_field(qpc_mask->byte_192_ext_sge, 2766 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M, 2767 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0); 2768 2769 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 2770 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 2771 2772 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M, 2773 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0); 2774 roce_set_field(qpc_mask->byte_200_sq_max, 2775 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M, 2776 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0); 2777 2778 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0); 2779 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0); 2780 2781 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 2782 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 2783 2784 qpc_mask->sq_timer = 0; 2785 2786 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 2787 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 2788 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 2789 roce_set_field(qpc_mask->byte_232_irrl_sge, 2790 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 2791 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 2792 2793 qpc_mask->irrl_cur_sge_offset = 0; 2794 2795 roce_set_field(qpc_mask->byte_240_irrl_tail, 2796 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 2797 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 2798 roce_set_field(qpc_mask->byte_240_irrl_tail, 2799 V2_QPC_BYTE_240_IRRL_TAIL_RD_M, 2800 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0); 2801 roce_set_field(qpc_mask->byte_240_irrl_tail, 2802 V2_QPC_BYTE_240_RX_ACK_MSN_M, 2803 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 2804 2805 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M, 2806 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 2807 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S, 2808 0); 2809 roce_set_field(qpc_mask->byte_248_ack_psn, 2810 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 2811 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 2812 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 2813 0); 2814 roce_set_bit(qpc_mask->byte_248_ack_psn, 2815 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 2816 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S, 2817 0); 2818 2819 hr_qp->access_flags = attr->qp_access_flags; 2820 hr_qp->pkey_index = attr->pkey_index; 2821 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2822 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2823 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2824 V2_QPC_BYTE_252_TX_CQN_S, 0); 2825 2826 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M, 2827 V2_QPC_BYTE_252_ERR_TYPE_S, 0); 2828 2829 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2830 V2_QPC_BYTE_256_RQ_CQE_IDX_M, 2831 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0); 2832 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2833 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M, 2834 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0); 2835 } 2836 2837 static void modify_qp_init_to_init(struct ib_qp *ibqp, 2838 const struct ib_qp_attr *attr, int attr_mask, 2839 struct hns_roce_v2_qp_context *context, 2840 struct hns_roce_v2_qp_context *qpc_mask) 2841 { 2842 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2843 2844 /* 2845 * In v2 engine, software pass context and context mask to hardware 2846 * when modifying qp. If software need modify some fields in context, 2847 * we should set all bits of the relevant fields in context mask to 2848 * 0 at the same time, else set them to 0x1. 2849 */ 2850 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2851 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2852 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2853 V2_QPC_BYTE_4_TST_S, 0); 2854 2855 if (ibqp->qp_type == IB_QPT_GSI) 2856 roce_set_field(context->byte_4_sqpn_tst, 2857 V2_QPC_BYTE_4_SGE_SHIFT_M, 2858 V2_QPC_BYTE_4_SGE_SHIFT_S, 2859 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2860 else 2861 roce_set_field(context->byte_4_sqpn_tst, 2862 V2_QPC_BYTE_4_SGE_SHIFT_M, 2863 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ? 2864 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2865 2866 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2867 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2868 2869 if (attr_mask & IB_QP_ACCESS_FLAGS) { 2870 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2871 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); 2872 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2873 0); 2874 2875 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2876 !!(attr->qp_access_flags & 2877 IB_ACCESS_REMOTE_WRITE)); 2878 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2879 0); 2880 2881 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2882 !!(attr->qp_access_flags & 2883 IB_ACCESS_REMOTE_ATOMIC)); 2884 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2885 0); 2886 } else { 2887 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2888 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); 2889 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2890 0); 2891 2892 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2893 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); 2894 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2895 0); 2896 2897 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2898 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2899 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2900 0); 2901 } 2902 2903 roce_set_field(context->byte_20_smac_sgid_idx, 2904 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2905 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2906 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2907 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2908 2909 roce_set_field(context->byte_20_smac_sgid_idx, 2910 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2911 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2912 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2913 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2914 2915 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2916 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2917 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2918 V2_QPC_BYTE_16_PD_S, 0); 2919 2920 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2921 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2922 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2923 V2_QPC_BYTE_80_RX_CQN_S, 0); 2924 2925 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2926 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2927 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2928 V2_QPC_BYTE_252_TX_CQN_S, 0); 2929 2930 if (ibqp->srq) { 2931 roce_set_bit(context->byte_76_srqn_op_en, 2932 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2933 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2934 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2935 roce_set_field(context->byte_76_srqn_op_en, 2936 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2937 to_hr_srq(ibqp->srq)->srqn); 2938 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2939 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2940 } 2941 2942 if (attr_mask & IB_QP_QKEY) { 2943 context->qkey_xrcd = attr->qkey; 2944 qpc_mask->qkey_xrcd = 0; 2945 } 2946 2947 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2948 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2949 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2950 V2_QPC_BYTE_4_SQPN_S, 0); 2951 2952 if (attr_mask & IB_QP_DEST_QPN) { 2953 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2954 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 2955 roce_set_field(qpc_mask->byte_56_dqpn_err, 2956 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 2957 } 2958 roce_set_field(context->byte_168_irrl_idx, 2959 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2960 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2961 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2962 roce_set_field(qpc_mask->byte_168_irrl_idx, 2963 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2964 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2965 } 2966 2967 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 2968 const struct ib_qp_attr *attr, int attr_mask, 2969 struct hns_roce_v2_qp_context *context, 2970 struct hns_roce_v2_qp_context *qpc_mask) 2971 { 2972 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 2973 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2974 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2975 struct device *dev = hr_dev->dev; 2976 dma_addr_t dma_handle_3; 2977 dma_addr_t dma_handle_2; 2978 dma_addr_t dma_handle; 2979 u32 page_size; 2980 u8 port_num; 2981 u64 *mtts_3; 2982 u64 *mtts_2; 2983 u64 *mtts; 2984 u8 *dmac; 2985 u8 *smac; 2986 int port; 2987 2988 /* Search qp buf's mtts */ 2989 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 2990 hr_qp->mtt.first_seg, &dma_handle); 2991 if (!mtts) { 2992 dev_err(dev, "qp buf pa find failed\n"); 2993 return -EINVAL; 2994 } 2995 2996 /* Search IRRL's mtts */ 2997 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 2998 hr_qp->qpn, &dma_handle_2); 2999 if (!mtts_2) { 3000 dev_err(dev, "qp irrl_table find failed\n"); 3001 return -EINVAL; 3002 } 3003 3004 /* Search TRRL's mtts */ 3005 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 3006 hr_qp->qpn, &dma_handle_3); 3007 if (!mtts_3) { 3008 dev_err(dev, "qp trrl_table find failed\n"); 3009 return -EINVAL; 3010 } 3011 3012 if (attr_mask & IB_QP_ALT_PATH) { 3013 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask); 3014 return -EINVAL; 3015 } 3016 3017 dmac = (u8 *)attr->ah_attr.roce.dmac; 3018 context->wqe_sge_ba = (u32)(dma_handle >> 3); 3019 qpc_mask->wqe_sge_ba = 0; 3020 3021 /* 3022 * In v2 engine, software pass context and context mask to hardware 3023 * when modifying qp. If software need modify some fields in context, 3024 * we should set all bits of the relevant fields in context mask to 3025 * 0 at the same time, else set them to 0x1. 3026 */ 3027 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3028 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3)); 3029 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3030 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 3031 3032 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3033 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 3034 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 3035 0 : hr_dev->caps.mtt_hop_num); 3036 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3037 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 3038 3039 roce_set_field(context->byte_20_smac_sgid_idx, 3040 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3041 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 3042 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 3043 hr_dev->caps.mtt_hop_num : 0); 3044 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3045 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3046 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 3047 3048 roce_set_field(context->byte_20_smac_sgid_idx, 3049 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3050 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 3051 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 3052 0 : hr_dev->caps.mtt_hop_num); 3053 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3054 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3055 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 3056 3057 roce_set_field(context->byte_16_buf_ba_pg_sz, 3058 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3059 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 3060 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET); 3061 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3062 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3063 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 3064 3065 roce_set_field(context->byte_16_buf_ba_pg_sz, 3066 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3067 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 3068 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET); 3069 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3070 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3071 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 3072 3073 roce_set_field(context->byte_80_rnr_rx_cqn, 3074 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 3075 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer); 3076 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 3077 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 3078 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 3079 3080 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 3081 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size] 3082 >> PAGE_ADDR_SHIFT); 3083 qpc_mask->rq_cur_blk_addr = 0; 3084 3085 roce_set_field(context->byte_92_srq_info, 3086 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3087 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 3088 mtts[hr_qp->rq.offset / page_size] 3089 >> (32 + PAGE_ADDR_SHIFT)); 3090 roce_set_field(qpc_mask->byte_92_srq_info, 3091 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3092 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 3093 3094 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1] 3095 >> PAGE_ADDR_SHIFT); 3096 qpc_mask->rq_nxt_blk_addr = 0; 3097 3098 roce_set_field(context->byte_104_rq_sge, 3099 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3100 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 3101 mtts[hr_qp->rq.offset / page_size + 1] 3102 >> (32 + PAGE_ADDR_SHIFT)); 3103 roce_set_field(qpc_mask->byte_104_rq_sge, 3104 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3105 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 3106 3107 roce_set_field(context->byte_108_rx_reqepsn, 3108 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 3109 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 3110 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 3111 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 3112 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 3113 3114 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 3115 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4); 3116 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 3117 V2_QPC_BYTE_132_TRRL_BA_S, 0); 3118 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4)); 3119 qpc_mask->trrl_ba = 0; 3120 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 3121 V2_QPC_BYTE_140_TRRL_BA_S, 3122 (u32)(dma_handle_3 >> (32 + 16 + 4))); 3123 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 3124 V2_QPC_BYTE_140_TRRL_BA_S, 0); 3125 3126 context->irrl_ba = (u32)(dma_handle_2 >> 6); 3127 qpc_mask->irrl_ba = 0; 3128 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 3129 V2_QPC_BYTE_208_IRRL_BA_S, 3130 dma_handle_2 >> (32 + 6)); 3131 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 3132 V2_QPC_BYTE_208_IRRL_BA_S, 0); 3133 3134 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 3135 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 3136 3137 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 3138 hr_qp->sq_signal_bits); 3139 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 3140 0); 3141 3142 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 3143 3144 smac = (u8 *)hr_dev->dev_addr[port]; 3145 /* when dmac equals smac or loop_idc is 1, it should loopback */ 3146 if (ether_addr_equal_unaligned(dmac, smac) || 3147 hr_dev->loop_idc == 0x1) { 3148 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 3149 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 3150 } 3151 3152 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 3153 attr->max_dest_rd_atomic) { 3154 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 3155 V2_QPC_BYTE_140_RR_MAX_S, 3156 fls(attr->max_dest_rd_atomic - 1)); 3157 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 3158 V2_QPC_BYTE_140_RR_MAX_S, 0); 3159 } 3160 3161 if (attr_mask & IB_QP_DEST_QPN) { 3162 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 3163 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 3164 roce_set_field(qpc_mask->byte_56_dqpn_err, 3165 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 3166 } 3167 3168 /* Configure GID index */ 3169 port_num = rdma_ah_get_port_num(&attr->ah_attr); 3170 roce_set_field(context->byte_20_smac_sgid_idx, 3171 V2_QPC_BYTE_20_SGID_IDX_M, 3172 V2_QPC_BYTE_20_SGID_IDX_S, 3173 hns_get_gid_index(hr_dev, port_num - 1, 3174 grh->sgid_index)); 3175 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3176 V2_QPC_BYTE_20_SGID_IDX_M, 3177 V2_QPC_BYTE_20_SGID_IDX_S, 0); 3178 memcpy(&(context->dmac), dmac, 4); 3179 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 3180 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 3181 qpc_mask->dmac = 0; 3182 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 3183 V2_QPC_BYTE_52_DMAC_S, 0); 3184 3185 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 3186 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4); 3187 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 3188 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 3189 3190 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 3191 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 3192 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096); 3193 else if (attr_mask & IB_QP_PATH_MTU) 3194 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 3195 V2_QPC_BYTE_24_MTU_S, attr->path_mtu); 3196 3197 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 3198 V2_QPC_BYTE_24_MTU_S, 0); 3199 3200 roce_set_field(context->byte_84_rq_ci_pi, 3201 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3202 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 3203 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3204 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3205 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 3206 3207 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3208 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 3209 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 3210 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 3211 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 3212 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 3213 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 3214 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 3215 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 3216 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 3217 3218 context->rq_rnr_timer = 0; 3219 qpc_mask->rq_rnr_timer = 0; 3220 3221 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 3222 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 3223 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 3224 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 3225 3226 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 3227 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 3228 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 3229 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 3230 3231 roce_set_field(context->byte_168_irrl_idx, 3232 V2_QPC_BYTE_168_LP_SGEN_INI_M, 3233 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 3234 roce_set_field(qpc_mask->byte_168_irrl_idx, 3235 V2_QPC_BYTE_168_LP_SGEN_INI_M, 3236 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 3237 3238 return 0; 3239 } 3240 3241 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 3242 const struct ib_qp_attr *attr, int attr_mask, 3243 struct hns_roce_v2_qp_context *context, 3244 struct hns_roce_v2_qp_context *qpc_mask) 3245 { 3246 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3247 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3248 struct device *dev = hr_dev->dev; 3249 dma_addr_t dma_handle; 3250 u32 page_size; 3251 u64 *mtts; 3252 3253 /* Search qp buf's mtts */ 3254 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 3255 hr_qp->mtt.first_seg, &dma_handle); 3256 if (!mtts) { 3257 dev_err(dev, "qp buf pa find failed\n"); 3258 return -EINVAL; 3259 } 3260 3261 /* Not support alternate path and path migration */ 3262 if ((attr_mask & IB_QP_ALT_PATH) || 3263 (attr_mask & IB_QP_PATH_MIG_STATE)) { 3264 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 3265 return -EINVAL; 3266 } 3267 3268 /* 3269 * In v2 engine, software pass context and context mask to hardware 3270 * when modifying qp. If software need modify some fields in context, 3271 * we should set all bits of the relevant fields in context mask to 3272 * 0 at the same time, else set them to 0x1. 3273 */ 3274 roce_set_field(context->byte_60_qpst_mapid, 3275 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 3276 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt); 3277 roce_set_field(qpc_mask->byte_60_qpst_mapid, 3278 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 3279 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0); 3280 3281 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 3282 roce_set_field(context->byte_168_irrl_idx, 3283 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3284 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 3285 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 3286 qpc_mask->sq_cur_blk_addr = 0; 3287 roce_set_field(qpc_mask->byte_168_irrl_idx, 3288 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3289 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 3290 3291 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 3292 context->sq_cur_sge_blk_addr = 3293 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 3294 ((u32)(mtts[hr_qp->sge.offset / page_size] 3295 >> PAGE_ADDR_SHIFT)) : 0; 3296 roce_set_field(context->byte_184_irrl_idx, 3297 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3298 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 3299 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 3300 (mtts[hr_qp->sge.offset / page_size] >> 3301 (32 + PAGE_ADDR_SHIFT)) : 0); 3302 qpc_mask->sq_cur_sge_blk_addr = 0; 3303 roce_set_field(qpc_mask->byte_184_irrl_idx, 3304 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3305 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 3306 3307 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 3308 roce_set_field(context->byte_232_irrl_sge, 3309 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3310 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 3311 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 3312 qpc_mask->rx_sq_cur_blk_addr = 0; 3313 roce_set_field(qpc_mask->byte_232_irrl_sge, 3314 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3315 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 3316 3317 /* 3318 * Set some fields in context to zero, Because the default values 3319 * of all fields in context are zero, we need not set them to 0 again. 3320 * but we should set the relevant fields of context mask to 0. 3321 */ 3322 roce_set_field(qpc_mask->byte_232_irrl_sge, 3323 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 3324 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 3325 3326 roce_set_field(qpc_mask->byte_240_irrl_tail, 3327 V2_QPC_BYTE_240_RX_ACK_MSN_M, 3328 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 3329 3330 roce_set_field(context->byte_244_rnr_rxack, 3331 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 3332 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 3333 roce_set_field(qpc_mask->byte_244_rnr_rxack, 3334 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 3335 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 3336 3337 roce_set_field(qpc_mask->byte_248_ack_psn, 3338 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 3339 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 3340 roce_set_bit(qpc_mask->byte_248_ack_psn, 3341 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 3342 roce_set_field(qpc_mask->byte_248_ack_psn, 3343 V2_QPC_BYTE_248_IRRL_PSN_M, 3344 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 3345 3346 roce_set_field(qpc_mask->byte_240_irrl_tail, 3347 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 3348 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 3349 3350 roce_set_field(context->byte_220_retry_psn_msn, 3351 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 3352 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 3353 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 3354 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 3355 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 3356 3357 roce_set_field(context->byte_224_retry_msg, 3358 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 3359 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16); 3360 roce_set_field(qpc_mask->byte_224_retry_msg, 3361 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 3362 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 3363 3364 roce_set_field(context->byte_224_retry_msg, 3365 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3366 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn); 3367 roce_set_field(qpc_mask->byte_224_retry_msg, 3368 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3369 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 3370 3371 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 3372 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 3373 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 3374 3375 roce_set_bit(qpc_mask->byte_248_ack_psn, 3376 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 3377 3378 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 3379 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 3380 3381 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3382 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 3383 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3384 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 3385 3386 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3387 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt); 3388 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3389 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 3390 3391 roce_set_field(context->byte_244_rnr_rxack, 3392 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3393 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 3394 roce_set_field(qpc_mask->byte_244_rnr_rxack, 3395 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3396 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 3397 3398 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3399 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 3400 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3401 V2_QPC_BYTE_244_RNR_CNT_S, 0); 3402 3403 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3404 V2_QPC_BYTE_212_LSN_S, 0x100); 3405 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3406 V2_QPC_BYTE_212_LSN_S, 0); 3407 3408 if (attr_mask & IB_QP_TIMEOUT) { 3409 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3410 V2_QPC_BYTE_28_AT_S, attr->timeout); 3411 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3412 V2_QPC_BYTE_28_AT_S, 0); 3413 } 3414 3415 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3416 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 3417 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3418 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 3419 3420 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 3421 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 3422 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3423 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 3424 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3425 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 3426 3427 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 3428 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 3429 V2_QPC_BYTE_208_SR_MAX_S, 3430 fls(attr->max_rd_atomic - 1)); 3431 roce_set_field(qpc_mask->byte_208_irrl, 3432 V2_QPC_BYTE_208_SR_MAX_M, 3433 V2_QPC_BYTE_208_SR_MAX_S, 0); 3434 } 3435 return 0; 3436 } 3437 3438 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 3439 const struct ib_qp_attr *attr, 3440 int attr_mask, enum ib_qp_state cur_state, 3441 enum ib_qp_state new_state) 3442 { 3443 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3444 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3445 struct hns_roce_v2_qp_context *context; 3446 struct hns_roce_v2_qp_context *qpc_mask; 3447 struct device *dev = hr_dev->dev; 3448 int ret = -EINVAL; 3449 3450 context = kcalloc(2, sizeof(*context), GFP_KERNEL); 3451 if (!context) 3452 return -ENOMEM; 3453 3454 qpc_mask = context + 1; 3455 /* 3456 * In v2 engine, software pass context and context mask to hardware 3457 * when modifying qp. If software need modify some fields in context, 3458 * we should set all bits of the relevant fields in context mask to 3459 * 0 at the same time, else set them to 0x1. 3460 */ 3461 memset(qpc_mask, 0xff, sizeof(*qpc_mask)); 3462 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3463 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 3464 qpc_mask); 3465 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3466 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 3467 qpc_mask); 3468 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3469 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 3470 qpc_mask); 3471 if (ret) 3472 goto out; 3473 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3474 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 3475 qpc_mask); 3476 if (ret) 3477 goto out; 3478 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) || 3479 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) || 3480 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) || 3481 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) || 3482 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) || 3483 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) || 3484 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) || 3485 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) || 3486 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) || 3487 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) || 3488 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) || 3489 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) || 3490 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) || 3491 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) || 3492 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) { 3493 /* Nothing */ 3494 ; 3495 } else { 3496 dev_err(dev, "Illegal state for QP!\n"); 3497 ret = -EINVAL; 3498 goto out; 3499 } 3500 3501 /* When QP state is err, SQ and RQ WQE should be flushed */ 3502 if (new_state == IB_QPS_ERR) { 3503 roce_set_field(context->byte_160_sq_ci_pi, 3504 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 3505 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 3506 hr_qp->sq.head); 3507 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 3508 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 3509 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 3510 roce_set_field(context->byte_84_rq_ci_pi, 3511 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3512 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 3513 hr_qp->rq.head); 3514 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3515 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3516 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 3517 } 3518 3519 if (attr_mask & IB_QP_AV) { 3520 const struct ib_global_route *grh = 3521 rdma_ah_read_grh(&attr->ah_attr); 3522 const struct ib_gid_attr *gid_attr = NULL; 3523 u8 src_mac[ETH_ALEN]; 3524 int is_roce_protocol; 3525 u16 vlan = 0xffff; 3526 u8 ib_port; 3527 u8 hr_port; 3528 3529 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : 3530 hr_qp->port + 1; 3531 hr_port = ib_port - 1; 3532 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 3533 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 3534 3535 if (is_roce_protocol) { 3536 gid_attr = attr->ah_attr.grh.sgid_attr; 3537 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev); 3538 memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN); 3539 } 3540 3541 roce_set_field(context->byte_24_mtu_tc, 3542 V2_QPC_BYTE_24_VLAN_ID_M, 3543 V2_QPC_BYTE_24_VLAN_ID_S, vlan); 3544 roce_set_field(qpc_mask->byte_24_mtu_tc, 3545 V2_QPC_BYTE_24_VLAN_ID_M, 3546 V2_QPC_BYTE_24_VLAN_ID_S, 0); 3547 3548 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 3549 dev_err(hr_dev->dev, 3550 "sgid_index(%u) too large. max is %d\n", 3551 grh->sgid_index, 3552 hr_dev->caps.gid_table_len[hr_port]); 3553 ret = -EINVAL; 3554 goto out; 3555 } 3556 3557 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 3558 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n"); 3559 ret = -EINVAL; 3560 goto out; 3561 } 3562 3563 roce_set_field(context->byte_52_udpspn_dmac, 3564 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S, 3565 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3566 0 : 0x12b7); 3567 3568 roce_set_field(qpc_mask->byte_52_udpspn_dmac, 3569 V2_QPC_BYTE_52_UDPSPN_M, 3570 V2_QPC_BYTE_52_UDPSPN_S, 0); 3571 3572 roce_set_field(context->byte_20_smac_sgid_idx, 3573 V2_QPC_BYTE_20_SGID_IDX_M, 3574 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index); 3575 3576 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3577 V2_QPC_BYTE_20_SGID_IDX_M, 3578 V2_QPC_BYTE_20_SGID_IDX_S, 0); 3579 3580 roce_set_field(context->byte_24_mtu_tc, 3581 V2_QPC_BYTE_24_HOP_LIMIT_M, 3582 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 3583 roce_set_field(qpc_mask->byte_24_mtu_tc, 3584 V2_QPC_BYTE_24_HOP_LIMIT_M, 3585 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 3586 3587 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 3588 V2_QPC_BYTE_24_TC_S, grh->traffic_class); 3589 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 3590 V2_QPC_BYTE_24_TC_S, 0); 3591 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 3592 V2_QPC_BYTE_28_FL_S, grh->flow_label); 3593 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 3594 V2_QPC_BYTE_28_FL_S, 0); 3595 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 3596 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 3597 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3598 V2_QPC_BYTE_28_SL_S, 3599 rdma_ah_get_sl(&attr->ah_attr)); 3600 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3601 V2_QPC_BYTE_28_SL_S, 0); 3602 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 3603 } 3604 3605 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3606 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 3607 3608 /* Every status migrate must change state */ 3609 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3610 V2_QPC_BYTE_60_QP_ST_S, new_state); 3611 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3612 V2_QPC_BYTE_60_QP_ST_S, 0); 3613 3614 /* SW pass context to HW */ 3615 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state, 3616 context, hr_qp); 3617 if (ret) { 3618 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret); 3619 goto out; 3620 } 3621 3622 hr_qp->state = new_state; 3623 3624 if (attr_mask & IB_QP_ACCESS_FLAGS) 3625 hr_qp->atomic_rd_en = attr->qp_access_flags; 3626 3627 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3628 hr_qp->resp_depth = attr->max_dest_rd_atomic; 3629 if (attr_mask & IB_QP_PORT) { 3630 hr_qp->port = attr->port_num - 1; 3631 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 3632 } 3633 3634 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 3635 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 3636 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 3637 if (ibqp->send_cq != ibqp->recv_cq) 3638 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 3639 hr_qp->qpn, NULL); 3640 3641 hr_qp->rq.head = 0; 3642 hr_qp->rq.tail = 0; 3643 hr_qp->sq.head = 0; 3644 hr_qp->sq.tail = 0; 3645 hr_qp->sq_next_wqe = 0; 3646 hr_qp->next_sge = 0; 3647 if (hr_qp->rq.wqe_cnt) 3648 *hr_qp->rdb.db_record = 0; 3649 } 3650 3651 out: 3652 kfree(context); 3653 return ret; 3654 } 3655 3656 static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state) 3657 { 3658 switch (state) { 3659 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET; 3660 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT; 3661 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR; 3662 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS; 3663 case HNS_ROCE_QP_ST_SQ_DRAINING: 3664 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD; 3665 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE; 3666 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR; 3667 default: return -1; 3668 } 3669 } 3670 3671 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 3672 struct hns_roce_qp *hr_qp, 3673 struct hns_roce_v2_qp_context *hr_context) 3674 { 3675 struct hns_roce_cmd_mailbox *mailbox; 3676 int ret; 3677 3678 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3679 if (IS_ERR(mailbox)) 3680 return PTR_ERR(mailbox); 3681 3682 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 3683 HNS_ROCE_CMD_QUERY_QPC, 3684 HNS_ROCE_CMD_TIMEOUT_MSECS); 3685 if (ret) { 3686 dev_err(hr_dev->dev, "QUERY QP cmd process error\n"); 3687 goto out; 3688 } 3689 3690 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 3691 3692 out: 3693 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3694 return ret; 3695 } 3696 3697 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 3698 int qp_attr_mask, 3699 struct ib_qp_init_attr *qp_init_attr) 3700 { 3701 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3702 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3703 struct hns_roce_v2_qp_context *context; 3704 struct device *dev = hr_dev->dev; 3705 int tmp_qp_state; 3706 int state; 3707 int ret; 3708 3709 context = kzalloc(sizeof(*context), GFP_KERNEL); 3710 if (!context) 3711 return -ENOMEM; 3712 3713 memset(qp_attr, 0, sizeof(*qp_attr)); 3714 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 3715 3716 mutex_lock(&hr_qp->mutex); 3717 3718 if (hr_qp->state == IB_QPS_RESET) { 3719 qp_attr->qp_state = IB_QPS_RESET; 3720 ret = 0; 3721 goto done; 3722 } 3723 3724 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context); 3725 if (ret) { 3726 dev_err(dev, "query qpc error\n"); 3727 ret = -EINVAL; 3728 goto out; 3729 } 3730 3731 state = roce_get_field(context->byte_60_qpst_mapid, 3732 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 3733 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 3734 if (tmp_qp_state == -1) { 3735 dev_err(dev, "Illegal ib_qp_state\n"); 3736 ret = -EINVAL; 3737 goto out; 3738 } 3739 hr_qp->state = (u8)tmp_qp_state; 3740 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 3741 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc, 3742 V2_QPC_BYTE_24_MTU_M, 3743 V2_QPC_BYTE_24_MTU_S); 3744 qp_attr->path_mig_state = IB_MIG_ARMED; 3745 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 3746 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 3747 qp_attr->qkey = V2_QKEY_VAL; 3748 3749 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn, 3750 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 3751 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 3752 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn, 3753 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3754 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 3755 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err, 3756 V2_QPC_BYTE_56_DQPN_M, 3757 V2_QPC_BYTE_56_DQPN_S); 3758 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en, 3759 V2_QPC_BYTE_76_RRE_S)) << 2) | 3760 ((roce_get_bit(context->byte_76_srqn_op_en, 3761 V2_QPC_BYTE_76_RWE_S)) << 1) | 3762 ((roce_get_bit(context->byte_76_srqn_op_en, 3763 V2_QPC_BYTE_76_ATE_S)) << 3); 3764 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 3765 hr_qp->ibqp.qp_type == IB_QPT_UC) { 3766 struct ib_global_route *grh = 3767 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 3768 3769 rdma_ah_set_sl(&qp_attr->ah_attr, 3770 roce_get_field(context->byte_28_at_fl, 3771 V2_QPC_BYTE_28_SL_M, 3772 V2_QPC_BYTE_28_SL_S)); 3773 grh->flow_label = roce_get_field(context->byte_28_at_fl, 3774 V2_QPC_BYTE_28_FL_M, 3775 V2_QPC_BYTE_28_FL_S); 3776 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx, 3777 V2_QPC_BYTE_20_SGID_IDX_M, 3778 V2_QPC_BYTE_20_SGID_IDX_S); 3779 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc, 3780 V2_QPC_BYTE_24_HOP_LIMIT_M, 3781 V2_QPC_BYTE_24_HOP_LIMIT_S); 3782 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc, 3783 V2_QPC_BYTE_24_TC_M, 3784 V2_QPC_BYTE_24_TC_S); 3785 3786 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw)); 3787 } 3788 3789 qp_attr->port_num = hr_qp->port + 1; 3790 qp_attr->sq_draining = 0; 3791 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl, 3792 V2_QPC_BYTE_208_SR_MAX_M, 3793 V2_QPC_BYTE_208_SR_MAX_S); 3794 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq, 3795 V2_QPC_BYTE_140_RR_MAX_M, 3796 V2_QPC_BYTE_140_RR_MAX_S); 3797 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn, 3798 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 3799 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 3800 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl, 3801 V2_QPC_BYTE_28_AT_M, 3802 V2_QPC_BYTE_28_AT_S); 3803 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn, 3804 V2_QPC_BYTE_212_RETRY_CNT_M, 3805 V2_QPC_BYTE_212_RETRY_CNT_S); 3806 qp_attr->rnr_retry = context->rq_rnr_timer; 3807 3808 done: 3809 qp_attr->cur_qp_state = qp_attr->qp_state; 3810 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 3811 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; 3812 3813 if (!ibqp->uobject) { 3814 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 3815 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 3816 } else { 3817 qp_attr->cap.max_send_wr = 0; 3818 qp_attr->cap.max_send_sge = 0; 3819 } 3820 3821 qp_init_attr->cap = qp_attr->cap; 3822 3823 out: 3824 mutex_unlock(&hr_qp->mutex); 3825 kfree(context); 3826 return ret; 3827 } 3828 3829 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 3830 struct hns_roce_qp *hr_qp, 3831 int is_user) 3832 { 3833 struct hns_roce_cq *send_cq, *recv_cq; 3834 struct device *dev = hr_dev->dev; 3835 int ret; 3836 3837 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { 3838 /* Modify qp to reset before destroying qp */ 3839 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 3840 hr_qp->state, IB_QPS_RESET); 3841 if (ret) { 3842 dev_err(dev, "modify QP %06lx to ERR failed.\n", 3843 hr_qp->qpn); 3844 return ret; 3845 } 3846 } 3847 3848 send_cq = to_hr_cq(hr_qp->ibqp.send_cq); 3849 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq); 3850 3851 hns_roce_lock_cqs(send_cq, recv_cq); 3852 3853 if (!is_user) { 3854 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ? 3855 to_hr_srq(hr_qp->ibqp.srq) : NULL); 3856 if (send_cq != recv_cq) 3857 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 3858 } 3859 3860 hns_roce_qp_remove(hr_dev, hr_qp); 3861 3862 hns_roce_unlock_cqs(send_cq, recv_cq); 3863 3864 hns_roce_qp_free(hr_dev, hr_qp); 3865 3866 /* Not special_QP, free their QPN */ 3867 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) || 3868 (hr_qp->ibqp.qp_type == IB_QPT_UC) || 3869 (hr_qp->ibqp.qp_type == IB_QPT_UD)) 3870 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1); 3871 3872 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt); 3873 3874 if (is_user) { 3875 if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1)) 3876 hns_roce_db_unmap_user( 3877 to_hr_ucontext(hr_qp->ibqp.uobject->context), 3878 &hr_qp->sdb); 3879 3880 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1)) 3881 hns_roce_db_unmap_user( 3882 to_hr_ucontext(hr_qp->ibqp.uobject->context), 3883 &hr_qp->rdb); 3884 ib_umem_release(hr_qp->umem); 3885 } else { 3886 kfree(hr_qp->sq.wrid); 3887 kfree(hr_qp->rq.wrid); 3888 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); 3889 if (hr_qp->rq.wqe_cnt) 3890 hns_roce_free_db(hr_dev, &hr_qp->rdb); 3891 } 3892 3893 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 3894 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); 3895 kfree(hr_qp->rq_inl_buf.wqe_list); 3896 } 3897 3898 return 0; 3899 } 3900 3901 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp) 3902 { 3903 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3904 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3905 int ret; 3906 3907 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject); 3908 if (ret) { 3909 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret); 3910 return ret; 3911 } 3912 3913 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 3914 kfree(hr_to_hr_sqp(hr_qp)); 3915 else 3916 kfree(hr_qp); 3917 3918 return 0; 3919 } 3920 3921 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 3922 { 3923 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 3924 struct hns_roce_v2_cq_context *cq_context; 3925 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 3926 struct hns_roce_v2_cq_context *cqc_mask; 3927 struct hns_roce_cmd_mailbox *mailbox; 3928 int ret; 3929 3930 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3931 if (IS_ERR(mailbox)) 3932 return PTR_ERR(mailbox); 3933 3934 cq_context = mailbox->buf; 3935 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 3936 3937 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 3938 3939 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3940 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3941 cq_count); 3942 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3943 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3944 0); 3945 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3946 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3947 cq_period); 3948 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3949 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3950 0); 3951 3952 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 3953 HNS_ROCE_CMD_MODIFY_CQC, 3954 HNS_ROCE_CMD_TIMEOUT_MSECS); 3955 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3956 if (ret) 3957 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n"); 3958 3959 return ret; 3960 } 3961 3962 static void hns_roce_set_qps_to_err(struct hns_roce_dev *hr_dev, u32 qpn) 3963 { 3964 struct hns_roce_qp *hr_qp; 3965 struct ib_qp_attr attr; 3966 int attr_mask; 3967 int ret; 3968 3969 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3970 if (!hr_qp) { 3971 dev_warn(hr_dev->dev, "no hr_qp can be found!\n"); 3972 return; 3973 } 3974 3975 if (hr_qp->ibqp.uobject) { 3976 if (hr_qp->sdb_en == 1) { 3977 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr); 3978 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr); 3979 } else { 3980 dev_warn(hr_dev->dev, "flush cqe is unsupported in userspace!\n"); 3981 return; 3982 } 3983 } 3984 3985 attr_mask = IB_QP_STATE; 3986 attr.qp_state = IB_QPS_ERR; 3987 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, attr_mask, 3988 hr_qp->state, IB_QPS_ERR); 3989 if (ret) 3990 dev_err(hr_dev->dev, "failed to modify qp %d to err state.\n", 3991 qpn); 3992 } 3993 3994 static void hns_roce_irq_work_handle(struct work_struct *work) 3995 { 3996 struct hns_roce_work *irq_work = 3997 container_of(work, struct hns_roce_work, work); 3998 u32 qpn = irq_work->qpn; 3999 4000 switch (irq_work->event_type) { 4001 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 4002 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 4003 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 4004 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn); 4005 break; 4006 default: 4007 break; 4008 } 4009 4010 kfree(irq_work); 4011 } 4012 4013 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 4014 struct hns_roce_eq *eq, u32 qpn) 4015 { 4016 struct hns_roce_work *irq_work; 4017 4018 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 4019 if (!irq_work) 4020 return; 4021 4022 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 4023 irq_work->hr_dev = hr_dev; 4024 irq_work->qpn = qpn; 4025 irq_work->event_type = eq->event_type; 4026 irq_work->sub_type = eq->sub_type; 4027 queue_work(hr_dev->irq_workq, &(irq_work->work)); 4028 } 4029 4030 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 4031 { 4032 u32 doorbell[2]; 4033 4034 doorbell[0] = 0; 4035 doorbell[1] = 0; 4036 4037 if (eq->type_flag == HNS_ROCE_AEQ) { 4038 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 4039 HNS_ROCE_V2_EQ_DB_CMD_S, 4040 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 4041 HNS_ROCE_EQ_DB_CMD_AEQ : 4042 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 4043 } else { 4044 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 4045 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 4046 4047 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 4048 HNS_ROCE_V2_EQ_DB_CMD_S, 4049 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 4050 HNS_ROCE_EQ_DB_CMD_CEQ : 4051 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 4052 } 4053 4054 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 4055 HNS_ROCE_V2_EQ_DB_PARA_S, 4056 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 4057 4058 hns_roce_write64_k(doorbell, eq->doorbell); 4059 } 4060 4061 static void hns_roce_v2_wq_catas_err_handle(struct hns_roce_dev *hr_dev, 4062 struct hns_roce_aeqe *aeqe, 4063 u32 qpn) 4064 { 4065 struct device *dev = hr_dev->dev; 4066 int sub_type; 4067 4068 dev_warn(dev, "Local work queue catastrophic error.\n"); 4069 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 4070 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 4071 switch (sub_type) { 4072 case HNS_ROCE_LWQCE_QPC_ERROR: 4073 dev_warn(dev, "QP %d, QPC error.\n", qpn); 4074 break; 4075 case HNS_ROCE_LWQCE_MTU_ERROR: 4076 dev_warn(dev, "QP %d, MTU error.\n", qpn); 4077 break; 4078 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR: 4079 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn); 4080 break; 4081 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR: 4082 dev_warn(dev, "QP %d, WQE addr error.\n", qpn); 4083 break; 4084 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR: 4085 dev_warn(dev, "QP %d, WQE shift error.\n", qpn); 4086 break; 4087 default: 4088 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 4089 break; 4090 } 4091 } 4092 4093 static void hns_roce_v2_local_wq_access_err_handle(struct hns_roce_dev *hr_dev, 4094 struct hns_roce_aeqe *aeqe, u32 qpn) 4095 { 4096 struct device *dev = hr_dev->dev; 4097 int sub_type; 4098 4099 dev_warn(dev, "Local access violation work queue error.\n"); 4100 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 4101 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 4102 switch (sub_type) { 4103 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION: 4104 dev_warn(dev, "QP %d, R_key violation.\n", qpn); 4105 break; 4106 case HNS_ROCE_LAVWQE_LENGTH_ERROR: 4107 dev_warn(dev, "QP %d, length error.\n", qpn); 4108 break; 4109 case HNS_ROCE_LAVWQE_VA_ERROR: 4110 dev_warn(dev, "QP %d, VA error.\n", qpn); 4111 break; 4112 case HNS_ROCE_LAVWQE_PD_ERROR: 4113 dev_err(dev, "QP %d, PD error.\n", qpn); 4114 break; 4115 case HNS_ROCE_LAVWQE_RW_ACC_ERROR: 4116 dev_warn(dev, "QP %d, rw acc error.\n", qpn); 4117 break; 4118 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR: 4119 dev_warn(dev, "QP %d, key state error.\n", qpn); 4120 break; 4121 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR: 4122 dev_warn(dev, "QP %d, MR operation error.\n", qpn); 4123 break; 4124 default: 4125 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 4126 break; 4127 } 4128 } 4129 4130 static void hns_roce_v2_qp_err_handle(struct hns_roce_dev *hr_dev, 4131 struct hns_roce_aeqe *aeqe, 4132 int event_type, u32 qpn) 4133 { 4134 struct device *dev = hr_dev->dev; 4135 4136 switch (event_type) { 4137 case HNS_ROCE_EVENT_TYPE_COMM_EST: 4138 dev_warn(dev, "Communication established.\n"); 4139 break; 4140 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 4141 dev_warn(dev, "Send queue drained.\n"); 4142 break; 4143 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 4144 hns_roce_v2_wq_catas_err_handle(hr_dev, aeqe, qpn); 4145 break; 4146 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 4147 dev_warn(dev, "Invalid request local work queue error.\n"); 4148 break; 4149 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 4150 hns_roce_v2_local_wq_access_err_handle(hr_dev, aeqe, qpn); 4151 break; 4152 default: 4153 break; 4154 } 4155 4156 hns_roce_qp_event(hr_dev, qpn, event_type); 4157 } 4158 4159 static void hns_roce_v2_cq_err_handle(struct hns_roce_dev *hr_dev, 4160 struct hns_roce_aeqe *aeqe, 4161 int event_type, u32 cqn) 4162 { 4163 struct device *dev = hr_dev->dev; 4164 4165 switch (event_type) { 4166 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 4167 dev_warn(dev, "CQ 0x%x access err.\n", cqn); 4168 break; 4169 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 4170 dev_warn(dev, "CQ 0x%x overflow\n", cqn); 4171 break; 4172 default: 4173 break; 4174 } 4175 4176 hns_roce_cq_event(hr_dev, cqn, event_type); 4177 } 4178 4179 static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry) 4180 { 4181 u32 buf_chk_sz; 4182 unsigned long off; 4183 4184 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4185 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 4186 4187 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) + 4188 off % buf_chk_sz); 4189 } 4190 4191 static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry) 4192 { 4193 u32 buf_chk_sz; 4194 unsigned long off; 4195 4196 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4197 4198 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 4199 4200 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 4201 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) + 4202 off % buf_chk_sz); 4203 else 4204 return (struct hns_roce_aeqe *)((u8 *) 4205 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz); 4206 } 4207 4208 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 4209 { 4210 struct hns_roce_aeqe *aeqe; 4211 4212 if (!eq->hop_num) 4213 aeqe = get_aeqe_v2(eq, eq->cons_index); 4214 else 4215 aeqe = mhop_get_aeqe(eq, eq->cons_index); 4216 4217 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 4218 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 4219 } 4220 4221 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 4222 struct hns_roce_eq *eq) 4223 { 4224 struct device *dev = hr_dev->dev; 4225 struct hns_roce_aeqe *aeqe; 4226 int aeqe_found = 0; 4227 int event_type; 4228 int sub_type; 4229 u32 qpn; 4230 u32 cqn; 4231 4232 while ((aeqe = next_aeqe_sw_v2(eq))) { 4233 4234 /* Make sure we read AEQ entry after we have checked the 4235 * ownership bit 4236 */ 4237 dma_rmb(); 4238 4239 event_type = roce_get_field(aeqe->asyn, 4240 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 4241 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 4242 sub_type = roce_get_field(aeqe->asyn, 4243 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 4244 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 4245 qpn = roce_get_field(aeqe->event.qp_event.qp, 4246 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 4247 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 4248 cqn = roce_get_field(aeqe->event.cq_event.cq, 4249 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 4250 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 4251 4252 switch (event_type) { 4253 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 4254 dev_warn(dev, "Path migrated succeeded.\n"); 4255 break; 4256 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 4257 dev_warn(dev, "Path migration failed.\n"); 4258 break; 4259 case HNS_ROCE_EVENT_TYPE_COMM_EST: 4260 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 4261 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 4262 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 4263 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 4264 hns_roce_v2_qp_err_handle(hr_dev, aeqe, event_type, 4265 qpn); 4266 break; 4267 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 4268 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 4269 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 4270 dev_warn(dev, "SRQ not support.\n"); 4271 break; 4272 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 4273 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 4274 hns_roce_v2_cq_err_handle(hr_dev, aeqe, event_type, 4275 cqn); 4276 break; 4277 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 4278 dev_warn(dev, "DB overflow.\n"); 4279 break; 4280 case HNS_ROCE_EVENT_TYPE_MB: 4281 hns_roce_cmd_event(hr_dev, 4282 le16_to_cpu(aeqe->event.cmd.token), 4283 aeqe->event.cmd.status, 4284 le64_to_cpu(aeqe->event.cmd.out_param)); 4285 break; 4286 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: 4287 dev_warn(dev, "CEQ overflow.\n"); 4288 break; 4289 case HNS_ROCE_EVENT_TYPE_FLR: 4290 dev_warn(dev, "Function level reset.\n"); 4291 break; 4292 default: 4293 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 4294 event_type, eq->eqn, eq->cons_index); 4295 break; 4296 }; 4297 4298 eq->event_type = event_type; 4299 eq->sub_type = sub_type; 4300 ++eq->cons_index; 4301 aeqe_found = 1; 4302 4303 if (eq->cons_index > (2 * eq->entries - 1)) { 4304 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 4305 eq->cons_index = 0; 4306 } 4307 hns_roce_v2_init_irq_work(hr_dev, eq, qpn); 4308 } 4309 4310 set_eq_cons_index_v2(eq); 4311 return aeqe_found; 4312 } 4313 4314 static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry) 4315 { 4316 u32 buf_chk_sz; 4317 unsigned long off; 4318 4319 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4320 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 4321 4322 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) + 4323 off % buf_chk_sz); 4324 } 4325 4326 static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry) 4327 { 4328 u32 buf_chk_sz; 4329 unsigned long off; 4330 4331 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4332 4333 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 4334 4335 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 4336 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) + 4337 off % buf_chk_sz); 4338 else 4339 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off / 4340 buf_chk_sz]) + off % buf_chk_sz); 4341 } 4342 4343 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 4344 { 4345 struct hns_roce_ceqe *ceqe; 4346 4347 if (!eq->hop_num) 4348 ceqe = get_ceqe_v2(eq, eq->cons_index); 4349 else 4350 ceqe = mhop_get_ceqe(eq, eq->cons_index); 4351 4352 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 4353 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 4354 } 4355 4356 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 4357 struct hns_roce_eq *eq) 4358 { 4359 struct device *dev = hr_dev->dev; 4360 struct hns_roce_ceqe *ceqe; 4361 int ceqe_found = 0; 4362 u32 cqn; 4363 4364 while ((ceqe = next_ceqe_sw_v2(eq))) { 4365 4366 /* Make sure we read CEQ entry after we have checked the 4367 * ownership bit 4368 */ 4369 dma_rmb(); 4370 4371 cqn = roce_get_field(ceqe->comp, 4372 HNS_ROCE_V2_CEQE_COMP_CQN_M, 4373 HNS_ROCE_V2_CEQE_COMP_CQN_S); 4374 4375 hns_roce_cq_completion(hr_dev, cqn); 4376 4377 ++eq->cons_index; 4378 ceqe_found = 1; 4379 4380 if (eq->cons_index > (2 * eq->entries - 1)) { 4381 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 4382 eq->cons_index = 0; 4383 } 4384 } 4385 4386 set_eq_cons_index_v2(eq); 4387 4388 return ceqe_found; 4389 } 4390 4391 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 4392 { 4393 struct hns_roce_eq *eq = eq_ptr; 4394 struct hns_roce_dev *hr_dev = eq->hr_dev; 4395 int int_work = 0; 4396 4397 if (eq->type_flag == HNS_ROCE_CEQ) 4398 /* Completion event interrupt */ 4399 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 4400 else 4401 /* Asychronous event interrupt */ 4402 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 4403 4404 return IRQ_RETVAL(int_work); 4405 } 4406 4407 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 4408 { 4409 struct hns_roce_dev *hr_dev = dev_id; 4410 struct device *dev = hr_dev->dev; 4411 int int_work = 0; 4412 u32 int_st; 4413 u32 int_en; 4414 4415 /* Abnormal interrupt */ 4416 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 4417 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 4418 4419 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 4420 dev_err(dev, "AEQ overflow!\n"); 4421 4422 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1); 4423 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 4424 4425 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 4426 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 4427 4428 int_work = 1; 4429 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 4430 dev_err(dev, "BUS ERR!\n"); 4431 4432 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1); 4433 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 4434 4435 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 4436 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 4437 4438 int_work = 1; 4439 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 4440 dev_err(dev, "OTHER ERR!\n"); 4441 4442 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1); 4443 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 4444 4445 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 4446 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 4447 4448 int_work = 1; 4449 } else 4450 dev_err(dev, "There is no abnormal irq found!\n"); 4451 4452 return IRQ_RETVAL(int_work); 4453 } 4454 4455 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 4456 int eq_num, int enable_flag) 4457 { 4458 int i; 4459 4460 if (enable_flag == EQ_ENABLE) { 4461 for (i = 0; i < eq_num; i++) 4462 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 4463 i * EQ_REG_OFFSET, 4464 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 4465 4466 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 4467 HNS_ROCE_V2_VF_ABN_INT_EN_M); 4468 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 4469 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 4470 } else { 4471 for (i = 0; i < eq_num; i++) 4472 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 4473 i * EQ_REG_OFFSET, 4474 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 4475 4476 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 4477 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 4478 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 4479 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 4480 } 4481 } 4482 4483 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 4484 { 4485 struct device *dev = hr_dev->dev; 4486 int ret; 4487 4488 if (eqn < hr_dev->caps.num_comp_vectors) 4489 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 4490 0, HNS_ROCE_CMD_DESTROY_CEQC, 4491 HNS_ROCE_CMD_TIMEOUT_MSECS); 4492 else 4493 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 4494 0, HNS_ROCE_CMD_DESTROY_AEQC, 4495 HNS_ROCE_CMD_TIMEOUT_MSECS); 4496 if (ret) 4497 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 4498 } 4499 4500 static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev, 4501 struct hns_roce_eq *eq) 4502 { 4503 struct device *dev = hr_dev->dev; 4504 u64 idx; 4505 u64 size; 4506 u32 buf_chk_sz; 4507 u32 bt_chk_sz; 4508 u32 mhop_num; 4509 int eqe_alloc; 4510 int i = 0; 4511 int j = 0; 4512 4513 mhop_num = hr_dev->caps.eqe_hop_num; 4514 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4515 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 4516 4517 /* hop_num = 0 */ 4518 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 4519 dma_free_coherent(dev, (unsigned int)(eq->entries * 4520 eq->eqe_size), eq->bt_l0, eq->l0_dma); 4521 return; 4522 } 4523 4524 /* hop_num = 1 or hop = 2 */ 4525 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4526 if (mhop_num == 1) { 4527 for (i = 0; i < eq->l0_last_num; i++) { 4528 if (i == eq->l0_last_num - 1) { 4529 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 4530 size = (eq->entries - eqe_alloc) * eq->eqe_size; 4531 dma_free_coherent(dev, size, eq->buf[i], 4532 eq->buf_dma[i]); 4533 break; 4534 } 4535 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 4536 eq->buf_dma[i]); 4537 } 4538 } else if (mhop_num == 2) { 4539 for (i = 0; i < eq->l0_last_num; i++) { 4540 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4541 eq->l1_dma[i]); 4542 4543 for (j = 0; j < bt_chk_sz / 8; j++) { 4544 idx = i * (bt_chk_sz / 8) + j; 4545 if ((i == eq->l0_last_num - 1) 4546 && j == eq->l1_last_num - 1) { 4547 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4548 * idx; 4549 size = (eq->entries - eqe_alloc) 4550 * eq->eqe_size; 4551 dma_free_coherent(dev, size, 4552 eq->buf[idx], 4553 eq->buf_dma[idx]); 4554 break; 4555 } 4556 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4557 eq->buf_dma[idx]); 4558 } 4559 } 4560 } 4561 kfree(eq->buf_dma); 4562 kfree(eq->buf); 4563 kfree(eq->l1_dma); 4564 kfree(eq->bt_l1); 4565 eq->buf_dma = NULL; 4566 eq->buf = NULL; 4567 eq->l1_dma = NULL; 4568 eq->bt_l1 = NULL; 4569 } 4570 4571 static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev, 4572 struct hns_roce_eq *eq) 4573 { 4574 u32 buf_chk_sz; 4575 4576 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4577 4578 if (hr_dev->caps.eqe_hop_num) { 4579 hns_roce_mhop_free_eq(hr_dev, eq); 4580 return; 4581 } 4582 4583 if (eq->buf_list) 4584 dma_free_coherent(hr_dev->dev, buf_chk_sz, 4585 eq->buf_list->buf, eq->buf_list->map); 4586 } 4587 4588 static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev, 4589 struct hns_roce_eq *eq, 4590 void *mb_buf) 4591 { 4592 struct hns_roce_eq_context *eqc; 4593 4594 eqc = mb_buf; 4595 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 4596 4597 /* init eqc */ 4598 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 4599 eq->hop_num = hr_dev->caps.eqe_hop_num; 4600 eq->cons_index = 0; 4601 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 4602 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 4603 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 4604 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz; 4605 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz; 4606 eq->shift = ilog2((unsigned int)eq->entries); 4607 4608 if (!eq->hop_num) 4609 eq->eqe_ba = eq->buf_list->map; 4610 else 4611 eq->eqe_ba = eq->l0_dma; 4612 4613 /* set eqc state */ 4614 roce_set_field(eqc->byte_4, 4615 HNS_ROCE_EQC_EQ_ST_M, 4616 HNS_ROCE_EQC_EQ_ST_S, 4617 HNS_ROCE_V2_EQ_STATE_VALID); 4618 4619 /* set eqe hop num */ 4620 roce_set_field(eqc->byte_4, 4621 HNS_ROCE_EQC_HOP_NUM_M, 4622 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 4623 4624 /* set eqc over_ignore */ 4625 roce_set_field(eqc->byte_4, 4626 HNS_ROCE_EQC_OVER_IGNORE_M, 4627 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 4628 4629 /* set eqc coalesce */ 4630 roce_set_field(eqc->byte_4, 4631 HNS_ROCE_EQC_COALESCE_M, 4632 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 4633 4634 /* set eqc arm_state */ 4635 roce_set_field(eqc->byte_4, 4636 HNS_ROCE_EQC_ARM_ST_M, 4637 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 4638 4639 /* set eqn */ 4640 roce_set_field(eqc->byte_4, 4641 HNS_ROCE_EQC_EQN_M, 4642 HNS_ROCE_EQC_EQN_S, eq->eqn); 4643 4644 /* set eqe_cnt */ 4645 roce_set_field(eqc->byte_4, 4646 HNS_ROCE_EQC_EQE_CNT_M, 4647 HNS_ROCE_EQC_EQE_CNT_S, 4648 HNS_ROCE_EQ_INIT_EQE_CNT); 4649 4650 /* set eqe_ba_pg_sz */ 4651 roce_set_field(eqc->byte_8, 4652 HNS_ROCE_EQC_BA_PG_SZ_M, 4653 HNS_ROCE_EQC_BA_PG_SZ_S, 4654 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET); 4655 4656 /* set eqe_buf_pg_sz */ 4657 roce_set_field(eqc->byte_8, 4658 HNS_ROCE_EQC_BUF_PG_SZ_M, 4659 HNS_ROCE_EQC_BUF_PG_SZ_S, 4660 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET); 4661 4662 /* set eq_producer_idx */ 4663 roce_set_field(eqc->byte_8, 4664 HNS_ROCE_EQC_PROD_INDX_M, 4665 HNS_ROCE_EQC_PROD_INDX_S, 4666 HNS_ROCE_EQ_INIT_PROD_IDX); 4667 4668 /* set eq_max_cnt */ 4669 roce_set_field(eqc->byte_12, 4670 HNS_ROCE_EQC_MAX_CNT_M, 4671 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 4672 4673 /* set eq_period */ 4674 roce_set_field(eqc->byte_12, 4675 HNS_ROCE_EQC_PERIOD_M, 4676 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 4677 4678 /* set eqe_report_timer */ 4679 roce_set_field(eqc->eqe_report_timer, 4680 HNS_ROCE_EQC_REPORT_TIMER_M, 4681 HNS_ROCE_EQC_REPORT_TIMER_S, 4682 HNS_ROCE_EQ_INIT_REPORT_TIMER); 4683 4684 /* set eqe_ba [34:3] */ 4685 roce_set_field(eqc->eqe_ba0, 4686 HNS_ROCE_EQC_EQE_BA_L_M, 4687 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3); 4688 4689 /* set eqe_ba [64:35] */ 4690 roce_set_field(eqc->eqe_ba1, 4691 HNS_ROCE_EQC_EQE_BA_H_M, 4692 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35); 4693 4694 /* set eq shift */ 4695 roce_set_field(eqc->byte_28, 4696 HNS_ROCE_EQC_SHIFT_M, 4697 HNS_ROCE_EQC_SHIFT_S, eq->shift); 4698 4699 /* set eq MSI_IDX */ 4700 roce_set_field(eqc->byte_28, 4701 HNS_ROCE_EQC_MSI_INDX_M, 4702 HNS_ROCE_EQC_MSI_INDX_S, 4703 HNS_ROCE_EQ_INIT_MSI_IDX); 4704 4705 /* set cur_eqe_ba [27:12] */ 4706 roce_set_field(eqc->byte_28, 4707 HNS_ROCE_EQC_CUR_EQE_BA_L_M, 4708 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12); 4709 4710 /* set cur_eqe_ba [59:28] */ 4711 roce_set_field(eqc->byte_32, 4712 HNS_ROCE_EQC_CUR_EQE_BA_M_M, 4713 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28); 4714 4715 /* set cur_eqe_ba [63:60] */ 4716 roce_set_field(eqc->byte_36, 4717 HNS_ROCE_EQC_CUR_EQE_BA_H_M, 4718 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60); 4719 4720 /* set eq consumer idx */ 4721 roce_set_field(eqc->byte_36, 4722 HNS_ROCE_EQC_CONS_INDX_M, 4723 HNS_ROCE_EQC_CONS_INDX_S, 4724 HNS_ROCE_EQ_INIT_CONS_IDX); 4725 4726 /* set nex_eqe_ba[43:12] */ 4727 roce_set_field(eqc->nxt_eqe_ba0, 4728 HNS_ROCE_EQC_NXT_EQE_BA_L_M, 4729 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12); 4730 4731 /* set nex_eqe_ba[63:44] */ 4732 roce_set_field(eqc->nxt_eqe_ba1, 4733 HNS_ROCE_EQC_NXT_EQE_BA_H_M, 4734 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44); 4735 } 4736 4737 static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev, 4738 struct hns_roce_eq *eq) 4739 { 4740 struct device *dev = hr_dev->dev; 4741 int eq_alloc_done = 0; 4742 int eq_buf_cnt = 0; 4743 int eqe_alloc; 4744 u32 buf_chk_sz; 4745 u32 bt_chk_sz; 4746 u32 mhop_num; 4747 u64 size; 4748 u64 idx; 4749 int ba_num; 4750 int bt_num; 4751 int record_i; 4752 int record_j; 4753 int i = 0; 4754 int j = 0; 4755 4756 mhop_num = hr_dev->caps.eqe_hop_num; 4757 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4758 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 4759 4760 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1) 4761 / buf_chk_sz; 4762 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8); 4763 4764 /* hop_num = 0 */ 4765 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 4766 if (eq->entries > buf_chk_sz / eq->eqe_size) { 4767 dev_err(dev, "eq entries %d is larger than buf_pg_sz!", 4768 eq->entries); 4769 return -EINVAL; 4770 } 4771 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size, 4772 &(eq->l0_dma), GFP_KERNEL); 4773 if (!eq->bt_l0) 4774 return -ENOMEM; 4775 4776 eq->cur_eqe_ba = eq->l0_dma; 4777 eq->nxt_eqe_ba = 0; 4778 4779 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size); 4780 4781 return 0; 4782 } 4783 4784 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL); 4785 if (!eq->buf_dma) 4786 return -ENOMEM; 4787 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL); 4788 if (!eq->buf) 4789 goto err_kcalloc_buf; 4790 4791 if (mhop_num == 2) { 4792 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL); 4793 if (!eq->l1_dma) 4794 goto err_kcalloc_l1_dma; 4795 4796 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL); 4797 if (!eq->bt_l1) 4798 goto err_kcalloc_bt_l1; 4799 } 4800 4801 /* alloc L0 BT */ 4802 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL); 4803 if (!eq->bt_l0) 4804 goto err_dma_alloc_l0; 4805 4806 if (mhop_num == 1) { 4807 if (ba_num > (bt_chk_sz / 8)) 4808 dev_err(dev, "ba_num %d is too large for 1 hop\n", 4809 ba_num); 4810 4811 /* alloc buf */ 4812 for (i = 0; i < bt_chk_sz / 8; i++) { 4813 if (eq_buf_cnt + 1 < ba_num) { 4814 size = buf_chk_sz; 4815 } else { 4816 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 4817 size = (eq->entries - eqe_alloc) * eq->eqe_size; 4818 } 4819 eq->buf[i] = dma_alloc_coherent(dev, size, 4820 &(eq->buf_dma[i]), 4821 GFP_KERNEL); 4822 if (!eq->buf[i]) 4823 goto err_dma_alloc_buf; 4824 4825 memset(eq->buf[i], 0, size); 4826 *(eq->bt_l0 + i) = eq->buf_dma[i]; 4827 4828 eq_buf_cnt++; 4829 if (eq_buf_cnt >= ba_num) 4830 break; 4831 } 4832 eq->cur_eqe_ba = eq->buf_dma[0]; 4833 eq->nxt_eqe_ba = eq->buf_dma[1]; 4834 4835 } else if (mhop_num == 2) { 4836 /* alloc L1 BT and buf */ 4837 for (i = 0; i < bt_chk_sz / 8; i++) { 4838 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz, 4839 &(eq->l1_dma[i]), 4840 GFP_KERNEL); 4841 if (!eq->bt_l1[i]) 4842 goto err_dma_alloc_l1; 4843 *(eq->bt_l0 + i) = eq->l1_dma[i]; 4844 4845 for (j = 0; j < bt_chk_sz / 8; j++) { 4846 idx = i * bt_chk_sz / 8 + j; 4847 if (eq_buf_cnt + 1 < ba_num) { 4848 size = buf_chk_sz; 4849 } else { 4850 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4851 * idx; 4852 size = (eq->entries - eqe_alloc) 4853 * eq->eqe_size; 4854 } 4855 eq->buf[idx] = dma_alloc_coherent(dev, size, 4856 &(eq->buf_dma[idx]), 4857 GFP_KERNEL); 4858 if (!eq->buf[idx]) 4859 goto err_dma_alloc_buf; 4860 4861 memset(eq->buf[idx], 0, size); 4862 *(eq->bt_l1[i] + j) = eq->buf_dma[idx]; 4863 4864 eq_buf_cnt++; 4865 if (eq_buf_cnt >= ba_num) { 4866 eq_alloc_done = 1; 4867 break; 4868 } 4869 } 4870 4871 if (eq_alloc_done) 4872 break; 4873 } 4874 eq->cur_eqe_ba = eq->buf_dma[0]; 4875 eq->nxt_eqe_ba = eq->buf_dma[1]; 4876 } 4877 4878 eq->l0_last_num = i + 1; 4879 if (mhop_num == 2) 4880 eq->l1_last_num = j + 1; 4881 4882 return 0; 4883 4884 err_dma_alloc_l1: 4885 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4886 eq->bt_l0 = NULL; 4887 eq->l0_dma = 0; 4888 for (i -= 1; i >= 0; i--) { 4889 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4890 eq->l1_dma[i]); 4891 4892 for (j = 0; j < bt_chk_sz / 8; j++) { 4893 idx = i * bt_chk_sz / 8 + j; 4894 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4895 eq->buf_dma[idx]); 4896 } 4897 } 4898 goto err_dma_alloc_l0; 4899 4900 err_dma_alloc_buf: 4901 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4902 eq->bt_l0 = NULL; 4903 eq->l0_dma = 0; 4904 4905 if (mhop_num == 1) 4906 for (i -= 1; i >= 0; i--) 4907 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 4908 eq->buf_dma[i]); 4909 else if (mhop_num == 2) { 4910 record_i = i; 4911 record_j = j; 4912 for (; i >= 0; i--) { 4913 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4914 eq->l1_dma[i]); 4915 4916 for (j = 0; j < bt_chk_sz / 8; j++) { 4917 if (i == record_i && j >= record_j) 4918 break; 4919 4920 idx = i * bt_chk_sz / 8 + j; 4921 dma_free_coherent(dev, buf_chk_sz, 4922 eq->buf[idx], 4923 eq->buf_dma[idx]); 4924 } 4925 } 4926 } 4927 4928 err_dma_alloc_l0: 4929 kfree(eq->bt_l1); 4930 eq->bt_l1 = NULL; 4931 4932 err_kcalloc_bt_l1: 4933 kfree(eq->l1_dma); 4934 eq->l1_dma = NULL; 4935 4936 err_kcalloc_l1_dma: 4937 kfree(eq->buf); 4938 eq->buf = NULL; 4939 4940 err_kcalloc_buf: 4941 kfree(eq->buf_dma); 4942 eq->buf_dma = NULL; 4943 4944 return -ENOMEM; 4945 } 4946 4947 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 4948 struct hns_roce_eq *eq, 4949 unsigned int eq_cmd) 4950 { 4951 struct device *dev = hr_dev->dev; 4952 struct hns_roce_cmd_mailbox *mailbox; 4953 u32 buf_chk_sz = 0; 4954 int ret; 4955 4956 /* Allocate mailbox memory */ 4957 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4958 if (IS_ERR(mailbox)) 4959 return PTR_ERR(mailbox); 4960 4961 if (!hr_dev->caps.eqe_hop_num) { 4962 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4963 4964 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list), 4965 GFP_KERNEL); 4966 if (!eq->buf_list) { 4967 ret = -ENOMEM; 4968 goto free_cmd_mbox; 4969 } 4970 4971 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz, 4972 &(eq->buf_list->map), 4973 GFP_KERNEL); 4974 if (!eq->buf_list->buf) { 4975 ret = -ENOMEM; 4976 goto err_alloc_buf; 4977 } 4978 4979 memset(eq->buf_list->buf, 0, buf_chk_sz); 4980 } else { 4981 ret = hns_roce_mhop_alloc_eq(hr_dev, eq); 4982 if (ret) { 4983 ret = -ENOMEM; 4984 goto free_cmd_mbox; 4985 } 4986 } 4987 4988 hns_roce_config_eqc(hr_dev, eq, mailbox->buf); 4989 4990 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 4991 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 4992 if (ret) { 4993 dev_err(dev, "[mailbox cmd] create eqc failed.\n"); 4994 goto err_cmd_mbox; 4995 } 4996 4997 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4998 4999 return 0; 5000 5001 err_cmd_mbox: 5002 if (!hr_dev->caps.eqe_hop_num) 5003 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf, 5004 eq->buf_list->map); 5005 else { 5006 hns_roce_mhop_free_eq(hr_dev, eq); 5007 goto free_cmd_mbox; 5008 } 5009 5010 err_alloc_buf: 5011 kfree(eq->buf_list); 5012 5013 free_cmd_mbox: 5014 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5015 5016 return ret; 5017 } 5018 5019 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 5020 { 5021 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5022 struct device *dev = hr_dev->dev; 5023 struct hns_roce_eq *eq; 5024 unsigned int eq_cmd; 5025 int irq_num; 5026 int eq_num; 5027 int other_num; 5028 int comp_num; 5029 int aeq_num; 5030 int i, j, k; 5031 int ret; 5032 5033 other_num = hr_dev->caps.num_other_vectors; 5034 comp_num = hr_dev->caps.num_comp_vectors; 5035 aeq_num = hr_dev->caps.num_aeq_vectors; 5036 5037 eq_num = comp_num + aeq_num; 5038 irq_num = eq_num + other_num; 5039 5040 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 5041 if (!eq_table->eq) 5042 return -ENOMEM; 5043 5044 for (i = 0; i < irq_num; i++) { 5045 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 5046 GFP_KERNEL); 5047 if (!hr_dev->irq_names[i]) { 5048 ret = -ENOMEM; 5049 goto err_failed_kzalloc; 5050 } 5051 } 5052 5053 /* create eq */ 5054 for (j = 0; j < eq_num; j++) { 5055 eq = &eq_table->eq[j]; 5056 eq->hr_dev = hr_dev; 5057 eq->eqn = j; 5058 if (j < comp_num) { 5059 /* CEQ */ 5060 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 5061 eq->type_flag = HNS_ROCE_CEQ; 5062 eq->entries = hr_dev->caps.ceqe_depth; 5063 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; 5064 eq->irq = hr_dev->irq[j + other_num + aeq_num]; 5065 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 5066 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 5067 } else { 5068 /* AEQ */ 5069 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 5070 eq->type_flag = HNS_ROCE_AEQ; 5071 eq->entries = hr_dev->caps.aeqe_depth; 5072 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; 5073 eq->irq = hr_dev->irq[j - comp_num + other_num]; 5074 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 5075 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 5076 } 5077 5078 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 5079 if (ret) { 5080 dev_err(dev, "eq create failed.\n"); 5081 goto err_create_eq_fail; 5082 } 5083 } 5084 5085 /* enable irq */ 5086 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 5087 5088 /* irq contains: abnormal + AEQ + CEQ*/ 5089 for (k = 0; k < irq_num; k++) 5090 if (k < other_num) 5091 snprintf((char *)hr_dev->irq_names[k], 5092 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k); 5093 else if (k < (other_num + aeq_num)) 5094 snprintf((char *)hr_dev->irq_names[k], 5095 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d", 5096 k - other_num); 5097 else 5098 snprintf((char *)hr_dev->irq_names[k], 5099 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d", 5100 k - other_num - aeq_num); 5101 5102 for (k = 0; k < irq_num; k++) { 5103 if (k < other_num) 5104 ret = request_irq(hr_dev->irq[k], 5105 hns_roce_v2_msix_interrupt_abn, 5106 0, hr_dev->irq_names[k], hr_dev); 5107 5108 else if (k < (other_num + comp_num)) 5109 ret = request_irq(eq_table->eq[k - other_num].irq, 5110 hns_roce_v2_msix_interrupt_eq, 5111 0, hr_dev->irq_names[k + aeq_num], 5112 &eq_table->eq[k - other_num]); 5113 else 5114 ret = request_irq(eq_table->eq[k - other_num].irq, 5115 hns_roce_v2_msix_interrupt_eq, 5116 0, hr_dev->irq_names[k - comp_num], 5117 &eq_table->eq[k - other_num]); 5118 if (ret) { 5119 dev_err(dev, "Request irq error!\n"); 5120 goto err_request_irq_fail; 5121 } 5122 } 5123 5124 hr_dev->irq_workq = 5125 create_singlethread_workqueue("hns_roce_irq_workqueue"); 5126 if (!hr_dev->irq_workq) { 5127 dev_err(dev, "Create irq workqueue failed!\n"); 5128 goto err_request_irq_fail; 5129 } 5130 5131 return 0; 5132 5133 err_request_irq_fail: 5134 for (k -= 1; k >= 0; k--) 5135 if (k < other_num) 5136 free_irq(hr_dev->irq[k], hr_dev); 5137 else 5138 free_irq(eq_table->eq[k - other_num].irq, 5139 &eq_table->eq[k - other_num]); 5140 5141 err_create_eq_fail: 5142 for (j -= 1; j >= 0; j--) 5143 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]); 5144 5145 err_failed_kzalloc: 5146 for (i -= 1; i >= 0; i--) 5147 kfree(hr_dev->irq_names[i]); 5148 kfree(eq_table->eq); 5149 5150 return ret; 5151 } 5152 5153 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 5154 { 5155 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5156 int irq_num; 5157 int eq_num; 5158 int i; 5159 5160 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 5161 irq_num = eq_num + hr_dev->caps.num_other_vectors; 5162 5163 /* Disable irq */ 5164 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 5165 5166 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 5167 free_irq(hr_dev->irq[i], hr_dev); 5168 5169 for (i = 0; i < eq_num; i++) { 5170 hns_roce_v2_destroy_eqc(hr_dev, i); 5171 5172 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]); 5173 5174 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]); 5175 } 5176 5177 for (i = 0; i < irq_num; i++) 5178 kfree(hr_dev->irq_names[i]); 5179 5180 kfree(eq_table->eq); 5181 5182 flush_workqueue(hr_dev->irq_workq); 5183 destroy_workqueue(hr_dev->irq_workq); 5184 } 5185 5186 static const struct hns_roce_hw hns_roce_hw_v2 = { 5187 .cmq_init = hns_roce_v2_cmq_init, 5188 .cmq_exit = hns_roce_v2_cmq_exit, 5189 .hw_profile = hns_roce_v2_profile, 5190 .hw_init = hns_roce_v2_init, 5191 .hw_exit = hns_roce_v2_exit, 5192 .post_mbox = hns_roce_v2_post_mbox, 5193 .chk_mbox = hns_roce_v2_chk_mbox, 5194 .set_gid = hns_roce_v2_set_gid, 5195 .set_mac = hns_roce_v2_set_mac, 5196 .write_mtpt = hns_roce_v2_write_mtpt, 5197 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 5198 .write_cqc = hns_roce_v2_write_cqc, 5199 .set_hem = hns_roce_v2_set_hem, 5200 .clear_hem = hns_roce_v2_clear_hem, 5201 .modify_qp = hns_roce_v2_modify_qp, 5202 .query_qp = hns_roce_v2_query_qp, 5203 .destroy_qp = hns_roce_v2_destroy_qp, 5204 .modify_cq = hns_roce_v2_modify_cq, 5205 .post_send = hns_roce_v2_post_send, 5206 .post_recv = hns_roce_v2_post_recv, 5207 .req_notify_cq = hns_roce_v2_req_notify_cq, 5208 .poll_cq = hns_roce_v2_poll_cq, 5209 .init_eq = hns_roce_v2_init_eq_table, 5210 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 5211 }; 5212 5213 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 5214 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 5215 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 5216 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 5217 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 5218 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 5219 /* required last entry */ 5220 {0, } 5221 }; 5222 5223 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 5224 5225 static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 5226 struct hnae3_handle *handle) 5227 { 5228 const struct pci_device_id *id; 5229 int i; 5230 5231 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 5232 if (!id) { 5233 dev_err(hr_dev->dev, "device is not compatible!\n"); 5234 return -ENXIO; 5235 } 5236 5237 hr_dev->hw = &hns_roce_hw_v2; 5238 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 5239 hr_dev->odb_offset = hr_dev->sdb_offset; 5240 5241 /* Get info from NIC driver. */ 5242 hr_dev->reg_base = handle->rinfo.roce_io_base; 5243 hr_dev->caps.num_ports = 1; 5244 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 5245 hr_dev->iboe.phy_port[0] = 0; 5246 5247 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 5248 hr_dev->iboe.netdevs[0]->dev_addr); 5249 5250 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 5251 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 5252 i + handle->rinfo.base_vector); 5253 5254 /* cmd issue mode: 0 is poll, 1 is event */ 5255 hr_dev->cmd_mod = 1; 5256 hr_dev->loop_idc = 0; 5257 5258 return 0; 5259 } 5260 5261 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 5262 { 5263 struct hns_roce_dev *hr_dev; 5264 int ret; 5265 5266 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev)); 5267 if (!hr_dev) 5268 return -ENOMEM; 5269 5270 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 5271 if (!hr_dev->priv) { 5272 ret = -ENOMEM; 5273 goto error_failed_kzalloc; 5274 } 5275 5276 hr_dev->pci_dev = handle->pdev; 5277 hr_dev->dev = &handle->pdev->dev; 5278 handle->priv = hr_dev; 5279 5280 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle); 5281 if (ret) { 5282 dev_err(hr_dev->dev, "Get Configuration failed!\n"); 5283 goto error_failed_get_cfg; 5284 } 5285 5286 ret = hns_roce_init(hr_dev); 5287 if (ret) { 5288 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 5289 goto error_failed_get_cfg; 5290 } 5291 5292 return 0; 5293 5294 error_failed_get_cfg: 5295 kfree(hr_dev->priv); 5296 5297 error_failed_kzalloc: 5298 ib_dealloc_device(&hr_dev->ib_dev); 5299 5300 return ret; 5301 } 5302 5303 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 5304 bool reset) 5305 { 5306 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 5307 5308 if (!hr_dev) 5309 return; 5310 5311 hns_roce_exit(hr_dev); 5312 kfree(hr_dev->priv); 5313 ib_dealloc_device(&hr_dev->ib_dev); 5314 } 5315 5316 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 5317 { 5318 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 5319 struct ib_event event; 5320 5321 if (!hr_dev) { 5322 dev_err(&handle->pdev->dev, 5323 "Input parameter handle->priv is NULL!\n"); 5324 return -EINVAL; 5325 } 5326 5327 hr_dev->active = false; 5328 hr_dev->is_reset = true; 5329 5330 event.event = IB_EVENT_DEVICE_FATAL; 5331 event.device = &hr_dev->ib_dev; 5332 event.element.port_num = 1; 5333 ib_dispatch_event(&event); 5334 5335 return 0; 5336 } 5337 5338 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 5339 { 5340 int ret; 5341 5342 ret = hns_roce_hw_v2_init_instance(handle); 5343 if (ret) { 5344 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 5345 * callback function, RoCE Engine reinitialize. If RoCE reinit 5346 * failed, we should inform NIC driver. 5347 */ 5348 handle->priv = NULL; 5349 dev_err(&handle->pdev->dev, 5350 "In reset process RoCE reinit failed %d.\n", ret); 5351 } 5352 5353 return ret; 5354 } 5355 5356 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 5357 { 5358 msleep(100); 5359 hns_roce_hw_v2_uninit_instance(handle, false); 5360 return 0; 5361 } 5362 5363 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 5364 enum hnae3_reset_notify_type type) 5365 { 5366 int ret = 0; 5367 5368 switch (type) { 5369 case HNAE3_DOWN_CLIENT: 5370 ret = hns_roce_hw_v2_reset_notify_down(handle); 5371 break; 5372 case HNAE3_INIT_CLIENT: 5373 ret = hns_roce_hw_v2_reset_notify_init(handle); 5374 break; 5375 case HNAE3_UNINIT_CLIENT: 5376 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 5377 break; 5378 default: 5379 break; 5380 } 5381 5382 return ret; 5383 } 5384 5385 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 5386 .init_instance = hns_roce_hw_v2_init_instance, 5387 .uninit_instance = hns_roce_hw_v2_uninit_instance, 5388 .reset_notify = hns_roce_hw_v2_reset_notify, 5389 }; 5390 5391 static struct hnae3_client hns_roce_hw_v2_client = { 5392 .name = "hns_roce_hw_v2", 5393 .type = HNAE3_CLIENT_ROCE, 5394 .ops = &hns_roce_hw_v2_ops, 5395 }; 5396 5397 static int __init hns_roce_hw_v2_init(void) 5398 { 5399 return hnae3_register_client(&hns_roce_hw_v2_client); 5400 } 5401 5402 static void __exit hns_roce_hw_v2_exit(void) 5403 { 5404 hnae3_unregister_client(&hns_roce_hw_v2_client); 5405 } 5406 5407 module_init(hns_roce_hw_v2_init); 5408 module_exit(hns_roce_hw_v2_exit); 5409 5410 MODULE_LICENSE("Dual BSD/GPL"); 5411 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 5412 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 5413 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 5414 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 5415