1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <linux/workqueue.h> 40 #include <net/addrconf.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <rdma/ib_umem.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include "hnae3.h" 47 #include "hns_roce_common.h" 48 #include "hns_roce_device.h" 49 #include "hns_roce_cmd.h" 50 #include "hns_roce_hem.h" 51 #include "hns_roce_hw_v2.h" 52 53 enum { 54 CMD_RST_PRC_OTHERS, 55 CMD_RST_PRC_SUCCESS, 56 CMD_RST_PRC_EBUSY, 57 }; 58 59 enum ecc_resource_type { 60 ECC_RESOURCE_QPC, 61 ECC_RESOURCE_CQC, 62 ECC_RESOURCE_MPT, 63 ECC_RESOURCE_SRQC, 64 ECC_RESOURCE_GMV, 65 ECC_RESOURCE_QPC_TIMER, 66 ECC_RESOURCE_CQC_TIMER, 67 ECC_RESOURCE_SCCC, 68 ECC_RESOURCE_COUNT, 69 }; 70 71 static const struct { 72 const char *name; 73 u8 read_bt0_op; 74 u8 write_bt0_op; 75 } fmea_ram_res[] = { 76 { "ECC_RESOURCE_QPC", 77 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 78 { "ECC_RESOURCE_CQC", 79 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 80 { "ECC_RESOURCE_MPT", 81 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 82 { "ECC_RESOURCE_SRQC", 83 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 84 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 85 { "ECC_RESOURCE_GMV", 86 0, 0 }, 87 { "ECC_RESOURCE_QPC_TIMER", 88 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 89 { "ECC_RESOURCE_CQC_TIMER", 90 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 91 { "ECC_RESOURCE_SCCC", 92 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 93 }; 94 95 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 96 struct ib_sge *sg) 97 { 98 dseg->lkey = cpu_to_le32(sg->lkey); 99 dseg->addr = cpu_to_le64(sg->addr); 100 dseg->len = cpu_to_le32(sg->length); 101 } 102 103 /* 104 * mapped-value = 1 + real-value 105 * The hns wr opcode real value is start from 0, In order to distinguish between 106 * initialized and uninitialized map values, we plus 1 to the actual value when 107 * defining the mapping, so that the validity can be identified by checking the 108 * mapped value is greater than 0. 109 */ 110 #define HR_OPC_MAP(ib_key, hr_key) \ 111 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 112 113 static const u32 hns_roce_op_code[] = { 114 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 115 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 116 HR_OPC_MAP(SEND, SEND), 117 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 118 HR_OPC_MAP(RDMA_READ, RDMA_READ), 119 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 120 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 121 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 122 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 123 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 124 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 125 }; 126 127 static u32 to_hr_opcode(u32 ib_opcode) 128 { 129 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 130 return HNS_ROCE_V2_WQE_OP_MASK; 131 132 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 133 HNS_ROCE_V2_WQE_OP_MASK; 134 } 135 136 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 137 const struct ib_reg_wr *wr) 138 { 139 struct hns_roce_wqe_frmr_seg *fseg = 140 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 141 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 142 u64 pbl_ba; 143 144 /* use ib_access_flags */ 145 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 146 hr_reg_write_bool(fseg, FRMR_ATOMIC, 147 wr->access & IB_ACCESS_REMOTE_ATOMIC); 148 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 149 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 150 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 151 152 /* Data structure reuse may lead to confusion */ 153 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 154 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 155 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 156 157 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 158 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 159 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 160 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 161 162 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 163 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 164 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 165 hr_reg_clear(fseg, FRMR_BLK_MODE); 166 } 167 168 static void set_atomic_seg(const struct ib_send_wr *wr, 169 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 170 unsigned int valid_num_sge) 171 { 172 struct hns_roce_v2_wqe_data_seg *dseg = 173 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 174 struct hns_roce_wqe_atomic_seg *aseg = 175 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 176 177 set_data_seg_v2(dseg, wr->sg_list); 178 179 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 180 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 181 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 182 } else { 183 aseg->fetchadd_swap_data = 184 cpu_to_le64(atomic_wr(wr)->compare_add); 185 aseg->cmp_data = 0; 186 } 187 188 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 189 } 190 191 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 192 const struct ib_send_wr *wr, 193 unsigned int *sge_idx, u32 msg_len) 194 { 195 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 196 unsigned int left_len_in_pg; 197 unsigned int idx = *sge_idx; 198 unsigned int i = 0; 199 unsigned int len; 200 void *addr; 201 void *dseg; 202 203 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 204 ibdev_err(ibdev, 205 "no enough extended sge space for inline data.\n"); 206 return -EINVAL; 207 } 208 209 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 210 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 211 len = wr->sg_list[0].length; 212 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 213 214 /* When copying data to extended sge space, the left length in page may 215 * not long enough for current user's sge. So the data should be 216 * splited into several parts, one in the first page, and the others in 217 * the subsequent pages. 218 */ 219 while (1) { 220 if (len <= left_len_in_pg) { 221 memcpy(dseg, addr, len); 222 223 idx += len / HNS_ROCE_SGE_SIZE; 224 225 i++; 226 if (i >= wr->num_sge) 227 break; 228 229 left_len_in_pg -= len; 230 len = wr->sg_list[i].length; 231 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 232 dseg += len; 233 } else { 234 memcpy(dseg, addr, left_len_in_pg); 235 236 len -= left_len_in_pg; 237 addr += left_len_in_pg; 238 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 239 dseg = hns_roce_get_extend_sge(qp, 240 idx & (qp->sge.sge_cnt - 1)); 241 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 242 } 243 } 244 245 *sge_idx = idx; 246 247 return 0; 248 } 249 250 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 251 unsigned int *sge_ind, unsigned int cnt) 252 { 253 struct hns_roce_v2_wqe_data_seg *dseg; 254 unsigned int idx = *sge_ind; 255 256 while (cnt > 0) { 257 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 258 if (likely(sge->length)) { 259 set_data_seg_v2(dseg, sge); 260 idx++; 261 cnt--; 262 } 263 sge++; 264 } 265 266 *sge_ind = idx; 267 } 268 269 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 270 { 271 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 272 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 273 274 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 275 ibdev_err(&hr_dev->ib_dev, 276 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 277 len, qp->max_inline_data, mtu); 278 return false; 279 } 280 281 return true; 282 } 283 284 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 285 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 286 unsigned int *sge_idx) 287 { 288 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 289 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 290 struct ib_device *ibdev = &hr_dev->ib_dev; 291 unsigned int curr_idx = *sge_idx; 292 void *dseg = rc_sq_wqe; 293 unsigned int i; 294 int ret; 295 296 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 297 ibdev_err(ibdev, "invalid inline parameters!\n"); 298 return -EINVAL; 299 } 300 301 if (!check_inl_data_len(qp, msg_len)) 302 return -EINVAL; 303 304 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 305 306 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 307 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 308 309 for (i = 0; i < wr->num_sge; i++) { 310 memcpy(dseg, ((void *)wr->sg_list[i].addr), 311 wr->sg_list[i].length); 312 dseg += wr->sg_list[i].length; 313 } 314 } else { 315 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 316 317 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 318 if (ret) 319 return ret; 320 321 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 322 } 323 324 *sge_idx = curr_idx; 325 326 return 0; 327 } 328 329 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 330 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 331 unsigned int *sge_ind, 332 unsigned int valid_num_sge) 333 { 334 struct hns_roce_v2_wqe_data_seg *dseg = 335 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 336 struct hns_roce_qp *qp = to_hr_qp(ibqp); 337 int j = 0; 338 int i; 339 340 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 341 (*sge_ind) & (qp->sge.sge_cnt - 1)); 342 343 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 344 !!(wr->send_flags & IB_SEND_INLINE)); 345 if (wr->send_flags & IB_SEND_INLINE) 346 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 347 348 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 349 for (i = 0; i < wr->num_sge; i++) { 350 if (likely(wr->sg_list[i].length)) { 351 set_data_seg_v2(dseg, wr->sg_list + i); 352 dseg++; 353 } 354 } 355 } else { 356 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 357 if (likely(wr->sg_list[i].length)) { 358 set_data_seg_v2(dseg, wr->sg_list + i); 359 dseg++; 360 j++; 361 } 362 } 363 364 set_extend_sge(qp, wr->sg_list + i, sge_ind, 365 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 366 } 367 368 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 369 370 return 0; 371 } 372 373 static int check_send_valid(struct hns_roce_dev *hr_dev, 374 struct hns_roce_qp *hr_qp) 375 { 376 if (unlikely(hr_qp->state == IB_QPS_RESET || 377 hr_qp->state == IB_QPS_INIT || 378 hr_qp->state == IB_QPS_RTR)) 379 return -EINVAL; 380 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 381 return -EIO; 382 383 return 0; 384 } 385 386 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 387 unsigned int *sge_len) 388 { 389 unsigned int valid_num = 0; 390 unsigned int len = 0; 391 int i; 392 393 for (i = 0; i < wr->num_sge; i++) { 394 if (likely(wr->sg_list[i].length)) { 395 len += wr->sg_list[i].length; 396 valid_num++; 397 } 398 } 399 400 *sge_len = len; 401 return valid_num; 402 } 403 404 static __le32 get_immtdata(const struct ib_send_wr *wr) 405 { 406 switch (wr->opcode) { 407 case IB_WR_SEND_WITH_IMM: 408 case IB_WR_RDMA_WRITE_WITH_IMM: 409 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 410 default: 411 return 0; 412 } 413 } 414 415 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 416 const struct ib_send_wr *wr) 417 { 418 u32 ib_op = wr->opcode; 419 420 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 421 return -EINVAL; 422 423 ud_sq_wqe->immtdata = get_immtdata(wr); 424 425 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 426 427 return 0; 428 } 429 430 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 431 struct hns_roce_ah *ah) 432 { 433 struct ib_device *ib_dev = ah->ibah.device; 434 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 435 436 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 437 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 441 442 ud_sq_wqe->sgid_index = ah->av.gid_index; 443 444 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 445 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 446 447 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 448 return 0; 449 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 451 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 452 453 return 0; 454 } 455 456 static inline int set_ud_wqe(struct hns_roce_qp *qp, 457 const struct ib_send_wr *wr, 458 void *wqe, unsigned int *sge_idx, 459 unsigned int owner_bit) 460 { 461 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 462 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 463 unsigned int curr_idx = *sge_idx; 464 unsigned int valid_num_sge; 465 u32 msg_len = 0; 466 int ret; 467 468 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 469 470 ret = set_ud_opcode(ud_sq_wqe, wr); 471 if (WARN_ON(ret)) 472 return ret; 473 474 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 475 476 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 477 !!(wr->send_flags & IB_SEND_SIGNALED)); 478 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 479 !!(wr->send_flags & IB_SEND_SOLICITED)); 480 481 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 482 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 483 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 484 curr_idx & (qp->sge.sge_cnt - 1)); 485 486 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 487 qp->qkey : ud_wr(wr)->remote_qkey); 488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 489 490 ret = fill_ud_av(ud_sq_wqe, ah); 491 if (ret) 492 return ret; 493 494 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 495 496 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 497 498 /* 499 * The pipeline can sequentially post all valid WQEs into WQ buffer, 500 * including new WQEs waiting for the doorbell to update the PI again. 501 * Therefore, the owner bit of WQE MUST be updated after all fields 502 * and extSGEs have been written into DDR instead of cache. 503 */ 504 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 505 dma_wmb(); 506 507 *sge_idx = curr_idx; 508 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 509 510 return 0; 511 } 512 513 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 514 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 515 const struct ib_send_wr *wr) 516 { 517 u32 ib_op = wr->opcode; 518 int ret = 0; 519 520 rc_sq_wqe->immtdata = get_immtdata(wr); 521 522 switch (ib_op) { 523 case IB_WR_RDMA_READ: 524 case IB_WR_RDMA_WRITE: 525 case IB_WR_RDMA_WRITE_WITH_IMM: 526 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 527 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 528 break; 529 case IB_WR_SEND: 530 case IB_WR_SEND_WITH_IMM: 531 break; 532 case IB_WR_ATOMIC_CMP_AND_SWP: 533 case IB_WR_ATOMIC_FETCH_AND_ADD: 534 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 535 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 536 break; 537 case IB_WR_REG_MR: 538 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 539 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 540 else 541 ret = -EOPNOTSUPP; 542 break; 543 case IB_WR_SEND_WITH_INV: 544 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 545 break; 546 default: 547 ret = -EINVAL; 548 } 549 550 if (unlikely(ret)) 551 return ret; 552 553 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 554 555 return ret; 556 } 557 558 static inline int set_rc_wqe(struct hns_roce_qp *qp, 559 const struct ib_send_wr *wr, 560 void *wqe, unsigned int *sge_idx, 561 unsigned int owner_bit) 562 { 563 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 564 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 565 unsigned int curr_idx = *sge_idx; 566 unsigned int valid_num_sge; 567 u32 msg_len = 0; 568 int ret; 569 570 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 571 572 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 573 574 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 575 if (WARN_ON(ret)) 576 return ret; 577 578 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO, 579 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 580 581 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 582 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 583 584 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 585 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 586 587 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 588 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 589 if (msg_len != ATOMIC_WR_LEN) 590 return -EINVAL; 591 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 592 } else if (wr->opcode != IB_WR_REG_MR) { 593 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 594 &curr_idx, valid_num_sge); 595 if (ret) 596 return ret; 597 } 598 599 /* 600 * The pipeline can sequentially post all valid WQEs into WQ buffer, 601 * including new WQEs waiting for the doorbell to update the PI again. 602 * Therefore, the owner bit of WQE MUST be updated after all fields 603 * and extSGEs have been written into DDR instead of cache. 604 */ 605 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 606 dma_wmb(); 607 608 *sge_idx = curr_idx; 609 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 610 611 return ret; 612 } 613 614 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 615 struct hns_roce_qp *qp) 616 { 617 if (unlikely(qp->state == IB_QPS_ERR)) { 618 flush_cqe(hr_dev, qp); 619 } else { 620 struct hns_roce_v2_db sq_db = {}; 621 622 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 623 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 624 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 625 hr_reg_write(&sq_db, DB_SL, qp->sl); 626 627 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 628 } 629 } 630 631 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 632 struct hns_roce_qp *qp) 633 { 634 if (unlikely(qp->state == IB_QPS_ERR)) { 635 flush_cqe(hr_dev, qp); 636 } else { 637 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 638 *qp->rdb.db_record = 639 qp->rq.head & V2_DB_PRODUCER_IDX_M; 640 } else { 641 struct hns_roce_v2_db rq_db = {}; 642 643 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 644 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 645 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 646 647 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 648 qp->rq.db_reg); 649 } 650 } 651 } 652 653 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 654 u64 __iomem *dest) 655 { 656 #define HNS_ROCE_WRITE_TIMES 8 657 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 658 struct hnae3_handle *handle = priv->handle; 659 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 660 int i; 661 662 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 663 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 664 writeq_relaxed(*(val + i), dest + i); 665 } 666 667 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 668 void *wqe) 669 { 670 #define HNS_ROCE_SL_SHIFT 2 671 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 672 673 /* All kinds of DirectWQE have the same header field layout */ 674 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 675 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 676 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 677 qp->sl >> HNS_ROCE_SL_SHIFT); 678 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 679 680 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 681 } 682 683 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 684 const struct ib_send_wr *wr, 685 const struct ib_send_wr **bad_wr) 686 { 687 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 688 struct ib_device *ibdev = &hr_dev->ib_dev; 689 struct hns_roce_qp *qp = to_hr_qp(ibqp); 690 unsigned long flags = 0; 691 unsigned int owner_bit; 692 unsigned int sge_idx; 693 unsigned int wqe_idx; 694 void *wqe = NULL; 695 u32 nreq; 696 int ret; 697 698 spin_lock_irqsave(&qp->sq.lock, flags); 699 700 ret = check_send_valid(hr_dev, qp); 701 if (unlikely(ret)) { 702 *bad_wr = wr; 703 nreq = 0; 704 goto out; 705 } 706 707 sge_idx = qp->next_sge; 708 709 for (nreq = 0; wr; ++nreq, wr = wr->next) { 710 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 711 ret = -ENOMEM; 712 *bad_wr = wr; 713 goto out; 714 } 715 716 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 717 718 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 719 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 720 wr->num_sge, qp->sq.max_gs); 721 ret = -EINVAL; 722 *bad_wr = wr; 723 goto out; 724 } 725 726 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 727 qp->sq.wrid[wqe_idx] = wr->wr_id; 728 owner_bit = 729 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 730 731 /* Corresponding to the QP type, wqe process separately */ 732 if (ibqp->qp_type == IB_QPT_RC) 733 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 734 else 735 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 736 737 if (unlikely(ret)) { 738 *bad_wr = wr; 739 goto out; 740 } 741 } 742 743 out: 744 if (likely(nreq)) { 745 qp->sq.head += nreq; 746 qp->next_sge = sge_idx; 747 748 if (nreq == 1 && !ret && 749 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 750 write_dwqe(hr_dev, qp, wqe); 751 else 752 update_sq_db(hr_dev, qp); 753 } 754 755 spin_unlock_irqrestore(&qp->sq.lock, flags); 756 757 return ret; 758 } 759 760 static int check_recv_valid(struct hns_roce_dev *hr_dev, 761 struct hns_roce_qp *hr_qp) 762 { 763 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 764 return -EIO; 765 766 if (hr_qp->state == IB_QPS_RESET) 767 return -EINVAL; 768 769 return 0; 770 } 771 772 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 773 u32 max_sge, bool rsv) 774 { 775 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 776 u32 i, cnt; 777 778 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 779 /* Skip zero-length sge */ 780 if (!wr->sg_list[i].length) 781 continue; 782 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 783 cnt++; 784 } 785 786 /* Fill a reserved sge to make hw stop reading remaining segments */ 787 if (rsv) { 788 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 789 dseg[cnt].addr = 0; 790 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 791 } else { 792 /* Clear remaining segments to make ROCEE ignore sges */ 793 if (cnt < max_sge) 794 memset(dseg + cnt, 0, 795 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 796 } 797 } 798 799 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 800 u32 wqe_idx, u32 max_sge) 801 { 802 void *wqe = NULL; 803 804 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 805 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 806 } 807 808 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 809 const struct ib_recv_wr *wr, 810 const struct ib_recv_wr **bad_wr) 811 { 812 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 813 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 814 struct ib_device *ibdev = &hr_dev->ib_dev; 815 u32 wqe_idx, nreq, max_sge; 816 unsigned long flags; 817 int ret; 818 819 spin_lock_irqsave(&hr_qp->rq.lock, flags); 820 821 ret = check_recv_valid(hr_dev, hr_qp); 822 if (unlikely(ret)) { 823 *bad_wr = wr; 824 nreq = 0; 825 goto out; 826 } 827 828 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 829 for (nreq = 0; wr; ++nreq, wr = wr->next) { 830 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 831 hr_qp->ibqp.recv_cq))) { 832 ret = -ENOMEM; 833 *bad_wr = wr; 834 goto out; 835 } 836 837 if (unlikely(wr->num_sge > max_sge)) { 838 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 839 wr->num_sge, max_sge); 840 ret = -EINVAL; 841 *bad_wr = wr; 842 goto out; 843 } 844 845 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 846 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 847 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 848 } 849 850 out: 851 if (likely(nreq)) { 852 hr_qp->rq.head += nreq; 853 854 update_rq_db(hr_dev, hr_qp); 855 } 856 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 857 858 return ret; 859 } 860 861 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 862 { 863 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 864 } 865 866 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 867 { 868 return hns_roce_buf_offset(idx_que->mtr.kmem, 869 n << idx_que->entry_shift); 870 } 871 872 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 873 { 874 /* always called with interrupts disabled. */ 875 spin_lock(&srq->lock); 876 877 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 878 srq->idx_que.tail++; 879 880 spin_unlock(&srq->lock); 881 } 882 883 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 884 { 885 struct hns_roce_idx_que *idx_que = &srq->idx_que; 886 887 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 888 } 889 890 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 891 const struct ib_recv_wr *wr) 892 { 893 struct ib_device *ib_dev = srq->ibsrq.device; 894 895 if (unlikely(wr->num_sge > max_sge)) { 896 ibdev_err(ib_dev, 897 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 898 wr->num_sge, max_sge); 899 return -EINVAL; 900 } 901 902 if (unlikely(hns_roce_srqwq_overflow(srq))) { 903 ibdev_err(ib_dev, 904 "failed to check srqwq status, srqwq is full.\n"); 905 return -ENOMEM; 906 } 907 908 return 0; 909 } 910 911 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 912 { 913 struct hns_roce_idx_que *idx_que = &srq->idx_que; 914 u32 pos; 915 916 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 917 if (unlikely(pos == srq->wqe_cnt)) 918 return -ENOSPC; 919 920 bitmap_set(idx_que->bitmap, pos, 1); 921 *wqe_idx = pos; 922 return 0; 923 } 924 925 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 926 { 927 struct hns_roce_idx_que *idx_que = &srq->idx_que; 928 unsigned int head; 929 __le32 *buf; 930 931 head = idx_que->head & (srq->wqe_cnt - 1); 932 933 buf = get_idx_buf(idx_que, head); 934 *buf = cpu_to_le32(wqe_idx); 935 936 idx_que->head++; 937 } 938 939 static void update_srq_db(struct hns_roce_srq *srq) 940 { 941 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 942 struct hns_roce_v2_db db; 943 944 hr_reg_write(&db, DB_TAG, srq->srqn); 945 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 946 hr_reg_write(&db, DB_PI, srq->idx_que.head); 947 948 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 949 } 950 951 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 952 const struct ib_recv_wr *wr, 953 const struct ib_recv_wr **bad_wr) 954 { 955 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 956 unsigned long flags; 957 int ret = 0; 958 u32 max_sge; 959 u32 wqe_idx; 960 void *wqe; 961 u32 nreq; 962 963 spin_lock_irqsave(&srq->lock, flags); 964 965 max_sge = srq->max_gs - srq->rsv_sge; 966 for (nreq = 0; wr; ++nreq, wr = wr->next) { 967 ret = check_post_srq_valid(srq, max_sge, wr); 968 if (ret) { 969 *bad_wr = wr; 970 break; 971 } 972 973 ret = get_srq_wqe_idx(srq, &wqe_idx); 974 if (unlikely(ret)) { 975 *bad_wr = wr; 976 break; 977 } 978 979 wqe = get_srq_wqe_buf(srq, wqe_idx); 980 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 981 fill_wqe_idx(srq, wqe_idx); 982 srq->wrid[wqe_idx] = wr->wr_id; 983 } 984 985 if (likely(nreq)) { 986 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 987 *srq->rdb.db_record = srq->idx_que.head & 988 V2_DB_PRODUCER_IDX_M; 989 else 990 update_srq_db(srq); 991 } 992 993 spin_unlock_irqrestore(&srq->lock, flags); 994 995 return ret; 996 } 997 998 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 999 unsigned long instance_stage, 1000 unsigned long reset_stage) 1001 { 1002 /* When hardware reset has been completed once or more, we should stop 1003 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1004 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1005 * stage of soft reset process, we should exit with error, and then 1006 * HNAE3_INIT_CLIENT related process can rollback the operation like 1007 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1008 * process will exit with error to notify NIC driver to reschedule soft 1009 * reset process once again. 1010 */ 1011 hr_dev->is_reset = true; 1012 hr_dev->dis_db = true; 1013 1014 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1015 instance_stage == HNS_ROCE_STATE_INIT) 1016 return CMD_RST_PRC_EBUSY; 1017 1018 return CMD_RST_PRC_SUCCESS; 1019 } 1020 1021 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1022 unsigned long instance_stage, 1023 unsigned long reset_stage) 1024 { 1025 #define HW_RESET_TIMEOUT_US 1000000 1026 #define HW_RESET_SLEEP_US 1000 1027 1028 struct hns_roce_v2_priv *priv = hr_dev->priv; 1029 struct hnae3_handle *handle = priv->handle; 1030 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1031 unsigned long val; 1032 int ret; 1033 1034 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1035 * doorbell to hardware. If now in .init_instance() function, we should 1036 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1037 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1038 * related process can rollback the operation like notifing hardware to 1039 * free resources, HNAE3_INIT_CLIENT related process will exit with 1040 * error to notify NIC driver to reschedule soft reset process once 1041 * again. 1042 */ 1043 hr_dev->dis_db = true; 1044 1045 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1046 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1047 HW_RESET_TIMEOUT_US, false, handle); 1048 if (!ret) 1049 hr_dev->is_reset = true; 1050 1051 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1052 instance_stage == HNS_ROCE_STATE_INIT) 1053 return CMD_RST_PRC_EBUSY; 1054 1055 return CMD_RST_PRC_SUCCESS; 1056 } 1057 1058 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1059 { 1060 struct hns_roce_v2_priv *priv = hr_dev->priv; 1061 struct hnae3_handle *handle = priv->handle; 1062 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1063 1064 /* When software reset is detected at .init_instance() function, we 1065 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1066 * with error. 1067 */ 1068 hr_dev->dis_db = true; 1069 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1070 hr_dev->is_reset = true; 1071 1072 return CMD_RST_PRC_EBUSY; 1073 } 1074 1075 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1076 struct hnae3_handle *handle) 1077 { 1078 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1079 unsigned long instance_stage; /* the current instance stage */ 1080 unsigned long reset_stage; /* the current reset stage */ 1081 unsigned long reset_cnt; 1082 bool sw_resetting; 1083 bool hw_resetting; 1084 1085 /* Get information about reset from NIC driver or RoCE driver itself, 1086 * the meaning of the following variables from NIC driver are described 1087 * as below: 1088 * reset_cnt -- The count value of completed hardware reset. 1089 * hw_resetting -- Whether hardware device is resetting now. 1090 * sw_resetting -- Whether NIC's software reset process is running now. 1091 */ 1092 instance_stage = handle->rinfo.instance_state; 1093 reset_stage = handle->rinfo.reset_state; 1094 reset_cnt = ops->ae_dev_reset_cnt(handle); 1095 if (reset_cnt != hr_dev->reset_cnt) 1096 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1097 reset_stage); 1098 1099 hw_resetting = ops->get_cmdq_stat(handle); 1100 if (hw_resetting) 1101 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1102 reset_stage); 1103 1104 sw_resetting = ops->ae_dev_resetting(handle); 1105 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1106 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1107 1108 return CMD_RST_PRC_OTHERS; 1109 } 1110 1111 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1112 { 1113 struct hns_roce_v2_priv *priv = hr_dev->priv; 1114 struct hnae3_handle *handle = priv->handle; 1115 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1116 1117 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1118 return true; 1119 1120 if (ops->get_hw_reset_stat(handle)) 1121 return true; 1122 1123 if (ops->ae_dev_resetting(handle)) 1124 return true; 1125 1126 return false; 1127 } 1128 1129 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1130 { 1131 struct hns_roce_v2_priv *priv = hr_dev->priv; 1132 u32 status; 1133 1134 if (hr_dev->is_reset) 1135 status = CMD_RST_PRC_SUCCESS; 1136 else 1137 status = check_aedev_reset_status(hr_dev, priv->handle); 1138 1139 *busy = (status == CMD_RST_PRC_EBUSY); 1140 1141 return status == CMD_RST_PRC_OTHERS; 1142 } 1143 1144 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1145 struct hns_roce_v2_cmq_ring *ring) 1146 { 1147 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1148 1149 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1150 &ring->desc_dma_addr, GFP_KERNEL); 1151 if (!ring->desc) 1152 return -ENOMEM; 1153 1154 return 0; 1155 } 1156 1157 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1158 struct hns_roce_v2_cmq_ring *ring) 1159 { 1160 dma_free_coherent(hr_dev->dev, 1161 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1162 ring->desc, ring->desc_dma_addr); 1163 1164 ring->desc_dma_addr = 0; 1165 } 1166 1167 static int init_csq(struct hns_roce_dev *hr_dev, 1168 struct hns_roce_v2_cmq_ring *csq) 1169 { 1170 dma_addr_t dma; 1171 int ret; 1172 1173 csq->desc_num = CMD_CSQ_DESC_NUM; 1174 spin_lock_init(&csq->lock); 1175 csq->flag = TYPE_CSQ; 1176 csq->head = 0; 1177 1178 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1179 if (ret) 1180 return ret; 1181 1182 dma = csq->desc_dma_addr; 1183 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1184 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1185 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1186 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1187 1188 /* Make sure to write CI first and then PI */ 1189 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1190 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1191 1192 return 0; 1193 } 1194 1195 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1196 { 1197 struct hns_roce_v2_priv *priv = hr_dev->priv; 1198 int ret; 1199 1200 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1201 1202 ret = init_csq(hr_dev, &priv->cmq.csq); 1203 if (ret) 1204 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1205 1206 return ret; 1207 } 1208 1209 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1210 { 1211 struct hns_roce_v2_priv *priv = hr_dev->priv; 1212 1213 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1214 } 1215 1216 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1217 enum hns_roce_opcode_type opcode, 1218 bool is_read) 1219 { 1220 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1221 desc->opcode = cpu_to_le16(opcode); 1222 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1223 if (is_read) 1224 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1225 else 1226 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1227 } 1228 1229 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1230 { 1231 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1232 struct hns_roce_v2_priv *priv = hr_dev->priv; 1233 1234 return tail == priv->cmq.csq.head; 1235 } 1236 1237 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1238 { 1239 struct hns_roce_v2_priv *priv = hr_dev->priv; 1240 struct hnae3_handle *handle = priv->handle; 1241 1242 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1243 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1244 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1245 } 1246 1247 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1248 { 1249 struct hns_roce_cmd_errcode errcode_table[] = { 1250 {CMD_EXEC_SUCCESS, 0}, 1251 {CMD_NO_AUTH, -EPERM}, 1252 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1253 {CMD_CRQ_FULL, -EXFULL}, 1254 {CMD_NEXT_ERR, -ENOSR}, 1255 {CMD_NOT_EXEC, -ENOTBLK}, 1256 {CMD_PARA_ERR, -EINVAL}, 1257 {CMD_RESULT_ERR, -ERANGE}, 1258 {CMD_TIMEOUT, -ETIME}, 1259 {CMD_HILINK_ERR, -ENOLINK}, 1260 {CMD_INFO_ILLEGAL, -ENXIO}, 1261 {CMD_INVALID, -EBADR}, 1262 }; 1263 u16 i; 1264 1265 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1266 if (desc_ret == errcode_table[i].return_status) 1267 return errcode_table[i].errno; 1268 return -EIO; 1269 } 1270 1271 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 1272 { 1273 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = { 1274 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT}, 1275 }; 1276 int i; 1277 1278 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++) 1279 if (cmdq_tx_timeout[i].opcode == opcode) 1280 return cmdq_tx_timeout[i].tx_timeout; 1281 1282 return tx_timeout; 1283 } 1284 1285 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u16 opcode) 1286 { 1287 struct hns_roce_v2_priv *priv = hr_dev->priv; 1288 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout); 1289 u32 timeout = 0; 1290 1291 do { 1292 if (hns_roce_cmq_csq_done(hr_dev)) 1293 break; 1294 udelay(1); 1295 } while (++timeout < tx_timeout); 1296 } 1297 1298 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1299 struct hns_roce_cmq_desc *desc, int num) 1300 { 1301 struct hns_roce_v2_priv *priv = hr_dev->priv; 1302 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1303 u16 desc_ret; 1304 u32 tail; 1305 int ret; 1306 int i; 1307 1308 spin_lock_bh(&csq->lock); 1309 1310 tail = csq->head; 1311 1312 for (i = 0; i < num; i++) { 1313 csq->desc[csq->head++] = desc[i]; 1314 if (csq->head == csq->desc_num) 1315 csq->head = 0; 1316 } 1317 1318 /* Write to hardware */ 1319 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1320 1321 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1322 1323 hns_roce_wait_csq_done(hr_dev, le16_to_cpu(desc->opcode)); 1324 if (hns_roce_cmq_csq_done(hr_dev)) { 1325 ret = 0; 1326 for (i = 0; i < num; i++) { 1327 /* check the result of hardware write back */ 1328 desc[i] = csq->desc[tail++]; 1329 if (tail == csq->desc_num) 1330 tail = 0; 1331 1332 desc_ret = le16_to_cpu(desc[i].retval); 1333 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1334 continue; 1335 1336 dev_err_ratelimited(hr_dev->dev, 1337 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1338 desc->opcode, desc_ret); 1339 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1340 } 1341 } else { 1342 /* FW/HW reset or incorrect number of desc */ 1343 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1344 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1345 csq->head, tail); 1346 csq->head = tail; 1347 1348 update_cmdq_status(hr_dev); 1349 1350 ret = -EAGAIN; 1351 } 1352 1353 spin_unlock_bh(&csq->lock); 1354 1355 if (ret) 1356 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1357 1358 return ret; 1359 } 1360 1361 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1362 struct hns_roce_cmq_desc *desc, int num) 1363 { 1364 bool busy; 1365 int ret; 1366 1367 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1368 return -EIO; 1369 1370 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1371 return busy ? -EBUSY : 0; 1372 1373 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1374 if (ret) { 1375 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1376 return busy ? -EBUSY : 0; 1377 } 1378 1379 return ret; 1380 } 1381 1382 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1383 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1384 { 1385 struct hns_roce_cmd_mailbox *mbox; 1386 int ret; 1387 1388 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1389 if (IS_ERR(mbox)) 1390 return PTR_ERR(mbox); 1391 1392 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1393 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1394 return ret; 1395 } 1396 1397 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1398 { 1399 struct hns_roce_query_version *resp; 1400 struct hns_roce_cmq_desc desc; 1401 int ret; 1402 1403 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1404 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1405 if (ret) 1406 return ret; 1407 1408 resp = (struct hns_roce_query_version *)desc.data; 1409 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1410 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1411 1412 return 0; 1413 } 1414 1415 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1416 struct hnae3_handle *handle) 1417 { 1418 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1419 unsigned long end; 1420 1421 hr_dev->dis_db = true; 1422 1423 dev_warn(hr_dev->dev, 1424 "func clear is pending, device in resetting state.\n"); 1425 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1426 while (end) { 1427 if (!ops->get_hw_reset_stat(handle)) { 1428 hr_dev->is_reset = true; 1429 dev_info(hr_dev->dev, 1430 "func clear success after reset.\n"); 1431 return; 1432 } 1433 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1434 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1435 } 1436 1437 dev_warn(hr_dev->dev, "func clear failed.\n"); 1438 } 1439 1440 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1441 struct hnae3_handle *handle) 1442 { 1443 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1444 unsigned long end; 1445 1446 hr_dev->dis_db = true; 1447 1448 dev_warn(hr_dev->dev, 1449 "func clear is pending, device in resetting state.\n"); 1450 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1451 while (end) { 1452 if (ops->ae_dev_reset_cnt(handle) != 1453 hr_dev->reset_cnt) { 1454 hr_dev->is_reset = true; 1455 dev_info(hr_dev->dev, 1456 "func clear success after sw reset\n"); 1457 return; 1458 } 1459 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1460 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1461 } 1462 1463 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1464 } 1465 1466 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1467 int flag) 1468 { 1469 struct hns_roce_v2_priv *priv = hr_dev->priv; 1470 struct hnae3_handle *handle = priv->handle; 1471 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1472 1473 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1474 hr_dev->dis_db = true; 1475 hr_dev->is_reset = true; 1476 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1477 return; 1478 } 1479 1480 if (ops->get_hw_reset_stat(handle)) { 1481 func_clr_hw_resetting_state(hr_dev, handle); 1482 return; 1483 } 1484 1485 if (ops->ae_dev_resetting(handle) && 1486 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1487 func_clr_sw_resetting_state(hr_dev, handle); 1488 return; 1489 } 1490 1491 if (retval && !flag) 1492 dev_warn(hr_dev->dev, 1493 "func clear read failed, ret = %d.\n", retval); 1494 1495 dev_warn(hr_dev->dev, "func clear failed.\n"); 1496 } 1497 1498 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1499 { 1500 bool fclr_write_fail_flag = false; 1501 struct hns_roce_func_clear *resp; 1502 struct hns_roce_cmq_desc desc; 1503 unsigned long end; 1504 int ret = 0; 1505 1506 if (check_device_is_in_reset(hr_dev)) 1507 goto out; 1508 1509 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1510 resp = (struct hns_roce_func_clear *)desc.data; 1511 resp->rst_funcid_en = cpu_to_le32(vf_id); 1512 1513 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1514 if (ret) { 1515 fclr_write_fail_flag = true; 1516 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1517 ret); 1518 goto out; 1519 } 1520 1521 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1522 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1523 while (end) { 1524 if (check_device_is_in_reset(hr_dev)) 1525 goto out; 1526 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1527 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1528 1529 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1530 true); 1531 1532 resp->rst_funcid_en = cpu_to_le32(vf_id); 1533 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1534 if (ret) 1535 continue; 1536 1537 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1538 if (vf_id == 0) 1539 hr_dev->is_reset = true; 1540 return; 1541 } 1542 } 1543 1544 out: 1545 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1546 } 1547 1548 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1549 { 1550 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1551 struct hns_roce_cmq_desc desc[2]; 1552 struct hns_roce_cmq_req *req_a; 1553 1554 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1555 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1556 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1557 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1558 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1559 1560 return hns_roce_cmq_send(hr_dev, desc, 2); 1561 } 1562 1563 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1564 { 1565 int ret; 1566 int i; 1567 1568 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1569 return; 1570 1571 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1572 __hns_roce_function_clear(hr_dev, i); 1573 1574 if (i == 0) 1575 continue; 1576 1577 ret = hns_roce_free_vf_resource(hr_dev, i); 1578 if (ret) 1579 ibdev_err(&hr_dev->ib_dev, 1580 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1581 i, ret); 1582 } 1583 } 1584 1585 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1586 { 1587 struct hns_roce_cmq_desc desc; 1588 int ret; 1589 1590 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1591 false); 1592 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1593 if (ret) 1594 ibdev_err(&hr_dev->ib_dev, 1595 "failed to clear extended doorbell info, ret = %d.\n", 1596 ret); 1597 1598 return ret; 1599 } 1600 1601 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1602 { 1603 struct hns_roce_query_fw_info *resp; 1604 struct hns_roce_cmq_desc desc; 1605 int ret; 1606 1607 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1608 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1609 if (ret) 1610 return ret; 1611 1612 resp = (struct hns_roce_query_fw_info *)desc.data; 1613 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1614 1615 return 0; 1616 } 1617 1618 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1619 { 1620 struct hns_roce_cmq_desc desc; 1621 int ret; 1622 1623 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1624 hr_dev->func_num = 1; 1625 return 0; 1626 } 1627 1628 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1629 true); 1630 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1631 if (ret) { 1632 hr_dev->func_num = 1; 1633 return ret; 1634 } 1635 1636 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1637 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1638 1639 return 0; 1640 } 1641 1642 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1643 u64 *stats, u32 port, int *num_counters) 1644 { 1645 #define CNT_PER_DESC 3 1646 struct hns_roce_cmq_desc *desc; 1647 int bd_idx, cnt_idx; 1648 __le64 *cnt_data; 1649 int desc_num; 1650 int ret; 1651 int i; 1652 1653 if (port > hr_dev->caps.num_ports) 1654 return -EINVAL; 1655 1656 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1657 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1658 if (!desc) 1659 return -ENOMEM; 1660 1661 for (i = 0; i < desc_num; i++) { 1662 hns_roce_cmq_setup_basic_desc(&desc[i], 1663 HNS_ROCE_OPC_QUERY_COUNTER, true); 1664 if (i != desc_num - 1) 1665 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1666 } 1667 1668 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1669 if (ret) { 1670 ibdev_err(&hr_dev->ib_dev, 1671 "failed to get counter, ret = %d.\n", ret); 1672 goto err_out; 1673 } 1674 1675 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1676 bd_idx = i / CNT_PER_DESC; 1677 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC && 1678 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT))) 1679 break; 1680 1681 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1682 cnt_idx = i % CNT_PER_DESC; 1683 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1684 } 1685 *num_counters = i; 1686 1687 err_out: 1688 kfree(desc); 1689 return ret; 1690 } 1691 1692 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1693 { 1694 struct hns_roce_cmq_desc desc; 1695 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1696 u32 clock_cycles_of_1us; 1697 1698 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1699 false); 1700 1701 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1702 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1703 else 1704 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1705 1706 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1707 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1708 1709 return hns_roce_cmq_send(hr_dev, &desc, 1); 1710 } 1711 1712 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1713 { 1714 struct hns_roce_cmq_desc desc[2]; 1715 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1716 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1717 struct hns_roce_caps *caps = &hr_dev->caps; 1718 enum hns_roce_opcode_type opcode; 1719 u32 func_num; 1720 int ret; 1721 1722 if (is_vf) { 1723 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1724 func_num = 1; 1725 } else { 1726 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1727 func_num = hr_dev->func_num; 1728 } 1729 1730 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1731 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1732 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1733 1734 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1735 if (ret) 1736 return ret; 1737 1738 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1739 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1740 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1741 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1742 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1743 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1744 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1745 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1746 1747 if (is_vf) { 1748 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1749 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1750 func_num; 1751 } else { 1752 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1753 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1754 func_num; 1755 } 1756 1757 return 0; 1758 } 1759 1760 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1761 { 1762 struct hns_roce_cmq_desc desc; 1763 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1764 struct hns_roce_caps *caps = &hr_dev->caps; 1765 int ret; 1766 1767 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1768 true); 1769 1770 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1771 if (ret) 1772 return ret; 1773 1774 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1775 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1776 1777 return 0; 1778 } 1779 1780 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1781 { 1782 struct device *dev = hr_dev->dev; 1783 int ret; 1784 1785 ret = load_func_res_caps(hr_dev, false); 1786 if (ret) { 1787 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1788 return ret; 1789 } 1790 1791 ret = load_pf_timer_res_caps(hr_dev); 1792 if (ret) 1793 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1794 ret); 1795 1796 return ret; 1797 } 1798 1799 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1800 { 1801 struct device *dev = hr_dev->dev; 1802 int ret; 1803 1804 ret = load_func_res_caps(hr_dev, true); 1805 if (ret) 1806 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1807 1808 return ret; 1809 } 1810 1811 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1812 u32 vf_id) 1813 { 1814 struct hns_roce_vf_switch *swt; 1815 struct hns_roce_cmq_desc desc; 1816 int ret; 1817 1818 swt = (struct hns_roce_vf_switch *)desc.data; 1819 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1820 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1821 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1822 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1823 if (ret) 1824 return ret; 1825 1826 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1827 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1828 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1829 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1830 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1831 1832 return hns_roce_cmq_send(hr_dev, &desc, 1); 1833 } 1834 1835 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1836 { 1837 u32 vf_id; 1838 int ret; 1839 1840 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1841 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1842 if (ret) 1843 return ret; 1844 } 1845 return 0; 1846 } 1847 1848 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1849 { 1850 struct hns_roce_cmq_desc desc[2]; 1851 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1852 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1853 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1854 struct hns_roce_caps *caps = &hr_dev->caps; 1855 1856 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1857 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1858 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1859 1860 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1861 1862 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1863 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1864 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1865 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1866 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1867 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1868 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1869 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1870 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1871 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1872 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1873 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1874 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1875 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1876 1877 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1878 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1879 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1880 vf_id * caps->gmv_bt_num); 1881 } else { 1882 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1883 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1884 vf_id * caps->sgid_bt_num); 1885 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1886 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1887 vf_id * caps->smac_bt_num); 1888 } 1889 1890 return hns_roce_cmq_send(hr_dev, desc, 2); 1891 } 1892 1893 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1894 { 1895 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1896 u32 vf_id; 1897 int ret; 1898 1899 for (vf_id = 0; vf_id < func_num; vf_id++) { 1900 ret = config_vf_hem_resource(hr_dev, vf_id); 1901 if (ret) { 1902 dev_err(hr_dev->dev, 1903 "failed to config vf-%u hem res, ret = %d.\n", 1904 vf_id, ret); 1905 return ret; 1906 } 1907 } 1908 1909 return 0; 1910 } 1911 1912 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1913 { 1914 struct hns_roce_cmq_desc desc; 1915 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1916 struct hns_roce_caps *caps = &hr_dev->caps; 1917 1918 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1919 1920 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1921 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1922 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1923 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1924 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1925 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1926 1927 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1928 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1929 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1930 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1931 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1932 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1933 1934 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1935 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1936 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1937 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1938 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1939 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1940 1941 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1942 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1943 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1944 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1945 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1946 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1947 1948 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1949 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1950 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1951 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1952 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1953 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1954 1955 return hns_roce_cmq_send(hr_dev, &desc, 1); 1956 } 1957 1958 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1959 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1960 { 1961 u64 obj_per_chunk; 1962 u64 bt_chunk_size = PAGE_SIZE; 1963 u64 buf_chunk_size = PAGE_SIZE; 1964 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1965 1966 *buf_page_size = 0; 1967 *bt_page_size = 0; 1968 1969 switch (hop_num) { 1970 case 3: 1971 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1972 (bt_chunk_size / BA_BYTE_LEN) * 1973 (bt_chunk_size / BA_BYTE_LEN) * 1974 obj_per_chunk_default; 1975 break; 1976 case 2: 1977 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1978 (bt_chunk_size / BA_BYTE_LEN) * 1979 obj_per_chunk_default; 1980 break; 1981 case 1: 1982 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1983 obj_per_chunk_default; 1984 break; 1985 case HNS_ROCE_HOP_NUM_0: 1986 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1987 break; 1988 default: 1989 pr_err("table %u not support hop_num = %u!\n", hem_type, 1990 hop_num); 1991 return; 1992 } 1993 1994 if (hem_type >= HEM_TYPE_MTT) 1995 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1996 else 1997 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1998 } 1999 2000 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2001 { 2002 struct hns_roce_caps *caps = &hr_dev->caps; 2003 2004 /* EQ */ 2005 caps->eqe_ba_pg_sz = 0; 2006 caps->eqe_buf_pg_sz = 0; 2007 2008 /* Link Table */ 2009 caps->llm_buf_pg_sz = 0; 2010 2011 /* MR */ 2012 caps->mpt_ba_pg_sz = 0; 2013 caps->mpt_buf_pg_sz = 0; 2014 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2015 caps->pbl_buf_pg_sz = 0; 2016 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2017 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2018 HEM_TYPE_MTPT); 2019 2020 /* QP */ 2021 caps->qpc_ba_pg_sz = 0; 2022 caps->qpc_buf_pg_sz = 0; 2023 caps->qpc_timer_ba_pg_sz = 0; 2024 caps->qpc_timer_buf_pg_sz = 0; 2025 caps->sccc_ba_pg_sz = 0; 2026 caps->sccc_buf_pg_sz = 0; 2027 caps->mtt_ba_pg_sz = 0; 2028 caps->mtt_buf_pg_sz = 0; 2029 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2030 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2031 HEM_TYPE_QPC); 2032 2033 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2034 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2035 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2036 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2037 2038 /* CQ */ 2039 caps->cqc_ba_pg_sz = 0; 2040 caps->cqc_buf_pg_sz = 0; 2041 caps->cqc_timer_ba_pg_sz = 0; 2042 caps->cqc_timer_buf_pg_sz = 0; 2043 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2044 caps->cqe_buf_pg_sz = 0; 2045 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2046 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2047 HEM_TYPE_CQC); 2048 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2049 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2050 2051 /* SRQ */ 2052 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2053 caps->srqc_ba_pg_sz = 0; 2054 caps->srqc_buf_pg_sz = 0; 2055 caps->srqwqe_ba_pg_sz = 0; 2056 caps->srqwqe_buf_pg_sz = 0; 2057 caps->idx_ba_pg_sz = 0; 2058 caps->idx_buf_pg_sz = 0; 2059 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2060 caps->srqc_hop_num, caps->srqc_bt_num, 2061 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2062 HEM_TYPE_SRQC); 2063 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2064 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2065 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2066 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2067 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2068 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2069 } 2070 2071 /* GMV */ 2072 caps->gmv_ba_pg_sz = 0; 2073 caps->gmv_buf_pg_sz = 0; 2074 } 2075 2076 /* Apply all loaded caps before setting to hardware */ 2077 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2078 { 2079 #define MAX_GID_TBL_LEN 256 2080 struct hns_roce_caps *caps = &hr_dev->caps; 2081 struct hns_roce_v2_priv *priv = hr_dev->priv; 2082 2083 /* The following configurations don't need to be got from firmware. */ 2084 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2085 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2086 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2087 2088 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2089 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2090 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2091 2092 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2093 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2094 2095 if (!caps->num_comp_vectors) 2096 caps->num_comp_vectors = 2097 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2098 (u32)priv->handle->rinfo.num_vectors - 2099 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2100 2101 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2102 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2103 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2104 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2105 2106 /* The following configurations will be overwritten */ 2107 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2108 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2109 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2110 2111 /* The following configurations are not got from firmware */ 2112 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2113 2114 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2115 2116 /* It's meaningless to support excessively large gid_table_len, 2117 * as the type of sgid_index in kernel struct ib_global_route 2118 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2119 */ 2120 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2121 caps->gmv_bt_num * 2122 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2123 2124 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2125 caps->gmv_entry_sz); 2126 } else { 2127 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2128 2129 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2130 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2131 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2132 caps->gid_table_len[0] /= func_num; 2133 } 2134 2135 if (hr_dev->is_vf) { 2136 caps->default_aeq_arm_st = 0x3; 2137 caps->default_ceq_arm_st = 0x3; 2138 caps->default_ceq_max_cnt = 0x1; 2139 caps->default_ceq_period = 0x10; 2140 caps->default_aeq_max_cnt = 0x1; 2141 caps->default_aeq_period = 0x10; 2142 } 2143 2144 set_hem_page_size(hr_dev); 2145 } 2146 2147 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2148 { 2149 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2150 struct hns_roce_caps *caps = &hr_dev->caps; 2151 struct hns_roce_query_pf_caps_a *resp_a; 2152 struct hns_roce_query_pf_caps_b *resp_b; 2153 struct hns_roce_query_pf_caps_c *resp_c; 2154 struct hns_roce_query_pf_caps_d *resp_d; 2155 struct hns_roce_query_pf_caps_e *resp_e; 2156 enum hns_roce_opcode_type cmd; 2157 int ctx_hop_num; 2158 int pbl_hop_num; 2159 int ret; 2160 int i; 2161 2162 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2163 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2164 2165 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2166 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2167 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2168 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2169 else 2170 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2171 } 2172 2173 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2174 if (ret) 2175 return ret; 2176 2177 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2178 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2179 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2180 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2181 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2182 2183 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2184 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2185 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2186 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2187 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2188 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2189 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2190 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2191 caps->num_other_vectors = resp_a->num_other_vectors; 2192 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2193 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2194 2195 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2196 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2197 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2198 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2199 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2200 caps->idx_entry_sz = resp_b->idx_entry_sz; 2201 caps->sccc_sz = resp_b->sccc_sz; 2202 caps->max_mtu = resp_b->max_mtu; 2203 caps->min_cqes = resp_b->min_cqes; 2204 caps->min_wqes = resp_b->min_wqes; 2205 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2206 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2207 caps->phy_num_uars = resp_b->phy_num_uars; 2208 ctx_hop_num = resp_b->ctx_hop_num; 2209 pbl_hop_num = resp_b->pbl_hop_num; 2210 2211 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2212 2213 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2214 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2215 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2216 2217 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2218 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2219 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2220 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2221 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2222 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2223 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2224 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2225 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2226 2227 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2228 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2229 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2230 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2231 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2232 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2233 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2234 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2235 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2236 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2237 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2238 2239 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2240 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2241 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2242 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2243 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2244 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2245 2246 caps->qpc_hop_num = ctx_hop_num; 2247 caps->sccc_hop_num = ctx_hop_num; 2248 caps->srqc_hop_num = ctx_hop_num; 2249 caps->cqc_hop_num = ctx_hop_num; 2250 caps->mpt_hop_num = ctx_hop_num; 2251 caps->mtt_hop_num = pbl_hop_num; 2252 caps->cqe_hop_num = pbl_hop_num; 2253 caps->srqwqe_hop_num = pbl_hop_num; 2254 caps->idx_hop_num = pbl_hop_num; 2255 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2256 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2257 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2258 2259 if (!(caps->page_size_cap & PAGE_SIZE)) 2260 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2261 2262 if (!hr_dev->is_vf) { 2263 caps->cqe_sz = resp_a->cqe_sz; 2264 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2265 caps->default_aeq_arm_st = 2266 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2267 caps->default_ceq_arm_st = 2268 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2269 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2270 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2271 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2272 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2273 } 2274 2275 return 0; 2276 } 2277 2278 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2279 { 2280 struct hns_roce_cmq_desc desc; 2281 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2282 2283 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2284 false); 2285 2286 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2287 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2288 2289 return hns_roce_cmq_send(hr_dev, &desc, 1); 2290 } 2291 2292 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2293 { 2294 struct hns_roce_caps *caps = &hr_dev->caps; 2295 int ret; 2296 2297 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2298 return 0; 2299 2300 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2301 caps->qpc_sz); 2302 if (ret) { 2303 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2304 return ret; 2305 } 2306 2307 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2308 caps->sccc_sz); 2309 if (ret) 2310 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2311 2312 return ret; 2313 } 2314 2315 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2316 { 2317 struct device *dev = hr_dev->dev; 2318 int ret; 2319 2320 hr_dev->func_num = 1; 2321 2322 ret = hns_roce_query_caps(hr_dev); 2323 if (ret) { 2324 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2325 return ret; 2326 } 2327 2328 ret = hns_roce_query_vf_resource(hr_dev); 2329 if (ret) { 2330 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2331 return ret; 2332 } 2333 2334 apply_func_caps(hr_dev); 2335 2336 ret = hns_roce_v2_set_bt(hr_dev); 2337 if (ret) 2338 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2339 2340 return ret; 2341 } 2342 2343 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2344 { 2345 struct device *dev = hr_dev->dev; 2346 int ret; 2347 2348 ret = hns_roce_query_func_info(hr_dev); 2349 if (ret) { 2350 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2351 return ret; 2352 } 2353 2354 ret = hns_roce_config_global_param(hr_dev); 2355 if (ret) { 2356 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2357 return ret; 2358 } 2359 2360 ret = hns_roce_set_vf_switch_param(hr_dev); 2361 if (ret) { 2362 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2363 return ret; 2364 } 2365 2366 ret = hns_roce_query_caps(hr_dev); 2367 if (ret) { 2368 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2369 return ret; 2370 } 2371 2372 ret = hns_roce_query_pf_resource(hr_dev); 2373 if (ret) { 2374 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2375 return ret; 2376 } 2377 2378 apply_func_caps(hr_dev); 2379 2380 ret = hns_roce_alloc_vf_resource(hr_dev); 2381 if (ret) { 2382 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2383 return ret; 2384 } 2385 2386 ret = hns_roce_v2_set_bt(hr_dev); 2387 if (ret) { 2388 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2389 return ret; 2390 } 2391 2392 /* Configure the size of QPC, SCCC, etc. */ 2393 return hns_roce_config_entry_size(hr_dev); 2394 } 2395 2396 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2397 { 2398 struct device *dev = hr_dev->dev; 2399 int ret; 2400 2401 ret = hns_roce_cmq_query_hw_info(hr_dev); 2402 if (ret) { 2403 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2404 return ret; 2405 } 2406 2407 ret = hns_roce_query_fw_ver(hr_dev); 2408 if (ret) { 2409 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2410 return ret; 2411 } 2412 2413 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2414 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2415 2416 if (hr_dev->is_vf) 2417 return hns_roce_v2_vf_profile(hr_dev); 2418 else 2419 return hns_roce_v2_pf_profile(hr_dev); 2420 } 2421 2422 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2423 { 2424 u32 i, next_ptr, page_num; 2425 __le64 *entry = cfg_buf; 2426 dma_addr_t addr; 2427 u64 val; 2428 2429 page_num = data_buf->npages; 2430 for (i = 0; i < page_num; i++) { 2431 addr = hns_roce_buf_page(data_buf, i); 2432 if (i == (page_num - 1)) 2433 next_ptr = 0; 2434 else 2435 next_ptr = i + 1; 2436 2437 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2438 entry[i] = cpu_to_le64(val); 2439 } 2440 } 2441 2442 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2443 struct hns_roce_link_table *table) 2444 { 2445 struct hns_roce_cmq_desc desc[2]; 2446 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2447 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2448 struct hns_roce_buf *buf = table->buf; 2449 enum hns_roce_opcode_type opcode; 2450 dma_addr_t addr; 2451 2452 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2453 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2454 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2455 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2456 2457 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2458 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2459 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2460 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2461 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2462 2463 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2464 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2465 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2466 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2467 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2468 2469 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2470 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2471 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2472 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2473 2474 return hns_roce_cmq_send(hr_dev, desc, 2); 2475 } 2476 2477 static struct hns_roce_link_table * 2478 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2479 { 2480 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2481 struct hns_roce_v2_priv *priv = hr_dev->priv; 2482 struct hns_roce_link_table *link_tbl; 2483 u32 pg_shift, size, min_size; 2484 2485 link_tbl = &priv->ext_llm; 2486 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2487 size = hr_dev->caps.num_qps * hr_dev->func_num * 2488 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2489 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2490 2491 /* Alloc data table */ 2492 size = max(size, min_size); 2493 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2494 if (IS_ERR(link_tbl->buf)) 2495 return ERR_PTR(-ENOMEM); 2496 2497 /* Alloc config table */ 2498 size = link_tbl->buf->npages * sizeof(u64); 2499 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2500 &link_tbl->table.map, 2501 GFP_KERNEL); 2502 if (!link_tbl->table.buf) { 2503 hns_roce_buf_free(hr_dev, link_tbl->buf); 2504 return ERR_PTR(-ENOMEM); 2505 } 2506 2507 return link_tbl; 2508 } 2509 2510 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2511 struct hns_roce_link_table *tbl) 2512 { 2513 if (tbl->buf) { 2514 u32 size = tbl->buf->npages * sizeof(u64); 2515 2516 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2517 tbl->table.map); 2518 } 2519 2520 hns_roce_buf_free(hr_dev, tbl->buf); 2521 } 2522 2523 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2524 { 2525 struct hns_roce_link_table *link_tbl; 2526 int ret; 2527 2528 link_tbl = alloc_link_table_buf(hr_dev); 2529 if (IS_ERR(link_tbl)) 2530 return -ENOMEM; 2531 2532 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2533 ret = -EINVAL; 2534 goto err_alloc; 2535 } 2536 2537 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2538 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2539 if (ret) 2540 goto err_alloc; 2541 2542 return 0; 2543 2544 err_alloc: 2545 free_link_table_buf(hr_dev, link_tbl); 2546 return ret; 2547 } 2548 2549 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2550 { 2551 struct hns_roce_v2_priv *priv = hr_dev->priv; 2552 2553 free_link_table_buf(hr_dev, &priv->ext_llm); 2554 } 2555 2556 static void free_dip_entry(struct hns_roce_dev *hr_dev) 2557 { 2558 struct hns_roce_dip *hr_dip; 2559 unsigned long idx; 2560 2561 xa_lock(&hr_dev->qp_table.dip_xa); 2562 2563 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) { 2564 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx); 2565 kfree(hr_dip); 2566 } 2567 2568 xa_unlock(&hr_dev->qp_table.dip_xa); 2569 } 2570 2571 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2572 { 2573 struct hns_roce_v2_priv *priv = hr_dev->priv; 2574 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2575 struct ib_device *ibdev = &hr_dev->ib_dev; 2576 struct hns_roce_pd *hr_pd; 2577 struct ib_pd *pd; 2578 2579 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2580 if (ZERO_OR_NULL_PTR(hr_pd)) 2581 return NULL; 2582 pd = &hr_pd->ibpd; 2583 pd->device = ibdev; 2584 2585 if (hns_roce_alloc_pd(pd, NULL)) { 2586 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2587 kfree(hr_pd); 2588 return NULL; 2589 } 2590 free_mr->rsv_pd = to_hr_pd(pd); 2591 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2592 free_mr->rsv_pd->ibpd.uobject = NULL; 2593 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2594 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2595 2596 return pd; 2597 } 2598 2599 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2600 { 2601 struct hns_roce_v2_priv *priv = hr_dev->priv; 2602 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2603 struct ib_device *ibdev = &hr_dev->ib_dev; 2604 struct ib_cq_init_attr cq_init_attr = {}; 2605 struct hns_roce_cq *hr_cq; 2606 struct ib_cq *cq; 2607 2608 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2609 2610 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2611 if (ZERO_OR_NULL_PTR(hr_cq)) 2612 return NULL; 2613 2614 cq = &hr_cq->ib_cq; 2615 cq->device = ibdev; 2616 2617 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2618 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2619 kfree(hr_cq); 2620 return NULL; 2621 } 2622 free_mr->rsv_cq = to_hr_cq(cq); 2623 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2624 free_mr->rsv_cq->ib_cq.uobject = NULL; 2625 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2626 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2627 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2628 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2629 2630 return cq; 2631 } 2632 2633 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2634 struct ib_qp_init_attr *init_attr, int i) 2635 { 2636 struct hns_roce_v2_priv *priv = hr_dev->priv; 2637 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2638 struct ib_device *ibdev = &hr_dev->ib_dev; 2639 struct hns_roce_qp *hr_qp; 2640 struct ib_qp *qp; 2641 int ret; 2642 2643 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2644 if (ZERO_OR_NULL_PTR(hr_qp)) 2645 return -ENOMEM; 2646 2647 qp = &hr_qp->ibqp; 2648 qp->device = ibdev; 2649 2650 ret = hns_roce_create_qp(qp, init_attr, NULL); 2651 if (ret) { 2652 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2653 kfree(hr_qp); 2654 return ret; 2655 } 2656 2657 free_mr->rsv_qp[i] = hr_qp; 2658 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2659 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2660 2661 return 0; 2662 } 2663 2664 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2665 { 2666 struct hns_roce_v2_priv *priv = hr_dev->priv; 2667 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2668 struct ib_qp *qp; 2669 int i; 2670 2671 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2672 if (free_mr->rsv_qp[i]) { 2673 qp = &free_mr->rsv_qp[i]->ibqp; 2674 hns_roce_v2_destroy_qp(qp, NULL); 2675 kfree(free_mr->rsv_qp[i]); 2676 free_mr->rsv_qp[i] = NULL; 2677 } 2678 } 2679 2680 if (free_mr->rsv_cq) { 2681 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2682 kfree(free_mr->rsv_cq); 2683 free_mr->rsv_cq = NULL; 2684 } 2685 2686 if (free_mr->rsv_pd) { 2687 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2688 kfree(free_mr->rsv_pd); 2689 free_mr->rsv_pd = NULL; 2690 } 2691 2692 mutex_destroy(&free_mr->mutex); 2693 } 2694 2695 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2696 { 2697 struct hns_roce_v2_priv *priv = hr_dev->priv; 2698 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2699 struct ib_qp_init_attr qp_init_attr = {}; 2700 struct ib_pd *pd; 2701 struct ib_cq *cq; 2702 int ret; 2703 int i; 2704 2705 pd = free_mr_init_pd(hr_dev); 2706 if (!pd) 2707 return -ENOMEM; 2708 2709 cq = free_mr_init_cq(hr_dev); 2710 if (!cq) { 2711 ret = -ENOMEM; 2712 goto create_failed_cq; 2713 } 2714 2715 qp_init_attr.qp_type = IB_QPT_RC; 2716 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2717 qp_init_attr.send_cq = cq; 2718 qp_init_attr.recv_cq = cq; 2719 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2720 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2721 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2722 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2723 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2724 2725 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2726 if (ret) 2727 goto create_failed_qp; 2728 } 2729 2730 return 0; 2731 2732 create_failed_qp: 2733 for (i--; i >= 0; i--) { 2734 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 2735 kfree(free_mr->rsv_qp[i]); 2736 } 2737 hns_roce_destroy_cq(cq, NULL); 2738 kfree(cq); 2739 2740 create_failed_cq: 2741 hns_roce_dealloc_pd(pd, NULL); 2742 kfree(pd); 2743 2744 return ret; 2745 } 2746 2747 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2748 struct ib_qp_attr *attr, int sl_num) 2749 { 2750 struct hns_roce_v2_priv *priv = hr_dev->priv; 2751 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2752 struct ib_device *ibdev = &hr_dev->ib_dev; 2753 struct hns_roce_qp *hr_qp; 2754 int loopback; 2755 int mask; 2756 int ret; 2757 2758 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2759 hr_qp->free_mr_en = 1; 2760 hr_qp->ibqp.device = ibdev; 2761 hr_qp->ibqp.qp_type = IB_QPT_RC; 2762 2763 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2764 attr->qp_state = IB_QPS_INIT; 2765 attr->port_num = 1; 2766 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2767 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2768 IB_QPS_INIT, NULL); 2769 if (ret) { 2770 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n", 2771 ret); 2772 return ret; 2773 } 2774 2775 loopback = hr_dev->loop_idc; 2776 /* Set qpc lbi = 1 incidate loopback IO */ 2777 hr_dev->loop_idc = 1; 2778 2779 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2780 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2781 attr->qp_state = IB_QPS_RTR; 2782 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2783 attr->path_mtu = IB_MTU_256; 2784 attr->dest_qp_num = hr_qp->qpn; 2785 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2786 2787 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2788 2789 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2790 IB_QPS_RTR, NULL); 2791 hr_dev->loop_idc = loopback; 2792 if (ret) { 2793 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2794 ret); 2795 return ret; 2796 } 2797 2798 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2799 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2800 attr->qp_state = IB_QPS_RTS; 2801 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2802 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2803 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2804 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2805 IB_QPS_RTS, NULL); 2806 if (ret) 2807 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2808 ret); 2809 2810 return ret; 2811 } 2812 2813 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2814 { 2815 struct hns_roce_v2_priv *priv = hr_dev->priv; 2816 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2817 struct ib_qp_attr attr = {}; 2818 int ret; 2819 int i; 2820 2821 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2822 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2823 rdma_ah_set_port_num(&attr.ah_attr, 1); 2824 2825 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2826 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2827 if (ret) 2828 return ret; 2829 } 2830 2831 return 0; 2832 } 2833 2834 static int free_mr_init(struct hns_roce_dev *hr_dev) 2835 { 2836 struct hns_roce_v2_priv *priv = hr_dev->priv; 2837 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2838 int ret; 2839 2840 mutex_init(&free_mr->mutex); 2841 2842 ret = free_mr_alloc_res(hr_dev); 2843 if (ret) { 2844 mutex_destroy(&free_mr->mutex); 2845 return ret; 2846 } 2847 2848 ret = free_mr_modify_qp(hr_dev); 2849 if (ret) 2850 goto err_modify_qp; 2851 2852 return 0; 2853 2854 err_modify_qp: 2855 free_mr_exit(hr_dev); 2856 2857 return ret; 2858 } 2859 2860 static int get_hem_table(struct hns_roce_dev *hr_dev) 2861 { 2862 unsigned int qpc_count; 2863 unsigned int cqc_count; 2864 unsigned int gmv_count; 2865 int ret; 2866 int i; 2867 2868 /* Alloc memory for source address table buffer space chunk */ 2869 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2870 gmv_count++) { 2871 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2872 if (ret) 2873 goto err_gmv_failed; 2874 } 2875 2876 if (hr_dev->is_vf) 2877 return 0; 2878 2879 /* Alloc memory for QPC Timer buffer space chunk */ 2880 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2881 qpc_count++) { 2882 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2883 qpc_count); 2884 if (ret) { 2885 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2886 goto err_qpc_timer_failed; 2887 } 2888 } 2889 2890 /* Alloc memory for CQC Timer buffer space chunk */ 2891 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2892 cqc_count++) { 2893 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2894 cqc_count); 2895 if (ret) { 2896 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2897 goto err_cqc_timer_failed; 2898 } 2899 } 2900 2901 return 0; 2902 2903 err_cqc_timer_failed: 2904 for (i = 0; i < cqc_count; i++) 2905 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2906 2907 err_qpc_timer_failed: 2908 for (i = 0; i < qpc_count; i++) 2909 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2910 2911 err_gmv_failed: 2912 for (i = 0; i < gmv_count; i++) 2913 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2914 2915 return ret; 2916 } 2917 2918 static void put_hem_table(struct hns_roce_dev *hr_dev) 2919 { 2920 int i; 2921 2922 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2923 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2924 2925 if (hr_dev->is_vf) 2926 return; 2927 2928 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2929 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2930 2931 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2932 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2933 } 2934 2935 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2936 { 2937 int ret; 2938 2939 /* The hns ROCEE requires the extdb info to be cleared before using */ 2940 ret = hns_roce_clear_extdb_list_info(hr_dev); 2941 if (ret) 2942 return ret; 2943 2944 ret = get_hem_table(hr_dev); 2945 if (ret) 2946 return ret; 2947 2948 if (hr_dev->is_vf) 2949 return 0; 2950 2951 ret = hns_roce_init_link_table(hr_dev); 2952 if (ret) { 2953 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2954 goto err_llm_init_failed; 2955 } 2956 2957 return 0; 2958 2959 err_llm_init_failed: 2960 put_hem_table(hr_dev); 2961 2962 return ret; 2963 } 2964 2965 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2966 { 2967 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2968 free_mr_exit(hr_dev); 2969 2970 hns_roce_function_clear(hr_dev); 2971 2972 if (!hr_dev->is_vf) 2973 hns_roce_free_link_table(hr_dev); 2974 2975 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2976 free_dip_entry(hr_dev); 2977 } 2978 2979 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2980 struct hns_roce_mbox_msg *mbox_msg) 2981 { 2982 struct hns_roce_cmq_desc desc; 2983 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2984 2985 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2986 2987 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2988 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2989 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2990 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2991 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2992 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2993 mbox_msg->token); 2994 2995 return hns_roce_cmq_send(hr_dev, &desc, 1); 2996 } 2997 2998 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2999 u8 *complete_status) 3000 { 3001 struct hns_roce_mbox_status *mb_st; 3002 struct hns_roce_cmq_desc desc; 3003 unsigned long end; 3004 int ret = -EBUSY; 3005 u32 status; 3006 bool busy; 3007 3008 mb_st = (struct hns_roce_mbox_status *)desc.data; 3009 end = msecs_to_jiffies(timeout) + jiffies; 3010 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3011 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3012 return -EIO; 3013 3014 status = 0; 3015 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3016 true); 3017 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3018 if (!ret) { 3019 status = le32_to_cpu(mb_st->mb_status_hw_run); 3020 /* No pending message exists in ROCEE mbox. */ 3021 if (!(status & MB_ST_HW_RUN_M)) 3022 break; 3023 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3024 break; 3025 } 3026 3027 if (time_after(jiffies, end)) { 3028 dev_err_ratelimited(hr_dev->dev, 3029 "failed to wait mbox status 0x%x\n", 3030 status); 3031 return -ETIMEDOUT; 3032 } 3033 3034 cond_resched(); 3035 ret = -EBUSY; 3036 } 3037 3038 if (!ret) { 3039 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3040 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3041 /* Ignore all errors if the mbox is unavailable. */ 3042 ret = 0; 3043 *complete_status = MB_ST_COMPLETE_M; 3044 } 3045 3046 return ret; 3047 } 3048 3049 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3050 struct hns_roce_mbox_msg *mbox_msg) 3051 { 3052 u8 status = 0; 3053 int ret; 3054 3055 /* Waiting for the mbox to be idle */ 3056 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3057 &status); 3058 if (unlikely(ret)) { 3059 dev_err_ratelimited(hr_dev->dev, 3060 "failed to check post mbox status = 0x%x, ret = %d.\n", 3061 status, ret); 3062 return ret; 3063 } 3064 3065 /* Post new message to mbox */ 3066 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3067 if (ret) 3068 dev_err_ratelimited(hr_dev->dev, 3069 "failed to post mailbox, ret = %d.\n", ret); 3070 3071 return ret; 3072 } 3073 3074 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3075 { 3076 u8 status = 0; 3077 int ret; 3078 3079 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3080 &status); 3081 if (!ret) { 3082 if (status != MB_ST_COMPLETE_SUCC) 3083 return -EBUSY; 3084 } else { 3085 dev_err_ratelimited(hr_dev->dev, 3086 "failed to check mbox status = 0x%x, ret = %d.\n", 3087 status, ret); 3088 } 3089 3090 return ret; 3091 } 3092 3093 static void copy_gid(void *dest, const union ib_gid *gid) 3094 { 3095 #define GID_SIZE 4 3096 const union ib_gid *src = gid; 3097 __le32 (*p)[GID_SIZE] = dest; 3098 int i; 3099 3100 if (!gid) 3101 src = &zgid; 3102 3103 for (i = 0; i < GID_SIZE; i++) 3104 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3105 } 3106 3107 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3108 int gid_index, const union ib_gid *gid, 3109 enum hns_roce_sgid_type sgid_type) 3110 { 3111 struct hns_roce_cmq_desc desc; 3112 struct hns_roce_cfg_sgid_tb *sgid_tb = 3113 (struct hns_roce_cfg_sgid_tb *)desc.data; 3114 3115 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3116 3117 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3118 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3119 3120 copy_gid(&sgid_tb->vf_sgid_l, gid); 3121 3122 return hns_roce_cmq_send(hr_dev, &desc, 1); 3123 } 3124 3125 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3126 int gid_index, const union ib_gid *gid, 3127 enum hns_roce_sgid_type sgid_type, 3128 const struct ib_gid_attr *attr) 3129 { 3130 struct hns_roce_cmq_desc desc[2]; 3131 struct hns_roce_cfg_gmv_tb_a *tb_a = 3132 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3133 struct hns_roce_cfg_gmv_tb_b *tb_b = 3134 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3135 3136 u16 vlan_id = VLAN_CFI_MASK; 3137 u8 mac[ETH_ALEN] = {}; 3138 int ret; 3139 3140 if (gid) { 3141 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3142 if (ret) 3143 return ret; 3144 } 3145 3146 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3147 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3148 3149 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3150 3151 copy_gid(&tb_a->vf_sgid_l, gid); 3152 3153 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3154 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3155 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3156 3157 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3158 3159 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3160 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3161 3162 return hns_roce_cmq_send(hr_dev, desc, 2); 3163 } 3164 3165 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3166 const union ib_gid *gid, 3167 const struct ib_gid_attr *attr) 3168 { 3169 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3170 int ret; 3171 3172 if (gid) { 3173 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3174 if (ipv6_addr_v4mapped((void *)gid)) 3175 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3176 else 3177 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3178 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3179 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3180 } 3181 } 3182 3183 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3184 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3185 else 3186 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3187 3188 if (ret) 3189 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3190 ret); 3191 3192 return ret; 3193 } 3194 3195 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3196 const u8 *addr) 3197 { 3198 struct hns_roce_cmq_desc desc; 3199 struct hns_roce_cfg_smac_tb *smac_tb = 3200 (struct hns_roce_cfg_smac_tb *)desc.data; 3201 u16 reg_smac_h; 3202 u32 reg_smac_l; 3203 3204 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3205 3206 reg_smac_l = *(u32 *)(&addr[0]); 3207 reg_smac_h = *(u16 *)(&addr[4]); 3208 3209 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3210 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3211 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3212 3213 return hns_roce_cmq_send(hr_dev, &desc, 1); 3214 } 3215 3216 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3217 struct hns_roce_v2_mpt_entry *mpt_entry, 3218 struct hns_roce_mr *mr) 3219 { 3220 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3221 struct ib_device *ibdev = &hr_dev->ib_dev; 3222 dma_addr_t pbl_ba; 3223 int ret; 3224 int i; 3225 3226 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3227 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3228 if (ret) { 3229 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3230 return ret; 3231 } 3232 3233 /* Aligned to the hardware address access unit */ 3234 for (i = 0; i < ARRAY_SIZE(pages); i++) 3235 pages[i] >>= MPT_PBL_BUF_ADDR_S; 3236 3237 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3238 3239 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3240 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S); 3241 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3242 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3243 3244 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3245 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3246 3247 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3248 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3249 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3250 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3251 3252 return 0; 3253 } 3254 3255 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3256 void *mb_buf, struct hns_roce_mr *mr) 3257 { 3258 struct hns_roce_v2_mpt_entry *mpt_entry; 3259 3260 mpt_entry = mb_buf; 3261 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3262 3263 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3264 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3265 3266 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3267 mr->access & IB_ACCESS_MW_BIND); 3268 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3269 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3270 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3271 mr->access & IB_ACCESS_REMOTE_READ); 3272 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3273 mr->access & IB_ACCESS_REMOTE_WRITE); 3274 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3275 mr->access & IB_ACCESS_LOCAL_WRITE); 3276 3277 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3278 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3279 mpt_entry->lkey = cpu_to_le32(mr->key); 3280 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3281 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3282 3283 if (mr->type != MR_TYPE_MR) 3284 hr_reg_enable(mpt_entry, MPT_PA); 3285 3286 if (mr->type == MR_TYPE_DMA) 3287 return 0; 3288 3289 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3290 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3291 3292 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3293 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3294 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3295 3296 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3297 } 3298 3299 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3300 struct hns_roce_mr *mr, int flags, 3301 void *mb_buf) 3302 { 3303 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3304 u32 mr_access_flags = mr->access; 3305 int ret = 0; 3306 3307 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3308 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3309 3310 if (flags & IB_MR_REREG_ACCESS) { 3311 hr_reg_write(mpt_entry, MPT_BIND_EN, 3312 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3313 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3314 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3315 hr_reg_write(mpt_entry, MPT_RR_EN, 3316 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3317 hr_reg_write(mpt_entry, MPT_RW_EN, 3318 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3319 hr_reg_write(mpt_entry, MPT_LW_EN, 3320 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3321 } 3322 3323 if (flags & IB_MR_REREG_TRANS) { 3324 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3325 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3326 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3327 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3328 3329 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3330 } 3331 3332 return ret; 3333 } 3334 3335 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 3336 { 3337 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3338 struct hns_roce_v2_mpt_entry *mpt_entry; 3339 3340 mpt_entry = mb_buf; 3341 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3342 3343 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3344 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3345 3346 hr_reg_enable(mpt_entry, MPT_RA_EN); 3347 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3348 3349 hr_reg_enable(mpt_entry, MPT_FRE); 3350 hr_reg_clear(mpt_entry, MPT_MR_MW); 3351 hr_reg_enable(mpt_entry, MPT_BPD); 3352 hr_reg_clear(mpt_entry, MPT_PA); 3353 3354 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3355 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3356 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3357 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3358 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3359 3360 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3361 3362 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3363 MPT_PBL_BA_ADDR_S)); 3364 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3365 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3366 3367 return 0; 3368 } 3369 3370 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3371 { 3372 struct hns_roce_v2_mpt_entry *mpt_entry; 3373 3374 mpt_entry = mb_buf; 3375 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3376 3377 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3378 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3379 3380 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3381 hr_reg_enable(mpt_entry, MPT_LW_EN); 3382 3383 hr_reg_enable(mpt_entry, MPT_MR_MW); 3384 hr_reg_enable(mpt_entry, MPT_BPD); 3385 hr_reg_clear(mpt_entry, MPT_PA); 3386 hr_reg_write(mpt_entry, MPT_BQP, 3387 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3388 3389 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3390 3391 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3392 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3393 mw->pbl_hop_num); 3394 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3395 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3396 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3397 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3398 3399 return 0; 3400 } 3401 3402 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3403 { 3404 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3405 struct ib_device *ibdev = &hr_dev->ib_dev; 3406 const struct ib_send_wr *bad_wr; 3407 struct ib_rdma_wr rdma_wr = {}; 3408 struct ib_send_wr *send_wr; 3409 int ret; 3410 3411 send_wr = &rdma_wr.wr; 3412 send_wr->opcode = IB_WR_RDMA_WRITE; 3413 3414 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3415 if (ret) { 3416 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3417 ret); 3418 return ret; 3419 } 3420 3421 return 0; 3422 } 3423 3424 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3425 struct ib_wc *wc); 3426 3427 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3428 { 3429 struct hns_roce_v2_priv *priv = hr_dev->priv; 3430 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3431 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3432 struct ib_device *ibdev = &hr_dev->ib_dev; 3433 struct hns_roce_qp *hr_qp; 3434 unsigned long end; 3435 int cqe_cnt = 0; 3436 int npolled; 3437 int ret; 3438 int i; 3439 3440 /* 3441 * If the device initialization is not complete or in the uninstall 3442 * process, then there is no need to execute free mr. 3443 */ 3444 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3445 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3446 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3447 return; 3448 3449 mutex_lock(&free_mr->mutex); 3450 3451 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3452 hr_qp = free_mr->rsv_qp[i]; 3453 3454 ret = free_mr_post_send_lp_wqe(hr_qp); 3455 if (ret) { 3456 ibdev_err_ratelimited(ibdev, 3457 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3458 hr_qp->qpn, ret); 3459 break; 3460 } 3461 3462 cqe_cnt++; 3463 } 3464 3465 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3466 while (cqe_cnt) { 3467 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3468 if (npolled < 0) { 3469 ibdev_err_ratelimited(ibdev, 3470 "failed to poll cqe for free mr, remain %d cqe.\n", 3471 cqe_cnt); 3472 goto out; 3473 } 3474 3475 if (time_after(jiffies, end)) { 3476 ibdev_err_ratelimited(ibdev, 3477 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3478 cqe_cnt); 3479 goto out; 3480 } 3481 cqe_cnt -= npolled; 3482 } 3483 3484 out: 3485 mutex_unlock(&free_mr->mutex); 3486 } 3487 3488 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3489 { 3490 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3491 free_mr_send_cmd_to_hw(hr_dev); 3492 } 3493 3494 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3495 { 3496 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3497 } 3498 3499 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3500 { 3501 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3502 3503 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3504 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3505 NULL; 3506 } 3507 3508 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3509 struct hns_roce_cq *hr_cq) 3510 { 3511 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3512 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3513 } else { 3514 struct hns_roce_v2_db cq_db = {}; 3515 3516 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3517 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3518 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3519 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3520 3521 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3522 } 3523 } 3524 3525 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3526 struct hns_roce_srq *srq) 3527 { 3528 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3529 struct hns_roce_v2_cqe *cqe, *dest; 3530 u32 prod_index; 3531 int nfreed = 0; 3532 int wqe_index; 3533 u8 owner_bit; 3534 3535 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3536 ++prod_index) { 3537 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3538 break; 3539 } 3540 3541 /* 3542 * Now backwards through the CQ, removing CQ entries 3543 * that match our QP by overwriting them with next entries. 3544 */ 3545 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3546 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3547 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3548 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3549 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3550 hns_roce_free_srq_wqe(srq, wqe_index); 3551 } 3552 ++nfreed; 3553 } else if (nfreed) { 3554 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3555 hr_cq->ib_cq.cqe); 3556 owner_bit = hr_reg_read(dest, CQE_OWNER); 3557 memcpy(dest, cqe, hr_cq->cqe_size); 3558 hr_reg_write(dest, CQE_OWNER, owner_bit); 3559 } 3560 } 3561 3562 if (nfreed) { 3563 hr_cq->cons_index += nfreed; 3564 update_cq_db(hr_dev, hr_cq); 3565 } 3566 } 3567 3568 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3569 struct hns_roce_srq *srq) 3570 { 3571 spin_lock_irq(&hr_cq->lock); 3572 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3573 spin_unlock_irq(&hr_cq->lock); 3574 } 3575 3576 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3577 struct hns_roce_cq *hr_cq, void *mb_buf, 3578 u64 *mtts, dma_addr_t dma_handle) 3579 { 3580 struct hns_roce_v2_cq_context *cq_context; 3581 3582 cq_context = mb_buf; 3583 memset(cq_context, 0, sizeof(*cq_context)); 3584 3585 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3586 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3587 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3588 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3589 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3590 3591 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3592 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3593 3594 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3595 hr_reg_enable(cq_context, CQC_STASH); 3596 3597 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3598 to_hr_hw_page_addr(mtts[0])); 3599 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3600 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3601 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3602 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3603 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3604 to_hr_hw_page_addr(mtts[1])); 3605 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3606 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3607 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3608 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3609 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3610 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3611 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S); 3612 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S); 3613 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3614 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3615 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3616 ((u32)hr_cq->db.dma) >> 1); 3617 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3618 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S); 3619 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3620 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3621 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3622 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3623 } 3624 3625 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3626 enum ib_cq_notify_flags flags) 3627 { 3628 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3629 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3630 struct hns_roce_v2_db cq_db = {}; 3631 u32 notify_flag; 3632 3633 /* 3634 * flags = 0, then notify_flag : next 3635 * flags = 1, then notify flag : solocited 3636 */ 3637 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3638 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3639 3640 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3641 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3642 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3643 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3644 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3645 3646 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3647 3648 return 0; 3649 } 3650 3651 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3652 int num_entries, struct ib_wc *wc) 3653 { 3654 unsigned int left; 3655 int npolled = 0; 3656 3657 left = wq->head - wq->tail; 3658 if (left == 0) 3659 return 0; 3660 3661 left = min_t(unsigned int, (unsigned int)num_entries, left); 3662 while (npolled < left) { 3663 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3664 wc->status = IB_WC_WR_FLUSH_ERR; 3665 wc->vendor_err = 0; 3666 wc->qp = &hr_qp->ibqp; 3667 3668 wq->tail++; 3669 wc++; 3670 npolled++; 3671 } 3672 3673 return npolled; 3674 } 3675 3676 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3677 struct ib_wc *wc) 3678 { 3679 struct hns_roce_qp *hr_qp; 3680 int npolled = 0; 3681 3682 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3683 npolled += sw_comp(hr_qp, &hr_qp->sq, 3684 num_entries - npolled, wc + npolled); 3685 if (npolled >= num_entries) 3686 goto out; 3687 } 3688 3689 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3690 npolled += sw_comp(hr_qp, &hr_qp->rq, 3691 num_entries - npolled, wc + npolled); 3692 if (npolled >= num_entries) 3693 goto out; 3694 } 3695 3696 out: 3697 return npolled; 3698 } 3699 3700 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3701 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3702 struct ib_wc *wc) 3703 { 3704 static const struct { 3705 u32 cqe_status; 3706 enum ib_wc_status wc_status; 3707 } map[] = { 3708 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3709 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3710 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3711 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3712 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3713 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3714 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3715 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3716 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3717 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3718 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3719 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3720 IB_WC_RETRY_EXC_ERR }, 3721 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3722 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3723 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3724 }; 3725 3726 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3727 int i; 3728 3729 wc->status = IB_WC_GENERAL_ERR; 3730 for (i = 0; i < ARRAY_SIZE(map); i++) 3731 if (cqe_status == map[i].cqe_status) { 3732 wc->status = map[i].wc_status; 3733 break; 3734 } 3735 3736 if (likely(wc->status == IB_WC_SUCCESS || 3737 wc->status == IB_WC_WR_FLUSH_ERR)) 3738 return; 3739 3740 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 3741 cqe_status); 3742 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3743 cq->cqe_size, false); 3744 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3745 3746 /* 3747 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3748 * the standard protocol, the driver must ignore it and needn't to set 3749 * the QP to an error state. 3750 */ 3751 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3752 return; 3753 3754 flush_cqe(hr_dev, qp); 3755 } 3756 3757 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3758 struct hns_roce_qp **cur_qp) 3759 { 3760 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3761 struct hns_roce_qp *hr_qp = *cur_qp; 3762 u32 qpn; 3763 3764 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3765 3766 if (!hr_qp || qpn != hr_qp->qpn) { 3767 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3768 if (unlikely(!hr_qp)) { 3769 ibdev_err(&hr_dev->ib_dev, 3770 "CQ %06lx with entry for unknown QPN %06x\n", 3771 hr_cq->cqn, qpn); 3772 return -EINVAL; 3773 } 3774 *cur_qp = hr_qp; 3775 } 3776 3777 return 0; 3778 } 3779 3780 /* 3781 * mapped-value = 1 + real-value 3782 * The ib wc opcode's real value is start from 0, In order to distinguish 3783 * between initialized and uninitialized map values, we plus 1 to the actual 3784 * value when defining the mapping, so that the validity can be identified by 3785 * checking whether the mapped value is greater than 0. 3786 */ 3787 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3788 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3789 3790 static const u32 wc_send_op_map[] = { 3791 HR_WC_OP_MAP(SEND, SEND), 3792 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3793 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3794 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3795 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3796 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3797 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3798 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3799 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3800 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3801 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3802 HR_WC_OP_MAP(BIND_MW, REG_MR), 3803 }; 3804 3805 static int to_ib_wc_send_op(u32 hr_opcode) 3806 { 3807 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3808 return -EINVAL; 3809 3810 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3811 -EINVAL; 3812 } 3813 3814 static const u32 wc_recv_op_map[] = { 3815 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3816 HR_WC_OP_MAP(SEND, RECV), 3817 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3818 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3819 }; 3820 3821 static int to_ib_wc_recv_op(u32 hr_opcode) 3822 { 3823 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3824 return -EINVAL; 3825 3826 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3827 -EINVAL; 3828 } 3829 3830 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3831 { 3832 u32 hr_opcode; 3833 int ib_opcode; 3834 3835 wc->wc_flags = 0; 3836 3837 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3838 switch (hr_opcode) { 3839 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3840 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3841 break; 3842 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3843 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3844 wc->wc_flags |= IB_WC_WITH_IMM; 3845 break; 3846 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3847 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3848 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3849 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3850 wc->byte_len = 8; 3851 break; 3852 default: 3853 break; 3854 } 3855 3856 ib_opcode = to_ib_wc_send_op(hr_opcode); 3857 if (ib_opcode < 0) 3858 wc->status = IB_WC_GENERAL_ERR; 3859 else 3860 wc->opcode = ib_opcode; 3861 } 3862 3863 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3864 { 3865 u32 hr_opcode; 3866 int ib_opcode; 3867 3868 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3869 3870 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3871 switch (hr_opcode) { 3872 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3873 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3874 wc->wc_flags = IB_WC_WITH_IMM; 3875 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3876 break; 3877 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3878 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3879 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3880 break; 3881 default: 3882 wc->wc_flags = 0; 3883 } 3884 3885 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3886 if (ib_opcode < 0) 3887 wc->status = IB_WC_GENERAL_ERR; 3888 else 3889 wc->opcode = ib_opcode; 3890 3891 wc->sl = hr_reg_read(cqe, CQE_SL); 3892 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3893 wc->slid = 0; 3894 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3895 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3896 wc->pkey_index = 0; 3897 3898 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3899 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3900 wc->wc_flags |= IB_WC_WITH_VLAN; 3901 } else { 3902 wc->vlan_id = 0xffff; 3903 } 3904 3905 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3906 3907 return 0; 3908 } 3909 3910 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3911 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3912 { 3913 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3914 struct hns_roce_qp *qp = *cur_qp; 3915 struct hns_roce_srq *srq = NULL; 3916 struct hns_roce_v2_cqe *cqe; 3917 struct hns_roce_wq *wq; 3918 int is_send; 3919 u16 wqe_idx; 3920 int ret; 3921 3922 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3923 if (!cqe) 3924 return -EAGAIN; 3925 3926 ++hr_cq->cons_index; 3927 /* Memory barrier */ 3928 rmb(); 3929 3930 ret = get_cur_qp(hr_cq, cqe, &qp); 3931 if (ret) 3932 return ret; 3933 3934 wc->qp = &qp->ibqp; 3935 wc->vendor_err = 0; 3936 3937 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3938 3939 is_send = !hr_reg_read(cqe, CQE_S_R); 3940 if (is_send) { 3941 wq = &qp->sq; 3942 3943 /* If sg_signal_bit is set, tail pointer will be updated to 3944 * the WQE corresponding to the current CQE. 3945 */ 3946 if (qp->sq_signal_bits) 3947 wq->tail += (wqe_idx - (u16)wq->tail) & 3948 (wq->wqe_cnt - 1); 3949 3950 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3951 ++wq->tail; 3952 3953 fill_send_wc(wc, cqe); 3954 } else { 3955 if (qp->ibqp.srq) { 3956 srq = to_hr_srq(qp->ibqp.srq); 3957 wc->wr_id = srq->wrid[wqe_idx]; 3958 hns_roce_free_srq_wqe(srq, wqe_idx); 3959 } else { 3960 wq = &qp->rq; 3961 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3962 ++wq->tail; 3963 } 3964 3965 ret = fill_recv_wc(wc, cqe); 3966 } 3967 3968 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3969 if (unlikely(wc->status != IB_WC_SUCCESS)) 3970 return 0; 3971 3972 return ret; 3973 } 3974 3975 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3976 struct ib_wc *wc) 3977 { 3978 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3979 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3980 struct hns_roce_qp *cur_qp = NULL; 3981 unsigned long flags; 3982 int npolled; 3983 3984 spin_lock_irqsave(&hr_cq->lock, flags); 3985 3986 /* 3987 * When the device starts to reset, the state is RST_DOWN. At this time, 3988 * there may still be some valid CQEs in the hardware that are not 3989 * polled. Therefore, it is not allowed to switch to the software mode 3990 * immediately. When the state changes to UNINIT, CQE no longer exists 3991 * in the hardware, and then switch to software mode. 3992 */ 3993 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3994 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3995 goto out; 3996 } 3997 3998 for (npolled = 0; npolled < num_entries; ++npolled) { 3999 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4000 break; 4001 } 4002 4003 if (npolled) 4004 update_cq_db(hr_dev, hr_cq); 4005 4006 out: 4007 spin_unlock_irqrestore(&hr_cq->lock, flags); 4008 4009 return npolled; 4010 } 4011 4012 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4013 u32 step_idx, u8 *mbox_cmd) 4014 { 4015 u8 cmd; 4016 4017 switch (type) { 4018 case HEM_TYPE_QPC: 4019 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4020 break; 4021 case HEM_TYPE_MTPT: 4022 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4023 break; 4024 case HEM_TYPE_CQC: 4025 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4026 break; 4027 case HEM_TYPE_SRQC: 4028 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4029 break; 4030 case HEM_TYPE_SCCC: 4031 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4032 break; 4033 case HEM_TYPE_QPC_TIMER: 4034 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4035 break; 4036 case HEM_TYPE_CQC_TIMER: 4037 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4038 break; 4039 default: 4040 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4041 return -EINVAL; 4042 } 4043 4044 *mbox_cmd = cmd + step_idx; 4045 4046 return 0; 4047 } 4048 4049 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4050 dma_addr_t base_addr) 4051 { 4052 struct hns_roce_cmq_desc desc; 4053 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4054 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4055 u64 addr = to_hr_hw_page_addr(base_addr); 4056 4057 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4058 4059 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4060 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4061 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4062 4063 return hns_roce_cmq_send(hr_dev, &desc, 1); 4064 } 4065 4066 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4067 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4068 { 4069 int ret; 4070 u8 cmd; 4071 4072 if (unlikely(hem_type == HEM_TYPE_GMV)) 4073 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4074 4075 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4076 return 0; 4077 4078 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4079 if (ret < 0) 4080 return ret; 4081 4082 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4083 } 4084 4085 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4086 struct hns_roce_hem_table *table, int obj, 4087 u32 step_idx) 4088 { 4089 struct hns_roce_hem_mhop mhop; 4090 struct hns_roce_hem *hem; 4091 unsigned long mhop_obj = obj; 4092 int i, j, k; 4093 int ret = 0; 4094 u64 hem_idx = 0; 4095 u64 l1_idx = 0; 4096 u64 bt_ba = 0; 4097 u32 chunk_ba_num; 4098 u32 hop_num; 4099 4100 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4101 return 0; 4102 4103 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4104 i = mhop.l0_idx; 4105 j = mhop.l1_idx; 4106 k = mhop.l2_idx; 4107 hop_num = mhop.hop_num; 4108 chunk_ba_num = mhop.bt_chunk_size / 8; 4109 4110 if (hop_num == 2) { 4111 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4112 k; 4113 l1_idx = i * chunk_ba_num + j; 4114 } else if (hop_num == 1) { 4115 hem_idx = i * chunk_ba_num + j; 4116 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4117 hem_idx = i; 4118 } 4119 4120 if (table->type == HEM_TYPE_SCCC) 4121 obj = mhop.l0_idx; 4122 4123 if (check_whether_last_step(hop_num, step_idx)) { 4124 hem = table->hem[hem_idx]; 4125 4126 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4127 } else { 4128 if (step_idx == 0) 4129 bt_ba = table->bt_l0_dma_addr[i]; 4130 else if (step_idx == 1 && hop_num == 2) 4131 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4132 4133 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4134 } 4135 4136 return ret; 4137 } 4138 4139 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4140 struct hns_roce_hem_table *table, 4141 int tag, u32 step_idx) 4142 { 4143 struct hns_roce_cmd_mailbox *mailbox; 4144 struct device *dev = hr_dev->dev; 4145 u8 cmd = 0xff; 4146 int ret; 4147 4148 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4149 return 0; 4150 4151 switch (table->type) { 4152 case HEM_TYPE_QPC: 4153 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4154 break; 4155 case HEM_TYPE_MTPT: 4156 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4157 break; 4158 case HEM_TYPE_CQC: 4159 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4160 break; 4161 case HEM_TYPE_SRQC: 4162 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4163 break; 4164 case HEM_TYPE_SCCC: 4165 case HEM_TYPE_QPC_TIMER: 4166 case HEM_TYPE_CQC_TIMER: 4167 case HEM_TYPE_GMV: 4168 return 0; 4169 default: 4170 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4171 table->type); 4172 return 0; 4173 } 4174 4175 cmd += step_idx; 4176 4177 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4178 if (IS_ERR(mailbox)) 4179 return PTR_ERR(mailbox); 4180 4181 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4182 4183 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4184 return ret; 4185 } 4186 4187 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4188 struct hns_roce_v2_qp_context *context, 4189 struct hns_roce_v2_qp_context *qpc_mask, 4190 struct hns_roce_qp *hr_qp) 4191 { 4192 struct hns_roce_cmd_mailbox *mailbox; 4193 int qpc_size; 4194 int ret; 4195 4196 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4197 if (IS_ERR(mailbox)) 4198 return PTR_ERR(mailbox); 4199 4200 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4201 qpc_size = hr_dev->caps.qpc_sz; 4202 memcpy(mailbox->buf, context, qpc_size); 4203 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4204 4205 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4206 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4207 4208 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4209 4210 return ret; 4211 } 4212 4213 static void set_access_flags(struct hns_roce_qp *hr_qp, 4214 struct hns_roce_v2_qp_context *context, 4215 struct hns_roce_v2_qp_context *qpc_mask, 4216 const struct ib_qp_attr *attr, int attr_mask) 4217 { 4218 u8 dest_rd_atomic; 4219 u32 access_flags; 4220 4221 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4222 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4223 4224 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4225 attr->qp_access_flags : hr_qp->atomic_rd_en; 4226 4227 if (!dest_rd_atomic) 4228 access_flags &= IB_ACCESS_REMOTE_WRITE; 4229 4230 hr_reg_write_bool(context, QPC_RRE, 4231 access_flags & IB_ACCESS_REMOTE_READ); 4232 hr_reg_clear(qpc_mask, QPC_RRE); 4233 4234 hr_reg_write_bool(context, QPC_RWE, 4235 access_flags & IB_ACCESS_REMOTE_WRITE); 4236 hr_reg_clear(qpc_mask, QPC_RWE); 4237 4238 hr_reg_write_bool(context, QPC_ATE, 4239 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4240 hr_reg_clear(qpc_mask, QPC_ATE); 4241 hr_reg_write_bool(context, QPC_EXT_ATE, 4242 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4243 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4244 } 4245 4246 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4247 struct hns_roce_v2_qp_context *context) 4248 { 4249 hr_reg_write(context, QPC_SGE_SHIFT, 4250 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4251 hr_qp->sge.sge_shift)); 4252 4253 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4254 4255 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4256 } 4257 4258 static inline int get_cqn(struct ib_cq *ib_cq) 4259 { 4260 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4261 } 4262 4263 static inline int get_pdn(struct ib_pd *ib_pd) 4264 { 4265 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4266 } 4267 4268 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4269 struct hns_roce_v2_qp_context *context, 4270 struct hns_roce_v2_qp_context *qpc_mask) 4271 { 4272 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4273 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4274 4275 /* 4276 * In v2 engine, software pass context and context mask to hardware 4277 * when modifying qp. If software need modify some fields in context, 4278 * we should set all bits of the relevant fields in context mask to 4279 * 0 at the same time, else set them to 0x1. 4280 */ 4281 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4282 4283 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4284 4285 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4286 4287 set_qpc_wqe_cnt(hr_qp, context); 4288 4289 /* No VLAN need to set 0xFFF */ 4290 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4291 4292 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4293 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4294 4295 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4296 } 4297 4298 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4299 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4300 4301 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4302 hr_reg_enable(context, QPC_OWNER_MODE); 4303 4304 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4305 lower_32_bits(hr_qp->rdb.dma) >> 1); 4306 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4307 upper_32_bits(hr_qp->rdb.dma)); 4308 4309 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4310 4311 if (ibqp->srq) { 4312 hr_reg_enable(context, QPC_SRQ_EN); 4313 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4314 } 4315 4316 hr_reg_enable(context, QPC_FRE); 4317 4318 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4319 4320 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4321 return; 4322 4323 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4324 hr_reg_enable(&context->ext, QPCEX_STASH); 4325 } 4326 4327 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4328 struct hns_roce_v2_qp_context *context, 4329 struct hns_roce_v2_qp_context *qpc_mask) 4330 { 4331 /* 4332 * In v2 engine, software pass context and context mask to hardware 4333 * when modifying qp. If software need modify some fields in context, 4334 * we should set all bits of the relevant fields in context mask to 4335 * 0 at the same time, else set them to 0x1. 4336 */ 4337 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4338 hr_reg_clear(qpc_mask, QPC_TST); 4339 4340 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4341 hr_reg_clear(qpc_mask, QPC_PD); 4342 4343 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4344 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4345 4346 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4347 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4348 4349 if (ibqp->srq) { 4350 hr_reg_enable(context, QPC_SRQ_EN); 4351 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4352 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4353 hr_reg_clear(qpc_mask, QPC_SRQN); 4354 } 4355 } 4356 4357 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4358 struct hns_roce_qp *hr_qp, 4359 struct hns_roce_v2_qp_context *context, 4360 struct hns_roce_v2_qp_context *qpc_mask) 4361 { 4362 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4363 u64 wqe_sge_ba; 4364 int ret; 4365 4366 /* Search qp buf's mtts */ 4367 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4368 MTT_MIN_COUNT); 4369 if (hr_qp->rq.wqe_cnt && ret) { 4370 ibdev_err(&hr_dev->ib_dev, 4371 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4372 hr_qp->qpn, ret); 4373 return ret; 4374 } 4375 4376 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4377 4378 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4379 qpc_mask->wqe_sge_ba = 0; 4380 4381 /* 4382 * In v2 engine, software pass context and context mask to hardware 4383 * when modifying qp. If software need modify some fields in context, 4384 * we should set all bits of the relevant fields in context mask to 4385 * 0 at the same time, else set them to 0x1. 4386 */ 4387 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4388 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4389 4390 hr_reg_write(context, QPC_SQ_HOP_NUM, 4391 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4392 hr_qp->sq.wqe_cnt)); 4393 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4394 4395 hr_reg_write(context, QPC_SGE_HOP_NUM, 4396 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4397 hr_qp->sge.sge_cnt)); 4398 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4399 4400 hr_reg_write(context, QPC_RQ_HOP_NUM, 4401 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4402 hr_qp->rq.wqe_cnt)); 4403 4404 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4405 4406 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4407 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4408 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4409 4410 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4411 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4412 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4413 4414 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4415 qpc_mask->rq_cur_blk_addr = 0; 4416 4417 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4418 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4419 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4420 4421 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4422 context->rq_nxt_blk_addr = 4423 cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4424 qpc_mask->rq_nxt_blk_addr = 0; 4425 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4426 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4427 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4428 } 4429 4430 return 0; 4431 } 4432 4433 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4434 struct hns_roce_qp *hr_qp, 4435 struct hns_roce_v2_qp_context *context, 4436 struct hns_roce_v2_qp_context *qpc_mask) 4437 { 4438 struct ib_device *ibdev = &hr_dev->ib_dev; 4439 u64 sge_cur_blk = 0; 4440 u64 sq_cur_blk = 0; 4441 int ret; 4442 4443 /* search qp buf's mtts */ 4444 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4445 &sq_cur_blk, 1); 4446 if (ret) { 4447 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4448 hr_qp->qpn, ret); 4449 return ret; 4450 } 4451 if (hr_qp->sge.sge_cnt > 0) { 4452 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4453 hr_qp->sge.offset, &sge_cur_blk, 1); 4454 if (ret) { 4455 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4456 hr_qp->qpn, ret); 4457 return ret; 4458 } 4459 } 4460 4461 /* 4462 * In v2 engine, software pass context and context mask to hardware 4463 * when modifying qp. If software need modify some fields in context, 4464 * we should set all bits of the relevant fields in context mask to 4465 * 0 at the same time, else set them to 0x1. 4466 */ 4467 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4468 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4469 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4470 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4471 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4472 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4473 4474 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4475 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4476 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4477 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4478 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4479 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4480 4481 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4482 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4483 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4484 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4485 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4486 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4487 4488 return 0; 4489 } 4490 4491 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4492 const struct ib_qp_attr *attr) 4493 { 4494 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4495 return IB_MTU_4096; 4496 4497 return attr->path_mtu; 4498 } 4499 4500 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4501 const struct ib_qp_attr *attr, int attr_mask, 4502 struct hns_roce_v2_qp_context *context, 4503 struct hns_roce_v2_qp_context *qpc_mask, 4504 struct ib_udata *udata) 4505 { 4506 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4507 struct hns_roce_ucontext, ibucontext); 4508 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4509 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4510 struct ib_device *ibdev = &hr_dev->ib_dev; 4511 dma_addr_t trrl_ba; 4512 dma_addr_t irrl_ba; 4513 enum ib_mtu ib_mtu; 4514 const u8 *smac; 4515 u8 lp_pktn_ini; 4516 u64 *mtts; 4517 u8 *dmac; 4518 u32 port; 4519 int mtu; 4520 int ret; 4521 4522 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4523 if (ret) { 4524 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4525 return ret; 4526 } 4527 4528 /* Search IRRL's mtts */ 4529 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4530 hr_qp->qpn, &irrl_ba); 4531 if (!mtts) { 4532 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4533 return -EINVAL; 4534 } 4535 4536 /* Search TRRL's mtts */ 4537 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4538 hr_qp->qpn, &trrl_ba); 4539 if (!mtts) { 4540 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4541 return -EINVAL; 4542 } 4543 4544 if (attr_mask & IB_QP_ALT_PATH) { 4545 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4546 attr_mask); 4547 return -EINVAL; 4548 } 4549 4550 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S); 4551 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4552 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S); 4553 qpc_mask->trrl_ba = 0; 4554 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S); 4555 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4556 4557 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S); 4558 qpc_mask->irrl_ba = 0; 4559 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S); 4560 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4561 4562 hr_reg_enable(context, QPC_RMT_E2E); 4563 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4564 4565 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4566 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4567 4568 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4569 4570 smac = (const u8 *)hr_dev->dev_addr[port]; 4571 dmac = (u8 *)attr->ah_attr.roce.dmac; 4572 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4573 if (ether_addr_equal_unaligned(dmac, smac) || 4574 hr_dev->loop_idc == 0x1) { 4575 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4576 hr_reg_clear(qpc_mask, QPC_LBI); 4577 } 4578 4579 if (attr_mask & IB_QP_DEST_QPN) { 4580 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4581 hr_reg_clear(qpc_mask, QPC_DQPN); 4582 } 4583 4584 memcpy(&context->dmac, dmac, sizeof(u32)); 4585 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4586 qpc_mask->dmac = 0; 4587 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4588 4589 ib_mtu = get_mtu(ibqp, attr); 4590 hr_qp->path_mtu = ib_mtu; 4591 4592 mtu = ib_mtu_enum_to_int(ib_mtu); 4593 if (WARN_ON(mtu <= 0)) 4594 return -EINVAL; 4595 #define MIN_LP_MSG_LEN 1024 4596 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4597 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4598 4599 if (attr_mask & IB_QP_PATH_MTU) { 4600 hr_reg_write(context, QPC_MTU, ib_mtu); 4601 hr_reg_clear(qpc_mask, QPC_MTU); 4602 } 4603 4604 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4605 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4606 4607 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4608 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4609 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4610 4611 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4612 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4613 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4614 4615 context->rq_rnr_timer = 0; 4616 qpc_mask->rq_rnr_timer = 0; 4617 4618 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4619 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4620 4621 #define MAX_LP_SGEN 3 4622 /* rocee send 2^lp_sgen_ini segs every time */ 4623 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN); 4624 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4625 4626 if (udata && ibqp->qp_type == IB_QPT_RC && 4627 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4628 hr_reg_write_bool(context, QPC_RQIE, 4629 hr_dev->caps.flags & 4630 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4631 hr_reg_clear(qpc_mask, QPC_RQIE); 4632 } 4633 4634 if (udata && 4635 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4636 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4637 hr_reg_write_bool(context, QPC_CQEIE, 4638 hr_dev->caps.flags & 4639 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4640 hr_reg_clear(qpc_mask, QPC_CQEIE); 4641 4642 hr_reg_write(context, QPC_CQEIS, 0); 4643 hr_reg_clear(qpc_mask, QPC_CQEIS); 4644 } 4645 4646 return 0; 4647 } 4648 4649 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, 4650 struct hns_roce_v2_qp_context *context, 4651 struct hns_roce_v2_qp_context *qpc_mask) 4652 { 4653 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4654 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4655 struct ib_device *ibdev = &hr_dev->ib_dev; 4656 int ret; 4657 4658 /* Not support alternate path and path migration */ 4659 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4660 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4661 return -EINVAL; 4662 } 4663 4664 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4665 if (ret) { 4666 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4667 return ret; 4668 } 4669 4670 /* 4671 * Set some fields in context to zero, Because the default values 4672 * of all fields in context are zero, we need not set them to 0 again. 4673 * but we should set the relevant fields of context mask to 0. 4674 */ 4675 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4676 4677 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4678 4679 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4680 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4681 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4682 4683 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4684 4685 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4686 4687 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4688 4689 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4690 4691 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4692 4693 return 0; 4694 } 4695 4696 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn) 4697 { 4698 struct hns_roce_dip *hr_dip; 4699 int ret; 4700 4701 hr_dip = xa_load(dip_xa, qpn); 4702 if (hr_dip) 4703 return 0; 4704 4705 hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL); 4706 if (!hr_dip) 4707 return -ENOMEM; 4708 4709 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL)); 4710 if (ret) 4711 kfree(hr_dip); 4712 4713 return ret; 4714 } 4715 4716 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4717 u32 *dip_idx) 4718 { 4719 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4720 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4721 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa; 4722 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4723 struct hns_roce_dip *hr_dip; 4724 unsigned long idx; 4725 int ret = 0; 4726 4727 ret = alloc_dip_entry(dip_xa, ibqp->qp_num); 4728 if (ret) 4729 return ret; 4730 4731 xa_lock(dip_xa); 4732 4733 xa_for_each(dip_xa, idx, hr_dip) { 4734 if (hr_dip->qp_cnt && 4735 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) { 4736 *dip_idx = hr_dip->dip_idx; 4737 hr_dip->qp_cnt++; 4738 hr_qp->dip = hr_dip; 4739 goto out; 4740 } 4741 } 4742 4743 /* If no dgid is found, a new dip and a mapping between dgid and 4744 * dip_idx will be created. 4745 */ 4746 xa_for_each(dip_xa, idx, hr_dip) { 4747 if (hr_dip->qp_cnt) 4748 continue; 4749 4750 *dip_idx = idx; 4751 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4752 hr_dip->dip_idx = idx; 4753 hr_dip->qp_cnt++; 4754 hr_qp->dip = hr_dip; 4755 break; 4756 } 4757 4758 /* This should never happen. */ 4759 if (WARN_ON_ONCE(!hr_qp->dip)) 4760 ret = -ENOSPC; 4761 4762 out: 4763 xa_unlock(dip_xa); 4764 return ret; 4765 } 4766 4767 enum { 4768 CONG_DCQCN, 4769 CONG_WINDOW, 4770 }; 4771 4772 enum { 4773 UNSUPPORT_CONG_LEVEL, 4774 SUPPORT_CONG_LEVEL, 4775 }; 4776 4777 enum { 4778 CONG_LDCP, 4779 CONG_HC3, 4780 }; 4781 4782 enum { 4783 DIP_INVALID, 4784 DIP_VALID, 4785 }; 4786 4787 enum { 4788 WND_LIMIT, 4789 WND_UNLIMIT, 4790 }; 4791 4792 static int check_cong_type(struct ib_qp *ibqp, 4793 struct hns_roce_congestion_algorithm *cong_alg) 4794 { 4795 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4796 4797 /* different congestion types match different configurations */ 4798 switch (hr_qp->cong_type) { 4799 case CONG_TYPE_DCQCN: 4800 cong_alg->alg_sel = CONG_DCQCN; 4801 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4802 cong_alg->dip_vld = DIP_INVALID; 4803 cong_alg->wnd_mode_sel = WND_LIMIT; 4804 break; 4805 case CONG_TYPE_LDCP: 4806 cong_alg->alg_sel = CONG_WINDOW; 4807 cong_alg->alg_sub_sel = CONG_LDCP; 4808 cong_alg->dip_vld = DIP_INVALID; 4809 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4810 break; 4811 case CONG_TYPE_HC3: 4812 cong_alg->alg_sel = CONG_WINDOW; 4813 cong_alg->alg_sub_sel = CONG_HC3; 4814 cong_alg->dip_vld = DIP_INVALID; 4815 cong_alg->wnd_mode_sel = WND_LIMIT; 4816 break; 4817 case CONG_TYPE_DIP: 4818 cong_alg->alg_sel = CONG_DCQCN; 4819 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4820 cong_alg->dip_vld = DIP_VALID; 4821 cong_alg->wnd_mode_sel = WND_LIMIT; 4822 break; 4823 default: 4824 hr_qp->cong_type = CONG_TYPE_DCQCN; 4825 cong_alg->alg_sel = CONG_DCQCN; 4826 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4827 cong_alg->dip_vld = DIP_INVALID; 4828 cong_alg->wnd_mode_sel = WND_LIMIT; 4829 break; 4830 } 4831 4832 return 0; 4833 } 4834 4835 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4836 struct hns_roce_v2_qp_context *context, 4837 struct hns_roce_v2_qp_context *qpc_mask) 4838 { 4839 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4840 struct hns_roce_congestion_algorithm cong_field; 4841 struct ib_device *ibdev = ibqp->device; 4842 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4843 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4844 u32 dip_idx = 0; 4845 int ret; 4846 4847 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4848 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4849 return 0; 4850 4851 ret = check_cong_type(ibqp, &cong_field); 4852 if (ret) 4853 return ret; 4854 4855 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4856 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 4857 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4858 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4859 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4860 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4861 cong_field.alg_sub_sel); 4862 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4863 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4864 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4865 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4866 cong_field.wnd_mode_sel); 4867 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4868 4869 /* if dip is disabled, there is no need to set dip idx */ 4870 if (cong_field.dip_vld == 0) 4871 return 0; 4872 4873 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4874 if (ret) { 4875 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4876 return ret; 4877 } 4878 4879 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4880 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4881 4882 return 0; 4883 } 4884 4885 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, 4886 u8 *tc_mode, u8 *priority) 4887 { 4888 struct hns_roce_v2_priv *priv = hr_dev->priv; 4889 struct hnae3_handle *handle = priv->handle; 4890 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 4891 4892 if (!ops->get_dscp_prio) 4893 return -EOPNOTSUPP; 4894 4895 return ops->get_dscp_prio(handle, dscp, tc_mode, priority); 4896 } 4897 4898 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) 4899 { 4900 u32 max_sl; 4901 4902 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4903 if (unlikely(sl > max_sl)) { 4904 ibdev_err_ratelimited(&hr_dev->ib_dev, 4905 "failed to set SL(%u). Shouldn't be larger than %u.\n", 4906 sl, max_sl); 4907 return false; 4908 } 4909 4910 return true; 4911 } 4912 4913 static int hns_roce_set_sl(struct ib_qp *ibqp, 4914 const struct ib_qp_attr *attr, 4915 struct hns_roce_v2_qp_context *context, 4916 struct hns_roce_v2_qp_context *qpc_mask) 4917 { 4918 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4919 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4920 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4921 struct ib_device *ibdev = &hr_dev->ib_dev; 4922 int ret; 4923 4924 ret = hns_roce_hw_v2_get_dscp(hr_dev, get_tclass(&attr->ah_attr.grh), 4925 &hr_qp->tc_mode, &hr_qp->priority); 4926 if (ret && ret != -EOPNOTSUPP && 4927 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 4928 ibdev_err_ratelimited(ibdev, 4929 "failed to get dscp, ret = %d.\n", ret); 4930 return ret; 4931 } 4932 4933 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP && 4934 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 4935 hr_qp->sl = hr_qp->priority; 4936 else 4937 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4938 4939 if (!check_sl_valid(hr_dev, hr_qp->sl)) 4940 return -EINVAL; 4941 4942 hr_reg_write(context, QPC_SL, hr_qp->sl); 4943 hr_reg_clear(qpc_mask, QPC_SL); 4944 4945 return 0; 4946 } 4947 4948 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4949 const struct ib_qp_attr *attr, 4950 int attr_mask, 4951 struct hns_roce_v2_qp_context *context, 4952 struct hns_roce_v2_qp_context *qpc_mask) 4953 { 4954 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4955 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4956 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4957 struct ib_device *ibdev = &hr_dev->ib_dev; 4958 const struct ib_gid_attr *gid_attr = NULL; 4959 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4960 int is_roce_protocol; 4961 u16 vlan_id = 0xffff; 4962 bool is_udp = false; 4963 u8 ib_port; 4964 u8 hr_port; 4965 int ret; 4966 4967 /* 4968 * If free_mr_en of qp is set, it means that this qp comes from 4969 * free mr. This qp will perform the loopback operation. 4970 * In the loopback scenario, only sl needs to be set. 4971 */ 4972 if (hr_qp->free_mr_en) { 4973 if (!check_sl_valid(hr_dev, sl)) 4974 return -EINVAL; 4975 hr_reg_write(context, QPC_SL, sl); 4976 hr_reg_clear(qpc_mask, QPC_SL); 4977 hr_qp->sl = sl; 4978 return 0; 4979 } 4980 4981 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4982 hr_port = ib_port - 1; 4983 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4984 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4985 4986 if (is_roce_protocol) { 4987 gid_attr = attr->ah_attr.grh.sgid_attr; 4988 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4989 if (ret) 4990 return ret; 4991 4992 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4993 } 4994 4995 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4996 if (vlan_id < VLAN_N_VID && 4997 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4998 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4999 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 5000 hr_reg_enable(context, QPC_SQ_VLAN_EN); 5001 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 5002 } 5003 5004 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 5005 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 5006 5007 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 5008 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 5009 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 5010 return -EINVAL; 5011 } 5012 5013 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 5014 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 5015 return -EINVAL; 5016 } 5017 5018 hr_reg_write(context, QPC_UDPSPN, 5019 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 5020 attr->dest_qp_num) : 5021 0); 5022 5023 hr_reg_clear(qpc_mask, QPC_UDPSPN); 5024 5025 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5026 5027 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5028 5029 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5030 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5031 5032 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5033 if (ret) 5034 return ret; 5035 5036 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5037 hr_reg_clear(qpc_mask, QPC_TC); 5038 5039 hr_reg_write(context, QPC_FL, grh->flow_label); 5040 hr_reg_clear(qpc_mask, QPC_FL); 5041 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5042 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5043 5044 return hns_roce_set_sl(ibqp, attr, context, qpc_mask); 5045 } 5046 5047 static bool check_qp_state(enum ib_qp_state cur_state, 5048 enum ib_qp_state new_state) 5049 { 5050 static const bool sm[][IB_QPS_ERR + 1] = { 5051 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5052 [IB_QPS_INIT] = true }, 5053 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5054 [IB_QPS_INIT] = true, 5055 [IB_QPS_RTR] = true, 5056 [IB_QPS_ERR] = true }, 5057 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5058 [IB_QPS_RTS] = true, 5059 [IB_QPS_ERR] = true }, 5060 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5061 [IB_QPS_RTS] = true, 5062 [IB_QPS_ERR] = true }, 5063 [IB_QPS_SQD] = {}, 5064 [IB_QPS_SQE] = {}, 5065 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5066 [IB_QPS_ERR] = true } 5067 }; 5068 5069 return sm[cur_state][new_state]; 5070 } 5071 5072 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5073 const struct ib_qp_attr *attr, 5074 int attr_mask, 5075 enum ib_qp_state cur_state, 5076 enum ib_qp_state new_state, 5077 struct hns_roce_v2_qp_context *context, 5078 struct hns_roce_v2_qp_context *qpc_mask, 5079 struct ib_udata *udata) 5080 { 5081 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5082 int ret = 0; 5083 5084 if (!check_qp_state(cur_state, new_state)) 5085 return -EINVAL; 5086 5087 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5088 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5089 modify_qp_reset_to_init(ibqp, context, qpc_mask); 5090 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5091 modify_qp_init_to_init(ibqp, context, qpc_mask); 5092 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5093 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5094 qpc_mask, udata); 5095 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5096 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask); 5097 } 5098 5099 return ret; 5100 } 5101 5102 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5103 { 5104 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5105 #define QP_ACK_TIMEOUT_MAX 31 5106 5107 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5108 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5109 ibdev_warn(&hr_dev->ib_dev, 5110 "local ACK timeout shall be 0 to 20.\n"); 5111 return false; 5112 } 5113 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5114 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5115 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5116 ibdev_warn(&hr_dev->ib_dev, 5117 "local ACK timeout shall be 0 to 31.\n"); 5118 return false; 5119 } 5120 } 5121 5122 return true; 5123 } 5124 5125 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5126 const struct ib_qp_attr *attr, 5127 int attr_mask, 5128 struct hns_roce_v2_qp_context *context, 5129 struct hns_roce_v2_qp_context *qpc_mask) 5130 { 5131 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5132 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5133 int ret = 0; 5134 u8 timeout; 5135 5136 if (attr_mask & IB_QP_AV) { 5137 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5138 qpc_mask); 5139 if (ret) 5140 return ret; 5141 } 5142 5143 if (attr_mask & IB_QP_TIMEOUT) { 5144 timeout = attr->timeout; 5145 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5146 hr_reg_write(context, QPC_AT, timeout); 5147 hr_reg_clear(qpc_mask, QPC_AT); 5148 } 5149 } 5150 5151 if (attr_mask & IB_QP_RETRY_CNT) { 5152 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5153 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5154 5155 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5156 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5157 } 5158 5159 if (attr_mask & IB_QP_RNR_RETRY) { 5160 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5161 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5162 5163 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5164 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5165 } 5166 5167 if (attr_mask & IB_QP_SQ_PSN) { 5168 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5169 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5170 5171 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5172 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5173 5174 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5175 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5176 5177 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5178 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5179 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5180 5181 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5182 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5183 5184 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5185 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5186 } 5187 5188 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5189 attr->max_dest_rd_atomic) { 5190 hr_reg_write(context, QPC_RR_MAX, 5191 fls(attr->max_dest_rd_atomic - 1)); 5192 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5193 } 5194 5195 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5196 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5197 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5198 } 5199 5200 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5201 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5202 5203 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5204 hr_reg_write(context, QPC_MIN_RNR_TIME, 5205 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5206 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5207 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5208 } 5209 5210 if (attr_mask & IB_QP_RQ_PSN) { 5211 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5212 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5213 5214 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5215 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5216 } 5217 5218 if (attr_mask & IB_QP_QKEY) { 5219 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5220 qpc_mask->qkey_xrcd = 0; 5221 hr_qp->qkey = attr->qkey; 5222 } 5223 5224 return ret; 5225 } 5226 5227 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5228 const struct ib_qp_attr *attr, 5229 int attr_mask) 5230 { 5231 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5232 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5233 5234 if (attr_mask & IB_QP_ACCESS_FLAGS) 5235 hr_qp->atomic_rd_en = attr->qp_access_flags; 5236 5237 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5238 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5239 if (attr_mask & IB_QP_PORT) { 5240 hr_qp->port = attr->port_num - 1; 5241 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5242 } 5243 } 5244 5245 static void clear_qp(struct hns_roce_qp *hr_qp) 5246 { 5247 struct ib_qp *ibqp = &hr_qp->ibqp; 5248 5249 if (ibqp->send_cq) 5250 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5251 hr_qp->qpn, NULL); 5252 5253 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5254 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5255 hr_qp->qpn, ibqp->srq ? 5256 to_hr_srq(ibqp->srq) : NULL); 5257 5258 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5259 *hr_qp->rdb.db_record = 0; 5260 5261 hr_qp->rq.head = 0; 5262 hr_qp->rq.tail = 0; 5263 hr_qp->sq.head = 0; 5264 hr_qp->sq.tail = 0; 5265 hr_qp->next_sge = 0; 5266 } 5267 5268 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5269 struct hns_roce_v2_qp_context *context, 5270 struct hns_roce_v2_qp_context *qpc_mask) 5271 { 5272 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5273 unsigned long sq_flag = 0; 5274 unsigned long rq_flag = 0; 5275 5276 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5277 return; 5278 5279 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5280 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5281 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5282 hr_qp->state = IB_QPS_ERR; 5283 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5284 5285 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5286 return; 5287 5288 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5289 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5290 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5291 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5292 } 5293 5294 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5295 const struct ib_qp_attr *attr, 5296 int attr_mask, enum ib_qp_state cur_state, 5297 enum ib_qp_state new_state, struct ib_udata *udata) 5298 { 5299 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5300 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5301 struct hns_roce_v2_qp_context ctx[2]; 5302 struct hns_roce_v2_qp_context *context = ctx; 5303 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5304 struct ib_device *ibdev = &hr_dev->ib_dev; 5305 int ret; 5306 5307 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5308 return -EOPNOTSUPP; 5309 5310 /* 5311 * In v2 engine, software pass context and context mask to hardware 5312 * when modifying qp. If software need modify some fields in context, 5313 * we should set all bits of the relevant fields in context mask to 5314 * 0 at the same time, else set them to 0x1. 5315 */ 5316 memset(context, 0, hr_dev->caps.qpc_sz); 5317 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5318 5319 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5320 new_state, context, qpc_mask, udata); 5321 if (ret) 5322 goto out; 5323 5324 /* When QP state is err, SQ and RQ WQE should be flushed */ 5325 if (new_state == IB_QPS_ERR) 5326 v2_set_flushed_fields(ibqp, context, qpc_mask); 5327 5328 /* Configure the optional fields */ 5329 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5330 qpc_mask); 5331 if (ret) 5332 goto out; 5333 5334 hr_reg_write_bool(context, QPC_INV_CREDIT, 5335 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5336 ibqp->srq); 5337 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5338 5339 /* Every status migrate must change state */ 5340 hr_reg_write(context, QPC_QP_ST, new_state); 5341 hr_reg_clear(qpc_mask, QPC_QP_ST); 5342 5343 /* SW pass context to HW */ 5344 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5345 if (ret) { 5346 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret); 5347 goto out; 5348 } 5349 5350 hr_qp->state = new_state; 5351 5352 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5353 5354 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5355 clear_qp(hr_qp); 5356 5357 out: 5358 return ret; 5359 } 5360 5361 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5362 { 5363 static const enum ib_qp_state map[] = { 5364 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5365 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5366 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5367 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5368 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5369 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5370 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5371 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5372 }; 5373 5374 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5375 } 5376 5377 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5378 void *buffer) 5379 { 5380 struct hns_roce_cmd_mailbox *mailbox; 5381 int ret; 5382 5383 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5384 if (IS_ERR(mailbox)) 5385 return PTR_ERR(mailbox); 5386 5387 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5388 qpn); 5389 if (ret) 5390 goto out; 5391 5392 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5393 5394 out: 5395 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5396 return ret; 5397 } 5398 5399 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5400 void *buffer) 5401 { 5402 struct hns_roce_srq_context *context; 5403 struct hns_roce_cmd_mailbox *mailbox; 5404 int ret; 5405 5406 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5407 if (IS_ERR(mailbox)) 5408 return PTR_ERR(mailbox); 5409 5410 context = mailbox->buf; 5411 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5412 srqn); 5413 if (ret) 5414 goto out; 5415 5416 memcpy(buffer, context, sizeof(*context)); 5417 5418 out: 5419 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5420 return ret; 5421 } 5422 5423 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 qpn, 5424 void *buffer) 5425 { 5426 struct hns_roce_v2_scc_context *context; 5427 struct hns_roce_cmd_mailbox *mailbox; 5428 int ret; 5429 5430 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5431 if (IS_ERR(mailbox)) 5432 return PTR_ERR(mailbox); 5433 5434 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5435 qpn); 5436 if (ret) 5437 goto out; 5438 5439 context = mailbox->buf; 5440 memcpy(buffer, context, sizeof(*context)); 5441 5442 out: 5443 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5444 return ret; 5445 } 5446 5447 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5448 struct hns_roce_v2_qp_context *context) 5449 { 5450 u8 timeout; 5451 5452 timeout = (u8)hr_reg_read(context, QPC_AT); 5453 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5454 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5455 5456 return timeout; 5457 } 5458 5459 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5460 int qp_attr_mask, 5461 struct ib_qp_init_attr *qp_init_attr) 5462 { 5463 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5464 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5465 struct hns_roce_v2_qp_context context = {}; 5466 struct ib_device *ibdev = &hr_dev->ib_dev; 5467 int tmp_qp_state; 5468 int state; 5469 int ret; 5470 5471 memset(qp_attr, 0, sizeof(*qp_attr)); 5472 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5473 5474 mutex_lock(&hr_qp->mutex); 5475 5476 if (hr_qp->state == IB_QPS_RESET) { 5477 qp_attr->qp_state = IB_QPS_RESET; 5478 ret = 0; 5479 goto done; 5480 } 5481 5482 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5483 if (ret) { 5484 ibdev_err_ratelimited(ibdev, 5485 "failed to query QPC, ret = %d.\n", 5486 ret); 5487 ret = -EINVAL; 5488 goto out; 5489 } 5490 5491 state = hr_reg_read(&context, QPC_QP_ST); 5492 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5493 if (tmp_qp_state == -1) { 5494 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n"); 5495 ret = -EINVAL; 5496 goto out; 5497 } 5498 hr_qp->state = (u8)tmp_qp_state; 5499 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5500 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5501 qp_attr->path_mig_state = IB_MIG_ARMED; 5502 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5503 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5504 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5505 5506 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5507 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5508 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5509 qp_attr->qp_access_flags = 5510 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5511 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5512 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5513 5514 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5515 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5516 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5517 struct ib_global_route *grh = 5518 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5519 5520 rdma_ah_set_sl(&qp_attr->ah_attr, 5521 hr_reg_read(&context, QPC_SL)); 5522 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5523 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5524 grh->flow_label = hr_reg_read(&context, QPC_FL); 5525 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5526 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5527 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5528 5529 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5530 } 5531 5532 qp_attr->port_num = hr_qp->port + 1; 5533 qp_attr->sq_draining = 0; 5534 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5535 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5536 5537 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5538 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5539 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5540 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5541 5542 done: 5543 qp_attr->cur_qp_state = qp_attr->qp_state; 5544 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5545 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5546 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5547 5548 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5549 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5550 5551 qp_init_attr->qp_context = ibqp->qp_context; 5552 qp_init_attr->qp_type = ibqp->qp_type; 5553 qp_init_attr->recv_cq = ibqp->recv_cq; 5554 qp_init_attr->send_cq = ibqp->send_cq; 5555 qp_init_attr->srq = ibqp->srq; 5556 qp_init_attr->cap = qp_attr->cap; 5557 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5558 5559 out: 5560 mutex_unlock(&hr_qp->mutex); 5561 return ret; 5562 } 5563 5564 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5565 { 5566 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5567 hr_qp->ibqp.qp_type == IB_QPT_UD || 5568 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5569 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5570 hr_qp->state != IB_QPS_RESET); 5571 } 5572 5573 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5574 struct hns_roce_qp *hr_qp, 5575 struct ib_udata *udata) 5576 { 5577 struct ib_device *ibdev = &hr_dev->ib_dev; 5578 struct hns_roce_cq *send_cq, *recv_cq; 5579 unsigned long flags; 5580 int ret = 0; 5581 5582 if (modify_qp_is_ok(hr_qp)) { 5583 /* Modify qp to reset before destroying qp */ 5584 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5585 hr_qp->state, IB_QPS_RESET, udata); 5586 if (ret) 5587 ibdev_err_ratelimited(ibdev, 5588 "failed to modify QP to RST, ret = %d.\n", 5589 ret); 5590 } 5591 5592 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5593 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5594 5595 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5596 hns_roce_lock_cqs(send_cq, recv_cq); 5597 5598 if (!udata) { 5599 if (recv_cq) 5600 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5601 (hr_qp->ibqp.srq ? 5602 to_hr_srq(hr_qp->ibqp.srq) : 5603 NULL)); 5604 5605 if (send_cq && send_cq != recv_cq) 5606 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5607 } 5608 5609 hns_roce_qp_remove(hr_dev, hr_qp); 5610 5611 hns_roce_unlock_cqs(send_cq, recv_cq); 5612 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5613 5614 return ret; 5615 } 5616 5617 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev, 5618 struct hns_roce_qp *hr_qp) 5619 { 5620 struct hns_roce_dip *hr_dip = hr_qp->dip; 5621 5622 xa_lock(&hr_dev->qp_table.dip_xa); 5623 5624 hr_dip->qp_cnt--; 5625 if (!hr_dip->qp_cnt) 5626 memset(hr_dip->dgid, 0, GID_LEN_V2); 5627 5628 xa_unlock(&hr_dev->qp_table.dip_xa); 5629 } 5630 5631 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5632 { 5633 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5634 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5635 unsigned long flags; 5636 int ret; 5637 5638 /* Make sure flush_cqe() is completed */ 5639 spin_lock_irqsave(&hr_qp->flush_lock, flags); 5640 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag); 5641 spin_unlock_irqrestore(&hr_qp->flush_lock, flags); 5642 flush_work(&hr_qp->flush_work.work); 5643 5644 if (hr_qp->cong_type == CONG_TYPE_DIP) 5645 put_dip_ctx_idx(hr_dev, hr_qp); 5646 5647 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5648 if (ret) 5649 ibdev_err_ratelimited(&hr_dev->ib_dev, 5650 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5651 hr_qp->qpn, ret); 5652 5653 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5654 5655 return 0; 5656 } 5657 5658 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5659 struct hns_roce_qp *hr_qp) 5660 { 5661 struct ib_device *ibdev = &hr_dev->ib_dev; 5662 struct hns_roce_sccc_clr_done *resp; 5663 struct hns_roce_sccc_clr *clr; 5664 struct hns_roce_cmq_desc desc; 5665 int ret, i; 5666 5667 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5668 return 0; 5669 5670 mutex_lock(&hr_dev->qp_table.scc_mutex); 5671 5672 /* set scc ctx clear done flag */ 5673 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5674 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5675 if (ret) { 5676 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5677 goto out; 5678 } 5679 5680 /* clear scc context */ 5681 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5682 clr = (struct hns_roce_sccc_clr *)desc.data; 5683 clr->qpn = cpu_to_le32(hr_qp->qpn); 5684 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5685 if (ret) { 5686 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5687 goto out; 5688 } 5689 5690 /* query scc context clear is done or not */ 5691 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5692 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5693 hns_roce_cmq_setup_basic_desc(&desc, 5694 HNS_ROCE_OPC_QUERY_SCCC, true); 5695 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5696 if (ret) { 5697 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5698 ret); 5699 goto out; 5700 } 5701 5702 if (resp->clr_done) 5703 goto out; 5704 5705 msleep(20); 5706 } 5707 5708 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5709 ret = -ETIMEDOUT; 5710 5711 out: 5712 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5713 return ret; 5714 } 5715 5716 #define DMA_IDX_SHIFT 3 5717 #define DMA_WQE_SHIFT 3 5718 5719 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5720 struct hns_roce_srq_context *ctx) 5721 { 5722 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5723 struct ib_device *ibdev = srq->ibsrq.device; 5724 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5725 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5726 dma_addr_t dma_handle_idx; 5727 int ret; 5728 5729 /* Get physical address of idx que buf */ 5730 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5731 ARRAY_SIZE(mtts_idx)); 5732 if (ret) { 5733 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5734 ret); 5735 return ret; 5736 } 5737 5738 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 5739 5740 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5741 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5742 5743 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5744 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5745 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5746 5747 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5748 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5749 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5750 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5751 5752 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5753 to_hr_hw_page_addr(mtts_idx[0])); 5754 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5755 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5756 5757 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5758 to_hr_hw_page_addr(mtts_idx[1])); 5759 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5760 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5761 5762 return 0; 5763 } 5764 5765 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5766 { 5767 struct ib_device *ibdev = srq->ibsrq.device; 5768 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5769 struct hns_roce_srq_context *ctx = mb_buf; 5770 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5771 dma_addr_t dma_handle_wqe; 5772 int ret; 5773 5774 memset(ctx, 0, sizeof(*ctx)); 5775 5776 /* Get the physical address of srq buf */ 5777 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5778 ARRAY_SIZE(mtts_wqe)); 5779 if (ret) { 5780 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5781 ret); 5782 return ret; 5783 } 5784 5785 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 5786 5787 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5788 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5789 srq->ibsrq.srq_type == IB_SRQT_XRC); 5790 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5791 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5792 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5793 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5794 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5795 hr_reg_write(ctx, SRQC_RQWS, 5796 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5797 5798 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5799 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5800 srq->wqe_cnt)); 5801 5802 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5803 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5804 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5805 5806 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5807 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5808 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5809 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5810 5811 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5812 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5813 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5814 lower_32_bits(srq->rdb.dma) >> 1); 5815 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5816 upper_32_bits(srq->rdb.dma)); 5817 } 5818 5819 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5820 } 5821 5822 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5823 struct ib_srq_attr *srq_attr, 5824 enum ib_srq_attr_mask srq_attr_mask, 5825 struct ib_udata *udata) 5826 { 5827 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5828 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5829 struct hns_roce_srq_context *srq_context; 5830 struct hns_roce_srq_context *srqc_mask; 5831 struct hns_roce_cmd_mailbox *mailbox; 5832 int ret = 0; 5833 5834 /* Resizing SRQs is not supported yet */ 5835 if (srq_attr_mask & IB_SRQ_MAX_WR) { 5836 ret = -EOPNOTSUPP; 5837 goto out; 5838 } 5839 5840 if (srq_attr_mask & IB_SRQ_LIMIT) { 5841 if (srq_attr->srq_limit > srq->wqe_cnt) { 5842 ret = -EINVAL; 5843 goto out; 5844 } 5845 5846 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5847 if (IS_ERR(mailbox)) { 5848 ret = PTR_ERR(mailbox); 5849 goto out; 5850 } 5851 5852 srq_context = mailbox->buf; 5853 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5854 5855 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5856 5857 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5858 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5859 5860 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5861 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5862 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5863 if (ret) 5864 ibdev_err(&hr_dev->ib_dev, 5865 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5866 ret); 5867 } 5868 5869 out: 5870 if (ret) 5871 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 5872 5873 return ret; 5874 } 5875 5876 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5877 { 5878 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5879 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5880 struct hns_roce_srq_context *srq_context; 5881 struct hns_roce_cmd_mailbox *mailbox; 5882 int ret; 5883 5884 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5885 if (IS_ERR(mailbox)) 5886 return PTR_ERR(mailbox); 5887 5888 srq_context = mailbox->buf; 5889 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5890 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5891 if (ret) { 5892 ibdev_err(&hr_dev->ib_dev, 5893 "failed to process cmd of querying SRQ, ret = %d.\n", 5894 ret); 5895 goto out; 5896 } 5897 5898 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5899 attr->max_wr = srq->wqe_cnt; 5900 attr->max_sge = srq->max_gs - srq->rsv_sge; 5901 5902 out: 5903 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5904 return ret; 5905 } 5906 5907 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5908 { 5909 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5910 struct hns_roce_v2_cq_context *cq_context; 5911 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5912 struct hns_roce_v2_cq_context *cqc_mask; 5913 struct hns_roce_cmd_mailbox *mailbox; 5914 int ret; 5915 5916 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5917 ret = PTR_ERR_OR_ZERO(mailbox); 5918 if (ret) 5919 goto err_out; 5920 5921 cq_context = mailbox->buf; 5922 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5923 5924 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5925 5926 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5927 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5928 5929 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5930 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5931 dev_info(hr_dev->dev, 5932 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5933 cq_period); 5934 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 5935 } 5936 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5937 } 5938 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5939 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5940 5941 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5942 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5943 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5944 if (ret) 5945 ibdev_err_ratelimited(&hr_dev->ib_dev, 5946 "failed to process cmd when modifying CQ, ret = %d.\n", 5947 ret); 5948 5949 err_out: 5950 if (ret) 5951 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 5952 5953 return ret; 5954 } 5955 5956 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5957 void *buffer) 5958 { 5959 struct hns_roce_v2_cq_context *context; 5960 struct hns_roce_cmd_mailbox *mailbox; 5961 int ret; 5962 5963 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5964 if (IS_ERR(mailbox)) 5965 return PTR_ERR(mailbox); 5966 5967 context = mailbox->buf; 5968 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5969 HNS_ROCE_CMD_QUERY_CQC, cqn); 5970 if (ret) { 5971 ibdev_err_ratelimited(&hr_dev->ib_dev, 5972 "failed to process cmd when querying CQ, ret = %d.\n", 5973 ret); 5974 goto err_mailbox; 5975 } 5976 5977 memcpy(buffer, context, sizeof(*context)); 5978 5979 err_mailbox: 5980 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5981 5982 return ret; 5983 } 5984 5985 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5986 void *buffer) 5987 { 5988 struct hns_roce_v2_mpt_entry *context; 5989 struct hns_roce_cmd_mailbox *mailbox; 5990 int ret; 5991 5992 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5993 if (IS_ERR(mailbox)) 5994 return PTR_ERR(mailbox); 5995 5996 context = mailbox->buf; 5997 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5998 key_to_hw_index(key)); 5999 if (ret) { 6000 ibdev_err(&hr_dev->ib_dev, 6001 "failed to process cmd when querying MPT, ret = %d.\n", 6002 ret); 6003 goto err_mailbox; 6004 } 6005 6006 memcpy(buffer, context, sizeof(*context)); 6007 6008 err_mailbox: 6009 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6010 6011 return ret; 6012 } 6013 6014 static void dump_aeqe_log(struct hns_roce_work *irq_work) 6015 { 6016 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6017 struct ib_device *ibdev = &hr_dev->ib_dev; 6018 6019 switch (irq_work->event_type) { 6020 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6021 ibdev_info(ibdev, "path migrated succeeded.\n"); 6022 break; 6023 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6024 ibdev_warn(ibdev, "path migration failed.\n"); 6025 break; 6026 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6027 break; 6028 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6029 ibdev_dbg(ibdev, "send queue drained.\n"); 6030 break; 6031 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6032 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 6033 irq_work->queue_num, irq_work->sub_type); 6034 break; 6035 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6036 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 6037 irq_work->queue_num); 6038 break; 6039 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6040 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 6041 irq_work->queue_num, irq_work->sub_type); 6042 break; 6043 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6044 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 6045 break; 6046 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6047 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 6048 break; 6049 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6050 ibdev_err(ibdev, "SRQ catas error.\n"); 6051 break; 6052 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6053 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 6054 break; 6055 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6056 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 6057 break; 6058 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6059 ibdev_warn(ibdev, "DB overflow.\n"); 6060 break; 6061 case HNS_ROCE_EVENT_TYPE_MB: 6062 break; 6063 case HNS_ROCE_EVENT_TYPE_FLR: 6064 ibdev_warn(ibdev, "function level reset.\n"); 6065 break; 6066 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6067 ibdev_err(ibdev, "xrc domain violation error.\n"); 6068 break; 6069 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6070 ibdev_err(ibdev, "invalid xrceth error.\n"); 6071 break; 6072 default: 6073 ibdev_info(ibdev, "Undefined event %d.\n", 6074 irq_work->event_type); 6075 break; 6076 } 6077 } 6078 6079 static void hns_roce_irq_work_handle(struct work_struct *work) 6080 { 6081 struct hns_roce_work *irq_work = 6082 container_of(work, struct hns_roce_work, work); 6083 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6084 int event_type = irq_work->event_type; 6085 u32 queue_num = irq_work->queue_num; 6086 6087 switch (event_type) { 6088 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6089 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6090 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6091 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6092 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6093 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6094 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6095 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6096 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6097 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6098 hns_roce_qp_event(hr_dev, queue_num, event_type); 6099 break; 6100 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6101 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6102 hns_roce_srq_event(hr_dev, queue_num, event_type); 6103 break; 6104 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6105 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6106 hns_roce_cq_event(hr_dev, queue_num, event_type); 6107 break; 6108 default: 6109 break; 6110 } 6111 6112 dump_aeqe_log(irq_work); 6113 6114 kfree(irq_work); 6115 } 6116 6117 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 6118 struct hns_roce_eq *eq, u32 queue_num) 6119 { 6120 struct hns_roce_work *irq_work; 6121 6122 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 6123 if (!irq_work) 6124 return; 6125 6126 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 6127 irq_work->hr_dev = hr_dev; 6128 irq_work->event_type = eq->event_type; 6129 irq_work->sub_type = eq->sub_type; 6130 irq_work->queue_num = queue_num; 6131 queue_work(hr_dev->irq_workq, &irq_work->work); 6132 } 6133 6134 static void update_eq_db(struct hns_roce_eq *eq) 6135 { 6136 struct hns_roce_dev *hr_dev = eq->hr_dev; 6137 struct hns_roce_v2_db eq_db = {}; 6138 6139 if (eq->type_flag == HNS_ROCE_AEQ) { 6140 hr_reg_write(&eq_db, EQ_DB_CMD, 6141 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6142 HNS_ROCE_EQ_DB_CMD_AEQ : 6143 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 6144 } else { 6145 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 6146 6147 hr_reg_write(&eq_db, EQ_DB_CMD, 6148 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6149 HNS_ROCE_EQ_DB_CMD_CEQ : 6150 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 6151 } 6152 6153 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 6154 6155 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 6156 } 6157 6158 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6159 { 6160 struct hns_roce_aeqe *aeqe; 6161 6162 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6163 (eq->cons_index & (eq->entries - 1)) * 6164 eq->eqe_size); 6165 6166 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6167 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6168 } 6169 6170 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6171 struct hns_roce_eq *eq) 6172 { 6173 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6174 irqreturn_t aeqe_found = IRQ_NONE; 6175 int num_aeqes = 0; 6176 int event_type; 6177 u32 queue_num; 6178 int sub_type; 6179 6180 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) { 6181 /* Make sure we read AEQ entry after we have checked the 6182 * ownership bit 6183 */ 6184 dma_rmb(); 6185 6186 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6187 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6188 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6189 6190 switch (event_type) { 6191 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6192 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6193 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6194 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6195 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6196 hns_roce_flush_cqe(hr_dev, queue_num); 6197 break; 6198 case HNS_ROCE_EVENT_TYPE_MB: 6199 hns_roce_cmd_event(hr_dev, 6200 le16_to_cpu(aeqe->event.cmd.token), 6201 aeqe->event.cmd.status, 6202 le64_to_cpu(aeqe->event.cmd.out_param)); 6203 break; 6204 default: 6205 break; 6206 } 6207 6208 eq->event_type = event_type; 6209 eq->sub_type = sub_type; 6210 ++eq->cons_index; 6211 aeqe_found = IRQ_HANDLED; 6212 6213 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6214 6215 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6216 6217 aeqe = next_aeqe_sw_v2(eq); 6218 ++num_aeqes; 6219 } 6220 6221 update_eq_db(eq); 6222 6223 return IRQ_RETVAL(aeqe_found); 6224 } 6225 6226 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6227 { 6228 struct hns_roce_ceqe *ceqe; 6229 6230 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6231 (eq->cons_index & (eq->entries - 1)) * 6232 eq->eqe_size); 6233 6234 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6235 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6236 } 6237 6238 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) 6239 { 6240 queue_work(system_bh_wq, &eq->work); 6241 6242 return IRQ_HANDLED; 6243 } 6244 6245 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6246 { 6247 struct hns_roce_eq *eq = eq_ptr; 6248 struct hns_roce_dev *hr_dev = eq->hr_dev; 6249 irqreturn_t int_work; 6250 6251 if (eq->type_flag == HNS_ROCE_CEQ) 6252 /* Completion event interrupt */ 6253 int_work = hns_roce_v2_ceq_int(eq); 6254 else 6255 /* Asynchronous event interrupt */ 6256 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6257 6258 return IRQ_RETVAL(int_work); 6259 } 6260 6261 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6262 u32 int_st) 6263 { 6264 struct pci_dev *pdev = hr_dev->pci_dev; 6265 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6266 const struct hnae3_ae_ops *ops = ae_dev->ops; 6267 enum hnae3_reset_type reset_type; 6268 irqreturn_t int_work = IRQ_NONE; 6269 u32 int_en; 6270 6271 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6272 6273 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6274 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6275 6276 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6277 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6278 6279 reset_type = hr_dev->is_vf ? 6280 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET; 6281 6282 /* Set reset level for reset_event() */ 6283 if (ops->set_default_reset_request) 6284 ops->set_default_reset_request(ae_dev, reset_type); 6285 if (ops->reset_event) 6286 ops->reset_event(pdev, NULL); 6287 6288 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6289 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6290 6291 int_work = IRQ_HANDLED; 6292 } else { 6293 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6294 } 6295 6296 return IRQ_RETVAL(int_work); 6297 } 6298 6299 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6300 struct fmea_ram_ecc *ecc_info) 6301 { 6302 struct hns_roce_cmq_desc desc; 6303 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6304 int ret; 6305 6306 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6307 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6308 if (ret) 6309 return ret; 6310 6311 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6312 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6313 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6314 6315 return 0; 6316 } 6317 6318 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6319 { 6320 struct hns_roce_cmq_desc desc; 6321 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6322 u32 addr_upper; 6323 u32 addr_low; 6324 int ret; 6325 6326 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6327 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6328 6329 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6330 if (ret) { 6331 dev_err(hr_dev->dev, 6332 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6333 return ret; 6334 } 6335 6336 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6337 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6338 6339 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6340 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6341 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6342 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6343 6344 return hns_roce_cmq_send(hr_dev, &desc, 1); 6345 } 6346 6347 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6348 { 6349 if (res_type == ECC_RESOURCE_QPC_TIMER || 6350 res_type == ECC_RESOURCE_CQC_TIMER || 6351 res_type == ECC_RESOURCE_SCCC) 6352 return le64_to_cpu(*data); 6353 6354 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT; 6355 } 6356 6357 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6358 u32 index) 6359 { 6360 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6361 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6362 struct hns_roce_cmd_mailbox *mailbox; 6363 u64 addr; 6364 int ret; 6365 6366 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6367 if (IS_ERR(mailbox)) 6368 return PTR_ERR(mailbox); 6369 6370 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6371 if (ret) { 6372 dev_err(hr_dev->dev, 6373 "failed to execute cmd to read fmea ram, ret = %d.\n", 6374 ret); 6375 goto out; 6376 } 6377 6378 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6379 6380 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6381 if (ret) 6382 dev_err(hr_dev->dev, 6383 "failed to execute cmd to write fmea ram, ret = %d.\n", 6384 ret); 6385 6386 out: 6387 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6388 return ret; 6389 } 6390 6391 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6392 struct fmea_ram_ecc *ecc_info) 6393 { 6394 u32 res_type = ecc_info->res_type; 6395 u32 index = ecc_info->index; 6396 int ret; 6397 6398 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6399 6400 if (res_type >= ECC_RESOURCE_COUNT) { 6401 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6402 res_type); 6403 return; 6404 } 6405 6406 if (res_type == ECC_RESOURCE_GMV) 6407 ret = fmea_recover_gmv(hr_dev, index); 6408 else 6409 ret = fmea_recover_others(hr_dev, res_type, index); 6410 if (ret) 6411 dev_err(hr_dev->dev, 6412 "failed to recover %s, index = %u, ret = %d.\n", 6413 fmea_ram_res[res_type].name, index, ret); 6414 } 6415 6416 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6417 { 6418 struct hns_roce_dev *hr_dev = 6419 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6420 struct fmea_ram_ecc ecc_info = {}; 6421 6422 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6423 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6424 return; 6425 } 6426 6427 if (!ecc_info.is_ecc_err) { 6428 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6429 return; 6430 } 6431 6432 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6433 } 6434 6435 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6436 { 6437 struct hns_roce_dev *hr_dev = dev_id; 6438 irqreturn_t int_work = IRQ_NONE; 6439 u32 int_st; 6440 6441 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6442 6443 if (int_st) { 6444 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6445 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6446 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6447 int_work = IRQ_HANDLED; 6448 } else { 6449 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6450 } 6451 6452 return IRQ_RETVAL(int_work); 6453 } 6454 6455 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6456 int eq_num, u32 enable_flag) 6457 { 6458 int i; 6459 6460 for (i = 0; i < eq_num; i++) 6461 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6462 i * EQ_REG_OFFSET, enable_flag); 6463 6464 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6465 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6466 } 6467 6468 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6469 { 6470 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6471 } 6472 6473 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6474 struct hns_roce_eq *eq) 6475 { 6476 struct device *dev = hr_dev->dev; 6477 int eqn = eq->eqn; 6478 int ret; 6479 u8 cmd; 6480 6481 if (eqn < hr_dev->caps.num_comp_vectors) 6482 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6483 else 6484 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6485 6486 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6487 if (ret) 6488 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6489 6490 free_eq_buf(hr_dev, eq); 6491 } 6492 6493 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6494 { 6495 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6496 eq->cons_index = 0; 6497 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6498 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6499 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6500 eq->shift = ilog2((unsigned int)eq->entries); 6501 } 6502 6503 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6504 void *mb_buf) 6505 { 6506 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6507 struct hns_roce_eq_context *eqc; 6508 u64 bt_ba = 0; 6509 int ret; 6510 6511 eqc = mb_buf; 6512 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6513 6514 init_eq_config(hr_dev, eq); 6515 6516 /* if not multi-hop, eqe buffer only use one trunk */ 6517 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6518 ARRAY_SIZE(eqe_ba)); 6519 if (ret) { 6520 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6521 return ret; 6522 } 6523 6524 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6525 6526 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6527 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6528 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6529 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6530 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6531 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6532 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6533 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6534 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6535 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6536 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6537 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6538 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6539 6540 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6541 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6542 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6543 eq->eq_period); 6544 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6545 } 6546 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6547 } 6548 6549 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6550 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6551 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6552 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6553 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6554 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6555 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6556 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6557 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6558 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6559 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6560 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6561 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6562 6563 return 0; 6564 } 6565 6566 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6567 { 6568 struct hns_roce_buf_attr buf_attr = {}; 6569 int err; 6570 6571 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6572 eq->hop_num = 0; 6573 else 6574 eq->hop_num = hr_dev->caps.eqe_hop_num; 6575 6576 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6577 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6578 buf_attr.region[0].hopnum = eq->hop_num; 6579 buf_attr.region_count = 1; 6580 6581 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6582 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6583 0); 6584 if (err) 6585 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6586 6587 return err; 6588 } 6589 6590 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6591 struct hns_roce_eq *eq, u8 eq_cmd) 6592 { 6593 struct hns_roce_cmd_mailbox *mailbox; 6594 int ret; 6595 6596 /* Allocate mailbox memory */ 6597 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6598 if (IS_ERR(mailbox)) 6599 return PTR_ERR(mailbox); 6600 6601 ret = alloc_eq_buf(hr_dev, eq); 6602 if (ret) 6603 goto free_cmd_mbox; 6604 6605 ret = config_eqc(hr_dev, eq, mailbox->buf); 6606 if (ret) 6607 goto err_cmd_mbox; 6608 6609 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6610 if (ret) { 6611 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6612 goto err_cmd_mbox; 6613 } 6614 6615 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6616 6617 return 0; 6618 6619 err_cmd_mbox: 6620 free_eq_buf(hr_dev, eq); 6621 6622 free_cmd_mbox: 6623 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6624 6625 return ret; 6626 } 6627 6628 static void hns_roce_ceq_work(struct work_struct *work) 6629 { 6630 struct hns_roce_eq *eq = from_work(eq, work, work); 6631 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6632 struct hns_roce_dev *hr_dev = eq->hr_dev; 6633 int ceqe_num = 0; 6634 u32 cqn; 6635 6636 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) { 6637 /* Make sure we read CEQ entry after we have checked the 6638 * ownership bit 6639 */ 6640 dma_rmb(); 6641 6642 cqn = hr_reg_read(ceqe, CEQE_CQN); 6643 6644 hns_roce_cq_completion(hr_dev, cqn); 6645 6646 ++eq->cons_index; 6647 ++ceqe_num; 6648 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6649 6650 ceqe = next_ceqe_sw_v2(eq); 6651 } 6652 6653 update_eq_db(eq); 6654 } 6655 6656 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6657 int comp_num, int aeq_num, int other_num) 6658 { 6659 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6660 int i, j; 6661 int ret; 6662 6663 for (i = 0; i < irq_num; i++) { 6664 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6665 GFP_KERNEL); 6666 if (!hr_dev->irq_names[i]) { 6667 ret = -ENOMEM; 6668 goto err_kzalloc_failed; 6669 } 6670 } 6671 6672 /* irq contains: abnormal + AEQ + CEQ */ 6673 for (j = 0; j < other_num; j++) 6674 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6675 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 6676 6677 for (j = other_num; j < (other_num + aeq_num); j++) 6678 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6679 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 6680 6681 for (j = (other_num + aeq_num); j < irq_num; j++) 6682 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6683 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 6684 j - other_num - aeq_num); 6685 6686 for (j = 0; j < irq_num; j++) { 6687 if (j < other_num) { 6688 ret = request_irq(hr_dev->irq[j], 6689 hns_roce_v2_msix_interrupt_abn, 6690 0, hr_dev->irq_names[j], hr_dev); 6691 } else if (j < (other_num + comp_num)) { 6692 INIT_WORK(&eq_table->eq[j - other_num].work, 6693 hns_roce_ceq_work); 6694 ret = request_irq(eq_table->eq[j - other_num].irq, 6695 hns_roce_v2_msix_interrupt_eq, 6696 0, hr_dev->irq_names[j + aeq_num], 6697 &eq_table->eq[j - other_num]); 6698 } else { 6699 ret = request_irq(eq_table->eq[j - other_num].irq, 6700 hns_roce_v2_msix_interrupt_eq, 6701 0, hr_dev->irq_names[j - comp_num], 6702 &eq_table->eq[j - other_num]); 6703 } 6704 6705 if (ret) { 6706 dev_err(hr_dev->dev, "request irq error!\n"); 6707 goto err_request_failed; 6708 } 6709 } 6710 6711 return 0; 6712 6713 err_request_failed: 6714 for (j -= 1; j >= 0; j--) { 6715 if (j < other_num) { 6716 free_irq(hr_dev->irq[j], hr_dev); 6717 continue; 6718 } 6719 free_irq(eq_table->eq[j - other_num].irq, 6720 &eq_table->eq[j - other_num]); 6721 if (j < other_num + comp_num) 6722 cancel_work_sync(&eq_table->eq[j - other_num].work); 6723 } 6724 6725 err_kzalloc_failed: 6726 for (i -= 1; i >= 0; i--) 6727 kfree(hr_dev->irq_names[i]); 6728 6729 return ret; 6730 } 6731 6732 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6733 { 6734 int irq_num; 6735 int eq_num; 6736 int i; 6737 6738 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6739 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6740 6741 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6742 free_irq(hr_dev->irq[i], hr_dev); 6743 6744 for (i = 0; i < eq_num; i++) { 6745 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6746 if (i < hr_dev->caps.num_comp_vectors) 6747 cancel_work_sync(&hr_dev->eq_table.eq[i].work); 6748 } 6749 6750 for (i = 0; i < irq_num; i++) 6751 kfree(hr_dev->irq_names[i]); 6752 } 6753 6754 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6755 { 6756 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6757 struct device *dev = hr_dev->dev; 6758 struct hns_roce_eq *eq; 6759 int other_num; 6760 int comp_num; 6761 int aeq_num; 6762 int irq_num; 6763 int eq_num; 6764 u8 eq_cmd; 6765 int ret; 6766 int i; 6767 6768 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET) 6769 return -EINVAL; 6770 6771 other_num = hr_dev->caps.num_other_vectors; 6772 comp_num = hr_dev->caps.num_comp_vectors; 6773 aeq_num = hr_dev->caps.num_aeq_vectors; 6774 6775 eq_num = comp_num + aeq_num; 6776 irq_num = eq_num + other_num; 6777 6778 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6779 if (!eq_table->eq) 6780 return -ENOMEM; 6781 6782 /* create eq */ 6783 for (i = 0; i < eq_num; i++) { 6784 eq = &eq_table->eq[i]; 6785 eq->hr_dev = hr_dev; 6786 eq->eqn = i; 6787 if (i < comp_num) { 6788 /* CEQ */ 6789 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6790 eq->type_flag = HNS_ROCE_CEQ; 6791 eq->entries = hr_dev->caps.ceqe_depth; 6792 eq->eqe_size = hr_dev->caps.ceqe_size; 6793 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6794 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6795 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6796 } else { 6797 /* AEQ */ 6798 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6799 eq->type_flag = HNS_ROCE_AEQ; 6800 eq->entries = hr_dev->caps.aeqe_depth; 6801 eq->eqe_size = hr_dev->caps.aeqe_size; 6802 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6803 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6804 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6805 } 6806 6807 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6808 if (ret) { 6809 dev_err(dev, "failed to create eq.\n"); 6810 goto err_create_eq_fail; 6811 } 6812 } 6813 6814 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6815 6816 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6817 if (!hr_dev->irq_workq) { 6818 dev_err(dev, "failed to create irq workqueue.\n"); 6819 ret = -ENOMEM; 6820 goto err_create_eq_fail; 6821 } 6822 6823 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6824 other_num); 6825 if (ret) { 6826 dev_err(dev, "failed to request irq.\n"); 6827 goto err_request_irq_fail; 6828 } 6829 6830 /* enable irq */ 6831 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6832 6833 return 0; 6834 6835 err_request_irq_fail: 6836 destroy_workqueue(hr_dev->irq_workq); 6837 6838 err_create_eq_fail: 6839 for (i -= 1; i >= 0; i--) 6840 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6841 kfree(eq_table->eq); 6842 6843 return ret; 6844 } 6845 6846 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6847 { 6848 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6849 int eq_num; 6850 int i; 6851 6852 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6853 6854 /* Disable irq */ 6855 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6856 6857 __hns_roce_free_irq(hr_dev); 6858 destroy_workqueue(hr_dev->irq_workq); 6859 6860 for (i = 0; i < eq_num; i++) 6861 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6862 6863 kfree(eq_table->eq); 6864 } 6865 6866 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6867 .destroy_qp = hns_roce_v2_destroy_qp, 6868 .modify_cq = hns_roce_v2_modify_cq, 6869 .poll_cq = hns_roce_v2_poll_cq, 6870 .post_recv = hns_roce_v2_post_recv, 6871 .post_send = hns_roce_v2_post_send, 6872 .query_qp = hns_roce_v2_query_qp, 6873 .req_notify_cq = hns_roce_v2_req_notify_cq, 6874 }; 6875 6876 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6877 .modify_srq = hns_roce_v2_modify_srq, 6878 .post_srq_recv = hns_roce_v2_post_srq_recv, 6879 .query_srq = hns_roce_v2_query_srq, 6880 }; 6881 6882 static const struct hns_roce_hw hns_roce_hw_v2 = { 6883 .cmq_init = hns_roce_v2_cmq_init, 6884 .cmq_exit = hns_roce_v2_cmq_exit, 6885 .hw_profile = hns_roce_v2_profile, 6886 .hw_init = hns_roce_v2_init, 6887 .hw_exit = hns_roce_v2_exit, 6888 .post_mbox = v2_post_mbox, 6889 .poll_mbox_done = v2_poll_mbox_done, 6890 .chk_mbox_avail = v2_chk_mbox_is_avail, 6891 .set_gid = hns_roce_v2_set_gid, 6892 .set_mac = hns_roce_v2_set_mac, 6893 .write_mtpt = hns_roce_v2_write_mtpt, 6894 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6895 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6896 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6897 .write_cqc = hns_roce_v2_write_cqc, 6898 .set_hem = hns_roce_v2_set_hem, 6899 .clear_hem = hns_roce_v2_clear_hem, 6900 .modify_qp = hns_roce_v2_modify_qp, 6901 .dereg_mr = hns_roce_v2_dereg_mr, 6902 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6903 .init_eq = hns_roce_v2_init_eq_table, 6904 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6905 .write_srqc = hns_roce_v2_write_srqc, 6906 .query_cqc = hns_roce_v2_query_cqc, 6907 .query_qpc = hns_roce_v2_query_qpc, 6908 .query_mpt = hns_roce_v2_query_mpt, 6909 .query_srqc = hns_roce_v2_query_srqc, 6910 .query_sccc = hns_roce_v2_query_sccc, 6911 .query_hw_counter = hns_roce_hw_v2_query_counter, 6912 .get_dscp = hns_roce_hw_v2_get_dscp, 6913 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6914 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6915 }; 6916 6917 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6918 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6919 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6920 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6921 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6922 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6923 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6924 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6925 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6926 /* required last entry */ 6927 {0, } 6928 }; 6929 6930 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6931 6932 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6933 struct hnae3_handle *handle) 6934 { 6935 struct hns_roce_v2_priv *priv = hr_dev->priv; 6936 const struct pci_device_id *id; 6937 int i; 6938 6939 hr_dev->pci_dev = handle->pdev; 6940 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6941 hr_dev->is_vf = id->driver_data; 6942 hr_dev->dev = &handle->pdev->dev; 6943 hr_dev->hw = &hns_roce_hw_v2; 6944 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6945 hr_dev->odb_offset = hr_dev->sdb_offset; 6946 6947 /* Get info from NIC driver. */ 6948 hr_dev->reg_base = handle->rinfo.roce_io_base; 6949 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6950 hr_dev->caps.num_ports = 1; 6951 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6952 hr_dev->iboe.phy_port[0] = 0; 6953 6954 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6955 hr_dev->iboe.netdevs[0]->dev_addr); 6956 6957 for (i = 0; i < handle->rinfo.num_vectors; i++) 6958 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6959 i + handle->rinfo.base_vector); 6960 6961 /* cmd issue mode: 0 is poll, 1 is event */ 6962 hr_dev->cmd_mod = 1; 6963 hr_dev->loop_idc = 0; 6964 6965 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6966 priv->handle = handle; 6967 } 6968 6969 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6970 { 6971 struct hns_roce_dev *hr_dev; 6972 int ret; 6973 6974 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6975 if (!hr_dev) 6976 return -ENOMEM; 6977 6978 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6979 if (!hr_dev->priv) { 6980 ret = -ENOMEM; 6981 goto error_failed_kzalloc; 6982 } 6983 6984 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6985 6986 ret = hns_roce_init(hr_dev); 6987 if (ret) { 6988 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6989 goto error_failed_roce_init; 6990 } 6991 6992 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6993 ret = free_mr_init(hr_dev); 6994 if (ret) { 6995 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6996 goto error_failed_free_mr_init; 6997 } 6998 } 6999 7000 handle->priv = hr_dev; 7001 7002 return 0; 7003 7004 error_failed_free_mr_init: 7005 hns_roce_exit(hr_dev); 7006 7007 error_failed_roce_init: 7008 kfree(hr_dev->priv); 7009 7010 error_failed_kzalloc: 7011 ib_dealloc_device(&hr_dev->ib_dev); 7012 7013 return ret; 7014 } 7015 7016 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7017 bool reset) 7018 { 7019 struct hns_roce_dev *hr_dev = handle->priv; 7020 7021 if (!hr_dev) 7022 return; 7023 7024 handle->priv = NULL; 7025 7026 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 7027 hns_roce_handle_device_err(hr_dev); 7028 7029 hns_roce_exit(hr_dev); 7030 kfree(hr_dev->priv); 7031 ib_dealloc_device(&hr_dev->ib_dev); 7032 } 7033 7034 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7035 { 7036 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 7037 const struct pci_device_id *id; 7038 struct device *dev = &handle->pdev->dev; 7039 int ret; 7040 7041 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 7042 7043 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 7044 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7045 goto reset_chk_err; 7046 } 7047 7048 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 7049 if (!id) 7050 return 0; 7051 7052 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 7053 return 0; 7054 7055 ret = __hns_roce_hw_v2_init_instance(handle); 7056 if (ret) { 7057 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7058 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 7059 if (ops->ae_dev_resetting(handle) || 7060 ops->get_hw_reset_stat(handle)) 7061 goto reset_chk_err; 7062 else 7063 return ret; 7064 } 7065 7066 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 7067 7068 return 0; 7069 7070 reset_chk_err: 7071 dev_err(dev, "Device is busy in resetting state.\n" 7072 "please retry later.\n"); 7073 7074 return -EBUSY; 7075 } 7076 7077 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7078 bool reset) 7079 { 7080 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7081 return; 7082 7083 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 7084 7085 __hns_roce_hw_v2_uninit_instance(handle, reset); 7086 7087 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7088 } 7089 7090 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 7091 { 7092 struct hns_roce_dev *hr_dev; 7093 7094 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 7095 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7096 return 0; 7097 } 7098 7099 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 7100 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7101 7102 hr_dev = handle->priv; 7103 if (!hr_dev) 7104 return 0; 7105 7106 hr_dev->active = false; 7107 hr_dev->dis_db = true; 7108 7109 rdma_user_mmap_disassociate(&hr_dev->ib_dev); 7110 7111 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 7112 7113 return 0; 7114 } 7115 7116 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 7117 { 7118 struct device *dev = &handle->pdev->dev; 7119 int ret; 7120 7121 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 7122 &handle->rinfo.state)) { 7123 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7124 return 0; 7125 } 7126 7127 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 7128 7129 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 7130 ret = __hns_roce_hw_v2_init_instance(handle); 7131 if (ret) { 7132 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 7133 * callback function, RoCE Engine reinitialize. If RoCE reinit 7134 * failed, we should inform NIC driver. 7135 */ 7136 handle->priv = NULL; 7137 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 7138 } else { 7139 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7140 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 7141 } 7142 7143 return ret; 7144 } 7145 7146 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 7147 { 7148 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 7149 return 0; 7150 7151 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 7152 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 7153 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 7154 __hns_roce_hw_v2_uninit_instance(handle, false); 7155 7156 return 0; 7157 } 7158 7159 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 7160 enum hnae3_reset_notify_type type) 7161 { 7162 int ret = 0; 7163 7164 switch (type) { 7165 case HNAE3_DOWN_CLIENT: 7166 ret = hns_roce_hw_v2_reset_notify_down(handle); 7167 break; 7168 case HNAE3_INIT_CLIENT: 7169 ret = hns_roce_hw_v2_reset_notify_init(handle); 7170 break; 7171 case HNAE3_UNINIT_CLIENT: 7172 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 7173 break; 7174 default: 7175 break; 7176 } 7177 7178 return ret; 7179 } 7180 7181 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7182 .init_instance = hns_roce_hw_v2_init_instance, 7183 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7184 .reset_notify = hns_roce_hw_v2_reset_notify, 7185 }; 7186 7187 static struct hnae3_client hns_roce_hw_v2_client = { 7188 .name = "hns_roce_hw_v2", 7189 .type = HNAE3_CLIENT_ROCE, 7190 .ops = &hns_roce_hw_v2_ops, 7191 }; 7192 7193 static int __init hns_roce_hw_v2_init(void) 7194 { 7195 hns_roce_init_debugfs(); 7196 return hnae3_register_client(&hns_roce_hw_v2_client); 7197 } 7198 7199 static void __exit hns_roce_hw_v2_exit(void) 7200 { 7201 hnae3_unregister_client(&hns_roce_hw_v2_client); 7202 hns_roce_cleanup_debugfs(); 7203 } 7204 7205 module_init(hns_roce_hw_v2_init); 7206 module_exit(hns_roce_hw_v2_exit); 7207 7208 MODULE_LICENSE("Dual BSD/GPL"); 7209 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7210 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7211 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7212 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7213