1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <linux/workqueue.h> 40 #include <net/addrconf.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <rdma/ib_umem.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 #define CREATE_TRACE_POINTS 53 #include "hns_roce_trace.h" 54 55 enum { 56 CMD_RST_PRC_OTHERS, 57 CMD_RST_PRC_SUCCESS, 58 CMD_RST_PRC_EBUSY, 59 }; 60 61 enum ecc_resource_type { 62 ECC_RESOURCE_QPC, 63 ECC_RESOURCE_CQC, 64 ECC_RESOURCE_MPT, 65 ECC_RESOURCE_SRQC, 66 ECC_RESOURCE_GMV, 67 ECC_RESOURCE_QPC_TIMER, 68 ECC_RESOURCE_CQC_TIMER, 69 ECC_RESOURCE_SCCC, 70 ECC_RESOURCE_COUNT, 71 }; 72 73 static const struct { 74 const char *name; 75 u8 read_bt0_op; 76 u8 write_bt0_op; 77 } fmea_ram_res[] = { 78 { "ECC_RESOURCE_QPC", 79 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 80 { "ECC_RESOURCE_CQC", 81 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 82 { "ECC_RESOURCE_MPT", 83 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 84 { "ECC_RESOURCE_SRQC", 85 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 86 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 87 { "ECC_RESOURCE_GMV", 88 0, 0 }, 89 { "ECC_RESOURCE_QPC_TIMER", 90 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 91 { "ECC_RESOURCE_CQC_TIMER", 92 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 93 { "ECC_RESOURCE_SCCC", 94 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 95 }; 96 97 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 98 struct ib_sge *sg) 99 { 100 dseg->lkey = cpu_to_le32(sg->lkey); 101 dseg->addr = cpu_to_le64(sg->addr); 102 dseg->len = cpu_to_le32(sg->length); 103 } 104 105 /* 106 * mapped-value = 1 + real-value 107 * The hns wr opcode real value is start from 0, In order to distinguish between 108 * initialized and uninitialized map values, we plus 1 to the actual value when 109 * defining the mapping, so that the validity can be identified by checking the 110 * mapped value is greater than 0. 111 */ 112 #define HR_OPC_MAP(ib_key, hr_key) \ 113 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 114 115 static const u32 hns_roce_op_code[] = { 116 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 117 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 118 HR_OPC_MAP(SEND, SEND), 119 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 120 HR_OPC_MAP(RDMA_READ, RDMA_READ), 121 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 122 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 123 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 124 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 125 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 126 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 127 }; 128 129 static u32 to_hr_opcode(u32 ib_opcode) 130 { 131 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 132 return HNS_ROCE_V2_WQE_OP_MASK; 133 134 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 135 HNS_ROCE_V2_WQE_OP_MASK; 136 } 137 138 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 139 const struct ib_reg_wr *wr) 140 { 141 struct hns_roce_wqe_frmr_seg *fseg = 142 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 143 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 144 u64 pbl_ba; 145 146 /* use ib_access_flags */ 147 hr_reg_write_bool(fseg, FRMR_BIND_EN, 0); 148 hr_reg_write_bool(fseg, FRMR_ATOMIC, 149 wr->access & IB_ACCESS_REMOTE_ATOMIC); 150 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 151 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 152 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 153 154 /* Data structure reuse may lead to confusion */ 155 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 156 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 157 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 158 159 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 160 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 161 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 162 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 163 164 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 165 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 166 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 167 hr_reg_clear(fseg, FRMR_BLK_MODE); 168 hr_reg_clear(fseg, FRMR_BLOCK_SIZE); 169 hr_reg_clear(fseg, FRMR_ZBVA); 170 } 171 172 static void set_atomic_seg(const struct ib_send_wr *wr, 173 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 174 unsigned int valid_num_sge) 175 { 176 struct hns_roce_v2_wqe_data_seg *dseg = 177 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 178 struct hns_roce_wqe_atomic_seg *aseg = 179 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 180 181 set_data_seg_v2(dseg, wr->sg_list); 182 183 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 184 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 185 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 186 } else { 187 aseg->fetchadd_swap_data = 188 cpu_to_le64(atomic_wr(wr)->compare_add); 189 aseg->cmp_data = 0; 190 } 191 192 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 193 } 194 195 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 196 const struct ib_send_wr *wr, 197 unsigned int *sge_idx, u32 msg_len) 198 { 199 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 200 unsigned int left_len_in_pg; 201 unsigned int idx = *sge_idx; 202 unsigned int i = 0; 203 unsigned int len; 204 void *addr; 205 void *dseg; 206 207 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 208 ibdev_err(ibdev, 209 "no enough extended sge space for inline data.\n"); 210 return -EINVAL; 211 } 212 213 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 214 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 215 len = wr->sg_list[0].length; 216 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 217 218 /* When copying data to extended sge space, the left length in page may 219 * not long enough for current user's sge. So the data should be 220 * splited into several parts, one in the first page, and the others in 221 * the subsequent pages. 222 */ 223 while (1) { 224 if (len <= left_len_in_pg) { 225 memcpy(dseg, addr, len); 226 227 idx += len / HNS_ROCE_SGE_SIZE; 228 229 i++; 230 if (i >= wr->num_sge) 231 break; 232 233 left_len_in_pg -= len; 234 len = wr->sg_list[i].length; 235 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 236 dseg += len; 237 } else { 238 memcpy(dseg, addr, left_len_in_pg); 239 240 len -= left_len_in_pg; 241 addr += left_len_in_pg; 242 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 243 dseg = hns_roce_get_extend_sge(qp, 244 idx & (qp->sge.sge_cnt - 1)); 245 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 246 } 247 } 248 249 *sge_idx = idx; 250 251 return 0; 252 } 253 254 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 255 unsigned int *sge_ind, unsigned int cnt) 256 { 257 struct hns_roce_v2_wqe_data_seg *dseg; 258 unsigned int idx = *sge_ind; 259 260 while (cnt > 0) { 261 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 262 if (likely(sge->length)) { 263 set_data_seg_v2(dseg, sge); 264 idx++; 265 cnt--; 266 } 267 sge++; 268 } 269 270 *sge_ind = idx; 271 } 272 273 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 274 { 275 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 276 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 277 278 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 279 ibdev_err(&hr_dev->ib_dev, 280 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 281 len, qp->max_inline_data, mtu); 282 return false; 283 } 284 285 return true; 286 } 287 288 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 289 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 290 unsigned int *sge_idx) 291 { 292 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 293 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 294 struct ib_device *ibdev = &hr_dev->ib_dev; 295 unsigned int curr_idx = *sge_idx; 296 void *dseg = rc_sq_wqe; 297 unsigned int i; 298 int ret; 299 300 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 301 ibdev_err(ibdev, "invalid inline parameters!\n"); 302 return -EINVAL; 303 } 304 305 if (!check_inl_data_len(qp, msg_len)) 306 return -EINVAL; 307 308 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 309 310 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 311 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 312 313 for (i = 0; i < wr->num_sge; i++) { 314 memcpy(dseg, ((void *)wr->sg_list[i].addr), 315 wr->sg_list[i].length); 316 dseg += wr->sg_list[i].length; 317 } 318 } else { 319 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 320 321 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 322 if (ret) 323 return ret; 324 325 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 326 } 327 328 *sge_idx = curr_idx; 329 330 return 0; 331 } 332 333 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 334 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 335 unsigned int *sge_ind, 336 unsigned int valid_num_sge) 337 { 338 struct hns_roce_v2_wqe_data_seg *dseg = 339 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 340 struct hns_roce_qp *qp = to_hr_qp(ibqp); 341 int j = 0; 342 int i; 343 344 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 345 !!(wr->send_flags & IB_SEND_INLINE)); 346 if (wr->send_flags & IB_SEND_INLINE) 347 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 348 349 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 350 for (i = 0; i < wr->num_sge; i++) { 351 if (likely(wr->sg_list[i].length)) { 352 set_data_seg_v2(dseg, wr->sg_list + i); 353 dseg++; 354 } 355 } 356 } else { 357 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 358 if (likely(wr->sg_list[i].length)) { 359 set_data_seg_v2(dseg, wr->sg_list + i); 360 dseg++; 361 j++; 362 } 363 } 364 365 set_extend_sge(qp, wr->sg_list + i, sge_ind, 366 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 367 } 368 369 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 370 371 return 0; 372 } 373 374 static int check_send_valid(struct hns_roce_dev *hr_dev, 375 struct hns_roce_qp *hr_qp) 376 { 377 if (unlikely(hr_qp->state == IB_QPS_RESET || 378 hr_qp->state == IB_QPS_INIT || 379 hr_qp->state == IB_QPS_RTR)) 380 return -EINVAL; 381 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 382 return -EIO; 383 384 return 0; 385 } 386 387 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 388 unsigned int *sge_len) 389 { 390 unsigned int valid_num = 0; 391 unsigned int len = 0; 392 int i; 393 394 for (i = 0; i < wr->num_sge; i++) { 395 if (likely(wr->sg_list[i].length)) { 396 len += wr->sg_list[i].length; 397 valid_num++; 398 } 399 } 400 401 *sge_len = len; 402 return valid_num; 403 } 404 405 static __le32 get_immtdata(const struct ib_send_wr *wr) 406 { 407 switch (wr->opcode) { 408 case IB_WR_SEND_WITH_IMM: 409 case IB_WR_RDMA_WRITE_WITH_IMM: 410 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 411 default: 412 return 0; 413 } 414 } 415 416 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 417 const struct ib_send_wr *wr) 418 { 419 u32 ib_op = wr->opcode; 420 421 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 422 return -EINVAL; 423 424 ud_sq_wqe->immtdata = get_immtdata(wr); 425 426 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 427 428 return 0; 429 } 430 431 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 432 struct hns_roce_ah *ah) 433 { 434 struct ib_device *ib_dev = ah->ibah.device; 435 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 436 437 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 441 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 442 443 ud_sq_wqe->sgid_index = ah->av.gid_index; 444 445 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 446 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 447 448 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 449 return 0; 450 451 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 452 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 453 454 return 0; 455 } 456 457 static inline int set_ud_wqe(struct hns_roce_qp *qp, 458 const struct ib_send_wr *wr, 459 void *wqe, unsigned int *sge_idx, 460 unsigned int owner_bit) 461 { 462 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 463 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 464 unsigned int curr_idx = *sge_idx; 465 unsigned int valid_num_sge; 466 u32 msg_len = 0; 467 int ret; 468 469 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 470 471 ret = set_ud_opcode(ud_sq_wqe, wr); 472 if (WARN_ON_ONCE(ret)) 473 return ret; 474 475 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 476 477 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 478 !!(wr->send_flags & IB_SEND_SIGNALED)); 479 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 480 !!(wr->send_flags & IB_SEND_SOLICITED)); 481 482 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 483 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 484 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 485 curr_idx & (qp->sge.sge_cnt - 1)); 486 487 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 488 qp->qkey : ud_wr(wr)->remote_qkey); 489 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 490 491 ret = fill_ud_av(ud_sq_wqe, ah); 492 if (ret) 493 return ret; 494 495 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 496 497 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 498 499 /* 500 * The pipeline can sequentially post all valid WQEs into WQ buffer, 501 * including new WQEs waiting for the doorbell to update the PI again. 502 * Therefore, the owner bit of WQE MUST be updated after all fields 503 * and extSGEs have been written into DDR instead of cache. 504 */ 505 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 506 dma_wmb(); 507 508 *sge_idx = curr_idx; 509 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 510 511 return 0; 512 } 513 514 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 515 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 516 const struct ib_send_wr *wr) 517 { 518 u32 ib_op = wr->opcode; 519 int ret = 0; 520 521 rc_sq_wqe->immtdata = get_immtdata(wr); 522 523 switch (ib_op) { 524 case IB_WR_RDMA_READ: 525 case IB_WR_RDMA_WRITE: 526 case IB_WR_RDMA_WRITE_WITH_IMM: 527 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 528 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 529 break; 530 case IB_WR_SEND: 531 case IB_WR_SEND_WITH_IMM: 532 break; 533 case IB_WR_ATOMIC_CMP_AND_SWP: 534 case IB_WR_ATOMIC_FETCH_AND_ADD: 535 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 536 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 537 break; 538 case IB_WR_REG_MR: 539 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 540 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 541 else 542 ret = -EOPNOTSUPP; 543 break; 544 case IB_WR_SEND_WITH_INV: 545 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 546 break; 547 default: 548 ret = -EINVAL; 549 } 550 551 if (unlikely(ret)) 552 return ret; 553 554 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 555 556 return ret; 557 } 558 559 static inline int set_rc_wqe(struct hns_roce_qp *qp, 560 const struct ib_send_wr *wr, 561 void *wqe, unsigned int *sge_idx, 562 unsigned int owner_bit) 563 { 564 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 565 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 566 unsigned int curr_idx = *sge_idx; 567 unsigned int valid_num_sge; 568 u32 msg_len = 0; 569 int ret; 570 571 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 572 573 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 574 575 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 576 if (WARN_ON_ONCE(ret)) 577 return ret; 578 579 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO, 580 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 581 582 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 583 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 584 585 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 586 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 587 588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 589 curr_idx & (qp->sge.sge_cnt - 1)); 590 591 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 592 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 593 if (msg_len != ATOMIC_WR_LEN) 594 return -EINVAL; 595 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 596 } else if (wr->opcode != IB_WR_REG_MR) { 597 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 598 &curr_idx, valid_num_sge); 599 if (ret) 600 return ret; 601 } 602 603 /* 604 * The pipeline can sequentially post all valid WQEs into WQ buffer, 605 * including new WQEs waiting for the doorbell to update the PI again. 606 * Therefore, the owner bit of WQE MUST be updated after all fields 607 * and extSGEs have been written into DDR instead of cache. 608 */ 609 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 610 dma_wmb(); 611 612 *sge_idx = curr_idx; 613 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 614 615 return ret; 616 } 617 618 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 619 struct hns_roce_qp *qp) 620 { 621 if (unlikely(qp->state == IB_QPS_ERR)) { 622 flush_cqe(hr_dev, qp); 623 } else { 624 struct hns_roce_v2_db sq_db = {}; 625 626 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 627 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 628 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 629 hr_reg_write(&sq_db, DB_SL, qp->sl); 630 631 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 632 } 633 } 634 635 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 636 struct hns_roce_qp *qp) 637 { 638 if (unlikely(qp->state == IB_QPS_ERR)) { 639 flush_cqe(hr_dev, qp); 640 } else { 641 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 642 *qp->rdb.db_record = 643 qp->rq.head & V2_DB_PRODUCER_IDX_M; 644 } else { 645 struct hns_roce_v2_db rq_db = {}; 646 647 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 648 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 649 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 650 651 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 652 qp->rq.db_reg); 653 } 654 } 655 } 656 657 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 658 u64 __iomem *dest) 659 { 660 #define HNS_ROCE_WRITE_TIMES 8 661 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 662 struct hnae3_handle *handle = priv->handle; 663 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 664 int i; 665 666 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 667 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 668 writeq_relaxed(*(val + i), dest + i); 669 } 670 671 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 672 void *wqe) 673 { 674 #define HNS_ROCE_SL_SHIFT 2 675 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 676 677 if (unlikely(qp->state == IB_QPS_ERR)) { 678 flush_cqe(hr_dev, qp); 679 return; 680 } 681 /* All kinds of DirectWQE have the same header field layout */ 682 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 684 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 685 qp->sl >> HNS_ROCE_SL_SHIFT); 686 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 687 688 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 689 } 690 691 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 692 const struct ib_send_wr *wr, 693 const struct ib_send_wr **bad_wr) 694 { 695 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 696 struct ib_device *ibdev = &hr_dev->ib_dev; 697 struct hns_roce_qp *qp = to_hr_qp(ibqp); 698 unsigned long flags = 0; 699 unsigned int owner_bit; 700 unsigned int sge_idx; 701 unsigned int wqe_idx; 702 void *wqe = NULL; 703 u32 nreq; 704 int ret; 705 706 spin_lock_irqsave(&qp->sq.lock, flags); 707 708 ret = check_send_valid(hr_dev, qp); 709 if (unlikely(ret)) { 710 *bad_wr = wr; 711 nreq = 0; 712 goto out; 713 } 714 715 sge_idx = qp->next_sge; 716 717 for (nreq = 0; wr; ++nreq, wr = wr->next) { 718 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 719 ret = -ENOMEM; 720 *bad_wr = wr; 721 goto out; 722 } 723 724 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 725 726 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 727 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 728 wr->num_sge, qp->sq.max_gs); 729 ret = -EINVAL; 730 *bad_wr = wr; 731 goto out; 732 } 733 734 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 735 qp->sq.wrid[wqe_idx] = wr->wr_id; 736 owner_bit = 737 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 738 739 /* RC and UD share the same DirectWQE field layout */ 740 ((struct hns_roce_v2_rc_send_wqe *)wqe)->byte_4 = 0; 741 742 /* Corresponding to the QP type, wqe process separately */ 743 if (ibqp->qp_type == IB_QPT_RC) 744 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 745 else 746 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 747 748 trace_hns_sq_wqe(qp->qpn, wqe_idx, wqe, 1 << qp->sq.wqe_shift, 749 wr->wr_id, TRACE_SQ); 750 if (unlikely(ret)) { 751 *bad_wr = wr; 752 goto out; 753 } 754 } 755 756 out: 757 if (likely(nreq)) { 758 qp->sq.head += nreq; 759 qp->next_sge = sge_idx; 760 761 if (nreq == 1 && !ret && 762 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 763 write_dwqe(hr_dev, qp, wqe); 764 else 765 update_sq_db(hr_dev, qp); 766 } 767 768 spin_unlock_irqrestore(&qp->sq.lock, flags); 769 770 return ret; 771 } 772 773 static int check_recv_valid(struct hns_roce_dev *hr_dev, 774 struct hns_roce_qp *hr_qp) 775 { 776 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 777 return -EIO; 778 779 if (hr_qp->state == IB_QPS_RESET) 780 return -EINVAL; 781 782 return 0; 783 } 784 785 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 786 u32 max_sge, bool rsv) 787 { 788 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 789 u32 i, cnt; 790 791 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 792 /* Skip zero-length sge */ 793 if (!wr->sg_list[i].length) 794 continue; 795 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 796 cnt++; 797 } 798 799 /* Fill a reserved sge to make hw stop reading remaining segments */ 800 if (rsv) { 801 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 802 dseg[cnt].addr = 0; 803 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 804 } else { 805 /* Clear remaining segments to make ROCEE ignore sges */ 806 if (cnt < max_sge) 807 memset(dseg + cnt, 0, 808 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 809 } 810 } 811 812 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 813 u32 wqe_idx, u32 max_sge) 814 { 815 void *wqe = NULL; 816 817 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 818 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 819 820 trace_hns_rq_wqe(hr_qp->qpn, wqe_idx, wqe, 1 << hr_qp->rq.wqe_shift, 821 wr->wr_id, TRACE_RQ); 822 } 823 824 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 825 const struct ib_recv_wr *wr, 826 const struct ib_recv_wr **bad_wr) 827 { 828 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 829 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 830 struct ib_device *ibdev = &hr_dev->ib_dev; 831 u32 wqe_idx, nreq, max_sge; 832 unsigned long flags; 833 int ret; 834 835 spin_lock_irqsave(&hr_qp->rq.lock, flags); 836 837 ret = check_recv_valid(hr_dev, hr_qp); 838 if (unlikely(ret)) { 839 *bad_wr = wr; 840 nreq = 0; 841 goto out; 842 } 843 844 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 845 for (nreq = 0; wr; ++nreq, wr = wr->next) { 846 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 847 hr_qp->ibqp.recv_cq))) { 848 ret = -ENOMEM; 849 *bad_wr = wr; 850 goto out; 851 } 852 853 if (unlikely(wr->num_sge > max_sge)) { 854 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 855 wr->num_sge, max_sge); 856 ret = -EINVAL; 857 *bad_wr = wr; 858 goto out; 859 } 860 861 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 862 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 863 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 864 } 865 866 out: 867 if (likely(nreq)) { 868 hr_qp->rq.head += nreq; 869 870 update_rq_db(hr_dev, hr_qp); 871 } 872 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 873 874 return ret; 875 } 876 877 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 878 { 879 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 880 } 881 882 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 883 { 884 return hns_roce_buf_offset(idx_que->mtr.kmem, 885 n << idx_que->entry_shift); 886 } 887 888 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 889 { 890 /* always called with interrupts disabled. */ 891 spin_lock(&srq->lock); 892 893 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 894 srq->idx_que.tail++; 895 896 spin_unlock(&srq->lock); 897 } 898 899 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 900 { 901 struct hns_roce_idx_que *idx_que = &srq->idx_que; 902 903 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 904 } 905 906 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 907 const struct ib_recv_wr *wr) 908 { 909 struct ib_device *ib_dev = srq->ibsrq.device; 910 911 if (unlikely(wr->num_sge > max_sge)) { 912 ibdev_err(ib_dev, 913 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 914 wr->num_sge, max_sge); 915 return -EINVAL; 916 } 917 918 if (unlikely(hns_roce_srqwq_overflow(srq))) { 919 ibdev_err(ib_dev, 920 "failed to check srqwq status, srqwq is full.\n"); 921 return -ENOMEM; 922 } 923 924 return 0; 925 } 926 927 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 928 { 929 struct hns_roce_idx_que *idx_que = &srq->idx_que; 930 u32 pos; 931 932 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 933 if (unlikely(pos == srq->wqe_cnt)) 934 return -ENOSPC; 935 936 bitmap_set(idx_que->bitmap, pos, 1); 937 *wqe_idx = pos; 938 return 0; 939 } 940 941 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 942 { 943 struct hns_roce_idx_que *idx_que = &srq->idx_que; 944 unsigned int head; 945 __le32 *buf; 946 947 head = idx_que->head & (srq->wqe_cnt - 1); 948 949 buf = get_idx_buf(idx_que, head); 950 *buf = cpu_to_le32(wqe_idx); 951 952 idx_que->head++; 953 } 954 955 static void update_srq_db(struct hns_roce_srq *srq) 956 { 957 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 958 struct hns_roce_v2_db db = {}; 959 960 hr_reg_write(&db, DB_TAG, srq->srqn); 961 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 962 hr_reg_write(&db, DB_PI, srq->idx_que.head); 963 964 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 965 } 966 967 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 968 const struct ib_recv_wr *wr, 969 const struct ib_recv_wr **bad_wr) 970 { 971 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 972 unsigned long flags; 973 int ret = 0; 974 u32 max_sge; 975 u32 wqe_idx; 976 void *wqe; 977 u32 nreq; 978 979 spin_lock_irqsave(&srq->lock, flags); 980 981 max_sge = srq->max_gs - srq->rsv_sge; 982 for (nreq = 0; wr; ++nreq, wr = wr->next) { 983 ret = check_post_srq_valid(srq, max_sge, wr); 984 if (ret) { 985 *bad_wr = wr; 986 break; 987 } 988 989 ret = get_srq_wqe_idx(srq, &wqe_idx); 990 if (unlikely(ret)) { 991 *bad_wr = wr; 992 break; 993 } 994 995 wqe = get_srq_wqe_buf(srq, wqe_idx); 996 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 997 fill_wqe_idx(srq, wqe_idx); 998 srq->wrid[wqe_idx] = wr->wr_id; 999 1000 trace_hns_srq_wqe(srq->srqn, wqe_idx, wqe, 1 << srq->wqe_shift, 1001 wr->wr_id, TRACE_SRQ); 1002 } 1003 1004 if (likely(nreq)) { 1005 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 1006 *srq->rdb.db_record = srq->idx_que.head & 1007 V2_DB_PRODUCER_IDX_M; 1008 else 1009 update_srq_db(srq); 1010 } 1011 1012 spin_unlock_irqrestore(&srq->lock, flags); 1013 1014 return ret; 1015 } 1016 1017 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1018 unsigned long instance_stage, 1019 unsigned long reset_stage) 1020 { 1021 /* When hardware reset has been completed once or more, we should stop 1022 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1023 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1024 * stage of soft reset process, we should exit with error, and then 1025 * HNAE3_INIT_CLIENT related process can rollback the operation like 1026 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1027 * process will exit with error to notify NIC driver to reschedule soft 1028 * reset process once again. 1029 */ 1030 hr_dev->is_reset = true; 1031 hr_dev->dis_db = true; 1032 1033 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1034 instance_stage == HNS_ROCE_STATE_INIT) 1035 return CMD_RST_PRC_EBUSY; 1036 1037 return CMD_RST_PRC_SUCCESS; 1038 } 1039 1040 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1041 unsigned long instance_stage, 1042 unsigned long reset_stage) 1043 { 1044 #define HW_RESET_TIMEOUT_US 1000000 1045 #define HW_RESET_SLEEP_US 1000 1046 1047 struct hns_roce_v2_priv *priv = hr_dev->priv; 1048 struct hnae3_handle *handle = priv->handle; 1049 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1050 unsigned long val; 1051 int ret; 1052 1053 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1054 * doorbell to hardware. If now in .init_instance() function, we should 1055 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1056 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1057 * related process can rollback the operation like notifing hardware to 1058 * free resources, HNAE3_INIT_CLIENT related process will exit with 1059 * error to notify NIC driver to reschedule soft reset process once 1060 * again. 1061 */ 1062 hr_dev->dis_db = true; 1063 1064 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1065 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1066 HW_RESET_TIMEOUT_US, false, handle); 1067 if (!ret) 1068 hr_dev->is_reset = true; 1069 1070 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1071 instance_stage == HNS_ROCE_STATE_INIT) 1072 return CMD_RST_PRC_EBUSY; 1073 1074 return CMD_RST_PRC_SUCCESS; 1075 } 1076 1077 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1078 { 1079 struct hns_roce_v2_priv *priv = hr_dev->priv; 1080 struct hnae3_handle *handle = priv->handle; 1081 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1082 1083 /* When software reset is detected at .init_instance() function, we 1084 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1085 * with error. 1086 */ 1087 hr_dev->dis_db = true; 1088 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1089 hr_dev->is_reset = true; 1090 1091 return CMD_RST_PRC_EBUSY; 1092 } 1093 1094 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1095 struct hnae3_handle *handle) 1096 { 1097 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1098 unsigned long instance_stage; /* the current instance stage */ 1099 unsigned long reset_stage; /* the current reset stage */ 1100 unsigned long reset_cnt; 1101 bool sw_resetting; 1102 bool hw_resetting; 1103 1104 /* Get information about reset from NIC driver or RoCE driver itself, 1105 * the meaning of the following variables from NIC driver are described 1106 * as below: 1107 * reset_cnt -- The count value of completed hardware reset. 1108 * hw_resetting -- Whether hardware device is resetting now. 1109 * sw_resetting -- Whether NIC's software reset process is running now. 1110 */ 1111 instance_stage = handle->rinfo.instance_state; 1112 reset_stage = handle->rinfo.reset_state; 1113 reset_cnt = ops->ae_dev_reset_cnt(handle); 1114 if (reset_cnt != hr_dev->reset_cnt) 1115 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1116 reset_stage); 1117 1118 hw_resetting = ops->get_cmdq_stat(handle); 1119 if (hw_resetting) 1120 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1121 reset_stage); 1122 1123 sw_resetting = ops->ae_dev_resetting(handle); 1124 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1125 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1126 1127 return CMD_RST_PRC_OTHERS; 1128 } 1129 1130 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1131 { 1132 struct hns_roce_v2_priv *priv = hr_dev->priv; 1133 struct hnae3_handle *handle = priv->handle; 1134 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1135 1136 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1137 return true; 1138 1139 if (ops->get_hw_reset_stat(handle)) 1140 return true; 1141 1142 if (ops->ae_dev_resetting(handle)) 1143 return true; 1144 1145 return false; 1146 } 1147 1148 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1149 { 1150 struct hns_roce_v2_priv *priv = hr_dev->priv; 1151 u32 status; 1152 1153 if (hr_dev->is_reset) 1154 status = CMD_RST_PRC_SUCCESS; 1155 else 1156 status = check_aedev_reset_status(hr_dev, priv->handle); 1157 1158 *busy = (status == CMD_RST_PRC_EBUSY); 1159 1160 return status == CMD_RST_PRC_OTHERS; 1161 } 1162 1163 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1164 struct hns_roce_v2_cmq_ring *ring) 1165 { 1166 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1167 1168 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1169 &ring->desc_dma_addr, GFP_KERNEL); 1170 if (!ring->desc) 1171 return -ENOMEM; 1172 1173 return 0; 1174 } 1175 1176 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1177 struct hns_roce_v2_cmq_ring *ring) 1178 { 1179 dma_free_coherent(hr_dev->dev, 1180 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1181 ring->desc, ring->desc_dma_addr); 1182 1183 ring->desc_dma_addr = 0; 1184 } 1185 1186 static int init_csq(struct hns_roce_dev *hr_dev, 1187 struct hns_roce_v2_cmq_ring *csq) 1188 { 1189 dma_addr_t dma; 1190 int ret; 1191 1192 csq->desc_num = CMD_CSQ_DESC_NUM; 1193 spin_lock_init(&csq->lock); 1194 csq->flag = TYPE_CSQ; 1195 csq->head = 0; 1196 1197 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1198 if (ret) 1199 return ret; 1200 1201 dma = csq->desc_dma_addr; 1202 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1203 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1204 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1205 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1206 1207 /* Make sure to write CI first and then PI */ 1208 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1209 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1210 1211 return 0; 1212 } 1213 1214 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1215 { 1216 struct hns_roce_v2_priv *priv = hr_dev->priv; 1217 int ret; 1218 1219 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1220 1221 ret = init_csq(hr_dev, &priv->cmq.csq); 1222 if (ret) 1223 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1224 1225 return ret; 1226 } 1227 1228 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1229 { 1230 struct hns_roce_v2_priv *priv = hr_dev->priv; 1231 1232 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1233 } 1234 1235 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1236 enum hns_roce_opcode_type opcode, 1237 bool is_read) 1238 { 1239 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1240 desc->opcode = cpu_to_le16(opcode); 1241 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1242 if (is_read) 1243 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1244 else 1245 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1246 } 1247 1248 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1249 { 1250 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1251 struct hns_roce_v2_priv *priv = hr_dev->priv; 1252 1253 return tail == priv->cmq.csq.head; 1254 } 1255 1256 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1257 { 1258 struct hns_roce_v2_priv *priv = hr_dev->priv; 1259 struct hnae3_handle *handle = priv->handle; 1260 1261 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1262 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1263 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1264 } 1265 1266 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1267 { 1268 struct hns_roce_cmd_errcode errcode_table[] = { 1269 {CMD_EXEC_SUCCESS, 0}, 1270 {CMD_NO_AUTH, -EPERM}, 1271 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1272 {CMD_CRQ_FULL, -EXFULL}, 1273 {CMD_NEXT_ERR, -ENOSR}, 1274 {CMD_NOT_EXEC, -ENOTBLK}, 1275 {CMD_PARA_ERR, -EINVAL}, 1276 {CMD_RESULT_ERR, -ERANGE}, 1277 {CMD_TIMEOUT, -ETIME}, 1278 {CMD_HILINK_ERR, -ENOLINK}, 1279 {CMD_INFO_ILLEGAL, -ENXIO}, 1280 {CMD_INVALID, -EBADR}, 1281 }; 1282 u16 i; 1283 1284 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1285 if (desc_ret == errcode_table[i].return_status) 1286 return errcode_table[i].errno; 1287 return -EIO; 1288 } 1289 1290 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 1291 { 1292 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = { 1293 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT}, 1294 }; 1295 int i; 1296 1297 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++) 1298 if (cmdq_tx_timeout[i].opcode == opcode) 1299 return cmdq_tx_timeout[i].tx_timeout; 1300 1301 return tx_timeout; 1302 } 1303 1304 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout) 1305 { 1306 u32 timeout = 0; 1307 1308 do { 1309 if (hns_roce_cmq_csq_done(hr_dev)) 1310 break; 1311 udelay(1); 1312 } while (++timeout < tx_timeout); 1313 } 1314 1315 static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev, 1316 struct hns_roce_cmq_desc *desc, 1317 int num, u32 tx_timeout) 1318 { 1319 struct hns_roce_v2_priv *priv = hr_dev->priv; 1320 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1321 u16 desc_ret; 1322 u32 tail; 1323 int ret; 1324 int i; 1325 1326 tail = csq->head; 1327 1328 for (i = 0; i < num; i++) { 1329 trace_hns_cmdq_req(hr_dev, &desc[i]); 1330 1331 csq->desc[csq->head++] = desc[i]; 1332 if (csq->head == csq->desc_num) 1333 csq->head = 0; 1334 } 1335 1336 /* Write to hardware */ 1337 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1338 1339 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1340 1341 hns_roce_wait_csq_done(hr_dev, tx_timeout); 1342 if (hns_roce_cmq_csq_done(hr_dev)) { 1343 ret = 0; 1344 for (i = 0; i < num; i++) { 1345 trace_hns_cmdq_resp(hr_dev, &csq->desc[tail]); 1346 1347 /* check the result of hardware write back */ 1348 desc_ret = le16_to_cpu(csq->desc[tail++].retval); 1349 if (tail == csq->desc_num) 1350 tail = 0; 1351 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1352 continue; 1353 1354 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1355 } 1356 } else { 1357 /* FW/HW reset or incorrect number of desc */ 1358 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1359 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1360 csq->head, tail); 1361 csq->head = tail; 1362 1363 update_cmdq_status(hr_dev); 1364 1365 ret = -EAGAIN; 1366 } 1367 1368 if (ret) 1369 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1370 1371 return ret; 1372 } 1373 1374 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1375 struct hns_roce_cmq_desc *desc, int num) 1376 { 1377 struct hns_roce_v2_priv *priv = hr_dev->priv; 1378 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1379 u16 opcode = le16_to_cpu(desc->opcode); 1380 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout); 1381 u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT; 1382 u32 rsv_tail; 1383 int ret; 1384 int i; 1385 1386 while (try_cnt) { 1387 try_cnt--; 1388 1389 spin_lock_bh(&csq->lock); 1390 rsv_tail = csq->head; 1391 ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout); 1392 if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME && 1393 try_cnt) { 1394 spin_unlock_bh(&csq->lock); 1395 mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC); 1396 continue; 1397 } 1398 1399 for (i = 0; i < num; i++) { 1400 desc[i] = csq->desc[rsv_tail++]; 1401 if (rsv_tail == csq->desc_num) 1402 rsv_tail = 0; 1403 } 1404 spin_unlock_bh(&csq->lock); 1405 break; 1406 } 1407 1408 if (ret) 1409 dev_err_ratelimited(hr_dev->dev, 1410 "Cmdq IO error, opcode = 0x%x, return = %d.\n", 1411 opcode, ret); 1412 1413 return ret; 1414 } 1415 1416 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1417 struct hns_roce_cmq_desc *desc, int num) 1418 { 1419 bool busy; 1420 int ret; 1421 1422 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1423 return -EIO; 1424 1425 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1426 return busy ? -EBUSY : 0; 1427 1428 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1429 if (ret) { 1430 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1431 return busy ? -EBUSY : 0; 1432 } 1433 1434 return ret; 1435 } 1436 1437 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1438 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1439 { 1440 struct hns_roce_cmd_mailbox *mbox; 1441 int ret; 1442 1443 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1444 if (IS_ERR(mbox)) 1445 return PTR_ERR(mbox); 1446 1447 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1448 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1449 return ret; 1450 } 1451 1452 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1453 { 1454 struct hns_roce_query_version *resp; 1455 struct hns_roce_cmq_desc desc; 1456 int ret; 1457 1458 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1459 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1460 if (ret) 1461 return ret; 1462 1463 resp = (struct hns_roce_query_version *)desc.data; 1464 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1465 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1466 1467 return 0; 1468 } 1469 1470 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1471 struct hnae3_handle *handle) 1472 { 1473 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1474 unsigned long end; 1475 1476 hr_dev->dis_db = true; 1477 1478 dev_warn(hr_dev->dev, 1479 "func clear is pending, device in resetting state.\n"); 1480 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1481 while (end) { 1482 if (!ops->get_hw_reset_stat(handle)) { 1483 hr_dev->is_reset = true; 1484 dev_info(hr_dev->dev, 1485 "func clear success after reset.\n"); 1486 return; 1487 } 1488 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1489 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1490 } 1491 1492 dev_warn(hr_dev->dev, "func clear failed.\n"); 1493 } 1494 1495 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1496 struct hnae3_handle *handle) 1497 { 1498 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1499 unsigned long end; 1500 1501 hr_dev->dis_db = true; 1502 1503 dev_warn(hr_dev->dev, 1504 "func clear is pending, device in resetting state.\n"); 1505 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1506 while (end) { 1507 if (ops->ae_dev_reset_cnt(handle) != 1508 hr_dev->reset_cnt) { 1509 hr_dev->is_reset = true; 1510 dev_info(hr_dev->dev, 1511 "func clear success after sw reset\n"); 1512 return; 1513 } 1514 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1515 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1516 } 1517 1518 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1519 } 1520 1521 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1522 int flag) 1523 { 1524 struct hns_roce_v2_priv *priv = hr_dev->priv; 1525 struct hnae3_handle *handle = priv->handle; 1526 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1527 1528 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1529 hr_dev->dis_db = true; 1530 hr_dev->is_reset = true; 1531 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1532 return; 1533 } 1534 1535 if (ops->get_hw_reset_stat(handle)) { 1536 func_clr_hw_resetting_state(hr_dev, handle); 1537 return; 1538 } 1539 1540 if (ops->ae_dev_resetting(handle) && 1541 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1542 func_clr_sw_resetting_state(hr_dev, handle); 1543 return; 1544 } 1545 1546 if (retval && !flag) 1547 dev_warn(hr_dev->dev, 1548 "func clear read failed, ret = %d.\n", retval); 1549 1550 dev_warn(hr_dev->dev, "func clear failed.\n"); 1551 } 1552 1553 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1554 { 1555 bool fclr_write_fail_flag = false; 1556 struct hns_roce_func_clear *resp; 1557 struct hns_roce_cmq_desc desc; 1558 unsigned long end; 1559 int ret = 0; 1560 1561 if (check_device_is_in_reset(hr_dev)) 1562 goto out; 1563 1564 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1565 resp = (struct hns_roce_func_clear *)desc.data; 1566 resp->rst_funcid_en = cpu_to_le32(vf_id); 1567 1568 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1569 if (ret) { 1570 fclr_write_fail_flag = true; 1571 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1572 ret); 1573 goto out; 1574 } 1575 1576 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1577 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1578 while (end) { 1579 if (check_device_is_in_reset(hr_dev)) 1580 goto out; 1581 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1582 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1583 1584 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1585 true); 1586 1587 resp->rst_funcid_en = cpu_to_le32(vf_id); 1588 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1589 if (ret) 1590 continue; 1591 1592 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1593 if (vf_id == 0) 1594 hr_dev->is_reset = true; 1595 return; 1596 } 1597 } 1598 1599 out: 1600 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1601 } 1602 1603 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1604 { 1605 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1606 struct hns_roce_cmq_desc desc[2]; 1607 struct hns_roce_cmq_req *req_a; 1608 1609 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1610 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1611 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1612 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1613 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1614 1615 return hns_roce_cmq_send(hr_dev, desc, 2); 1616 } 1617 1618 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1619 { 1620 int ret; 1621 int i; 1622 1623 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1624 return; 1625 1626 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1627 __hns_roce_function_clear(hr_dev, i); 1628 1629 if (i == 0) 1630 continue; 1631 1632 ret = hns_roce_free_vf_resource(hr_dev, i); 1633 if (ret) 1634 ibdev_err(&hr_dev->ib_dev, 1635 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1636 i, ret); 1637 } 1638 } 1639 1640 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1641 { 1642 struct hns_roce_cmq_desc desc; 1643 int ret; 1644 1645 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1646 false); 1647 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1648 if (ret) 1649 ibdev_err(&hr_dev->ib_dev, 1650 "failed to clear extended doorbell info, ret = %d.\n", 1651 ret); 1652 1653 return ret; 1654 } 1655 1656 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1657 { 1658 struct hns_roce_query_fw_info *resp; 1659 struct hns_roce_cmq_desc desc; 1660 int ret; 1661 1662 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1663 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1664 if (ret) 1665 return ret; 1666 1667 resp = (struct hns_roce_query_fw_info *)desc.data; 1668 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1669 1670 return 0; 1671 } 1672 1673 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1674 { 1675 struct hns_roce_cmq_desc desc; 1676 int ret; 1677 1678 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1679 hr_dev->func_num = 1; 1680 return 0; 1681 } 1682 1683 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1684 true); 1685 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1686 if (ret) { 1687 hr_dev->func_num = 1; 1688 return ret; 1689 } 1690 1691 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1692 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1693 1694 return 0; 1695 } 1696 1697 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1698 u64 *stats, u32 port, int *num_counters) 1699 { 1700 #define CNT_PER_DESC 3 1701 struct hns_roce_cmq_desc *desc; 1702 int bd_idx, cnt_idx; 1703 __le64 *cnt_data; 1704 int desc_num; 1705 int ret; 1706 int i; 1707 1708 if (port > hr_dev->caps.num_ports) 1709 return -EINVAL; 1710 1711 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1712 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1713 if (!desc) 1714 return -ENOMEM; 1715 1716 for (i = 0; i < desc_num; i++) { 1717 hns_roce_cmq_setup_basic_desc(&desc[i], 1718 HNS_ROCE_OPC_QUERY_COUNTER, true); 1719 if (i != desc_num - 1) 1720 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1721 } 1722 1723 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1724 if (ret) { 1725 ibdev_err(&hr_dev->ib_dev, 1726 "failed to get counter, ret = %d.\n", ret); 1727 goto err_out; 1728 } 1729 1730 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1731 bd_idx = i / CNT_PER_DESC; 1732 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC && 1733 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT))) 1734 break; 1735 1736 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1737 cnt_idx = i % CNT_PER_DESC; 1738 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1739 } 1740 *num_counters = i; 1741 1742 err_out: 1743 kfree(desc); 1744 return ret; 1745 } 1746 1747 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1748 { 1749 struct hns_roce_cmq_desc desc; 1750 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1751 u32 clock_cycles_of_1us; 1752 1753 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1754 false); 1755 1756 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1757 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1758 else 1759 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1760 1761 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1762 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1763 1764 return hns_roce_cmq_send(hr_dev, &desc, 1); 1765 } 1766 1767 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1768 { 1769 struct hns_roce_cmq_desc desc[2]; 1770 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1771 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1772 struct hns_roce_caps *caps = &hr_dev->caps; 1773 enum hns_roce_opcode_type opcode; 1774 u32 func_num; 1775 int ret; 1776 1777 if (is_vf) { 1778 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1779 func_num = 1; 1780 } else { 1781 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1782 func_num = hr_dev->func_num; 1783 } 1784 1785 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1786 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1787 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1788 1789 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1790 if (ret) 1791 return ret; 1792 1793 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1794 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1795 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1796 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1797 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1798 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1799 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1800 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1801 1802 if (is_vf) { 1803 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1804 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1805 func_num; 1806 } else { 1807 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1808 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1809 func_num; 1810 } 1811 1812 return 0; 1813 } 1814 1815 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1816 { 1817 struct hns_roce_cmq_desc desc; 1818 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1819 struct hns_roce_caps *caps = &hr_dev->caps; 1820 int ret; 1821 1822 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1823 true); 1824 1825 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1826 if (ret) 1827 return ret; 1828 1829 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1830 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1831 1832 return 0; 1833 } 1834 1835 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1836 { 1837 struct device *dev = hr_dev->dev; 1838 int ret; 1839 1840 ret = load_func_res_caps(hr_dev, false); 1841 if (ret) { 1842 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1843 return ret; 1844 } 1845 1846 ret = load_pf_timer_res_caps(hr_dev); 1847 if (ret) 1848 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1849 ret); 1850 1851 return ret; 1852 } 1853 1854 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1855 { 1856 struct device *dev = hr_dev->dev; 1857 int ret; 1858 1859 ret = load_func_res_caps(hr_dev, true); 1860 if (ret) 1861 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1862 1863 return ret; 1864 } 1865 1866 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1867 u32 vf_id) 1868 { 1869 struct hns_roce_vf_switch *swt; 1870 struct hns_roce_cmq_desc desc; 1871 int ret; 1872 1873 swt = (struct hns_roce_vf_switch *)desc.data; 1874 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1875 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1876 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1877 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1878 if (ret) 1879 return ret; 1880 1881 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1882 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1883 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1884 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1885 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1886 1887 return hns_roce_cmq_send(hr_dev, &desc, 1); 1888 } 1889 1890 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1891 { 1892 u32 vf_id; 1893 int ret; 1894 1895 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1896 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1897 if (ret) 1898 return ret; 1899 } 1900 return 0; 1901 } 1902 1903 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1904 { 1905 struct hns_roce_cmq_desc desc[2]; 1906 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1907 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1908 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1909 struct hns_roce_caps *caps = &hr_dev->caps; 1910 1911 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1912 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1913 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1914 1915 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1916 1917 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1918 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1919 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1920 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1921 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1922 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1923 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1924 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1925 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1926 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1927 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1928 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1929 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1930 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1931 1932 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1933 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1934 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1935 vf_id * caps->gmv_bt_num); 1936 } else { 1937 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1938 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1939 vf_id * caps->sgid_bt_num); 1940 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1941 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1942 vf_id * caps->smac_bt_num); 1943 } 1944 1945 return hns_roce_cmq_send(hr_dev, desc, 2); 1946 } 1947 1948 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1949 { 1950 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1951 u32 vf_id; 1952 int ret; 1953 1954 for (vf_id = 0; vf_id < func_num; vf_id++) { 1955 ret = config_vf_hem_resource(hr_dev, vf_id); 1956 if (ret) { 1957 dev_err(hr_dev->dev, 1958 "failed to config vf-%u hem res, ret = %d.\n", 1959 vf_id, ret); 1960 return ret; 1961 } 1962 } 1963 1964 return 0; 1965 } 1966 1967 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1968 { 1969 struct hns_roce_cmq_desc desc; 1970 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1971 struct hns_roce_caps *caps = &hr_dev->caps; 1972 1973 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1974 1975 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1976 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1977 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1978 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1979 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1980 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1981 1982 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1983 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1984 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1985 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1986 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1987 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1988 1989 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1990 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1991 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1992 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1993 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1994 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1995 1996 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1997 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1998 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1999 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 2000 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 2001 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 2002 2003 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 2004 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 2005 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 2006 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 2007 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 2008 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 2009 2010 return hns_roce_cmq_send(hr_dev, &desc, 1); 2011 } 2012 2013 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2014 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2015 { 2016 u64 obj_per_chunk; 2017 u64 bt_chunk_size = PAGE_SIZE; 2018 u64 buf_chunk_size = PAGE_SIZE; 2019 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2020 2021 *buf_page_size = 0; 2022 *bt_page_size = 0; 2023 2024 switch (hop_num) { 2025 case 3: 2026 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2027 (bt_chunk_size / BA_BYTE_LEN) * 2028 (bt_chunk_size / BA_BYTE_LEN) * 2029 obj_per_chunk_default; 2030 break; 2031 case 2: 2032 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2033 (bt_chunk_size / BA_BYTE_LEN) * 2034 obj_per_chunk_default; 2035 break; 2036 case 1: 2037 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2038 obj_per_chunk_default; 2039 break; 2040 case HNS_ROCE_HOP_NUM_0: 2041 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2042 break; 2043 default: 2044 pr_err("table %u not support hop_num = %u!\n", hem_type, 2045 hop_num); 2046 return; 2047 } 2048 2049 if (hem_type >= HEM_TYPE_MTT) 2050 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2051 else 2052 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2053 } 2054 2055 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2056 { 2057 struct hns_roce_caps *caps = &hr_dev->caps; 2058 2059 /* EQ */ 2060 caps->eqe_ba_pg_sz = 0; 2061 caps->eqe_buf_pg_sz = 0; 2062 2063 /* Link Table */ 2064 caps->llm_buf_pg_sz = 0; 2065 2066 /* MR */ 2067 caps->mpt_ba_pg_sz = 0; 2068 caps->mpt_buf_pg_sz = 0; 2069 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2070 caps->pbl_buf_pg_sz = 0; 2071 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2072 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2073 HEM_TYPE_MTPT); 2074 2075 /* QP */ 2076 caps->qpc_ba_pg_sz = 0; 2077 caps->qpc_buf_pg_sz = 0; 2078 caps->qpc_timer_ba_pg_sz = 0; 2079 caps->qpc_timer_buf_pg_sz = 0; 2080 caps->sccc_ba_pg_sz = 0; 2081 caps->sccc_buf_pg_sz = 0; 2082 caps->mtt_ba_pg_sz = 0; 2083 caps->mtt_buf_pg_sz = 0; 2084 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2085 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2086 HEM_TYPE_QPC); 2087 2088 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2089 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2090 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2091 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2092 2093 /* CQ */ 2094 caps->cqc_ba_pg_sz = 0; 2095 caps->cqc_buf_pg_sz = 0; 2096 caps->cqc_timer_ba_pg_sz = 0; 2097 caps->cqc_timer_buf_pg_sz = 0; 2098 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2099 caps->cqe_buf_pg_sz = 0; 2100 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2101 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2102 HEM_TYPE_CQC); 2103 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2104 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2105 2106 /* SRQ */ 2107 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2108 caps->srqc_ba_pg_sz = 0; 2109 caps->srqc_buf_pg_sz = 0; 2110 caps->srqwqe_ba_pg_sz = 0; 2111 caps->srqwqe_buf_pg_sz = 0; 2112 caps->idx_ba_pg_sz = 0; 2113 caps->idx_buf_pg_sz = 0; 2114 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2115 caps->srqc_hop_num, caps->srqc_bt_num, 2116 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2117 HEM_TYPE_SRQC); 2118 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2119 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2120 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2121 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2122 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2123 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2124 } 2125 2126 /* GMV */ 2127 caps->gmv_ba_pg_sz = 0; 2128 caps->gmv_buf_pg_sz = 0; 2129 } 2130 2131 /* Apply all loaded caps before setting to hardware */ 2132 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2133 { 2134 #define MAX_GID_TBL_LEN 256 2135 struct hns_roce_caps *caps = &hr_dev->caps; 2136 struct hns_roce_v2_priv *priv = hr_dev->priv; 2137 2138 /* The following configurations don't need to be got from firmware. */ 2139 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2140 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2141 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2142 2143 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2144 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2145 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2146 2147 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2148 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2149 2150 if (!caps->num_comp_vectors) 2151 caps->num_comp_vectors = 2152 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2153 (u32)priv->handle->rinfo.num_vectors - 2154 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2155 2156 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2157 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2158 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2159 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2160 2161 /* The following configurations will be overwritten */ 2162 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2163 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2164 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2165 2166 /* The following configurations are not got from firmware */ 2167 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2168 2169 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2170 2171 /* It's meaningless to support excessively large gid_table_len, 2172 * as the type of sgid_index in kernel struct ib_global_route 2173 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2174 */ 2175 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2176 caps->gmv_bt_num * 2177 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2178 2179 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2180 caps->gmv_entry_sz); 2181 } else { 2182 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2183 2184 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2185 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2186 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2187 caps->gid_table_len[0] /= func_num; 2188 } 2189 2190 if (hr_dev->is_vf) { 2191 caps->default_aeq_arm_st = 0x3; 2192 caps->default_ceq_arm_st = 0x3; 2193 caps->default_ceq_max_cnt = 0x1; 2194 caps->default_ceq_period = 0x10; 2195 caps->default_aeq_max_cnt = 0x1; 2196 caps->default_aeq_period = 0x10; 2197 } 2198 2199 set_hem_page_size(hr_dev); 2200 } 2201 2202 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2203 { 2204 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM] = {}; 2205 struct hns_roce_caps *caps = &hr_dev->caps; 2206 struct hns_roce_query_pf_caps_a *resp_a; 2207 struct hns_roce_query_pf_caps_b *resp_b; 2208 struct hns_roce_query_pf_caps_c *resp_c; 2209 struct hns_roce_query_pf_caps_d *resp_d; 2210 struct hns_roce_query_pf_caps_e *resp_e; 2211 struct hns_roce_query_pf_caps_f *resp_f; 2212 enum hns_roce_opcode_type cmd; 2213 int ctx_hop_num; 2214 int pbl_hop_num; 2215 int cmd_num; 2216 int ret; 2217 int i; 2218 2219 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2220 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2221 cmd_num = hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 2222 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM_HIP08 : 2223 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; 2224 2225 for (i = 0; i < cmd_num - 1; i++) { 2226 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2227 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2228 } 2229 2230 hns_roce_cmq_setup_basic_desc(&desc[cmd_num - 1], cmd, true); 2231 desc[cmd_num - 1].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2232 2233 ret = hns_roce_cmq_send(hr_dev, desc, cmd_num); 2234 if (ret) 2235 return ret; 2236 2237 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2238 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2239 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2240 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2241 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2242 resp_f = (struct hns_roce_query_pf_caps_f *)desc[5].data; 2243 2244 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2245 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2246 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2247 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2248 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2249 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2250 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2251 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2252 caps->num_other_vectors = resp_a->num_other_vectors; 2253 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2254 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2255 2256 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2257 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2258 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2259 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2260 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2261 caps->idx_entry_sz = resp_b->idx_entry_sz; 2262 caps->sccc_sz = resp_b->sccc_sz; 2263 caps->max_mtu = resp_b->max_mtu; 2264 caps->min_cqes = resp_b->min_cqes; 2265 caps->min_wqes = resp_b->min_wqes; 2266 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2267 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2268 caps->phy_num_uars = resp_b->phy_num_uars; 2269 ctx_hop_num = resp_b->ctx_hop_num; 2270 pbl_hop_num = resp_b->pbl_hop_num; 2271 2272 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2273 2274 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2275 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2276 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2277 2278 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2279 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2280 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2281 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2282 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2283 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2284 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2285 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2286 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2287 2288 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2289 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2290 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2291 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2292 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2293 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2294 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2295 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2296 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2297 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2298 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2299 2300 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2301 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2302 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2303 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2304 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2305 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2306 2307 caps->max_ack_req_msg_len = le32_to_cpu(resp_f->max_ack_req_msg_len); 2308 2309 caps->qpc_hop_num = ctx_hop_num; 2310 caps->sccc_hop_num = ctx_hop_num; 2311 caps->srqc_hop_num = ctx_hop_num; 2312 caps->cqc_hop_num = ctx_hop_num; 2313 caps->mpt_hop_num = ctx_hop_num; 2314 caps->mtt_hop_num = pbl_hop_num; 2315 caps->cqe_hop_num = pbl_hop_num; 2316 caps->srqwqe_hop_num = pbl_hop_num; 2317 caps->idx_hop_num = pbl_hop_num; 2318 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2319 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2320 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2321 2322 if (!(caps->page_size_cap & PAGE_SIZE)) 2323 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2324 2325 if (!hr_dev->is_vf) { 2326 caps->cqe_sz = resp_a->cqe_sz; 2327 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2328 caps->default_aeq_arm_st = 2329 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2330 caps->default_ceq_arm_st = 2331 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2332 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2333 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2334 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2335 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2336 } 2337 2338 return 0; 2339 } 2340 2341 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2342 { 2343 struct hns_roce_cmq_desc desc; 2344 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2345 2346 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2347 false); 2348 2349 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2350 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2351 2352 return hns_roce_cmq_send(hr_dev, &desc, 1); 2353 } 2354 2355 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2356 { 2357 struct hns_roce_caps *caps = &hr_dev->caps; 2358 int ret; 2359 2360 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2361 return 0; 2362 2363 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2364 caps->qpc_sz); 2365 if (ret) { 2366 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2367 return ret; 2368 } 2369 2370 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2371 caps->sccc_sz); 2372 if (ret) 2373 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2374 2375 return ret; 2376 } 2377 2378 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2379 { 2380 struct device *dev = hr_dev->dev; 2381 int ret; 2382 2383 hr_dev->func_num = 1; 2384 2385 ret = hns_roce_query_caps(hr_dev); 2386 if (ret) { 2387 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2388 return ret; 2389 } 2390 2391 ret = hns_roce_query_vf_resource(hr_dev); 2392 if (ret) { 2393 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2394 return ret; 2395 } 2396 2397 apply_func_caps(hr_dev); 2398 2399 ret = hns_roce_v2_set_bt(hr_dev); 2400 if (ret) 2401 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2402 2403 return ret; 2404 } 2405 2406 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2407 { 2408 struct device *dev = hr_dev->dev; 2409 int ret; 2410 2411 ret = hns_roce_query_func_info(hr_dev); 2412 if (ret) { 2413 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2414 return ret; 2415 } 2416 2417 ret = hns_roce_config_global_param(hr_dev); 2418 if (ret) { 2419 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2420 return ret; 2421 } 2422 2423 ret = hns_roce_set_vf_switch_param(hr_dev); 2424 if (ret) { 2425 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2426 return ret; 2427 } 2428 2429 ret = hns_roce_query_caps(hr_dev); 2430 if (ret) { 2431 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2432 return ret; 2433 } 2434 2435 ret = hns_roce_query_pf_resource(hr_dev); 2436 if (ret) { 2437 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2438 return ret; 2439 } 2440 2441 apply_func_caps(hr_dev); 2442 2443 ret = hns_roce_alloc_vf_resource(hr_dev); 2444 if (ret) { 2445 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2446 return ret; 2447 } 2448 2449 ret = hns_roce_v2_set_bt(hr_dev); 2450 if (ret) { 2451 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2452 return ret; 2453 } 2454 2455 /* Configure the size of QPC, SCCC, etc. */ 2456 return hns_roce_config_entry_size(hr_dev); 2457 } 2458 2459 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2460 { 2461 struct device *dev = hr_dev->dev; 2462 int ret; 2463 2464 ret = hns_roce_cmq_query_hw_info(hr_dev); 2465 if (ret) { 2466 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2467 return ret; 2468 } 2469 2470 ret = hns_roce_query_fw_ver(hr_dev); 2471 if (ret) { 2472 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2473 return ret; 2474 } 2475 2476 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2477 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2478 2479 if (hr_dev->is_vf) 2480 return hns_roce_v2_vf_profile(hr_dev); 2481 else 2482 return hns_roce_v2_pf_profile(hr_dev); 2483 } 2484 2485 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2486 { 2487 u32 i, next_ptr, page_num; 2488 __le64 *entry = cfg_buf; 2489 dma_addr_t addr; 2490 u64 val; 2491 2492 page_num = data_buf->npages; 2493 for (i = 0; i < page_num; i++) { 2494 addr = hns_roce_buf_page(data_buf, i); 2495 if (i == (page_num - 1)) 2496 next_ptr = 0; 2497 else 2498 next_ptr = i + 1; 2499 2500 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2501 entry[i] = cpu_to_le64(val); 2502 } 2503 } 2504 2505 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2506 struct hns_roce_link_table *table) 2507 { 2508 struct hns_roce_cmq_desc desc[2]; 2509 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2510 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2511 struct hns_roce_buf *buf = table->buf; 2512 enum hns_roce_opcode_type opcode; 2513 dma_addr_t addr; 2514 2515 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2516 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2517 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2518 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2519 2520 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2521 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2522 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2523 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2524 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2525 2526 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2527 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2528 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2529 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2530 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2531 2532 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2533 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2534 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2535 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2536 2537 return hns_roce_cmq_send(hr_dev, desc, 2); 2538 } 2539 2540 static struct hns_roce_link_table * 2541 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2542 { 2543 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2544 struct hns_roce_v2_priv *priv = hr_dev->priv; 2545 struct hns_roce_link_table *link_tbl; 2546 u32 pg_shift, size, min_size; 2547 2548 link_tbl = &priv->ext_llm; 2549 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2550 size = hr_dev->caps.num_qps * hr_dev->func_num * 2551 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2552 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2553 2554 /* Alloc data table */ 2555 size = max(size, min_size); 2556 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2557 if (IS_ERR(link_tbl->buf)) 2558 return ERR_PTR(-ENOMEM); 2559 2560 /* Alloc config table */ 2561 size = link_tbl->buf->npages * sizeof(u64); 2562 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2563 &link_tbl->table.map, 2564 GFP_KERNEL); 2565 if (!link_tbl->table.buf) { 2566 hns_roce_buf_free(hr_dev, link_tbl->buf); 2567 return ERR_PTR(-ENOMEM); 2568 } 2569 2570 return link_tbl; 2571 } 2572 2573 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2574 struct hns_roce_link_table *tbl) 2575 { 2576 if (tbl->buf) { 2577 u32 size = tbl->buf->npages * sizeof(u64); 2578 2579 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2580 tbl->table.map); 2581 } 2582 2583 hns_roce_buf_free(hr_dev, tbl->buf); 2584 } 2585 2586 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2587 { 2588 struct hns_roce_link_table *link_tbl; 2589 int ret; 2590 2591 link_tbl = alloc_link_table_buf(hr_dev); 2592 if (IS_ERR(link_tbl)) 2593 return -ENOMEM; 2594 2595 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2596 ret = -EINVAL; 2597 goto err_alloc; 2598 } 2599 2600 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2601 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2602 if (ret) 2603 goto err_alloc; 2604 2605 return 0; 2606 2607 err_alloc: 2608 free_link_table_buf(hr_dev, link_tbl); 2609 return ret; 2610 } 2611 2612 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2613 { 2614 struct hns_roce_v2_priv *priv = hr_dev->priv; 2615 2616 free_link_table_buf(hr_dev, &priv->ext_llm); 2617 } 2618 2619 static void free_dip_entry(struct hns_roce_dev *hr_dev) 2620 { 2621 struct hns_roce_dip *hr_dip; 2622 unsigned long idx; 2623 2624 xa_lock(&hr_dev->qp_table.dip_xa); 2625 2626 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) { 2627 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx); 2628 kfree(hr_dip); 2629 } 2630 2631 xa_unlock(&hr_dev->qp_table.dip_xa); 2632 } 2633 2634 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2635 { 2636 struct hns_roce_v2_priv *priv = hr_dev->priv; 2637 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2638 struct ib_device *ibdev = &hr_dev->ib_dev; 2639 struct hns_roce_pd *hr_pd; 2640 struct ib_pd *pd; 2641 2642 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2643 if (!hr_pd) 2644 return NULL; 2645 pd = &hr_pd->ibpd; 2646 pd->device = ibdev; 2647 2648 if (hns_roce_alloc_pd(pd, NULL)) { 2649 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2650 kfree(hr_pd); 2651 return NULL; 2652 } 2653 free_mr->rsv_pd = to_hr_pd(pd); 2654 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2655 free_mr->rsv_pd->ibpd.uobject = NULL; 2656 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2657 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2658 2659 return pd; 2660 } 2661 2662 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2663 { 2664 struct hns_roce_v2_priv *priv = hr_dev->priv; 2665 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2666 struct ib_device *ibdev = &hr_dev->ib_dev; 2667 struct ib_cq_init_attr cq_init_attr = {}; 2668 struct hns_roce_cq *hr_cq; 2669 struct ib_cq *cq; 2670 2671 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2672 2673 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2674 if (!hr_cq) 2675 return NULL; 2676 2677 cq = &hr_cq->ib_cq; 2678 cq->device = ibdev; 2679 2680 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2681 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2682 kfree(hr_cq); 2683 return NULL; 2684 } 2685 free_mr->rsv_cq = to_hr_cq(cq); 2686 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2687 free_mr->rsv_cq->ib_cq.uobject = NULL; 2688 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2689 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2690 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2691 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2692 2693 return cq; 2694 } 2695 2696 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2697 struct ib_qp_init_attr *init_attr, int i) 2698 { 2699 struct hns_roce_v2_priv *priv = hr_dev->priv; 2700 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2701 struct ib_device *ibdev = &hr_dev->ib_dev; 2702 struct hns_roce_qp *hr_qp; 2703 struct ib_qp *qp; 2704 int ret; 2705 2706 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2707 if (!hr_qp) 2708 return -ENOMEM; 2709 2710 qp = &hr_qp->ibqp; 2711 qp->device = ibdev; 2712 2713 ret = hns_roce_create_qp(qp, init_attr, NULL); 2714 if (ret) { 2715 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2716 kfree(hr_qp); 2717 return ret; 2718 } 2719 2720 free_mr->rsv_qp[i] = hr_qp; 2721 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2722 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2723 2724 return 0; 2725 } 2726 2727 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2728 { 2729 struct hns_roce_v2_priv *priv = hr_dev->priv; 2730 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2731 struct ib_qp *qp; 2732 int i; 2733 2734 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2735 if (free_mr->rsv_qp[i]) { 2736 qp = &free_mr->rsv_qp[i]->ibqp; 2737 hns_roce_v2_destroy_qp(qp, NULL); 2738 kfree(free_mr->rsv_qp[i]); 2739 free_mr->rsv_qp[i] = NULL; 2740 } 2741 } 2742 2743 if (free_mr->rsv_cq) { 2744 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2745 kfree(free_mr->rsv_cq); 2746 free_mr->rsv_cq = NULL; 2747 } 2748 2749 if (free_mr->rsv_pd) { 2750 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2751 kfree(free_mr->rsv_pd); 2752 free_mr->rsv_pd = NULL; 2753 } 2754 2755 mutex_destroy(&free_mr->mutex); 2756 } 2757 2758 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2759 { 2760 struct hns_roce_v2_priv *priv = hr_dev->priv; 2761 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2762 struct ib_qp_init_attr qp_init_attr = {}; 2763 struct ib_pd *pd; 2764 struct ib_cq *cq; 2765 int ret; 2766 int i; 2767 2768 pd = free_mr_init_pd(hr_dev); 2769 if (!pd) 2770 return -ENOMEM; 2771 2772 cq = free_mr_init_cq(hr_dev); 2773 if (!cq) { 2774 ret = -ENOMEM; 2775 goto create_failed_cq; 2776 } 2777 2778 qp_init_attr.qp_type = IB_QPT_RC; 2779 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2780 qp_init_attr.send_cq = cq; 2781 qp_init_attr.recv_cq = cq; 2782 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2783 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2784 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2785 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2786 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2787 2788 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2789 if (ret) 2790 goto create_failed_qp; 2791 } 2792 2793 return 0; 2794 2795 create_failed_qp: 2796 for (i--; i >= 0; i--) { 2797 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 2798 kfree(free_mr->rsv_qp[i]); 2799 } 2800 hns_roce_destroy_cq(cq, NULL); 2801 kfree(cq); 2802 2803 create_failed_cq: 2804 hns_roce_dealloc_pd(pd, NULL); 2805 kfree(pd); 2806 2807 return ret; 2808 } 2809 2810 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2811 struct ib_qp_attr *attr, int sl_num) 2812 { 2813 struct hns_roce_v2_priv *priv = hr_dev->priv; 2814 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2815 struct ib_device *ibdev = &hr_dev->ib_dev; 2816 struct hns_roce_qp *hr_qp; 2817 int loopback; 2818 int mask; 2819 int ret; 2820 2821 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2822 hr_qp->free_mr_en = 1; 2823 hr_qp->ibqp.device = ibdev; 2824 hr_qp->ibqp.qp_type = IB_QPT_RC; 2825 2826 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2827 attr->qp_state = IB_QPS_INIT; 2828 attr->port_num = 1; 2829 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2830 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2831 IB_QPS_INIT, NULL); 2832 if (ret) { 2833 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n", 2834 ret); 2835 return ret; 2836 } 2837 2838 loopback = hr_dev->loop_idc; 2839 /* Set qpc lbi = 1 incidate loopback IO */ 2840 hr_dev->loop_idc = 1; 2841 2842 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2843 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2844 attr->qp_state = IB_QPS_RTR; 2845 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2846 attr->path_mtu = IB_MTU_256; 2847 attr->dest_qp_num = hr_qp->qpn; 2848 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2849 2850 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2851 2852 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2853 IB_QPS_RTR, NULL); 2854 hr_dev->loop_idc = loopback; 2855 if (ret) { 2856 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2857 ret); 2858 return ret; 2859 } 2860 2861 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2862 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2863 attr->qp_state = IB_QPS_RTS; 2864 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2865 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2866 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2867 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2868 IB_QPS_RTS, NULL); 2869 if (ret) 2870 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2871 ret); 2872 2873 return ret; 2874 } 2875 2876 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2877 { 2878 struct hns_roce_v2_priv *priv = hr_dev->priv; 2879 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2880 struct ib_qp_attr attr = {}; 2881 int ret; 2882 int i; 2883 2884 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2885 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2886 rdma_ah_set_port_num(&attr.ah_attr, 1); 2887 2888 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2889 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2890 if (ret) 2891 return ret; 2892 } 2893 2894 return 0; 2895 } 2896 2897 static int free_mr_init(struct hns_roce_dev *hr_dev) 2898 { 2899 struct hns_roce_v2_priv *priv = hr_dev->priv; 2900 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2901 int ret; 2902 2903 mutex_init(&free_mr->mutex); 2904 2905 ret = free_mr_alloc_res(hr_dev); 2906 if (ret) { 2907 mutex_destroy(&free_mr->mutex); 2908 return ret; 2909 } 2910 2911 ret = free_mr_modify_qp(hr_dev); 2912 if (ret) 2913 goto err_modify_qp; 2914 2915 return 0; 2916 2917 err_modify_qp: 2918 free_mr_exit(hr_dev); 2919 2920 return ret; 2921 } 2922 2923 static int get_hem_table(struct hns_roce_dev *hr_dev) 2924 { 2925 unsigned int qpc_count; 2926 unsigned int cqc_count; 2927 unsigned int gmv_count; 2928 int ret; 2929 int i; 2930 2931 /* Alloc memory for source address table buffer space chunk */ 2932 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2933 gmv_count++) { 2934 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2935 if (ret) 2936 goto err_gmv_failed; 2937 } 2938 2939 if (hr_dev->is_vf) 2940 return 0; 2941 2942 /* Alloc memory for QPC Timer buffer space chunk */ 2943 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2944 qpc_count++) { 2945 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2946 qpc_count); 2947 if (ret) { 2948 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2949 goto err_qpc_timer_failed; 2950 } 2951 } 2952 2953 /* Alloc memory for CQC Timer buffer space chunk */ 2954 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2955 cqc_count++) { 2956 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2957 cqc_count); 2958 if (ret) { 2959 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2960 goto err_cqc_timer_failed; 2961 } 2962 } 2963 2964 return 0; 2965 2966 err_cqc_timer_failed: 2967 for (i = 0; i < cqc_count; i++) 2968 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2969 2970 err_qpc_timer_failed: 2971 for (i = 0; i < qpc_count; i++) 2972 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2973 2974 err_gmv_failed: 2975 for (i = 0; i < gmv_count; i++) 2976 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2977 2978 return ret; 2979 } 2980 2981 static void put_hem_table(struct hns_roce_dev *hr_dev) 2982 { 2983 int i; 2984 2985 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2986 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2987 2988 if (hr_dev->is_vf) 2989 return; 2990 2991 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2992 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2993 2994 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2995 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2996 } 2997 2998 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2999 { 3000 int ret; 3001 3002 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 3003 ret = free_mr_init(hr_dev); 3004 if (ret) { 3005 dev_err(hr_dev->dev, "failed to init free mr!\n"); 3006 return ret; 3007 } 3008 } 3009 3010 /* The hns ROCEE requires the extdb info to be cleared before using */ 3011 ret = hns_roce_clear_extdb_list_info(hr_dev); 3012 if (ret) 3013 goto err_clear_extdb_failed; 3014 3015 ret = get_hem_table(hr_dev); 3016 if (ret) 3017 goto err_get_hem_table_failed; 3018 3019 if (hr_dev->is_vf) 3020 return 0; 3021 3022 ret = hns_roce_init_link_table(hr_dev); 3023 if (ret) { 3024 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 3025 goto err_llm_init_failed; 3026 } 3027 3028 return 0; 3029 3030 err_llm_init_failed: 3031 put_hem_table(hr_dev); 3032 err_get_hem_table_failed: 3033 hns_roce_function_clear(hr_dev); 3034 err_clear_extdb_failed: 3035 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3036 free_mr_exit(hr_dev); 3037 3038 return ret; 3039 } 3040 3041 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 3042 { 3043 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3044 free_mr_exit(hr_dev); 3045 3046 hns_roce_function_clear(hr_dev); 3047 3048 if (!hr_dev->is_vf) 3049 hns_roce_free_link_table(hr_dev); 3050 3051 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3052 free_dip_entry(hr_dev); 3053 } 3054 3055 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 3056 struct hns_roce_mbox_msg *mbox_msg) 3057 { 3058 struct hns_roce_cmq_desc desc; 3059 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 3060 3061 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 3062 3063 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 3064 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 3065 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 3066 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 3067 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 3068 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 3069 mbox_msg->token); 3070 3071 return hns_roce_cmq_send(hr_dev, &desc, 1); 3072 } 3073 3074 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 3075 u8 *complete_status) 3076 { 3077 struct hns_roce_mbox_status *mb_st; 3078 struct hns_roce_cmq_desc desc; 3079 unsigned long end; 3080 int ret = -EBUSY; 3081 u32 status; 3082 bool busy; 3083 3084 mb_st = (struct hns_roce_mbox_status *)desc.data; 3085 end = msecs_to_jiffies(timeout) + jiffies; 3086 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3087 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3088 return -EIO; 3089 3090 status = 0; 3091 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3092 true); 3093 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3094 if (!ret) { 3095 status = le32_to_cpu(mb_st->mb_status_hw_run); 3096 /* No pending message exists in ROCEE mbox. */ 3097 if (!(status & MB_ST_HW_RUN_M)) 3098 break; 3099 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3100 break; 3101 } 3102 3103 if (time_after(jiffies, end)) { 3104 dev_err_ratelimited(hr_dev->dev, 3105 "failed to wait mbox status 0x%x\n", 3106 status); 3107 return -ETIMEDOUT; 3108 } 3109 3110 cond_resched(); 3111 ret = -EBUSY; 3112 } 3113 3114 if (!ret) { 3115 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3116 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3117 /* Ignore all errors if the mbox is unavailable. */ 3118 ret = 0; 3119 *complete_status = MB_ST_COMPLETE_M; 3120 } 3121 3122 return ret; 3123 } 3124 3125 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3126 struct hns_roce_mbox_msg *mbox_msg) 3127 { 3128 u8 status = 0; 3129 int ret; 3130 3131 /* Waiting for the mbox to be idle */ 3132 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3133 &status); 3134 if (unlikely(ret)) { 3135 dev_err_ratelimited(hr_dev->dev, 3136 "failed to check post mbox status = 0x%x, ret = %d.\n", 3137 status, ret); 3138 return ret; 3139 } 3140 3141 /* Post new message to mbox */ 3142 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3143 if (ret) 3144 dev_err_ratelimited(hr_dev->dev, 3145 "failed to post mailbox, ret = %d.\n", ret); 3146 3147 return ret; 3148 } 3149 3150 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3151 { 3152 u8 status = 0; 3153 int ret; 3154 3155 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3156 &status); 3157 if (!ret) { 3158 if (status != MB_ST_COMPLETE_SUCC) 3159 return -EBUSY; 3160 } else { 3161 dev_err_ratelimited(hr_dev->dev, 3162 "failed to check mbox status = 0x%x, ret = %d.\n", 3163 status, ret); 3164 } 3165 3166 return ret; 3167 } 3168 3169 static void copy_gid(void *dest, const union ib_gid *gid) 3170 { 3171 #define GID_SIZE 4 3172 const union ib_gid *src = gid; 3173 __le32 (*p)[GID_SIZE] = dest; 3174 int i; 3175 3176 if (!gid) 3177 src = &zgid; 3178 3179 for (i = 0; i < GID_SIZE; i++) 3180 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3181 } 3182 3183 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3184 int gid_index, const union ib_gid *gid, 3185 enum hns_roce_sgid_type sgid_type) 3186 { 3187 struct hns_roce_cmq_desc desc; 3188 struct hns_roce_cfg_sgid_tb *sgid_tb = 3189 (struct hns_roce_cfg_sgid_tb *)desc.data; 3190 3191 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3192 3193 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3194 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3195 3196 copy_gid(&sgid_tb->vf_sgid_l, gid); 3197 3198 return hns_roce_cmq_send(hr_dev, &desc, 1); 3199 } 3200 3201 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3202 int gid_index, const union ib_gid *gid, 3203 enum hns_roce_sgid_type sgid_type, 3204 const struct ib_gid_attr *attr) 3205 { 3206 struct hns_roce_cmq_desc desc[2]; 3207 struct hns_roce_cfg_gmv_tb_a *tb_a = 3208 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3209 struct hns_roce_cfg_gmv_tb_b *tb_b = 3210 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3211 3212 u16 vlan_id = VLAN_CFI_MASK; 3213 u8 mac[ETH_ALEN] = {}; 3214 int ret; 3215 3216 if (gid) { 3217 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3218 if (ret) 3219 return ret; 3220 } 3221 3222 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3223 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3224 3225 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3226 3227 copy_gid(&tb_a->vf_sgid_l, gid); 3228 3229 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3230 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3231 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3232 3233 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3234 3235 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3236 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3237 3238 return hns_roce_cmq_send(hr_dev, desc, 2); 3239 } 3240 3241 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3242 const union ib_gid *gid, 3243 const struct ib_gid_attr *attr) 3244 { 3245 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3246 int ret; 3247 3248 if (gid) { 3249 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3250 if (ipv6_addr_v4mapped((void *)gid)) 3251 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3252 else 3253 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3254 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3255 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3256 } 3257 } 3258 3259 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3260 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3261 else 3262 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3263 3264 if (ret) 3265 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3266 ret); 3267 3268 return ret; 3269 } 3270 3271 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3272 const u8 *addr) 3273 { 3274 struct hns_roce_cmq_desc desc; 3275 struct hns_roce_cfg_smac_tb *smac_tb = 3276 (struct hns_roce_cfg_smac_tb *)desc.data; 3277 u16 reg_smac_h; 3278 u32 reg_smac_l; 3279 3280 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3281 3282 reg_smac_l = *(u32 *)(&addr[0]); 3283 reg_smac_h = *(u16 *)(&addr[4]); 3284 3285 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3286 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3287 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3288 3289 return hns_roce_cmq_send(hr_dev, &desc, 1); 3290 } 3291 3292 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3293 struct hns_roce_v2_mpt_entry *mpt_entry, 3294 struct hns_roce_mr *mr) 3295 { 3296 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3297 struct ib_device *ibdev = &hr_dev->ib_dev; 3298 dma_addr_t pbl_ba; 3299 int ret; 3300 int i; 3301 3302 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3303 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3304 if (ret) { 3305 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3306 return ret; 3307 } 3308 3309 /* Aligned to the hardware address access unit */ 3310 for (i = 0; i < ARRAY_SIZE(pages); i++) 3311 pages[i] >>= MPT_PBL_BUF_ADDR_S; 3312 3313 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3314 3315 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3316 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S); 3317 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3318 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3319 3320 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3321 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3322 3323 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3324 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3325 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3326 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3327 3328 return 0; 3329 } 3330 3331 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3332 void *mb_buf, struct hns_roce_mr *mr) 3333 { 3334 struct hns_roce_v2_mpt_entry *mpt_entry; 3335 3336 mpt_entry = mb_buf; 3337 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3338 3339 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3340 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3341 3342 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3343 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3344 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3345 mr->access & IB_ACCESS_REMOTE_READ); 3346 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3347 mr->access & IB_ACCESS_REMOTE_WRITE); 3348 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3349 mr->access & IB_ACCESS_LOCAL_WRITE); 3350 3351 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3352 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3353 mpt_entry->lkey = cpu_to_le32(mr->key); 3354 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3355 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3356 3357 if (mr->type != MR_TYPE_MR) 3358 hr_reg_enable(mpt_entry, MPT_PA); 3359 3360 if (mr->type == MR_TYPE_DMA) 3361 return 0; 3362 3363 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3364 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3365 3366 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3367 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3368 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3369 3370 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3371 } 3372 3373 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3374 struct hns_roce_mr *mr, int flags, 3375 void *mb_buf) 3376 { 3377 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3378 u32 mr_access_flags = mr->access; 3379 int ret = 0; 3380 3381 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3382 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3383 3384 if (flags & IB_MR_REREG_ACCESS) { 3385 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3386 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3387 hr_reg_write(mpt_entry, MPT_RR_EN, 3388 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3389 hr_reg_write(mpt_entry, MPT_RW_EN, 3390 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3391 hr_reg_write(mpt_entry, MPT_LW_EN, 3392 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3393 } 3394 3395 if (flags & IB_MR_REREG_TRANS) { 3396 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3397 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3398 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3399 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3400 3401 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3402 } 3403 3404 return ret; 3405 } 3406 3407 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 3408 { 3409 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3410 struct hns_roce_v2_mpt_entry *mpt_entry; 3411 3412 mpt_entry = mb_buf; 3413 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3414 3415 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3416 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3417 3418 hr_reg_enable(mpt_entry, MPT_RA_EN); 3419 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3420 3421 hr_reg_enable(mpt_entry, MPT_FRE); 3422 hr_reg_enable(mpt_entry, MPT_BPD); 3423 hr_reg_clear(mpt_entry, MPT_PA); 3424 3425 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3426 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3427 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3428 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3429 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3430 3431 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3432 3433 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3434 MPT_PBL_BA_ADDR_S)); 3435 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3436 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3437 3438 return 0; 3439 } 3440 3441 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3442 { 3443 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3444 struct ib_device *ibdev = &hr_dev->ib_dev; 3445 const struct ib_send_wr *bad_wr; 3446 struct ib_rdma_wr rdma_wr = {}; 3447 struct ib_send_wr *send_wr; 3448 int ret; 3449 3450 send_wr = &rdma_wr.wr; 3451 send_wr->opcode = IB_WR_RDMA_WRITE; 3452 3453 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3454 if (ret) { 3455 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3456 ret); 3457 return ret; 3458 } 3459 3460 return 0; 3461 } 3462 3463 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3464 struct ib_wc *wc); 3465 3466 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3467 { 3468 struct hns_roce_v2_priv *priv = hr_dev->priv; 3469 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3470 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3471 struct ib_device *ibdev = &hr_dev->ib_dev; 3472 struct hns_roce_qp *hr_qp; 3473 unsigned long end; 3474 int cqe_cnt = 0; 3475 int npolled; 3476 int ret; 3477 int i; 3478 3479 /* 3480 * If the device initialization is not complete or in the uninstall 3481 * process, then there is no need to execute free mr. 3482 */ 3483 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3484 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3485 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3486 return; 3487 3488 mutex_lock(&free_mr->mutex); 3489 3490 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3491 hr_qp = free_mr->rsv_qp[i]; 3492 3493 ret = free_mr_post_send_lp_wqe(hr_qp); 3494 if (ret) { 3495 ibdev_err_ratelimited(ibdev, 3496 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3497 hr_qp->qpn, ret); 3498 break; 3499 } 3500 3501 cqe_cnt++; 3502 } 3503 3504 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3505 while (cqe_cnt) { 3506 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3507 if (npolled < 0) { 3508 ibdev_err_ratelimited(ibdev, 3509 "failed to poll cqe for free mr, remain %d cqe.\n", 3510 cqe_cnt); 3511 goto out; 3512 } 3513 3514 if (time_after(jiffies, end)) { 3515 ibdev_err_ratelimited(ibdev, 3516 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3517 cqe_cnt); 3518 goto out; 3519 } 3520 cqe_cnt -= npolled; 3521 } 3522 3523 out: 3524 mutex_unlock(&free_mr->mutex); 3525 } 3526 3527 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3528 { 3529 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3530 free_mr_send_cmd_to_hw(hr_dev); 3531 } 3532 3533 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3534 { 3535 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3536 } 3537 3538 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3539 { 3540 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3541 3542 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3543 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3544 NULL; 3545 } 3546 3547 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3548 struct hns_roce_cq *hr_cq) 3549 { 3550 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3551 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3552 } else { 3553 struct hns_roce_v2_db cq_db = {}; 3554 3555 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3556 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3557 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3558 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3559 3560 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3561 } 3562 } 3563 3564 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3565 struct hns_roce_srq *srq) 3566 { 3567 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3568 struct hns_roce_v2_cqe *cqe, *dest; 3569 u32 prod_index; 3570 int nfreed = 0; 3571 int wqe_index; 3572 u8 owner_bit; 3573 3574 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3575 ++prod_index) { 3576 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3577 break; 3578 } 3579 3580 /* 3581 * Now backwards through the CQ, removing CQ entries 3582 * that match our QP by overwriting them with next entries. 3583 */ 3584 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3585 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3586 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3587 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3588 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3589 hns_roce_free_srq_wqe(srq, wqe_index); 3590 } 3591 ++nfreed; 3592 } else if (nfreed) { 3593 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3594 hr_cq->ib_cq.cqe); 3595 owner_bit = hr_reg_read(dest, CQE_OWNER); 3596 memcpy(dest, cqe, hr_cq->cqe_size); 3597 hr_reg_write(dest, CQE_OWNER, owner_bit); 3598 } 3599 } 3600 3601 if (nfreed) { 3602 hr_cq->cons_index += nfreed; 3603 update_cq_db(hr_dev, hr_cq); 3604 } 3605 } 3606 3607 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3608 struct hns_roce_srq *srq) 3609 { 3610 spin_lock_irq(&hr_cq->lock); 3611 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3612 spin_unlock_irq(&hr_cq->lock); 3613 } 3614 3615 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3616 struct hns_roce_cq *hr_cq, void *mb_buf, 3617 u64 *mtts, dma_addr_t dma_handle) 3618 { 3619 struct hns_roce_v2_cq_context *cq_context; 3620 3621 cq_context = mb_buf; 3622 memset(cq_context, 0, sizeof(*cq_context)); 3623 3624 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3625 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3626 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3627 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3628 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3629 3630 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3631 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3632 3633 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3634 hr_reg_enable(cq_context, CQC_STASH); 3635 3636 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3637 to_hr_hw_page_addr(mtts[0])); 3638 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3639 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3640 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3641 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3642 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3643 to_hr_hw_page_addr(mtts[1])); 3644 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3645 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3646 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3647 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3648 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3649 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3650 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S); 3651 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S); 3652 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3653 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3654 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3655 ((u32)hr_cq->db.dma) >> 1); 3656 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3657 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S); 3658 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3659 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3660 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3661 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3662 } 3663 3664 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3665 enum ib_cq_notify_flags flags) 3666 { 3667 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3668 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3669 struct hns_roce_v2_db cq_db = {}; 3670 u32 notify_flag; 3671 3672 /* 3673 * flags = 0, then notify_flag : next 3674 * flags = 1, then notify flag : solocited 3675 */ 3676 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3677 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3678 3679 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3680 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3681 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3682 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3683 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3684 3685 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3686 3687 return 0; 3688 } 3689 3690 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3691 int num_entries, struct ib_wc *wc) 3692 { 3693 unsigned int left; 3694 int npolled = 0; 3695 3696 left = wq->head - wq->tail; 3697 if (left == 0) 3698 return 0; 3699 3700 left = min_t(unsigned int, (unsigned int)num_entries, left); 3701 while (npolled < left) { 3702 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3703 wc->status = IB_WC_WR_FLUSH_ERR; 3704 wc->vendor_err = 0; 3705 wc->qp = &hr_qp->ibqp; 3706 3707 wq->tail++; 3708 wc++; 3709 npolled++; 3710 } 3711 3712 return npolled; 3713 } 3714 3715 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3716 struct ib_wc *wc) 3717 { 3718 struct hns_roce_qp *hr_qp; 3719 int npolled = 0; 3720 3721 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3722 npolled += sw_comp(hr_qp, &hr_qp->sq, 3723 num_entries - npolled, wc + npolled); 3724 if (npolled >= num_entries) 3725 goto out; 3726 } 3727 3728 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3729 npolled += sw_comp(hr_qp, &hr_qp->rq, 3730 num_entries - npolled, wc + npolled); 3731 if (npolled >= num_entries) 3732 goto out; 3733 } 3734 3735 out: 3736 return npolled; 3737 } 3738 3739 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3740 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3741 struct ib_wc *wc) 3742 { 3743 static const struct { 3744 u32 cqe_status; 3745 enum ib_wc_status wc_status; 3746 } map[] = { 3747 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3748 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3749 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3750 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3751 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3752 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3753 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3754 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3755 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3756 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3757 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3758 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3759 IB_WC_RETRY_EXC_ERR }, 3760 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3761 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3762 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3763 }; 3764 3765 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3766 int i; 3767 3768 wc->status = IB_WC_GENERAL_ERR; 3769 for (i = 0; i < ARRAY_SIZE(map); i++) 3770 if (cqe_status == map[i].cqe_status) { 3771 wc->status = map[i].wc_status; 3772 break; 3773 } 3774 3775 if (likely(wc->status == IB_WC_SUCCESS || 3776 wc->status == IB_WC_WR_FLUSH_ERR)) 3777 return; 3778 3779 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 3780 cqe_status); 3781 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3782 cq->cqe_size, false); 3783 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3784 3785 /* 3786 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3787 * the standard protocol, the driver must ignore it and needn't to set 3788 * the QP to an error state. 3789 */ 3790 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3791 return; 3792 3793 flush_cqe(hr_dev, qp); 3794 } 3795 3796 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3797 struct hns_roce_qp **cur_qp) 3798 { 3799 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3800 struct hns_roce_qp *hr_qp = *cur_qp; 3801 u32 qpn; 3802 3803 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3804 3805 if (!hr_qp || qpn != hr_qp->qpn) { 3806 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3807 if (unlikely(!hr_qp)) { 3808 ibdev_err(&hr_dev->ib_dev, 3809 "CQ %06lx with entry for unknown QPN %06x\n", 3810 hr_cq->cqn, qpn); 3811 return -EINVAL; 3812 } 3813 *cur_qp = hr_qp; 3814 } 3815 3816 return 0; 3817 } 3818 3819 /* 3820 * mapped-value = 1 + real-value 3821 * The ib wc opcode's real value is start from 0, In order to distinguish 3822 * between initialized and uninitialized map values, we plus 1 to the actual 3823 * value when defining the mapping, so that the validity can be identified by 3824 * checking whether the mapped value is greater than 0. 3825 */ 3826 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3827 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3828 3829 static const u32 wc_send_op_map[] = { 3830 HR_WC_OP_MAP(SEND, SEND), 3831 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3832 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3833 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3834 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3835 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3836 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3837 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3838 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3839 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3840 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3841 }; 3842 3843 static int to_ib_wc_send_op(u32 hr_opcode) 3844 { 3845 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3846 return -EINVAL; 3847 3848 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3849 -EINVAL; 3850 } 3851 3852 static const u32 wc_recv_op_map[] = { 3853 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3854 HR_WC_OP_MAP(SEND, RECV), 3855 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3856 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3857 }; 3858 3859 static int to_ib_wc_recv_op(u32 hr_opcode) 3860 { 3861 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3862 return -EINVAL; 3863 3864 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3865 -EINVAL; 3866 } 3867 3868 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3869 { 3870 u32 hr_opcode; 3871 int ib_opcode; 3872 3873 wc->wc_flags = 0; 3874 3875 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3876 switch (hr_opcode) { 3877 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3878 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3879 break; 3880 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3881 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3882 wc->wc_flags |= IB_WC_WITH_IMM; 3883 break; 3884 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3885 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3886 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3887 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3888 wc->byte_len = 8; 3889 break; 3890 default: 3891 break; 3892 } 3893 3894 ib_opcode = to_ib_wc_send_op(hr_opcode); 3895 if (ib_opcode < 0) 3896 wc->status = IB_WC_GENERAL_ERR; 3897 else 3898 wc->opcode = ib_opcode; 3899 } 3900 3901 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3902 { 3903 u32 hr_opcode; 3904 int ib_opcode; 3905 3906 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3907 3908 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3909 switch (hr_opcode) { 3910 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3911 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3912 wc->wc_flags = IB_WC_WITH_IMM; 3913 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3914 break; 3915 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3916 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3917 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3918 break; 3919 default: 3920 wc->wc_flags = 0; 3921 } 3922 3923 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3924 if (ib_opcode < 0) 3925 wc->status = IB_WC_GENERAL_ERR; 3926 else 3927 wc->opcode = ib_opcode; 3928 3929 wc->sl = hr_reg_read(cqe, CQE_SL); 3930 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3931 wc->slid = 0; 3932 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3933 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3934 wc->pkey_index = 0; 3935 3936 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3937 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3938 wc->wc_flags |= IB_WC_WITH_VLAN; 3939 } else { 3940 wc->vlan_id = 0xffff; 3941 } 3942 3943 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3944 3945 return 0; 3946 } 3947 3948 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3949 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3950 { 3951 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3952 struct hns_roce_qp *qp = *cur_qp; 3953 struct hns_roce_srq *srq = NULL; 3954 struct hns_roce_v2_cqe *cqe; 3955 struct hns_roce_wq *wq; 3956 int is_send; 3957 u16 wqe_idx; 3958 int ret; 3959 3960 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3961 if (!cqe) 3962 return -EAGAIN; 3963 3964 ++hr_cq->cons_index; 3965 /* Memory barrier */ 3966 rmb(); 3967 3968 ret = get_cur_qp(hr_cq, cqe, &qp); 3969 if (ret) 3970 return ret; 3971 3972 wc->qp = &qp->ibqp; 3973 wc->vendor_err = 0; 3974 3975 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3976 3977 is_send = !hr_reg_read(cqe, CQE_S_R); 3978 if (is_send) { 3979 wq = &qp->sq; 3980 3981 /* If sg_signal_bit is set, tail pointer will be updated to 3982 * the WQE corresponding to the current CQE. 3983 */ 3984 if (qp->sq_signal_bits) 3985 wq->tail += (wqe_idx - (u16)wq->tail) & 3986 (wq->wqe_cnt - 1); 3987 3988 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3989 ++wq->tail; 3990 3991 fill_send_wc(wc, cqe); 3992 } else { 3993 if (qp->ibqp.srq) { 3994 srq = to_hr_srq(qp->ibqp.srq); 3995 wc->wr_id = srq->wrid[wqe_idx]; 3996 hns_roce_free_srq_wqe(srq, wqe_idx); 3997 } else { 3998 wq = &qp->rq; 3999 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4000 ++wq->tail; 4001 } 4002 4003 ret = fill_recv_wc(wc, cqe); 4004 } 4005 4006 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 4007 if (unlikely(wc->status != IB_WC_SUCCESS)) 4008 return 0; 4009 4010 return ret; 4011 } 4012 4013 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 4014 struct ib_wc *wc) 4015 { 4016 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 4017 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 4018 struct hns_roce_qp *cur_qp = NULL; 4019 unsigned long flags; 4020 int npolled; 4021 4022 spin_lock_irqsave(&hr_cq->lock, flags); 4023 4024 /* 4025 * When the device starts to reset, the state is RST_DOWN. At this time, 4026 * there may still be some valid CQEs in the hardware that are not 4027 * polled. Therefore, it is not allowed to switch to the software mode 4028 * immediately. When the state changes to UNINIT, CQE no longer exists 4029 * in the hardware, and then switch to software mode. 4030 */ 4031 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 4032 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4033 goto out; 4034 } 4035 4036 for (npolled = 0; npolled < num_entries; ++npolled) { 4037 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4038 break; 4039 } 4040 4041 if (npolled) 4042 update_cq_db(hr_dev, hr_cq); 4043 4044 out: 4045 spin_unlock_irqrestore(&hr_cq->lock, flags); 4046 4047 return npolled; 4048 } 4049 4050 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4051 u32 step_idx, u8 *mbox_cmd) 4052 { 4053 u8 cmd; 4054 4055 switch (type) { 4056 case HEM_TYPE_QPC: 4057 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4058 break; 4059 case HEM_TYPE_MTPT: 4060 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4061 break; 4062 case HEM_TYPE_CQC: 4063 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4064 break; 4065 case HEM_TYPE_SRQC: 4066 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4067 break; 4068 case HEM_TYPE_SCCC: 4069 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4070 break; 4071 case HEM_TYPE_QPC_TIMER: 4072 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4073 break; 4074 case HEM_TYPE_CQC_TIMER: 4075 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4076 break; 4077 default: 4078 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4079 return -EINVAL; 4080 } 4081 4082 *mbox_cmd = cmd + step_idx; 4083 4084 return 0; 4085 } 4086 4087 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4088 dma_addr_t base_addr) 4089 { 4090 struct hns_roce_cmq_desc desc; 4091 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4092 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4093 u64 addr = to_hr_hw_page_addr(base_addr); 4094 4095 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4096 4097 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4098 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4099 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4100 4101 return hns_roce_cmq_send(hr_dev, &desc, 1); 4102 } 4103 4104 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4105 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4106 { 4107 int ret; 4108 u8 cmd; 4109 4110 if (unlikely(hem_type == HEM_TYPE_GMV)) 4111 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4112 4113 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4114 return 0; 4115 4116 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4117 if (ret < 0) 4118 return ret; 4119 4120 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4121 } 4122 4123 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4124 struct hns_roce_hem_table *table, int obj, 4125 u32 step_idx) 4126 { 4127 struct hns_roce_hem_mhop mhop; 4128 struct hns_roce_hem *hem; 4129 unsigned long mhop_obj = obj; 4130 int i, j, k; 4131 int ret = 0; 4132 u64 hem_idx = 0; 4133 u64 l1_idx = 0; 4134 u64 bt_ba = 0; 4135 u32 chunk_ba_num; 4136 u32 hop_num; 4137 4138 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4139 return 0; 4140 4141 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4142 i = mhop.l0_idx; 4143 j = mhop.l1_idx; 4144 k = mhop.l2_idx; 4145 hop_num = mhop.hop_num; 4146 chunk_ba_num = mhop.bt_chunk_size / 8; 4147 4148 if (hop_num == 2) { 4149 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4150 k; 4151 l1_idx = i * chunk_ba_num + j; 4152 } else if (hop_num == 1) { 4153 hem_idx = i * chunk_ba_num + j; 4154 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4155 hem_idx = i; 4156 } 4157 4158 if (table->type == HEM_TYPE_SCCC) 4159 obj = mhop.l0_idx; 4160 4161 if (check_whether_last_step(hop_num, step_idx)) { 4162 hem = table->hem[hem_idx]; 4163 4164 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4165 } else { 4166 if (step_idx == 0) 4167 bt_ba = table->bt_l0_dma_addr[i]; 4168 else if (step_idx == 1 && hop_num == 2) 4169 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4170 4171 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4172 } 4173 4174 return ret; 4175 } 4176 4177 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4178 struct hns_roce_hem_table *table, 4179 int tag, u32 step_idx) 4180 { 4181 struct hns_roce_cmd_mailbox *mailbox; 4182 struct device *dev = hr_dev->dev; 4183 u8 cmd = 0xff; 4184 int ret; 4185 4186 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4187 return 0; 4188 4189 switch (table->type) { 4190 case HEM_TYPE_QPC: 4191 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4192 break; 4193 case HEM_TYPE_MTPT: 4194 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4195 break; 4196 case HEM_TYPE_CQC: 4197 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4198 break; 4199 case HEM_TYPE_SRQC: 4200 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4201 break; 4202 case HEM_TYPE_SCCC: 4203 case HEM_TYPE_QPC_TIMER: 4204 case HEM_TYPE_CQC_TIMER: 4205 case HEM_TYPE_GMV: 4206 return 0; 4207 default: 4208 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4209 table->type); 4210 return 0; 4211 } 4212 4213 cmd += step_idx; 4214 4215 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4216 if (IS_ERR(mailbox)) 4217 return PTR_ERR(mailbox); 4218 4219 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4220 4221 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4222 return ret; 4223 } 4224 4225 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4226 struct hns_roce_v2_qp_context *context, 4227 struct hns_roce_v2_qp_context *qpc_mask, 4228 struct hns_roce_qp *hr_qp) 4229 { 4230 struct hns_roce_cmd_mailbox *mailbox; 4231 int qpc_size; 4232 int ret; 4233 4234 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4235 if (IS_ERR(mailbox)) 4236 return PTR_ERR(mailbox); 4237 4238 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4239 qpc_size = hr_dev->caps.qpc_sz; 4240 memcpy(mailbox->buf, context, qpc_size); 4241 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4242 4243 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4244 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4245 4246 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4247 4248 return ret; 4249 } 4250 4251 static void set_access_flags(struct hns_roce_qp *hr_qp, 4252 struct hns_roce_v2_qp_context *context, 4253 struct hns_roce_v2_qp_context *qpc_mask, 4254 const struct ib_qp_attr *attr, int attr_mask) 4255 { 4256 u8 dest_rd_atomic; 4257 u32 access_flags; 4258 4259 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4260 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4261 4262 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4263 attr->qp_access_flags : hr_qp->atomic_rd_en; 4264 4265 if (!dest_rd_atomic) 4266 access_flags &= IB_ACCESS_REMOTE_WRITE; 4267 4268 hr_reg_write_bool(context, QPC_RRE, 4269 access_flags & IB_ACCESS_REMOTE_READ); 4270 hr_reg_clear(qpc_mask, QPC_RRE); 4271 4272 hr_reg_write_bool(context, QPC_RWE, 4273 access_flags & IB_ACCESS_REMOTE_WRITE); 4274 hr_reg_clear(qpc_mask, QPC_RWE); 4275 4276 hr_reg_write_bool(context, QPC_ATE, 4277 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4278 hr_reg_clear(qpc_mask, QPC_ATE); 4279 hr_reg_write_bool(context, QPC_EXT_ATE, 4280 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4281 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4282 } 4283 4284 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4285 struct hns_roce_v2_qp_context *context) 4286 { 4287 hr_reg_write(context, QPC_SGE_SHIFT, 4288 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4289 hr_qp->sge.sge_shift)); 4290 4291 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4292 4293 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4294 } 4295 4296 static inline int get_cqn(struct ib_cq *ib_cq) 4297 { 4298 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4299 } 4300 4301 static inline int get_pdn(struct ib_pd *ib_pd) 4302 { 4303 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4304 } 4305 4306 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4307 struct hns_roce_v2_qp_context *context) 4308 { 4309 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4310 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4311 4312 /* 4313 * In v2 engine, software pass context and context mask to hardware 4314 * when modifying qp. If software need modify some fields in context, 4315 * we should set all bits of the relevant fields in context mask to 4316 * 0 at the same time, else set them to 0x1. 4317 */ 4318 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4319 4320 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4321 4322 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4323 4324 set_qpc_wqe_cnt(hr_qp, context); 4325 4326 /* No VLAN need to set 0xFFF */ 4327 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4328 4329 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4330 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4331 4332 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4333 } 4334 4335 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4336 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4337 4338 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4339 hr_reg_enable(context, QPC_OWNER_MODE); 4340 4341 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4342 lower_32_bits(hr_qp->rdb.dma) >> 1); 4343 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4344 upper_32_bits(hr_qp->rdb.dma)); 4345 4346 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4347 4348 if (ibqp->srq) { 4349 hr_reg_enable(context, QPC_SRQ_EN); 4350 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4351 } 4352 4353 hr_reg_enable(context, QPC_FRE); 4354 4355 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4356 4357 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4358 return; 4359 4360 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4361 hr_reg_enable(&context->ext, QPCEX_STASH); 4362 } 4363 4364 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4365 struct hns_roce_v2_qp_context *context, 4366 struct hns_roce_v2_qp_context *qpc_mask) 4367 { 4368 /* 4369 * In v2 engine, software pass context and context mask to hardware 4370 * when modifying qp. If software need modify some fields in context, 4371 * we should set all bits of the relevant fields in context mask to 4372 * 0 at the same time, else set them to 0x1. 4373 */ 4374 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4375 hr_reg_clear(qpc_mask, QPC_TST); 4376 4377 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4378 hr_reg_clear(qpc_mask, QPC_PD); 4379 4380 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4381 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4382 4383 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4384 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4385 4386 if (ibqp->srq) { 4387 hr_reg_enable(context, QPC_SRQ_EN); 4388 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4389 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4390 hr_reg_clear(qpc_mask, QPC_SRQN); 4391 } 4392 } 4393 4394 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4395 struct hns_roce_qp *hr_qp, 4396 struct hns_roce_v2_qp_context *context, 4397 struct hns_roce_v2_qp_context *qpc_mask) 4398 { 4399 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4400 u64 wqe_sge_ba; 4401 int ret; 4402 4403 /* Search qp buf's mtts */ 4404 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4405 MTT_MIN_COUNT); 4406 if (hr_qp->rq.wqe_cnt && ret) { 4407 ibdev_err(&hr_dev->ib_dev, 4408 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4409 hr_qp->qpn, ret); 4410 return ret; 4411 } 4412 4413 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4414 4415 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4416 qpc_mask->wqe_sge_ba = 0; 4417 4418 /* 4419 * In v2 engine, software pass context and context mask to hardware 4420 * when modifying qp. If software need modify some fields in context, 4421 * we should set all bits of the relevant fields in context mask to 4422 * 0 at the same time, else set them to 0x1. 4423 */ 4424 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4425 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4426 4427 hr_reg_write(context, QPC_SQ_HOP_NUM, 4428 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4429 hr_qp->sq.wqe_cnt)); 4430 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4431 4432 hr_reg_write(context, QPC_SGE_HOP_NUM, 4433 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4434 hr_qp->sge.sge_cnt)); 4435 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4436 4437 hr_reg_write(context, QPC_RQ_HOP_NUM, 4438 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4439 hr_qp->rq.wqe_cnt)); 4440 4441 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4442 4443 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4444 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4445 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4446 4447 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4448 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4449 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4450 4451 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4452 qpc_mask->rq_cur_blk_addr = 0; 4453 4454 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4455 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4456 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4457 4458 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4459 context->rq_nxt_blk_addr = 4460 cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4461 qpc_mask->rq_nxt_blk_addr = 0; 4462 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4463 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4464 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4465 } 4466 4467 return 0; 4468 } 4469 4470 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4471 struct hns_roce_qp *hr_qp, 4472 struct hns_roce_v2_qp_context *context, 4473 struct hns_roce_v2_qp_context *qpc_mask) 4474 { 4475 struct ib_device *ibdev = &hr_dev->ib_dev; 4476 u64 sge_cur_blk = 0; 4477 u64 sq_cur_blk = 0; 4478 int ret; 4479 4480 /* search qp buf's mtts */ 4481 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4482 &sq_cur_blk, 1); 4483 if (ret) { 4484 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4485 hr_qp->qpn, ret); 4486 return ret; 4487 } 4488 if (hr_qp->sge.sge_cnt > 0) { 4489 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4490 hr_qp->sge.offset, &sge_cur_blk, 1); 4491 if (ret) { 4492 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4493 hr_qp->qpn, ret); 4494 return ret; 4495 } 4496 } 4497 4498 /* 4499 * In v2 engine, software pass context and context mask to hardware 4500 * when modifying qp. If software need modify some fields in context, 4501 * we should set all bits of the relevant fields in context mask to 4502 * 0 at the same time, else set them to 0x1. 4503 */ 4504 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4505 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4506 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4507 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4508 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4509 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4510 4511 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4512 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4513 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4514 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4515 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4516 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4517 4518 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4519 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4520 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4521 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4522 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4523 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4524 4525 return 0; 4526 } 4527 4528 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4529 const struct ib_qp_attr *attr) 4530 { 4531 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4532 return IB_MTU_4096; 4533 4534 return attr->path_mtu; 4535 } 4536 4537 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4538 const struct ib_qp_attr *attr, int attr_mask, 4539 struct hns_roce_v2_qp_context *context, 4540 struct hns_roce_v2_qp_context *qpc_mask, 4541 struct ib_udata *udata) 4542 { 4543 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4544 struct hns_roce_ucontext, ibucontext); 4545 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4546 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4547 struct ib_device *ibdev = &hr_dev->ib_dev; 4548 dma_addr_t trrl_ba; 4549 dma_addr_t irrl_ba; 4550 enum ib_mtu ib_mtu; 4551 u8 ack_req_freq; 4552 const u8 *smac; 4553 int lp_msg_len; 4554 u8 lp_pktn_ini; 4555 u64 *mtts; 4556 u8 *dmac; 4557 u32 port; 4558 int mtu; 4559 int ret; 4560 4561 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4562 if (ret) { 4563 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4564 return ret; 4565 } 4566 4567 /* Search IRRL's mtts */ 4568 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4569 hr_qp->qpn, &irrl_ba); 4570 if (!mtts) { 4571 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4572 return -EINVAL; 4573 } 4574 4575 /* Search TRRL's mtts */ 4576 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4577 hr_qp->qpn, &trrl_ba); 4578 if (!mtts) { 4579 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4580 return -EINVAL; 4581 } 4582 4583 if (attr_mask & IB_QP_ALT_PATH) { 4584 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4585 attr_mask); 4586 return -EINVAL; 4587 } 4588 4589 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S); 4590 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4591 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S); 4592 qpc_mask->trrl_ba = 0; 4593 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S); 4594 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4595 4596 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S); 4597 qpc_mask->irrl_ba = 0; 4598 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S); 4599 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4600 4601 hr_reg_enable(context, QPC_RMT_E2E); 4602 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4603 4604 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4605 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4606 4607 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4608 4609 smac = (const u8 *)hr_dev->dev_addr[port]; 4610 dmac = (u8 *)attr->ah_attr.roce.dmac; 4611 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4612 if (ether_addr_equal_unaligned(dmac, smac) || 4613 hr_dev->loop_idc == 0x1) { 4614 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4615 hr_reg_clear(qpc_mask, QPC_LBI); 4616 } 4617 4618 if (attr_mask & IB_QP_DEST_QPN) { 4619 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4620 hr_reg_clear(qpc_mask, QPC_DQPN); 4621 } 4622 4623 memcpy(&context->dmac, dmac, sizeof(u32)); 4624 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4625 qpc_mask->dmac = 0; 4626 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4627 4628 ib_mtu = get_mtu(ibqp, attr); 4629 hr_qp->path_mtu = ib_mtu; 4630 4631 mtu = ib_mtu_enum_to_int(ib_mtu); 4632 if (WARN_ON(mtu <= 0)) 4633 return -EINVAL; 4634 #define MIN_LP_MSG_LEN 1024 4635 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4636 lp_msg_len = max(mtu, MIN_LP_MSG_LEN); 4637 lp_pktn_ini = ilog2(lp_msg_len / mtu); 4638 4639 if (attr_mask & IB_QP_PATH_MTU) { 4640 hr_reg_write(context, QPC_MTU, ib_mtu); 4641 hr_reg_clear(qpc_mask, QPC_MTU); 4642 } 4643 4644 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4645 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4646 4647 /* 4648 * There are several constraints for ACK_REQ_FREQ: 4649 * 1. mtu * (2 ^ ACK_REQ_FREQ) should not be too large, otherwise 4650 * it may cause some unexpected retries when sending large 4651 * payload. 4652 * 2. ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI. 4653 * 3. ACK_REQ_FREQ must be equal to LP_PKTN_INI when using LDCP 4654 * or HC3 congestion control algorithm. 4655 */ 4656 if (hr_qp->cong_type == CONG_TYPE_LDCP || 4657 hr_qp->cong_type == CONG_TYPE_HC3 || 4658 hr_dev->caps.max_ack_req_msg_len < lp_msg_len) 4659 ack_req_freq = lp_pktn_ini; 4660 else 4661 ack_req_freq = ilog2(hr_dev->caps.max_ack_req_msg_len / mtu); 4662 hr_reg_write(context, QPC_ACK_REQ_FREQ, ack_req_freq); 4663 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4664 4665 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4666 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4667 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4668 4669 context->rq_rnr_timer = 0; 4670 qpc_mask->rq_rnr_timer = 0; 4671 4672 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4673 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4674 4675 #define MAX_LP_SGEN 3 4676 /* rocee send 2^lp_sgen_ini segs every time */ 4677 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN); 4678 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4679 4680 if (udata && ibqp->qp_type == IB_QPT_RC && 4681 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4682 hr_reg_write_bool(context, QPC_RQIE, 4683 hr_dev->caps.flags & 4684 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4685 hr_reg_clear(qpc_mask, QPC_RQIE); 4686 } 4687 4688 if (udata && 4689 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4690 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4691 hr_reg_write_bool(context, QPC_CQEIE, 4692 hr_dev->caps.flags & 4693 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4694 hr_reg_clear(qpc_mask, QPC_CQEIE); 4695 4696 hr_reg_write(context, QPC_CQEIS, 0); 4697 hr_reg_clear(qpc_mask, QPC_CQEIS); 4698 } 4699 4700 return 0; 4701 } 4702 4703 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, 4704 struct hns_roce_v2_qp_context *context, 4705 struct hns_roce_v2_qp_context *qpc_mask) 4706 { 4707 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4708 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4709 struct ib_device *ibdev = &hr_dev->ib_dev; 4710 int ret; 4711 4712 /* Not support alternate path and path migration */ 4713 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4714 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4715 return -EINVAL; 4716 } 4717 4718 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4719 if (ret) { 4720 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4721 return ret; 4722 } 4723 4724 /* 4725 * Set some fields in context to zero, Because the default values 4726 * of all fields in context are zero, we need not set them to 0 again. 4727 * but we should set the relevant fields of context mask to 0. 4728 */ 4729 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4730 4731 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4732 4733 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4734 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4735 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4736 4737 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4738 4739 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4740 4741 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4742 4743 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4744 4745 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4746 4747 return 0; 4748 } 4749 4750 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn) 4751 { 4752 struct hns_roce_dip *hr_dip; 4753 int ret; 4754 4755 hr_dip = xa_load(dip_xa, qpn); 4756 if (hr_dip) 4757 return 0; 4758 4759 hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL); 4760 if (!hr_dip) 4761 return -ENOMEM; 4762 4763 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL)); 4764 if (ret) 4765 kfree(hr_dip); 4766 4767 return ret; 4768 } 4769 4770 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4771 u32 *dip_idx) 4772 { 4773 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4774 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4775 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa; 4776 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4777 struct hns_roce_dip *hr_dip; 4778 unsigned long idx; 4779 int ret = 0; 4780 4781 ret = alloc_dip_entry(dip_xa, ibqp->qp_num); 4782 if (ret) 4783 return ret; 4784 4785 xa_lock(dip_xa); 4786 4787 xa_for_each(dip_xa, idx, hr_dip) { 4788 if (hr_dip->qp_cnt && 4789 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) { 4790 *dip_idx = hr_dip->dip_idx; 4791 hr_dip->qp_cnt++; 4792 hr_qp->dip = hr_dip; 4793 goto out; 4794 } 4795 } 4796 4797 /* If no dgid is found, a new dip and a mapping between dgid and 4798 * dip_idx will be created. 4799 */ 4800 xa_for_each(dip_xa, idx, hr_dip) { 4801 if (hr_dip->qp_cnt) 4802 continue; 4803 4804 *dip_idx = idx; 4805 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4806 hr_dip->dip_idx = idx; 4807 hr_dip->qp_cnt++; 4808 hr_qp->dip = hr_dip; 4809 break; 4810 } 4811 4812 /* This should never happen. */ 4813 if (WARN_ON_ONCE(!hr_qp->dip)) 4814 ret = -ENOSPC; 4815 4816 out: 4817 xa_unlock(dip_xa); 4818 return ret; 4819 } 4820 4821 enum { 4822 CONG_DCQCN, 4823 CONG_WINDOW, 4824 }; 4825 4826 enum { 4827 UNSUPPORT_CONG_LEVEL, 4828 SUPPORT_CONG_LEVEL, 4829 }; 4830 4831 enum { 4832 CONG_LDCP, 4833 CONG_HC3, 4834 }; 4835 4836 enum { 4837 DIP_INVALID, 4838 DIP_VALID, 4839 }; 4840 4841 enum { 4842 WND_LIMIT, 4843 WND_UNLIMIT, 4844 }; 4845 4846 static int check_cong_type(struct ib_qp *ibqp, 4847 struct hns_roce_congestion_algorithm *cong_alg) 4848 { 4849 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4850 4851 /* different congestion types match different configurations */ 4852 switch (hr_qp->cong_type) { 4853 case CONG_TYPE_DCQCN: 4854 cong_alg->alg_sel = CONG_DCQCN; 4855 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4856 cong_alg->dip_vld = DIP_INVALID; 4857 cong_alg->wnd_mode_sel = WND_LIMIT; 4858 break; 4859 case CONG_TYPE_LDCP: 4860 cong_alg->alg_sel = CONG_WINDOW; 4861 cong_alg->alg_sub_sel = CONG_LDCP; 4862 cong_alg->dip_vld = DIP_INVALID; 4863 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4864 break; 4865 case CONG_TYPE_HC3: 4866 cong_alg->alg_sel = CONG_WINDOW; 4867 cong_alg->alg_sub_sel = CONG_HC3; 4868 cong_alg->dip_vld = DIP_INVALID; 4869 cong_alg->wnd_mode_sel = WND_LIMIT; 4870 break; 4871 case CONG_TYPE_DIP: 4872 cong_alg->alg_sel = CONG_DCQCN; 4873 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4874 cong_alg->dip_vld = DIP_VALID; 4875 cong_alg->wnd_mode_sel = WND_LIMIT; 4876 break; 4877 default: 4878 hr_qp->cong_type = CONG_TYPE_DCQCN; 4879 cong_alg->alg_sel = CONG_DCQCN; 4880 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4881 cong_alg->dip_vld = DIP_INVALID; 4882 cong_alg->wnd_mode_sel = WND_LIMIT; 4883 break; 4884 } 4885 4886 return 0; 4887 } 4888 4889 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4890 struct hns_roce_v2_qp_context *context, 4891 struct hns_roce_v2_qp_context *qpc_mask) 4892 { 4893 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4894 struct hns_roce_congestion_algorithm cong_field; 4895 struct ib_device *ibdev = ibqp->device; 4896 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4897 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4898 u32 dip_idx = 0; 4899 int ret; 4900 4901 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4902 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4903 return 0; 4904 4905 ret = check_cong_type(ibqp, &cong_field); 4906 if (ret) 4907 return ret; 4908 4909 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4910 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 4911 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4912 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4913 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4914 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4915 cong_field.alg_sub_sel); 4916 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4917 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4918 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4919 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4920 cong_field.wnd_mode_sel); 4921 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4922 4923 /* if dip is disabled, there is no need to set dip idx */ 4924 if (cong_field.dip_vld == 0) 4925 return 0; 4926 4927 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4928 if (ret) { 4929 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4930 return ret; 4931 } 4932 4933 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4934 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4935 4936 return 0; 4937 } 4938 4939 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, 4940 u8 *tc_mode, u8 *priority) 4941 { 4942 struct hns_roce_v2_priv *priv = hr_dev->priv; 4943 struct hnae3_handle *handle = priv->handle; 4944 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 4945 4946 if (!ops->get_dscp_prio) 4947 return -EOPNOTSUPP; 4948 4949 return ops->get_dscp_prio(handle, dscp, tc_mode, priority); 4950 } 4951 4952 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) 4953 { 4954 u32 max_sl; 4955 4956 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4957 if (unlikely(sl > max_sl)) { 4958 ibdev_err_ratelimited(&hr_dev->ib_dev, 4959 "failed to set SL(%u). Shouldn't be larger than %u.\n", 4960 sl, max_sl); 4961 return false; 4962 } 4963 4964 return true; 4965 } 4966 4967 static int hns_roce_set_sl(struct ib_qp *ibqp, 4968 const struct ib_qp_attr *attr, 4969 struct hns_roce_v2_qp_context *context, 4970 struct hns_roce_v2_qp_context *qpc_mask) 4971 { 4972 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4973 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4974 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4975 struct ib_device *ibdev = &hr_dev->ib_dev; 4976 int ret; 4977 4978 ret = hns_roce_hw_v2_get_dscp(hr_dev, get_tclass(&attr->ah_attr.grh), 4979 &hr_qp->tc_mode, &hr_qp->priority); 4980 if (ret && ret != -EOPNOTSUPP && 4981 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 4982 ibdev_err_ratelimited(ibdev, 4983 "failed to get dscp, ret = %d.\n", ret); 4984 return ret; 4985 } 4986 4987 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP && 4988 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 4989 hr_qp->sl = hr_qp->priority; 4990 else 4991 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4992 4993 if (!check_sl_valid(hr_dev, hr_qp->sl)) 4994 return -EINVAL; 4995 4996 hr_reg_write(context, QPC_SL, hr_qp->sl); 4997 hr_reg_clear(qpc_mask, QPC_SL); 4998 4999 return 0; 5000 } 5001 5002 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 5003 const struct ib_qp_attr *attr, 5004 int attr_mask, 5005 struct hns_roce_v2_qp_context *context, 5006 struct hns_roce_v2_qp_context *qpc_mask) 5007 { 5008 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5009 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5010 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5011 struct ib_device *ibdev = &hr_dev->ib_dev; 5012 const struct ib_gid_attr *gid_attr = NULL; 5013 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 5014 int is_roce_protocol; 5015 u16 vlan_id = 0xffff; 5016 bool is_udp = false; 5017 u8 ib_port; 5018 u8 hr_port; 5019 int ret; 5020 5021 /* 5022 * If free_mr_en of qp is set, it means that this qp comes from 5023 * free mr. This qp will perform the loopback operation. 5024 * In the loopback scenario, only sl needs to be set. 5025 */ 5026 if (hr_qp->free_mr_en) { 5027 if (!check_sl_valid(hr_dev, sl)) 5028 return -EINVAL; 5029 hr_reg_write(context, QPC_SL, sl); 5030 hr_reg_clear(qpc_mask, QPC_SL); 5031 hr_qp->sl = sl; 5032 return 0; 5033 } 5034 5035 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 5036 hr_port = ib_port - 1; 5037 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 5038 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 5039 5040 if (is_roce_protocol) { 5041 gid_attr = attr->ah_attr.grh.sgid_attr; 5042 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 5043 if (ret) 5044 return ret; 5045 5046 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 5047 } 5048 5049 /* Only HIP08 needs to set the vlan_en bits in QPC */ 5050 if (vlan_id < VLAN_N_VID && 5051 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5052 hr_reg_enable(context, QPC_RQ_VLAN_EN); 5053 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 5054 hr_reg_enable(context, QPC_SQ_VLAN_EN); 5055 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 5056 } 5057 5058 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 5059 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 5060 5061 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 5062 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 5063 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 5064 return -EINVAL; 5065 } 5066 5067 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 5068 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 5069 return -EINVAL; 5070 } 5071 5072 hr_reg_write(context, QPC_UDPSPN, 5073 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 5074 attr->dest_qp_num) : 5075 0); 5076 5077 hr_reg_clear(qpc_mask, QPC_UDPSPN); 5078 5079 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5080 5081 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5082 5083 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5084 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5085 5086 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5087 if (ret) 5088 return ret; 5089 5090 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5091 hr_reg_clear(qpc_mask, QPC_TC); 5092 5093 hr_reg_write(context, QPC_FL, grh->flow_label); 5094 hr_reg_clear(qpc_mask, QPC_FL); 5095 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5096 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5097 5098 return hns_roce_set_sl(ibqp, attr, context, qpc_mask); 5099 } 5100 5101 static bool check_qp_state(enum ib_qp_state cur_state, 5102 enum ib_qp_state new_state) 5103 { 5104 static const bool sm[][IB_QPS_ERR + 1] = { 5105 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5106 [IB_QPS_INIT] = true }, 5107 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5108 [IB_QPS_INIT] = true, 5109 [IB_QPS_RTR] = true, 5110 [IB_QPS_ERR] = true }, 5111 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5112 [IB_QPS_RTS] = true, 5113 [IB_QPS_ERR] = true }, 5114 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5115 [IB_QPS_RTS] = true, 5116 [IB_QPS_ERR] = true }, 5117 [IB_QPS_SQD] = {}, 5118 [IB_QPS_SQE] = {}, 5119 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5120 [IB_QPS_ERR] = true } 5121 }; 5122 5123 return sm[cur_state][new_state]; 5124 } 5125 5126 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5127 const struct ib_qp_attr *attr, 5128 int attr_mask, 5129 enum ib_qp_state cur_state, 5130 enum ib_qp_state new_state, 5131 struct hns_roce_v2_qp_context *context, 5132 struct hns_roce_v2_qp_context *qpc_mask, 5133 struct ib_udata *udata) 5134 { 5135 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5136 int ret = 0; 5137 5138 if (!check_qp_state(cur_state, new_state)) 5139 return -EINVAL; 5140 5141 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5142 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5143 modify_qp_reset_to_init(ibqp, context); 5144 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5145 modify_qp_init_to_init(ibqp, context, qpc_mask); 5146 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5147 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5148 qpc_mask, udata); 5149 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5150 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask); 5151 } 5152 5153 return ret; 5154 } 5155 5156 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5157 { 5158 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5159 #define QP_ACK_TIMEOUT_MAX 31 5160 5161 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5162 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5163 ibdev_warn(&hr_dev->ib_dev, 5164 "local ACK timeout shall be 0 to 20.\n"); 5165 return false; 5166 } 5167 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5168 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5169 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5170 ibdev_warn(&hr_dev->ib_dev, 5171 "local ACK timeout shall be 0 to 31.\n"); 5172 return false; 5173 } 5174 } 5175 5176 return true; 5177 } 5178 5179 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5180 const struct ib_qp_attr *attr, 5181 int attr_mask, 5182 struct hns_roce_v2_qp_context *context, 5183 struct hns_roce_v2_qp_context *qpc_mask) 5184 { 5185 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5186 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5187 int ret = 0; 5188 u8 timeout; 5189 5190 if (attr_mask & IB_QP_AV) { 5191 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5192 qpc_mask); 5193 if (ret) 5194 return ret; 5195 } 5196 5197 if (attr_mask & IB_QP_TIMEOUT) { 5198 timeout = attr->timeout; 5199 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5200 hr_reg_write(context, QPC_AT, timeout); 5201 hr_reg_clear(qpc_mask, QPC_AT); 5202 } 5203 } 5204 5205 if (attr_mask & IB_QP_RETRY_CNT) { 5206 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5207 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5208 5209 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5210 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5211 } 5212 5213 if (attr_mask & IB_QP_RNR_RETRY) { 5214 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5215 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5216 5217 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5218 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5219 } 5220 5221 if (attr_mask & IB_QP_SQ_PSN) { 5222 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5223 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5224 5225 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5226 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5227 5228 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5229 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5230 5231 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5232 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5233 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5234 5235 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5236 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5237 5238 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5239 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5240 } 5241 5242 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5243 attr->max_dest_rd_atomic) { 5244 hr_reg_write(context, QPC_RR_MAX, 5245 fls(attr->max_dest_rd_atomic - 1)); 5246 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5247 } 5248 5249 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5250 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5251 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5252 } 5253 5254 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5255 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5256 5257 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5258 hr_reg_write(context, QPC_MIN_RNR_TIME, 5259 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5260 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5261 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5262 } 5263 5264 if (attr_mask & IB_QP_RQ_PSN) { 5265 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5266 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5267 5268 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5269 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5270 } 5271 5272 if (attr_mask & IB_QP_QKEY) { 5273 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5274 qpc_mask->qkey_xrcd = 0; 5275 hr_qp->qkey = attr->qkey; 5276 } 5277 5278 return ret; 5279 } 5280 5281 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5282 const struct ib_qp_attr *attr, 5283 int attr_mask) 5284 { 5285 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5286 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5287 5288 if (attr_mask & IB_QP_ACCESS_FLAGS) 5289 hr_qp->atomic_rd_en = attr->qp_access_flags; 5290 5291 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5292 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5293 if (attr_mask & IB_QP_PORT) { 5294 hr_qp->port = attr->port_num - 1; 5295 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5296 } 5297 } 5298 5299 static void clear_qp(struct hns_roce_qp *hr_qp) 5300 { 5301 struct ib_qp *ibqp = &hr_qp->ibqp; 5302 5303 if (ibqp->send_cq) 5304 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5305 hr_qp->qpn, NULL); 5306 5307 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5308 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5309 hr_qp->qpn, ibqp->srq ? 5310 to_hr_srq(ibqp->srq) : NULL); 5311 5312 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5313 *hr_qp->rdb.db_record = 0; 5314 5315 hr_qp->rq.head = 0; 5316 hr_qp->rq.tail = 0; 5317 hr_qp->sq.head = 0; 5318 hr_qp->sq.tail = 0; 5319 hr_qp->next_sge = 0; 5320 } 5321 5322 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5323 struct hns_roce_v2_qp_context *context, 5324 struct hns_roce_v2_qp_context *qpc_mask) 5325 { 5326 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5327 unsigned long sq_flag = 0; 5328 unsigned long rq_flag = 0; 5329 5330 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5331 return; 5332 5333 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5334 trace_hns_sq_flush_cqe(hr_qp->qpn, hr_qp->sq.head, TRACE_SQ); 5335 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5336 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5337 hr_qp->state = IB_QPS_ERR; 5338 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5339 5340 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5341 return; 5342 5343 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5344 trace_hns_rq_flush_cqe(hr_qp->qpn, hr_qp->rq.head, TRACE_RQ); 5345 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5346 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5347 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5348 } 5349 5350 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5351 const struct ib_qp_attr *attr, 5352 int attr_mask, enum ib_qp_state cur_state, 5353 enum ib_qp_state new_state, struct ib_udata *udata) 5354 { 5355 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5356 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5357 struct hns_roce_v2_qp_context *context; 5358 struct hns_roce_v2_qp_context *qpc_mask; 5359 struct ib_device *ibdev = &hr_dev->ib_dev; 5360 int ret = -ENOMEM; 5361 5362 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5363 return -EOPNOTSUPP; 5364 5365 /* 5366 * In v2 engine, software pass context and context mask to hardware 5367 * when modifying qp. If software need modify some fields in context, 5368 * we should set all bits of the relevant fields in context mask to 5369 * 0 at the same time, else set them to 0x1. 5370 */ 5371 context = kvzalloc(sizeof(*context), GFP_KERNEL); 5372 qpc_mask = kvzalloc(sizeof(*qpc_mask), GFP_KERNEL); 5373 if (!context || !qpc_mask) 5374 goto out; 5375 5376 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5377 5378 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5379 new_state, context, qpc_mask, udata); 5380 if (ret) 5381 goto out; 5382 5383 /* When QP state is err, SQ and RQ WQE should be flushed */ 5384 if (new_state == IB_QPS_ERR) 5385 v2_set_flushed_fields(ibqp, context, qpc_mask); 5386 5387 /* Configure the optional fields */ 5388 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5389 qpc_mask); 5390 if (ret) 5391 goto out; 5392 5393 hr_reg_write_bool(context, QPC_INV_CREDIT, 5394 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5395 ibqp->srq); 5396 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5397 5398 /* Every status migrate must change state */ 5399 hr_reg_write(context, QPC_QP_ST, new_state); 5400 hr_reg_clear(qpc_mask, QPC_QP_ST); 5401 5402 /* SW pass context to HW */ 5403 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5404 if (ret) { 5405 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret); 5406 goto out; 5407 } 5408 5409 hr_qp->state = new_state; 5410 5411 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5412 5413 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5414 clear_qp(hr_qp); 5415 5416 out: 5417 kvfree(qpc_mask); 5418 kvfree(context); 5419 return ret; 5420 } 5421 5422 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5423 { 5424 static const enum ib_qp_state map[] = { 5425 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5426 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5427 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5428 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5429 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5430 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5431 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5432 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5433 }; 5434 5435 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5436 } 5437 5438 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5439 void *buffer) 5440 { 5441 struct hns_roce_cmd_mailbox *mailbox; 5442 int ret; 5443 5444 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5445 if (IS_ERR(mailbox)) 5446 return PTR_ERR(mailbox); 5447 5448 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5449 qpn); 5450 if (ret) 5451 goto out; 5452 5453 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5454 5455 out: 5456 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5457 return ret; 5458 } 5459 5460 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5461 void *buffer) 5462 { 5463 struct hns_roce_srq_context *context; 5464 struct hns_roce_cmd_mailbox *mailbox; 5465 int ret; 5466 5467 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5468 if (IS_ERR(mailbox)) 5469 return PTR_ERR(mailbox); 5470 5471 context = mailbox->buf; 5472 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5473 srqn); 5474 if (ret) 5475 goto out; 5476 5477 memcpy(buffer, context, sizeof(*context)); 5478 5479 out: 5480 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5481 return ret; 5482 } 5483 5484 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 sccn, 5485 void *buffer) 5486 { 5487 struct hns_roce_v2_scc_context *context; 5488 struct hns_roce_cmd_mailbox *mailbox; 5489 int ret; 5490 5491 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5492 if (IS_ERR(mailbox)) 5493 return PTR_ERR(mailbox); 5494 5495 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5496 sccn); 5497 if (ret) 5498 goto out; 5499 5500 context = mailbox->buf; 5501 memcpy(buffer, context, sizeof(*context)); 5502 5503 out: 5504 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5505 return ret; 5506 } 5507 5508 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5509 struct hns_roce_v2_qp_context *context) 5510 { 5511 u8 timeout; 5512 5513 timeout = (u8)hr_reg_read(context, QPC_AT); 5514 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5515 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5516 5517 return timeout; 5518 } 5519 5520 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5521 int qp_attr_mask, 5522 struct ib_qp_init_attr *qp_init_attr) 5523 { 5524 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5525 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5526 struct hns_roce_v2_qp_context context = {}; 5527 struct ib_device *ibdev = &hr_dev->ib_dev; 5528 int tmp_qp_state; 5529 int state; 5530 int ret; 5531 5532 memset(qp_attr, 0, sizeof(*qp_attr)); 5533 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5534 5535 mutex_lock(&hr_qp->mutex); 5536 5537 if (hr_qp->state == IB_QPS_RESET) { 5538 qp_attr->qp_state = IB_QPS_RESET; 5539 ret = 0; 5540 goto done; 5541 } 5542 5543 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5544 if (ret) { 5545 ibdev_err_ratelimited(ibdev, 5546 "failed to query QPC, ret = %d.\n", 5547 ret); 5548 ret = -EINVAL; 5549 goto out; 5550 } 5551 5552 state = hr_reg_read(&context, QPC_QP_ST); 5553 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5554 if (tmp_qp_state == -1) { 5555 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n"); 5556 ret = -EINVAL; 5557 goto out; 5558 } 5559 hr_qp->state = (u8)tmp_qp_state; 5560 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5561 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5562 qp_attr->path_mig_state = IB_MIG_ARMED; 5563 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5564 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5565 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5566 5567 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5568 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5569 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5570 qp_attr->qp_access_flags = 5571 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5572 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5573 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5574 5575 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5576 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5577 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5578 struct ib_global_route *grh = 5579 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5580 5581 rdma_ah_set_sl(&qp_attr->ah_attr, 5582 hr_reg_read(&context, QPC_SL)); 5583 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5584 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5585 grh->flow_label = hr_reg_read(&context, QPC_FL); 5586 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5587 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5588 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5589 5590 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5591 } 5592 5593 qp_attr->port_num = hr_qp->port + 1; 5594 qp_attr->sq_draining = 0; 5595 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5596 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5597 5598 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5599 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5600 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5601 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5602 5603 done: 5604 qp_attr->cur_qp_state = qp_attr->qp_state; 5605 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5606 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5607 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5608 5609 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5610 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5611 5612 qp_init_attr->qp_context = ibqp->qp_context; 5613 qp_init_attr->qp_type = ibqp->qp_type; 5614 qp_init_attr->recv_cq = ibqp->recv_cq; 5615 qp_init_attr->send_cq = ibqp->send_cq; 5616 qp_init_attr->srq = ibqp->srq; 5617 qp_init_attr->cap = qp_attr->cap; 5618 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5619 5620 out: 5621 mutex_unlock(&hr_qp->mutex); 5622 return ret; 5623 } 5624 5625 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5626 { 5627 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5628 hr_qp->ibqp.qp_type == IB_QPT_UD || 5629 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5630 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5631 hr_qp->state != IB_QPS_RESET); 5632 } 5633 5634 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5635 struct hns_roce_qp *hr_qp, 5636 struct ib_udata *udata) 5637 { 5638 struct ib_device *ibdev = &hr_dev->ib_dev; 5639 struct hns_roce_cq *send_cq, *recv_cq; 5640 unsigned long flags; 5641 int ret = 0; 5642 5643 if (modify_qp_is_ok(hr_qp)) { 5644 /* Modify qp to reset before destroying qp */ 5645 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5646 hr_qp->state, IB_QPS_RESET, udata); 5647 if (ret) 5648 ibdev_err_ratelimited(ibdev, 5649 "failed to modify QP to RST, ret = %d.\n", 5650 ret); 5651 } 5652 5653 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5654 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5655 5656 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5657 hns_roce_lock_cqs(send_cq, recv_cq); 5658 5659 if (!udata) { 5660 if (recv_cq) 5661 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5662 (hr_qp->ibqp.srq ? 5663 to_hr_srq(hr_qp->ibqp.srq) : 5664 NULL)); 5665 5666 if (send_cq && send_cq != recv_cq) 5667 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5668 } 5669 5670 hns_roce_qp_remove(hr_dev, hr_qp); 5671 5672 hns_roce_unlock_cqs(send_cq, recv_cq); 5673 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5674 5675 return ret; 5676 } 5677 5678 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev, 5679 struct hns_roce_qp *hr_qp) 5680 { 5681 struct hns_roce_dip *hr_dip = hr_qp->dip; 5682 5683 if (!hr_dip) 5684 return; 5685 5686 xa_lock(&hr_dev->qp_table.dip_xa); 5687 5688 hr_dip->qp_cnt--; 5689 if (!hr_dip->qp_cnt) 5690 memset(hr_dip->dgid, 0, GID_LEN_V2); 5691 5692 xa_unlock(&hr_dev->qp_table.dip_xa); 5693 } 5694 5695 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5696 { 5697 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5698 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5699 unsigned long flags; 5700 int ret; 5701 5702 /* Make sure flush_cqe() is completed */ 5703 spin_lock_irqsave(&hr_qp->flush_lock, flags); 5704 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag); 5705 spin_unlock_irqrestore(&hr_qp->flush_lock, flags); 5706 flush_work(&hr_qp->flush_work.work); 5707 5708 if (hr_qp->cong_type == CONG_TYPE_DIP) 5709 put_dip_ctx_idx(hr_dev, hr_qp); 5710 5711 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5712 if (ret) 5713 ibdev_err_ratelimited(&hr_dev->ib_dev, 5714 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5715 hr_qp->qpn, ret); 5716 5717 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5718 5719 return 0; 5720 } 5721 5722 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5723 struct hns_roce_qp *hr_qp) 5724 { 5725 struct ib_device *ibdev = &hr_dev->ib_dev; 5726 struct hns_roce_sccc_clr_done *resp; 5727 struct hns_roce_sccc_clr *clr; 5728 struct hns_roce_cmq_desc desc; 5729 int ret, i; 5730 5731 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5732 return 0; 5733 5734 mutex_lock(&hr_dev->qp_table.scc_mutex); 5735 5736 /* set scc ctx clear done flag */ 5737 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5738 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5739 if (ret) { 5740 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5741 goto out; 5742 } 5743 5744 /* clear scc context */ 5745 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5746 clr = (struct hns_roce_sccc_clr *)desc.data; 5747 clr->qpn = cpu_to_le32(hr_qp->qpn); 5748 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5749 if (ret) { 5750 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5751 goto out; 5752 } 5753 5754 /* query scc context clear is done or not */ 5755 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5756 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5757 hns_roce_cmq_setup_basic_desc(&desc, 5758 HNS_ROCE_OPC_QUERY_SCCC, true); 5759 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5760 if (ret) { 5761 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5762 ret); 5763 goto out; 5764 } 5765 5766 if (resp->clr_done) 5767 goto out; 5768 5769 msleep(20); 5770 } 5771 5772 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5773 ret = -ETIMEDOUT; 5774 5775 out: 5776 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5777 return ret; 5778 } 5779 5780 #define DMA_IDX_SHIFT 3 5781 #define DMA_WQE_SHIFT 3 5782 5783 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5784 struct hns_roce_srq_context *ctx) 5785 { 5786 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5787 struct ib_device *ibdev = srq->ibsrq.device; 5788 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5789 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5790 dma_addr_t dma_handle_idx; 5791 int ret; 5792 5793 /* Get physical address of idx que buf */ 5794 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5795 ARRAY_SIZE(mtts_idx)); 5796 if (ret) { 5797 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5798 ret); 5799 return ret; 5800 } 5801 5802 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 5803 5804 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5805 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5806 5807 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5808 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5809 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5810 5811 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5812 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5813 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5814 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5815 5816 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5817 to_hr_hw_page_addr(mtts_idx[0])); 5818 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5819 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5820 5821 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5822 to_hr_hw_page_addr(mtts_idx[1])); 5823 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5824 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5825 5826 return 0; 5827 } 5828 5829 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5830 { 5831 struct ib_device *ibdev = srq->ibsrq.device; 5832 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5833 struct hns_roce_srq_context *ctx = mb_buf; 5834 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5835 dma_addr_t dma_handle_wqe; 5836 int ret; 5837 5838 memset(ctx, 0, sizeof(*ctx)); 5839 5840 /* Get the physical address of srq buf */ 5841 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5842 ARRAY_SIZE(mtts_wqe)); 5843 if (ret) { 5844 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5845 ret); 5846 return ret; 5847 } 5848 5849 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 5850 5851 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5852 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5853 srq->ibsrq.srq_type == IB_SRQT_XRC); 5854 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5855 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5856 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5857 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5858 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5859 hr_reg_write(ctx, SRQC_RQWS, 5860 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5861 5862 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5863 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5864 srq->wqe_cnt)); 5865 5866 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5867 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5868 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5869 5870 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5871 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5872 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5873 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5874 5875 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5876 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5877 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5878 lower_32_bits(srq->rdb.dma) >> 1); 5879 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5880 upper_32_bits(srq->rdb.dma)); 5881 } 5882 5883 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5884 } 5885 5886 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5887 struct ib_srq_attr *srq_attr, 5888 enum ib_srq_attr_mask srq_attr_mask, 5889 struct ib_udata *udata) 5890 { 5891 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5892 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5893 struct hns_roce_srq_context *srq_context; 5894 struct hns_roce_srq_context *srqc_mask; 5895 struct hns_roce_cmd_mailbox *mailbox; 5896 int ret = 0; 5897 5898 /* Resizing SRQs is not supported yet */ 5899 if (srq_attr_mask & IB_SRQ_MAX_WR) { 5900 ret = -EOPNOTSUPP; 5901 goto out; 5902 } 5903 5904 if (srq_attr_mask & IB_SRQ_LIMIT) { 5905 if (srq_attr->srq_limit > srq->wqe_cnt) { 5906 ret = -EINVAL; 5907 goto out; 5908 } 5909 5910 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5911 if (IS_ERR(mailbox)) { 5912 ret = PTR_ERR(mailbox); 5913 goto out; 5914 } 5915 5916 srq_context = mailbox->buf; 5917 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5918 5919 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5920 5921 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5922 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5923 5924 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5925 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5926 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5927 if (ret) 5928 ibdev_err(&hr_dev->ib_dev, 5929 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5930 ret); 5931 } 5932 5933 out: 5934 if (ret) 5935 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 5936 5937 return ret; 5938 } 5939 5940 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5941 { 5942 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5943 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5944 struct hns_roce_srq_context *srq_context; 5945 struct hns_roce_cmd_mailbox *mailbox; 5946 int ret; 5947 5948 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5949 if (IS_ERR(mailbox)) 5950 return PTR_ERR(mailbox); 5951 5952 srq_context = mailbox->buf; 5953 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5954 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5955 if (ret) { 5956 ibdev_err(&hr_dev->ib_dev, 5957 "failed to process cmd of querying SRQ, ret = %d.\n", 5958 ret); 5959 goto out; 5960 } 5961 5962 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5963 attr->max_wr = srq->wqe_cnt; 5964 attr->max_sge = srq->max_gs - srq->rsv_sge; 5965 5966 out: 5967 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5968 return ret; 5969 } 5970 5971 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5972 { 5973 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5974 struct hns_roce_v2_cq_context *cq_context; 5975 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5976 struct hns_roce_v2_cq_context *cqc_mask; 5977 struct hns_roce_cmd_mailbox *mailbox; 5978 int ret; 5979 5980 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5981 ret = PTR_ERR_OR_ZERO(mailbox); 5982 if (ret) 5983 goto err_out; 5984 5985 cq_context = mailbox->buf; 5986 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5987 5988 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5989 5990 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5991 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5992 5993 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5994 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5995 dev_info(hr_dev->dev, 5996 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5997 cq_period); 5998 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 5999 } 6000 cq_period *= HNS_ROCE_CLOCK_ADJUST; 6001 } 6002 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 6003 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 6004 6005 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 6006 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 6007 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6008 if (ret) 6009 ibdev_err_ratelimited(&hr_dev->ib_dev, 6010 "failed to process cmd when modifying CQ, ret = %d.\n", 6011 ret); 6012 6013 err_out: 6014 if (ret) 6015 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 6016 6017 return ret; 6018 } 6019 6020 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 6021 void *buffer) 6022 { 6023 struct hns_roce_v2_cq_context *context; 6024 struct hns_roce_cmd_mailbox *mailbox; 6025 int ret; 6026 6027 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6028 if (IS_ERR(mailbox)) 6029 return PTR_ERR(mailbox); 6030 6031 context = mailbox->buf; 6032 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 6033 HNS_ROCE_CMD_QUERY_CQC, cqn); 6034 if (ret) { 6035 ibdev_err_ratelimited(&hr_dev->ib_dev, 6036 "failed to process cmd when querying CQ, ret = %d.\n", 6037 ret); 6038 goto err_mailbox; 6039 } 6040 6041 memcpy(buffer, context, sizeof(*context)); 6042 6043 err_mailbox: 6044 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6045 6046 return ret; 6047 } 6048 6049 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 6050 void *buffer) 6051 { 6052 struct hns_roce_v2_mpt_entry *context; 6053 struct hns_roce_cmd_mailbox *mailbox; 6054 int ret; 6055 6056 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6057 if (IS_ERR(mailbox)) 6058 return PTR_ERR(mailbox); 6059 6060 context = mailbox->buf; 6061 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 6062 key_to_hw_index(key)); 6063 if (ret) { 6064 ibdev_err(&hr_dev->ib_dev, 6065 "failed to process cmd when querying MPT, ret = %d.\n", 6066 ret); 6067 goto err_mailbox; 6068 } 6069 6070 memcpy(buffer, context, sizeof(*context)); 6071 6072 err_mailbox: 6073 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6074 6075 return ret; 6076 } 6077 6078 static void dump_aeqe_log(struct hns_roce_work *irq_work) 6079 { 6080 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6081 struct ib_device *ibdev = &hr_dev->ib_dev; 6082 6083 switch (irq_work->event_type) { 6084 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6085 ibdev_info(ibdev, "path migrated succeeded.\n"); 6086 break; 6087 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6088 ibdev_warn(ibdev, "path migration failed.\n"); 6089 break; 6090 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6091 break; 6092 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6093 ibdev_dbg(ibdev, "send queue drained.\n"); 6094 break; 6095 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6096 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 6097 irq_work->queue_num, irq_work->sub_type); 6098 break; 6099 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6100 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 6101 irq_work->queue_num); 6102 break; 6103 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6104 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 6105 irq_work->queue_num, irq_work->sub_type); 6106 break; 6107 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6108 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 6109 break; 6110 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6111 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 6112 break; 6113 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6114 ibdev_err(ibdev, "SRQ catas error.\n"); 6115 break; 6116 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6117 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 6118 break; 6119 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6120 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 6121 break; 6122 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6123 ibdev_warn(ibdev, "DB overflow.\n"); 6124 break; 6125 case HNS_ROCE_EVENT_TYPE_MB: 6126 break; 6127 case HNS_ROCE_EVENT_TYPE_FLR: 6128 ibdev_warn(ibdev, "function level reset.\n"); 6129 break; 6130 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6131 ibdev_err(ibdev, "xrc domain violation error.\n"); 6132 break; 6133 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6134 ibdev_err(ibdev, "invalid xrceth error.\n"); 6135 break; 6136 default: 6137 ibdev_info(ibdev, "Undefined event %d.\n", 6138 irq_work->event_type); 6139 break; 6140 } 6141 } 6142 6143 static void hns_roce_irq_work_handle(struct work_struct *work) 6144 { 6145 struct hns_roce_work *irq_work = 6146 container_of(work, struct hns_roce_work, work); 6147 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6148 int event_type = irq_work->event_type; 6149 u32 queue_num = irq_work->queue_num; 6150 6151 switch (event_type) { 6152 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6153 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6154 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6155 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6156 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6157 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6158 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6159 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6160 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6161 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6162 hns_roce_qp_event(hr_dev, queue_num, event_type); 6163 break; 6164 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6165 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6166 hns_roce_srq_event(hr_dev, queue_num, event_type); 6167 break; 6168 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6169 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6170 hns_roce_cq_event(hr_dev, queue_num, event_type); 6171 break; 6172 default: 6173 break; 6174 } 6175 6176 dump_aeqe_log(irq_work); 6177 6178 kfree(irq_work); 6179 } 6180 6181 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 6182 struct hns_roce_eq *eq, u32 queue_num) 6183 { 6184 struct hns_roce_work *irq_work; 6185 6186 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 6187 if (!irq_work) 6188 return; 6189 6190 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 6191 irq_work->hr_dev = hr_dev; 6192 irq_work->event_type = eq->event_type; 6193 irq_work->sub_type = eq->sub_type; 6194 irq_work->queue_num = queue_num; 6195 queue_work(hr_dev->irq_workq, &irq_work->work); 6196 } 6197 6198 static void update_eq_db(struct hns_roce_eq *eq) 6199 { 6200 struct hns_roce_dev *hr_dev = eq->hr_dev; 6201 struct hns_roce_v2_db eq_db = {}; 6202 6203 if (eq->type_flag == HNS_ROCE_AEQ) { 6204 hr_reg_write(&eq_db, EQ_DB_CMD, 6205 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6206 HNS_ROCE_EQ_DB_CMD_AEQ : 6207 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 6208 } else { 6209 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 6210 6211 hr_reg_write(&eq_db, EQ_DB_CMD, 6212 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6213 HNS_ROCE_EQ_DB_CMD_CEQ : 6214 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 6215 } 6216 6217 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 6218 6219 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 6220 } 6221 6222 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6223 { 6224 struct hns_roce_aeqe *aeqe; 6225 6226 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6227 (eq->cons_index & (eq->entries - 1)) * 6228 eq->eqe_size); 6229 6230 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6231 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6232 } 6233 6234 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6235 struct hns_roce_eq *eq) 6236 { 6237 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6238 irqreturn_t aeqe_found = IRQ_NONE; 6239 int num_aeqes = 0; 6240 int event_type; 6241 u32 queue_num; 6242 int sub_type; 6243 6244 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) { 6245 /* Make sure we read AEQ entry after we have checked the 6246 * ownership bit 6247 */ 6248 dma_rmb(); 6249 6250 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6251 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6252 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6253 6254 switch (event_type) { 6255 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6256 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6257 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6258 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6259 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6260 hns_roce_flush_cqe(hr_dev, queue_num); 6261 break; 6262 case HNS_ROCE_EVENT_TYPE_MB: 6263 hns_roce_cmd_event(hr_dev, 6264 le16_to_cpu(aeqe->event.cmd.token), 6265 aeqe->event.cmd.status, 6266 le64_to_cpu(aeqe->event.cmd.out_param)); 6267 break; 6268 default: 6269 break; 6270 } 6271 6272 eq->event_type = event_type; 6273 eq->sub_type = sub_type; 6274 ++eq->cons_index; 6275 aeqe_found = IRQ_HANDLED; 6276 trace_hns_ae_info(event_type, aeqe, eq->eqe_size); 6277 6278 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6279 6280 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6281 6282 aeqe = next_aeqe_sw_v2(eq); 6283 ++num_aeqes; 6284 } 6285 6286 update_eq_db(eq); 6287 6288 return IRQ_RETVAL(aeqe_found); 6289 } 6290 6291 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6292 { 6293 struct hns_roce_ceqe *ceqe; 6294 6295 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6296 (eq->cons_index & (eq->entries - 1)) * 6297 eq->eqe_size); 6298 6299 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6300 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6301 } 6302 6303 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) 6304 { 6305 queue_work(system_bh_wq, &eq->work); 6306 6307 return IRQ_HANDLED; 6308 } 6309 6310 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6311 { 6312 struct hns_roce_eq *eq = eq_ptr; 6313 struct hns_roce_dev *hr_dev = eq->hr_dev; 6314 irqreturn_t int_work; 6315 6316 if (eq->type_flag == HNS_ROCE_CEQ) 6317 /* Completion event interrupt */ 6318 int_work = hns_roce_v2_ceq_int(eq); 6319 else 6320 /* Asynchronous event interrupt */ 6321 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6322 6323 return IRQ_RETVAL(int_work); 6324 } 6325 6326 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6327 u32 int_st) 6328 { 6329 struct pci_dev *pdev = hr_dev->pci_dev; 6330 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6331 const struct hnae3_ae_ops *ops = ae_dev->ops; 6332 enum hnae3_reset_type reset_type; 6333 irqreturn_t int_work = IRQ_NONE; 6334 u32 int_en; 6335 6336 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6337 6338 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6339 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6340 6341 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6342 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6343 6344 reset_type = hr_dev->is_vf ? 6345 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET; 6346 6347 /* Set reset level for reset_event() */ 6348 if (ops->set_default_reset_request) 6349 ops->set_default_reset_request(ae_dev, reset_type); 6350 if (ops->reset_event) 6351 ops->reset_event(pdev, NULL); 6352 6353 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6354 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6355 6356 int_work = IRQ_HANDLED; 6357 } else { 6358 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6359 } 6360 6361 return IRQ_RETVAL(int_work); 6362 } 6363 6364 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6365 struct fmea_ram_ecc *ecc_info) 6366 { 6367 struct hns_roce_cmq_desc desc; 6368 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6369 int ret; 6370 6371 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6372 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6373 if (ret) 6374 return ret; 6375 6376 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6377 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6378 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6379 6380 return 0; 6381 } 6382 6383 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6384 { 6385 struct hns_roce_cmq_desc desc; 6386 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6387 u32 addr_upper; 6388 u32 addr_low; 6389 int ret; 6390 6391 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6392 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6393 6394 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6395 if (ret) { 6396 dev_err(hr_dev->dev, 6397 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6398 return ret; 6399 } 6400 6401 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6402 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6403 6404 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6405 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6406 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6407 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6408 6409 return hns_roce_cmq_send(hr_dev, &desc, 1); 6410 } 6411 6412 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6413 { 6414 if (res_type == ECC_RESOURCE_QPC_TIMER || 6415 res_type == ECC_RESOURCE_CQC_TIMER || 6416 res_type == ECC_RESOURCE_SCCC) 6417 return le64_to_cpu(*data); 6418 6419 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT; 6420 } 6421 6422 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6423 u32 index) 6424 { 6425 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6426 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6427 struct hns_roce_cmd_mailbox *mailbox; 6428 u64 addr; 6429 int ret; 6430 6431 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6432 if (IS_ERR(mailbox)) 6433 return PTR_ERR(mailbox); 6434 6435 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6436 if (ret) { 6437 dev_err(hr_dev->dev, 6438 "failed to execute cmd to read fmea ram, ret = %d.\n", 6439 ret); 6440 goto out; 6441 } 6442 6443 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6444 6445 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6446 if (ret) 6447 dev_err(hr_dev->dev, 6448 "failed to execute cmd to write fmea ram, ret = %d.\n", 6449 ret); 6450 6451 out: 6452 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6453 return ret; 6454 } 6455 6456 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6457 struct fmea_ram_ecc *ecc_info) 6458 { 6459 u32 res_type = ecc_info->res_type; 6460 u32 index = ecc_info->index; 6461 int ret; 6462 6463 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6464 6465 if (res_type >= ECC_RESOURCE_COUNT) { 6466 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6467 res_type); 6468 return; 6469 } 6470 6471 if (res_type == ECC_RESOURCE_GMV) 6472 ret = fmea_recover_gmv(hr_dev, index); 6473 else 6474 ret = fmea_recover_others(hr_dev, res_type, index); 6475 if (ret) 6476 dev_err(hr_dev->dev, 6477 "failed to recover %s, index = %u, ret = %d.\n", 6478 fmea_ram_res[res_type].name, index, ret); 6479 } 6480 6481 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6482 { 6483 struct hns_roce_dev *hr_dev = 6484 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6485 struct fmea_ram_ecc ecc_info = {}; 6486 6487 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6488 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6489 return; 6490 } 6491 6492 if (!ecc_info.is_ecc_err) { 6493 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6494 return; 6495 } 6496 6497 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6498 } 6499 6500 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6501 { 6502 struct hns_roce_dev *hr_dev = dev_id; 6503 irqreturn_t int_work = IRQ_NONE; 6504 u32 int_st; 6505 6506 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6507 6508 if (int_st) { 6509 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6510 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6511 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6512 int_work = IRQ_HANDLED; 6513 } else { 6514 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6515 } 6516 6517 return IRQ_RETVAL(int_work); 6518 } 6519 6520 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6521 int eq_num, u32 enable_flag) 6522 { 6523 int i; 6524 6525 for (i = 0; i < eq_num; i++) 6526 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6527 i * EQ_REG_OFFSET, enable_flag); 6528 6529 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6530 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6531 } 6532 6533 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6534 { 6535 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6536 } 6537 6538 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6539 struct hns_roce_eq *eq) 6540 { 6541 struct device *dev = hr_dev->dev; 6542 int eqn = eq->eqn; 6543 int ret; 6544 u8 cmd; 6545 6546 if (eqn < hr_dev->caps.num_comp_vectors) 6547 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6548 else 6549 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6550 6551 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6552 if (ret) 6553 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6554 6555 free_eq_buf(hr_dev, eq); 6556 } 6557 6558 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6559 { 6560 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6561 eq->cons_index = 0; 6562 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6563 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6564 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6565 eq->shift = ilog2((unsigned int)eq->entries); 6566 } 6567 6568 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6569 void *mb_buf) 6570 { 6571 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6572 struct hns_roce_eq_context *eqc; 6573 u64 bt_ba = 0; 6574 int ret; 6575 6576 eqc = mb_buf; 6577 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6578 6579 init_eq_config(hr_dev, eq); 6580 6581 /* if not multi-hop, eqe buffer only use one trunk */ 6582 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6583 ARRAY_SIZE(eqe_ba)); 6584 if (ret) { 6585 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6586 return ret; 6587 } 6588 6589 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6590 6591 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6592 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6593 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6594 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6595 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6596 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6597 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6598 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6599 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6600 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6601 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6602 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6603 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6604 6605 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6606 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6607 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6608 eq->eq_period); 6609 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6610 } 6611 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6612 } 6613 6614 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6615 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6616 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6617 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6618 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6619 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6620 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6621 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6622 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6623 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6624 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6625 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6626 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6627 6628 return 0; 6629 } 6630 6631 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6632 { 6633 struct hns_roce_buf_attr buf_attr = {}; 6634 int err; 6635 6636 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6637 eq->hop_num = 0; 6638 else 6639 eq->hop_num = hr_dev->caps.eqe_hop_num; 6640 6641 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6642 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6643 buf_attr.region[0].hopnum = eq->hop_num; 6644 buf_attr.region_count = 1; 6645 6646 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6647 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6648 0); 6649 if (err) 6650 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6651 6652 return err; 6653 } 6654 6655 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6656 struct hns_roce_eq *eq, u8 eq_cmd) 6657 { 6658 struct hns_roce_cmd_mailbox *mailbox; 6659 int ret; 6660 6661 /* Allocate mailbox memory */ 6662 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6663 if (IS_ERR(mailbox)) 6664 return PTR_ERR(mailbox); 6665 6666 ret = alloc_eq_buf(hr_dev, eq); 6667 if (ret) 6668 goto free_cmd_mbox; 6669 6670 ret = config_eqc(hr_dev, eq, mailbox->buf); 6671 if (ret) 6672 goto err_cmd_mbox; 6673 6674 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6675 if (ret) { 6676 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6677 goto err_cmd_mbox; 6678 } 6679 6680 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6681 6682 return 0; 6683 6684 err_cmd_mbox: 6685 free_eq_buf(hr_dev, eq); 6686 6687 free_cmd_mbox: 6688 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6689 6690 return ret; 6691 } 6692 6693 static void hns_roce_ceq_work(struct work_struct *work) 6694 { 6695 struct hns_roce_eq *eq = from_work(eq, work, work); 6696 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6697 struct hns_roce_dev *hr_dev = eq->hr_dev; 6698 int ceqe_num = 0; 6699 u32 cqn; 6700 6701 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) { 6702 /* Make sure we read CEQ entry after we have checked the 6703 * ownership bit 6704 */ 6705 dma_rmb(); 6706 6707 cqn = hr_reg_read(ceqe, CEQE_CQN); 6708 6709 hns_roce_cq_completion(hr_dev, cqn); 6710 6711 ++eq->cons_index; 6712 ++ceqe_num; 6713 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6714 6715 ceqe = next_ceqe_sw_v2(eq); 6716 } 6717 6718 update_eq_db(eq); 6719 } 6720 6721 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6722 int comp_num, int aeq_num, int other_num) 6723 { 6724 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6725 int i, j; 6726 int ret; 6727 6728 for (i = 0; i < irq_num; i++) { 6729 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6730 GFP_KERNEL); 6731 if (!hr_dev->irq_names[i]) { 6732 ret = -ENOMEM; 6733 goto err_kzalloc_failed; 6734 } 6735 } 6736 6737 /* irq contains: abnormal + AEQ + CEQ */ 6738 for (j = 0; j < other_num; j++) 6739 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6740 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 6741 6742 for (j = other_num; j < (other_num + aeq_num); j++) 6743 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6744 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 6745 6746 for (j = (other_num + aeq_num); j < irq_num; j++) 6747 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6748 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 6749 j - other_num - aeq_num); 6750 6751 for (j = 0; j < irq_num; j++) { 6752 if (j < other_num) { 6753 ret = request_irq(hr_dev->irq[j], 6754 hns_roce_v2_msix_interrupt_abn, 6755 0, hr_dev->irq_names[j], hr_dev); 6756 } else if (j < (other_num + comp_num)) { 6757 INIT_WORK(&eq_table->eq[j - other_num].work, 6758 hns_roce_ceq_work); 6759 ret = request_irq(eq_table->eq[j - other_num].irq, 6760 hns_roce_v2_msix_interrupt_eq, 6761 0, hr_dev->irq_names[j + aeq_num], 6762 &eq_table->eq[j - other_num]); 6763 } else { 6764 ret = request_irq(eq_table->eq[j - other_num].irq, 6765 hns_roce_v2_msix_interrupt_eq, 6766 0, hr_dev->irq_names[j - comp_num], 6767 &eq_table->eq[j - other_num]); 6768 } 6769 6770 if (ret) { 6771 dev_err(hr_dev->dev, "request irq error!\n"); 6772 goto err_request_failed; 6773 } 6774 } 6775 6776 return 0; 6777 6778 err_request_failed: 6779 for (j -= 1; j >= 0; j--) { 6780 if (j < other_num) { 6781 free_irq(hr_dev->irq[j], hr_dev); 6782 continue; 6783 } 6784 free_irq(eq_table->eq[j - other_num].irq, 6785 &eq_table->eq[j - other_num]); 6786 if (j < other_num + comp_num) 6787 cancel_work_sync(&eq_table->eq[j - other_num].work); 6788 } 6789 6790 err_kzalloc_failed: 6791 for (i -= 1; i >= 0; i--) 6792 kfree(hr_dev->irq_names[i]); 6793 6794 return ret; 6795 } 6796 6797 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6798 { 6799 int irq_num; 6800 int eq_num; 6801 int i; 6802 6803 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6804 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6805 6806 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6807 free_irq(hr_dev->irq[i], hr_dev); 6808 6809 for (i = 0; i < eq_num; i++) { 6810 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6811 if (i < hr_dev->caps.num_comp_vectors) 6812 cancel_work_sync(&hr_dev->eq_table.eq[i].work); 6813 } 6814 6815 for (i = 0; i < irq_num; i++) 6816 kfree(hr_dev->irq_names[i]); 6817 } 6818 6819 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6820 { 6821 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6822 struct device *dev = hr_dev->dev; 6823 struct hns_roce_eq *eq; 6824 int other_num; 6825 int comp_num; 6826 int aeq_num; 6827 int irq_num; 6828 int eq_num; 6829 u8 eq_cmd; 6830 int ret; 6831 int i; 6832 6833 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET) 6834 return -EINVAL; 6835 6836 other_num = hr_dev->caps.num_other_vectors; 6837 comp_num = hr_dev->caps.num_comp_vectors; 6838 aeq_num = hr_dev->caps.num_aeq_vectors; 6839 6840 eq_num = comp_num + aeq_num; 6841 irq_num = eq_num + other_num; 6842 6843 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6844 if (!eq_table->eq) 6845 return -ENOMEM; 6846 6847 /* create eq */ 6848 for (i = 0; i < eq_num; i++) { 6849 eq = &eq_table->eq[i]; 6850 eq->hr_dev = hr_dev; 6851 eq->eqn = i; 6852 if (i < comp_num) { 6853 /* CEQ */ 6854 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6855 eq->type_flag = HNS_ROCE_CEQ; 6856 eq->entries = hr_dev->caps.ceqe_depth; 6857 eq->eqe_size = hr_dev->caps.ceqe_size; 6858 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6859 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6860 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6861 } else { 6862 /* AEQ */ 6863 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6864 eq->type_flag = HNS_ROCE_AEQ; 6865 eq->entries = hr_dev->caps.aeqe_depth; 6866 eq->eqe_size = hr_dev->caps.aeqe_size; 6867 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6868 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6869 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6870 } 6871 6872 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6873 if (ret) { 6874 dev_err(dev, "failed to create eq.\n"); 6875 goto err_create_eq_fail; 6876 } 6877 } 6878 6879 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6880 6881 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6882 if (!hr_dev->irq_workq) { 6883 dev_err(dev, "failed to create irq workqueue.\n"); 6884 ret = -ENOMEM; 6885 goto err_create_eq_fail; 6886 } 6887 6888 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6889 other_num); 6890 if (ret) { 6891 dev_err(dev, "failed to request irq.\n"); 6892 goto err_request_irq_fail; 6893 } 6894 6895 /* enable irq */ 6896 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6897 6898 return 0; 6899 6900 err_request_irq_fail: 6901 destroy_workqueue(hr_dev->irq_workq); 6902 6903 err_create_eq_fail: 6904 for (i -= 1; i >= 0; i--) 6905 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6906 kfree(eq_table->eq); 6907 6908 return ret; 6909 } 6910 6911 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6912 { 6913 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6914 int eq_num; 6915 int i; 6916 6917 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6918 6919 /* Disable irq */ 6920 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6921 6922 __hns_roce_free_irq(hr_dev); 6923 destroy_workqueue(hr_dev->irq_workq); 6924 6925 for (i = 0; i < eq_num; i++) 6926 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6927 6928 kfree(eq_table->eq); 6929 } 6930 6931 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6932 .destroy_qp = hns_roce_v2_destroy_qp, 6933 .modify_cq = hns_roce_v2_modify_cq, 6934 .poll_cq = hns_roce_v2_poll_cq, 6935 .post_recv = hns_roce_v2_post_recv, 6936 .post_send = hns_roce_v2_post_send, 6937 .query_qp = hns_roce_v2_query_qp, 6938 .req_notify_cq = hns_roce_v2_req_notify_cq, 6939 }; 6940 6941 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6942 .modify_srq = hns_roce_v2_modify_srq, 6943 .post_srq_recv = hns_roce_v2_post_srq_recv, 6944 .query_srq = hns_roce_v2_query_srq, 6945 }; 6946 6947 static const struct hns_roce_hw hns_roce_hw_v2 = { 6948 .cmq_init = hns_roce_v2_cmq_init, 6949 .cmq_exit = hns_roce_v2_cmq_exit, 6950 .hw_profile = hns_roce_v2_profile, 6951 .hw_init = hns_roce_v2_init, 6952 .hw_exit = hns_roce_v2_exit, 6953 .post_mbox = v2_post_mbox, 6954 .poll_mbox_done = v2_poll_mbox_done, 6955 .chk_mbox_avail = v2_chk_mbox_is_avail, 6956 .set_gid = hns_roce_v2_set_gid, 6957 .set_mac = hns_roce_v2_set_mac, 6958 .write_mtpt = hns_roce_v2_write_mtpt, 6959 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6960 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6961 .write_cqc = hns_roce_v2_write_cqc, 6962 .set_hem = hns_roce_v2_set_hem, 6963 .clear_hem = hns_roce_v2_clear_hem, 6964 .modify_qp = hns_roce_v2_modify_qp, 6965 .dereg_mr = hns_roce_v2_dereg_mr, 6966 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6967 .init_eq = hns_roce_v2_init_eq_table, 6968 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6969 .write_srqc = hns_roce_v2_write_srqc, 6970 .query_cqc = hns_roce_v2_query_cqc, 6971 .query_qpc = hns_roce_v2_query_qpc, 6972 .query_mpt = hns_roce_v2_query_mpt, 6973 .query_srqc = hns_roce_v2_query_srqc, 6974 .query_sccc = hns_roce_v2_query_sccc, 6975 .query_hw_counter = hns_roce_hw_v2_query_counter, 6976 .get_dscp = hns_roce_hw_v2_get_dscp, 6977 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6978 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6979 }; 6980 6981 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6982 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6983 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6984 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6985 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6986 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6987 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6988 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6989 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6990 /* required last entry */ 6991 {0, } 6992 }; 6993 6994 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6995 6996 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6997 struct hnae3_handle *handle) 6998 { 6999 struct hns_roce_v2_priv *priv = hr_dev->priv; 7000 const struct pci_device_id *id; 7001 int i; 7002 7003 hr_dev->pci_dev = handle->pdev; 7004 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 7005 hr_dev->is_vf = id->driver_data; 7006 hr_dev->dev = &handle->pdev->dev; 7007 hr_dev->hw = &hns_roce_hw_v2; 7008 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 7009 hr_dev->odb_offset = hr_dev->sdb_offset; 7010 7011 /* Get info from NIC driver. */ 7012 hr_dev->reg_base = handle->rinfo.roce_io_base; 7013 hr_dev->mem_base = handle->rinfo.roce_mem_base; 7014 hr_dev->caps.num_ports = 1; 7015 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 7016 hr_dev->iboe.phy_port[0] = 0; 7017 7018 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 7019 hr_dev->iboe.netdevs[0]->dev_addr); 7020 7021 for (i = 0; i < handle->rinfo.num_vectors; i++) 7022 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 7023 i + handle->rinfo.base_vector); 7024 7025 /* cmd issue mode: 0 is poll, 1 is event */ 7026 hr_dev->cmd_mod = 1; 7027 hr_dev->loop_idc = 0; 7028 7029 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 7030 priv->handle = handle; 7031 } 7032 7033 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7034 { 7035 struct hns_roce_dev *hr_dev; 7036 int ret; 7037 7038 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 7039 if (!hr_dev) 7040 return -ENOMEM; 7041 7042 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 7043 if (!hr_dev->priv) { 7044 ret = -ENOMEM; 7045 goto error_failed_kzalloc; 7046 } 7047 7048 hns_roce_hw_v2_get_cfg(hr_dev, handle); 7049 7050 ret = hns_roce_init(hr_dev); 7051 if (ret) { 7052 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 7053 goto error_failed_roce_init; 7054 } 7055 7056 handle->priv = hr_dev; 7057 7058 return 0; 7059 7060 error_failed_roce_init: 7061 kfree(hr_dev->priv); 7062 7063 error_failed_kzalloc: 7064 ib_dealloc_device(&hr_dev->ib_dev); 7065 7066 return ret; 7067 } 7068 7069 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7070 bool reset) 7071 { 7072 struct hns_roce_dev *hr_dev = handle->priv; 7073 7074 if (!hr_dev) 7075 return; 7076 7077 handle->priv = NULL; 7078 7079 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 7080 hns_roce_handle_device_err(hr_dev); 7081 7082 hns_roce_exit(hr_dev); 7083 kfree(hr_dev->priv); 7084 ib_dealloc_device(&hr_dev->ib_dev); 7085 } 7086 7087 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7088 { 7089 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 7090 const struct pci_device_id *id; 7091 struct device *dev = &handle->pdev->dev; 7092 int ret; 7093 7094 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 7095 7096 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 7097 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7098 goto reset_chk_err; 7099 } 7100 7101 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 7102 if (!id) 7103 return 0; 7104 7105 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 7106 return 0; 7107 7108 ret = __hns_roce_hw_v2_init_instance(handle); 7109 if (ret) { 7110 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7111 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 7112 if (ops->ae_dev_resetting(handle) || 7113 ops->get_hw_reset_stat(handle)) 7114 goto reset_chk_err; 7115 else 7116 return ret; 7117 } 7118 7119 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 7120 7121 return 0; 7122 7123 reset_chk_err: 7124 dev_err(dev, "Device is busy in resetting state.\n" 7125 "please retry later.\n"); 7126 7127 return -EBUSY; 7128 } 7129 7130 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7131 bool reset) 7132 { 7133 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7134 return; 7135 7136 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 7137 7138 __hns_roce_hw_v2_uninit_instance(handle, reset); 7139 7140 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7141 } 7142 7143 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 7144 { 7145 struct hns_roce_dev *hr_dev; 7146 7147 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 7148 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7149 return 0; 7150 } 7151 7152 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 7153 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7154 7155 hr_dev = handle->priv; 7156 if (!hr_dev) 7157 return 0; 7158 7159 hr_dev->active = false; 7160 hr_dev->dis_db = true; 7161 7162 rdma_user_mmap_disassociate(&hr_dev->ib_dev); 7163 7164 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 7165 7166 return 0; 7167 } 7168 7169 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 7170 { 7171 struct device *dev = &handle->pdev->dev; 7172 int ret; 7173 7174 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 7175 &handle->rinfo.state)) { 7176 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7177 return 0; 7178 } 7179 7180 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 7181 7182 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 7183 ret = __hns_roce_hw_v2_init_instance(handle); 7184 if (ret) { 7185 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 7186 * callback function, RoCE Engine reinitialize. If RoCE reinit 7187 * failed, we should inform NIC driver. 7188 */ 7189 handle->priv = NULL; 7190 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 7191 } else { 7192 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7193 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 7194 } 7195 7196 return ret; 7197 } 7198 7199 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 7200 { 7201 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 7202 return 0; 7203 7204 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 7205 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 7206 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 7207 __hns_roce_hw_v2_uninit_instance(handle, false); 7208 7209 return 0; 7210 } 7211 7212 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 7213 enum hnae3_reset_notify_type type) 7214 { 7215 int ret = 0; 7216 7217 switch (type) { 7218 case HNAE3_DOWN_CLIENT: 7219 ret = hns_roce_hw_v2_reset_notify_down(handle); 7220 break; 7221 case HNAE3_INIT_CLIENT: 7222 ret = hns_roce_hw_v2_reset_notify_init(handle); 7223 break; 7224 case HNAE3_UNINIT_CLIENT: 7225 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 7226 break; 7227 default: 7228 break; 7229 } 7230 7231 return ret; 7232 } 7233 7234 static void hns_roce_hw_v2_link_status_change(struct hnae3_handle *handle, 7235 bool linkup) 7236 { 7237 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 7238 struct net_device *netdev = handle->rinfo.netdev; 7239 7240 if (linkup || !hr_dev) 7241 return; 7242 7243 ib_dispatch_port_state_event(&hr_dev->ib_dev, netdev); 7244 } 7245 7246 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7247 .init_instance = hns_roce_hw_v2_init_instance, 7248 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7249 .link_status_change = hns_roce_hw_v2_link_status_change, 7250 .reset_notify = hns_roce_hw_v2_reset_notify, 7251 }; 7252 7253 static struct hnae3_client hns_roce_hw_v2_client = { 7254 .name = "hns_roce_hw_v2", 7255 .type = HNAE3_CLIENT_ROCE, 7256 .ops = &hns_roce_hw_v2_ops, 7257 }; 7258 7259 static int __init hns_roce_hw_v2_init(void) 7260 { 7261 hns_roce_init_debugfs(); 7262 return hnae3_register_client(&hns_roce_hw_v2_client); 7263 } 7264 7265 static void __exit hns_roce_hw_v2_exit(void) 7266 { 7267 hnae3_unregister_client(&hns_roce_hw_v2_client); 7268 hns_roce_cleanup_debugfs(); 7269 } 7270 7271 module_init(hns_roce_hw_v2_init); 7272 module_exit(hns_roce_hw_v2_exit); 7273 7274 MODULE_LICENSE("Dual BSD/GPL"); 7275 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7276 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7277 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7278 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7279