1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <net/addrconf.h> 38 #include <rdma/ib_umem.h> 39 40 #include "hnae3.h" 41 #include "hns_roce_common.h" 42 #include "hns_roce_device.h" 43 #include "hns_roce_cmd.h" 44 #include "hns_roce_hem.h" 45 #include "hns_roce_hw_v2.h" 46 47 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 48 struct ib_sge *sg) 49 { 50 dseg->lkey = cpu_to_le32(sg->lkey); 51 dseg->addr = cpu_to_le64(sg->addr); 52 dseg->len = cpu_to_le32(sg->length); 53 } 54 55 static int set_rwqe_data_seg(struct ib_qp *ibqp, struct ib_send_wr *wr, 56 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 57 void *wqe, unsigned int *sge_ind, 58 struct ib_send_wr **bad_wr) 59 { 60 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 61 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 62 struct hns_roce_qp *qp = to_hr_qp(ibqp); 63 int i; 64 65 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) { 66 if (rc_sq_wqe->msg_len > hr_dev->caps.max_sq_inline) { 67 *bad_wr = wr; 68 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal", 69 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline); 70 return -EINVAL; 71 } 72 73 for (i = 0; i < wr->num_sge; i++) { 74 memcpy(wqe, ((void *)wr->sg_list[i].addr), 75 wr->sg_list[i].length); 76 wqe += wr->sg_list[i].length; 77 } 78 79 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 80 1); 81 } else { 82 if (wr->num_sge <= 2) { 83 for (i = 0; i < wr->num_sge; i++) { 84 if (likely(wr->sg_list[i].length)) { 85 set_data_seg_v2(dseg, wr->sg_list + i); 86 dseg++; 87 } 88 } 89 } else { 90 roce_set_field(rc_sq_wqe->byte_20, 91 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 92 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 93 (*sge_ind) & (qp->sge.sge_cnt - 1)); 94 95 for (i = 0; i < 2; i++) { 96 if (likely(wr->sg_list[i].length)) { 97 set_data_seg_v2(dseg, wr->sg_list + i); 98 dseg++; 99 } 100 } 101 102 dseg = get_send_extend_sge(qp, 103 (*sge_ind) & (qp->sge.sge_cnt - 1)); 104 105 for (i = 0; i < wr->num_sge - 2; i++) { 106 if (likely(wr->sg_list[i + 2].length)) { 107 set_data_seg_v2(dseg, 108 wr->sg_list + 2 + i); 109 dseg++; 110 (*sge_ind)++; 111 } 112 } 113 } 114 115 roce_set_field(rc_sq_wqe->byte_16, 116 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 117 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge); 118 } 119 120 return 0; 121 } 122 123 static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 124 struct ib_send_wr **bad_wr) 125 { 126 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 127 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 128 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe; 129 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe; 130 struct hns_roce_qp *qp = to_hr_qp(ibqp); 131 struct hns_roce_v2_wqe_data_seg *dseg; 132 struct device *dev = hr_dev->dev; 133 struct hns_roce_v2_db sq_db; 134 unsigned int sge_ind = 0; 135 unsigned int owner_bit; 136 unsigned long flags; 137 unsigned int ind; 138 void *wqe = NULL; 139 bool loopback; 140 int ret = 0; 141 u8 *smac; 142 int nreq; 143 int i; 144 145 if (unlikely(ibqp->qp_type != IB_QPT_RC && 146 ibqp->qp_type != IB_QPT_GSI && 147 ibqp->qp_type != IB_QPT_UD)) { 148 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type); 149 *bad_wr = NULL; 150 return -EOPNOTSUPP; 151 } 152 153 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT || 154 qp->state == IB_QPS_RTR)) { 155 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state); 156 *bad_wr = wr; 157 return -EINVAL; 158 } 159 160 spin_lock_irqsave(&qp->sq.lock, flags); 161 ind = qp->sq_next_wqe; 162 sge_ind = qp->next_sge; 163 164 for (nreq = 0; wr; ++nreq, wr = wr->next) { 165 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 166 ret = -ENOMEM; 167 *bad_wr = wr; 168 goto out; 169 } 170 171 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 172 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n", 173 wr->num_sge, qp->sq.max_gs); 174 ret = -EINVAL; 175 *bad_wr = wr; 176 goto out; 177 } 178 179 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 180 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = 181 wr->wr_id; 182 183 owner_bit = ~(qp->sq.head >> ilog2(qp->sq.wqe_cnt)) & 0x1; 184 185 /* Corresponding to the QP type, wqe process separately */ 186 if (ibqp->qp_type == IB_QPT_GSI) { 187 ud_sq_wqe = wqe; 188 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); 189 190 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, 191 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); 192 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, 193 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); 194 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, 195 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); 196 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, 197 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); 198 roce_set_field(ud_sq_wqe->byte_48, 199 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, 200 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, 201 ah->av.mac[4]); 202 roce_set_field(ud_sq_wqe->byte_48, 203 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, 204 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, 205 ah->av.mac[5]); 206 207 /* MAC loopback */ 208 smac = (u8 *)hr_dev->dev_addr[qp->port]; 209 loopback = ether_addr_equal_unaligned(ah->av.mac, 210 smac) ? 1 : 0; 211 212 roce_set_bit(ud_sq_wqe->byte_40, 213 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); 214 215 roce_set_field(ud_sq_wqe->byte_4, 216 V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 217 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, 218 HNS_ROCE_V2_WQE_OP_SEND); 219 220 for (i = 0; i < wr->num_sge; i++) 221 ud_sq_wqe->msg_len += wr->sg_list[i].length; 222 223 ud_sq_wqe->immtdata = send_ieth(wr); 224 225 /* Set sig attr */ 226 roce_set_bit(ud_sq_wqe->byte_4, 227 V2_UD_SEND_WQE_BYTE_4_CQE_S, 228 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 229 230 /* Set se attr */ 231 roce_set_bit(ud_sq_wqe->byte_4, 232 V2_UD_SEND_WQE_BYTE_4_SE_S, 233 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 234 235 roce_set_bit(ud_sq_wqe->byte_4, 236 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 237 238 roce_set_field(ud_sq_wqe->byte_16, 239 V2_UD_SEND_WQE_BYTE_16_PD_M, 240 V2_UD_SEND_WQE_BYTE_16_PD_S, 241 to_hr_pd(ibqp->pd)->pdn); 242 243 roce_set_field(ud_sq_wqe->byte_16, 244 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 245 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, 246 wr->num_sge); 247 248 roce_set_field(ud_sq_wqe->byte_20, 249 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 250 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 251 sge_ind & (qp->sge.sge_cnt - 1)); 252 253 roce_set_field(ud_sq_wqe->byte_24, 254 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 255 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); 256 ud_sq_wqe->qkey = 257 cpu_to_be32(ud_wr(wr)->remote_qkey & 0x80000000) ? 258 qp->qkey : ud_wr(wr)->remote_qkey; 259 roce_set_field(ud_sq_wqe->byte_32, 260 V2_UD_SEND_WQE_BYTE_32_DQPN_M, 261 V2_UD_SEND_WQE_BYTE_32_DQPN_S, 262 ud_wr(wr)->remote_qpn); 263 264 roce_set_field(ud_sq_wqe->byte_36, 265 V2_UD_SEND_WQE_BYTE_36_VLAN_M, 266 V2_UD_SEND_WQE_BYTE_36_VLAN_S, 267 ah->av.vlan); 268 roce_set_field(ud_sq_wqe->byte_36, 269 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 270 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, 271 ah->av.hop_limit); 272 roce_set_field(ud_sq_wqe->byte_36, 273 V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 274 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, 275 0); 276 roce_set_field(ud_sq_wqe->byte_36, 277 V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 278 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, 279 0); 280 roce_set_field(ud_sq_wqe->byte_40, 281 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 282 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, 0); 283 roce_set_field(ud_sq_wqe->byte_40, 284 V2_UD_SEND_WQE_BYTE_40_SL_M, 285 V2_UD_SEND_WQE_BYTE_40_SL_S, 286 ah->av.sl_tclass_flowlabel >> 287 HNS_ROCE_SL_SHIFT); 288 roce_set_field(ud_sq_wqe->byte_40, 289 V2_UD_SEND_WQE_BYTE_40_PORTN_M, 290 V2_UD_SEND_WQE_BYTE_40_PORTN_S, 291 qp->port); 292 293 roce_set_field(ud_sq_wqe->byte_48, 294 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, 295 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, 296 hns_get_gid_index(hr_dev, qp->phy_port, 297 ah->av.gid_index)); 298 299 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], 300 GID_LEN_V2); 301 302 dseg = get_send_extend_sge(qp, 303 sge_ind & (qp->sge.sge_cnt - 1)); 304 for (i = 0; i < wr->num_sge; i++) { 305 set_data_seg_v2(dseg + i, wr->sg_list + i); 306 sge_ind++; 307 } 308 309 ind++; 310 } else if (ibqp->qp_type == IB_QPT_RC) { 311 rc_sq_wqe = wqe; 312 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); 313 for (i = 0; i < wr->num_sge; i++) 314 rc_sq_wqe->msg_len += wr->sg_list[i].length; 315 316 rc_sq_wqe->inv_key_immtdata = send_ieth(wr); 317 318 roce_set_bit(rc_sq_wqe->byte_4, 319 V2_RC_SEND_WQE_BYTE_4_FENCE_S, 320 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 321 322 roce_set_bit(rc_sq_wqe->byte_4, 323 V2_RC_SEND_WQE_BYTE_4_SE_S, 324 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 325 326 roce_set_bit(rc_sq_wqe->byte_4, 327 V2_RC_SEND_WQE_BYTE_4_CQE_S, 328 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 329 330 roce_set_bit(rc_sq_wqe->byte_4, 331 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 332 333 switch (wr->opcode) { 334 case IB_WR_RDMA_READ: 335 roce_set_field(rc_sq_wqe->byte_4, 336 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 337 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 338 HNS_ROCE_V2_WQE_OP_RDMA_READ); 339 rc_sq_wqe->rkey = 340 cpu_to_le32(rdma_wr(wr)->rkey); 341 rc_sq_wqe->va = 342 cpu_to_le64(rdma_wr(wr)->remote_addr); 343 break; 344 case IB_WR_RDMA_WRITE: 345 roce_set_field(rc_sq_wqe->byte_4, 346 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 347 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 348 HNS_ROCE_V2_WQE_OP_RDMA_WRITE); 349 rc_sq_wqe->rkey = 350 cpu_to_le32(rdma_wr(wr)->rkey); 351 rc_sq_wqe->va = 352 cpu_to_le64(rdma_wr(wr)->remote_addr); 353 break; 354 case IB_WR_RDMA_WRITE_WITH_IMM: 355 roce_set_field(rc_sq_wqe->byte_4, 356 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 357 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 358 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM); 359 rc_sq_wqe->rkey = 360 cpu_to_le32(rdma_wr(wr)->rkey); 361 rc_sq_wqe->va = 362 cpu_to_le64(rdma_wr(wr)->remote_addr); 363 break; 364 case IB_WR_SEND: 365 roce_set_field(rc_sq_wqe->byte_4, 366 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 367 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 368 HNS_ROCE_V2_WQE_OP_SEND); 369 break; 370 case IB_WR_SEND_WITH_INV: 371 roce_set_field(rc_sq_wqe->byte_4, 372 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 373 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 374 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV); 375 break; 376 case IB_WR_SEND_WITH_IMM: 377 roce_set_field(rc_sq_wqe->byte_4, 378 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 379 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 380 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM); 381 break; 382 case IB_WR_LOCAL_INV: 383 roce_set_field(rc_sq_wqe->byte_4, 384 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 385 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 386 HNS_ROCE_V2_WQE_OP_LOCAL_INV); 387 break; 388 case IB_WR_ATOMIC_CMP_AND_SWP: 389 roce_set_field(rc_sq_wqe->byte_4, 390 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 391 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 392 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP); 393 break; 394 case IB_WR_ATOMIC_FETCH_AND_ADD: 395 roce_set_field(rc_sq_wqe->byte_4, 396 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 397 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 398 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD); 399 break; 400 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 401 roce_set_field(rc_sq_wqe->byte_4, 402 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 403 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 404 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP); 405 break; 406 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 407 roce_set_field(rc_sq_wqe->byte_4, 408 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 409 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 410 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD); 411 break; 412 default: 413 roce_set_field(rc_sq_wqe->byte_4, 414 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 415 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 416 HNS_ROCE_V2_WQE_OP_MASK); 417 break; 418 } 419 420 wqe += sizeof(struct hns_roce_v2_rc_send_wqe); 421 dseg = wqe; 422 423 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe, 424 &sge_ind, bad_wr); 425 if (ret) 426 goto out; 427 ind++; 428 } else { 429 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type); 430 spin_unlock_irqrestore(&qp->sq.lock, flags); 431 return -EOPNOTSUPP; 432 } 433 } 434 435 out: 436 if (likely(nreq)) { 437 qp->sq.head += nreq; 438 /* Memory barrier */ 439 wmb(); 440 441 sq_db.byte_4 = 0; 442 sq_db.parameter = 0; 443 444 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 445 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 446 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 447 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 448 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M, 449 V2_DB_PARAMETER_CONS_IDX_S, 450 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)); 451 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 452 V2_DB_PARAMETER_SL_S, qp->sl); 453 454 hns_roce_write64_k((__be32 *)&sq_db, qp->sq.db_reg_l); 455 456 qp->sq_next_wqe = ind; 457 qp->next_sge = sge_ind; 458 } 459 460 spin_unlock_irqrestore(&qp->sq.lock, flags); 461 462 return ret; 463 } 464 465 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 466 struct ib_recv_wr **bad_wr) 467 { 468 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 469 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 470 struct hns_roce_v2_wqe_data_seg *dseg; 471 struct hns_roce_rinl_sge *sge_list; 472 struct device *dev = hr_dev->dev; 473 struct hns_roce_v2_db rq_db; 474 unsigned long flags; 475 void *wqe = NULL; 476 int ret = 0; 477 int nreq; 478 int ind; 479 int i; 480 481 spin_lock_irqsave(&hr_qp->rq.lock, flags); 482 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1); 483 484 if (hr_qp->state == IB_QPS_RESET || hr_qp->state == IB_QPS_ERR) { 485 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 486 *bad_wr = wr; 487 return -EINVAL; 488 } 489 490 for (nreq = 0; wr; ++nreq, wr = wr->next) { 491 if (hns_roce_wq_overflow(&hr_qp->rq, nreq, 492 hr_qp->ibqp.recv_cq)) { 493 ret = -ENOMEM; 494 *bad_wr = wr; 495 goto out; 496 } 497 498 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) { 499 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n", 500 wr->num_sge, hr_qp->rq.max_gs); 501 ret = -EINVAL; 502 *bad_wr = wr; 503 goto out; 504 } 505 506 wqe = get_recv_wqe(hr_qp, ind); 507 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 508 for (i = 0; i < wr->num_sge; i++) { 509 if (!wr->sg_list[i].length) 510 continue; 511 set_data_seg_v2(dseg, wr->sg_list + i); 512 dseg++; 513 } 514 515 if (i < hr_qp->rq.max_gs) { 516 dseg[i].lkey = cpu_to_be32(HNS_ROCE_INVALID_LKEY); 517 dseg[i].addr = 0; 518 } 519 520 /* rq support inline data */ 521 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list; 522 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt = (u32)wr->num_sge; 523 for (i = 0; i < wr->num_sge; i++) { 524 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 525 sge_list[i].len = wr->sg_list[i].length; 526 } 527 528 hr_qp->rq.wrid[ind] = wr->wr_id; 529 530 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1); 531 } 532 533 out: 534 if (likely(nreq)) { 535 hr_qp->rq.head += nreq; 536 /* Memory barrier */ 537 wmb(); 538 539 rq_db.byte_4 = 0; 540 rq_db.parameter = 0; 541 542 roce_set_field(rq_db.byte_4, V2_DB_BYTE_4_TAG_M, 543 V2_DB_BYTE_4_TAG_S, hr_qp->qpn); 544 roce_set_field(rq_db.byte_4, V2_DB_BYTE_4_CMD_M, 545 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_RQ_DB); 546 roce_set_field(rq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M, 547 V2_DB_PARAMETER_CONS_IDX_S, hr_qp->rq.head); 548 549 hns_roce_write64_k((__be32 *)&rq_db, hr_qp->rq.db_reg_l); 550 } 551 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 552 553 return ret; 554 } 555 556 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) 557 { 558 int ntu = ring->next_to_use; 559 int ntc = ring->next_to_clean; 560 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 561 562 return ring->desc_num - used - 1; 563 } 564 565 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 566 struct hns_roce_v2_cmq_ring *ring) 567 { 568 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 569 570 ring->desc = kzalloc(size, GFP_KERNEL); 571 if (!ring->desc) 572 return -ENOMEM; 573 574 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 575 DMA_BIDIRECTIONAL); 576 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 577 ring->desc_dma_addr = 0; 578 kfree(ring->desc); 579 ring->desc = NULL; 580 return -ENOMEM; 581 } 582 583 return 0; 584 } 585 586 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 587 struct hns_roce_v2_cmq_ring *ring) 588 { 589 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 590 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 591 DMA_BIDIRECTIONAL); 592 kfree(ring->desc); 593 } 594 595 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 596 { 597 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 598 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 599 &priv->cmq.csq : &priv->cmq.crq; 600 601 ring->flag = ring_type; 602 ring->next_to_clean = 0; 603 ring->next_to_use = 0; 604 605 return hns_roce_alloc_cmq_desc(hr_dev, ring); 606 } 607 608 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 609 { 610 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 611 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 612 &priv->cmq.csq : &priv->cmq.crq; 613 dma_addr_t dma = ring->desc_dma_addr; 614 615 if (ring_type == TYPE_CSQ) { 616 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 617 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 618 upper_32_bits(dma)); 619 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 620 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 621 HNS_ROCE_CMQ_ENABLE); 622 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 623 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 624 } else { 625 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 626 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 627 upper_32_bits(dma)); 628 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 629 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 630 HNS_ROCE_CMQ_ENABLE); 631 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 632 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 633 } 634 } 635 636 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 637 { 638 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 639 int ret; 640 641 /* Setup the queue entries for command queue */ 642 priv->cmq.csq.desc_num = 1024; 643 priv->cmq.crq.desc_num = 1024; 644 645 /* Setup the lock for command queue */ 646 spin_lock_init(&priv->cmq.csq.lock); 647 spin_lock_init(&priv->cmq.crq.lock); 648 649 /* Setup Tx write back timeout */ 650 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 651 652 /* Init CSQ */ 653 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 654 if (ret) { 655 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 656 return ret; 657 } 658 659 /* Init CRQ */ 660 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 661 if (ret) { 662 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 663 goto err_crq; 664 } 665 666 /* Init CSQ REG */ 667 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 668 669 /* Init CRQ REG */ 670 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 671 672 return 0; 673 674 err_crq: 675 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 676 677 return ret; 678 } 679 680 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 681 { 682 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 683 684 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 685 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 686 } 687 688 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 689 enum hns_roce_opcode_type opcode, 690 bool is_read) 691 { 692 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 693 desc->opcode = cpu_to_le16(opcode); 694 desc->flag = 695 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 696 if (is_read) 697 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 698 else 699 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 700 } 701 702 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 703 { 704 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 705 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 706 707 return head == priv->cmq.csq.next_to_use; 708 } 709 710 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) 711 { 712 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 713 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 714 struct hns_roce_cmq_desc *desc; 715 u16 ntc = csq->next_to_clean; 716 u32 head; 717 int clean = 0; 718 719 desc = &csq->desc[ntc]; 720 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 721 while (head != ntc) { 722 memset(desc, 0, sizeof(*desc)); 723 ntc++; 724 if (ntc == csq->desc_num) 725 ntc = 0; 726 desc = &csq->desc[ntc]; 727 clean++; 728 } 729 csq->next_to_clean = ntc; 730 731 return clean; 732 } 733 734 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 735 struct hns_roce_cmq_desc *desc, int num) 736 { 737 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 738 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 739 struct hns_roce_cmq_desc *desc_to_use; 740 bool complete = false; 741 u32 timeout = 0; 742 int handle = 0; 743 u16 desc_ret; 744 int ret = 0; 745 int ntc; 746 747 spin_lock_bh(&csq->lock); 748 749 if (num > hns_roce_cmq_space(csq)) { 750 spin_unlock_bh(&csq->lock); 751 return -EBUSY; 752 } 753 754 /* 755 * Record the location of desc in the cmq for this time 756 * which will be use for hardware to write back 757 */ 758 ntc = csq->next_to_use; 759 760 while (handle < num) { 761 desc_to_use = &csq->desc[csq->next_to_use]; 762 *desc_to_use = desc[handle]; 763 dev_dbg(hr_dev->dev, "set cmq desc:\n"); 764 csq->next_to_use++; 765 if (csq->next_to_use == csq->desc_num) 766 csq->next_to_use = 0; 767 handle++; 768 } 769 770 /* Write to hardware */ 771 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); 772 773 /* 774 * If the command is sync, wait for the firmware to write back, 775 * if multi descriptors to be sent, use the first one to check 776 */ 777 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 778 do { 779 if (hns_roce_cmq_csq_done(hr_dev)) 780 break; 781 udelay(1); 782 timeout++; 783 } while (timeout < priv->cmq.tx_timeout); 784 } 785 786 if (hns_roce_cmq_csq_done(hr_dev)) { 787 complete = true; 788 handle = 0; 789 while (handle < num) { 790 /* get the result of hardware write back */ 791 desc_to_use = &csq->desc[ntc]; 792 desc[handle] = *desc_to_use; 793 dev_dbg(hr_dev->dev, "Get cmq desc:\n"); 794 desc_ret = desc[handle].retval; 795 if (desc_ret == CMD_EXEC_SUCCESS) 796 ret = 0; 797 else 798 ret = -EIO; 799 priv->cmq.last_status = desc_ret; 800 ntc++; 801 handle++; 802 if (ntc == csq->desc_num) 803 ntc = 0; 804 } 805 } 806 807 if (!complete) 808 ret = -EAGAIN; 809 810 /* clean the command send queue */ 811 handle = hns_roce_cmq_csq_clean(hr_dev); 812 if (handle != num) 813 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", 814 handle, num); 815 816 spin_unlock_bh(&csq->lock); 817 818 return ret; 819 } 820 821 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 822 { 823 struct hns_roce_query_version *resp; 824 struct hns_roce_cmq_desc desc; 825 int ret; 826 827 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 828 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 829 if (ret) 830 return ret; 831 832 resp = (struct hns_roce_query_version *)desc.data; 833 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version); 834 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id); 835 836 return 0; 837 } 838 839 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 840 { 841 struct hns_roce_cfg_global_param *req; 842 struct hns_roce_cmq_desc desc; 843 844 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 845 false); 846 847 req = (struct hns_roce_cfg_global_param *)desc.data; 848 memset(req, 0, sizeof(*req)); 849 roce_set_field(req->time_cfg_udp_port, 850 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 851 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 852 roce_set_field(req->time_cfg_udp_port, 853 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 854 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); 855 856 return hns_roce_cmq_send(hr_dev, &desc, 1); 857 } 858 859 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 860 { 861 struct hns_roce_cmq_desc desc[2]; 862 struct hns_roce_pf_res *res; 863 int ret; 864 int i; 865 866 for (i = 0; i < 2; i++) { 867 hns_roce_cmq_setup_basic_desc(&desc[i], 868 HNS_ROCE_OPC_QUERY_PF_RES, true); 869 870 if (i == 0) 871 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 872 else 873 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 874 } 875 876 ret = hns_roce_cmq_send(hr_dev, desc, 2); 877 if (ret) 878 return ret; 879 880 res = (struct hns_roce_pf_res *)desc[0].data; 881 882 hr_dev->caps.qpc_bt_num = roce_get_field(res->qpc_bt_idx_num, 883 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 884 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 885 hr_dev->caps.srqc_bt_num = roce_get_field(res->srqc_bt_idx_num, 886 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 887 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 888 hr_dev->caps.cqc_bt_num = roce_get_field(res->cqc_bt_idx_num, 889 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 890 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 891 hr_dev->caps.mpt_bt_num = roce_get_field(res->mpt_bt_idx_num, 892 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 893 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 894 895 return 0; 896 } 897 898 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 899 { 900 struct hns_roce_cmq_desc desc[2]; 901 struct hns_roce_vf_res_a *req_a; 902 struct hns_roce_vf_res_b *req_b; 903 int i; 904 905 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 906 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 907 memset(req_a, 0, sizeof(*req_a)); 908 memset(req_b, 0, sizeof(*req_b)); 909 for (i = 0; i < 2; i++) { 910 hns_roce_cmq_setup_basic_desc(&desc[i], 911 HNS_ROCE_OPC_ALLOC_VF_RES, false); 912 913 if (i == 0) 914 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 915 else 916 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 917 918 if (i == 0) { 919 roce_set_field(req_a->vf_qpc_bt_idx_num, 920 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 921 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 922 roce_set_field(req_a->vf_qpc_bt_idx_num, 923 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 924 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, 925 HNS_ROCE_VF_QPC_BT_NUM); 926 927 roce_set_field(req_a->vf_srqc_bt_idx_num, 928 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 929 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 930 roce_set_field(req_a->vf_srqc_bt_idx_num, 931 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 932 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 933 HNS_ROCE_VF_SRQC_BT_NUM); 934 935 roce_set_field(req_a->vf_cqc_bt_idx_num, 936 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 937 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 938 roce_set_field(req_a->vf_cqc_bt_idx_num, 939 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 940 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, 941 HNS_ROCE_VF_CQC_BT_NUM); 942 943 roce_set_field(req_a->vf_mpt_bt_idx_num, 944 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 945 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 946 roce_set_field(req_a->vf_mpt_bt_idx_num, 947 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 948 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, 949 HNS_ROCE_VF_MPT_BT_NUM); 950 951 roce_set_field(req_a->vf_eqc_bt_idx_num, 952 VF_RES_A_DATA_5_VF_EQC_IDX_M, 953 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 954 roce_set_field(req_a->vf_eqc_bt_idx_num, 955 VF_RES_A_DATA_5_VF_EQC_NUM_M, 956 VF_RES_A_DATA_5_VF_EQC_NUM_S, 957 HNS_ROCE_VF_EQC_NUM); 958 } else { 959 roce_set_field(req_b->vf_smac_idx_num, 960 VF_RES_B_DATA_1_VF_SMAC_IDX_M, 961 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 962 roce_set_field(req_b->vf_smac_idx_num, 963 VF_RES_B_DATA_1_VF_SMAC_NUM_M, 964 VF_RES_B_DATA_1_VF_SMAC_NUM_S, 965 HNS_ROCE_VF_SMAC_NUM); 966 967 roce_set_field(req_b->vf_sgid_idx_num, 968 VF_RES_B_DATA_2_VF_SGID_IDX_M, 969 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 970 roce_set_field(req_b->vf_sgid_idx_num, 971 VF_RES_B_DATA_2_VF_SGID_NUM_M, 972 VF_RES_B_DATA_2_VF_SGID_NUM_S, 973 HNS_ROCE_VF_SGID_NUM); 974 975 roce_set_field(req_b->vf_qid_idx_sl_num, 976 VF_RES_B_DATA_3_VF_QID_IDX_M, 977 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 978 roce_set_field(req_b->vf_qid_idx_sl_num, 979 VF_RES_B_DATA_3_VF_SL_NUM_M, 980 VF_RES_B_DATA_3_VF_SL_NUM_S, 981 HNS_ROCE_VF_SL_NUM); 982 } 983 } 984 985 return hns_roce_cmq_send(hr_dev, desc, 2); 986 } 987 988 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 989 { 990 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 991 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 992 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 993 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 994 struct hns_roce_cfg_bt_attr *req; 995 struct hns_roce_cmq_desc desc; 996 997 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 998 req = (struct hns_roce_cfg_bt_attr *)desc.data; 999 memset(req, 0, sizeof(*req)); 1000 1001 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1002 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1003 hr_dev->caps.qpc_ba_pg_sz); 1004 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1005 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1006 hr_dev->caps.qpc_buf_pg_sz); 1007 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1008 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1009 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1010 1011 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1012 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1013 hr_dev->caps.srqc_ba_pg_sz); 1014 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1015 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1016 hr_dev->caps.srqc_buf_pg_sz); 1017 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1018 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1019 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1020 1021 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1022 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1023 hr_dev->caps.cqc_ba_pg_sz); 1024 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1025 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1026 hr_dev->caps.cqc_buf_pg_sz); 1027 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1028 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1029 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1030 1031 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1032 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1033 hr_dev->caps.mpt_ba_pg_sz); 1034 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1035 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1036 hr_dev->caps.mpt_buf_pg_sz); 1037 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1038 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1039 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1040 1041 return hns_roce_cmq_send(hr_dev, &desc, 1); 1042 } 1043 1044 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 1045 { 1046 struct hns_roce_caps *caps = &hr_dev->caps; 1047 int ret; 1048 1049 ret = hns_roce_cmq_query_hw_info(hr_dev); 1050 if (ret) { 1051 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 1052 ret); 1053 return ret; 1054 } 1055 1056 ret = hns_roce_config_global_param(hr_dev); 1057 if (ret) { 1058 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 1059 ret); 1060 } 1061 1062 /* Get pf resource owned by every pf */ 1063 ret = hns_roce_query_pf_resource(hr_dev); 1064 if (ret) { 1065 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 1066 ret); 1067 return ret; 1068 } 1069 1070 ret = hns_roce_alloc_vf_resource(hr_dev); 1071 if (ret) { 1072 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 1073 ret); 1074 return ret; 1075 } 1076 1077 hr_dev->vendor_part_id = 0; 1078 hr_dev->sys_image_guid = 0; 1079 1080 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1081 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1082 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1083 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1084 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1085 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1086 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1087 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1088 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1089 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1090 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1091 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1092 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1093 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1094 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1095 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1096 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1097 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1098 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1099 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1100 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1101 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; 1102 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1103 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ; 1104 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1105 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1106 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1107 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; 1108 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1109 caps->reserved_lkey = 0; 1110 caps->reserved_pds = 0; 1111 caps->reserved_mrws = 1; 1112 caps->reserved_uars = 0; 1113 caps->reserved_cqs = 0; 1114 1115 caps->qpc_ba_pg_sz = 0; 1116 caps->qpc_buf_pg_sz = 0; 1117 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1118 caps->srqc_ba_pg_sz = 0; 1119 caps->srqc_buf_pg_sz = 0; 1120 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0; 1121 caps->cqc_ba_pg_sz = 0; 1122 caps->cqc_buf_pg_sz = 0; 1123 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1124 caps->mpt_ba_pg_sz = 0; 1125 caps->mpt_buf_pg_sz = 0; 1126 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1127 caps->pbl_ba_pg_sz = 0; 1128 caps->pbl_buf_pg_sz = 0; 1129 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 1130 caps->mtt_ba_pg_sz = 0; 1131 caps->mtt_buf_pg_sz = 0; 1132 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1133 caps->cqe_ba_pg_sz = 0; 1134 caps->cqe_buf_pg_sz = 0; 1135 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1136 caps->eqe_ba_pg_sz = 0; 1137 caps->eqe_buf_pg_sz = 0; 1138 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 1139 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1140 1141 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1142 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1143 HNS_ROCE_CAP_FLAG_RQ_INLINE; 1144 caps->pkey_table_len[0] = 1; 1145 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1146 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1147 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1148 caps->local_ca_ack_delay = 0; 1149 caps->max_mtu = IB_MTU_4096; 1150 1151 ret = hns_roce_v2_set_bt(hr_dev); 1152 if (ret) 1153 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", 1154 ret); 1155 1156 return ret; 1157 } 1158 1159 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 1160 { 1161 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1162 1163 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 1164 } 1165 1166 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 1167 { 1168 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1169 1170 return status & HNS_ROCE_HW_MB_STATUS_MASK; 1171 } 1172 1173 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 1174 u64 out_param, u32 in_modifier, u8 op_modifier, 1175 u16 op, u16 token, int event) 1176 { 1177 struct device *dev = hr_dev->dev; 1178 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + 1179 ROCEE_VF_MB_CFG0_REG); 1180 unsigned long end; 1181 u32 val0 = 0; 1182 u32 val1 = 0; 1183 1184 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 1185 while (hns_roce_v2_cmd_pending(hr_dev)) { 1186 if (time_after(jiffies, end)) { 1187 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 1188 (int)end); 1189 return -EAGAIN; 1190 } 1191 cond_resched(); 1192 } 1193 1194 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK, 1195 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier); 1196 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK, 1197 HNS_ROCE_VF_MB4_CMD_SHIFT, op); 1198 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK, 1199 HNS_ROCE_VF_MB5_EVENT_SHIFT, event); 1200 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK, 1201 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token); 1202 1203 __raw_writeq(cpu_to_le64(in_param), hcr + 0); 1204 __raw_writeq(cpu_to_le64(out_param), hcr + 2); 1205 1206 /* Memory barrier */ 1207 wmb(); 1208 1209 __raw_writel(cpu_to_le32(val0), hcr + 4); 1210 __raw_writel(cpu_to_le32(val1), hcr + 5); 1211 1212 mmiowb(); 1213 1214 return 0; 1215 } 1216 1217 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 1218 unsigned long timeout) 1219 { 1220 struct device *dev = hr_dev->dev; 1221 unsigned long end = 0; 1222 u32 status; 1223 1224 end = msecs_to_jiffies(timeout) + jiffies; 1225 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 1226 cond_resched(); 1227 1228 if (hns_roce_v2_cmd_pending(hr_dev)) { 1229 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 1230 return -ETIMEDOUT; 1231 } 1232 1233 status = hns_roce_v2_cmd_complete(hr_dev); 1234 if (status != 0x1) { 1235 dev_err(dev, "mailbox status 0x%x!\n", status); 1236 return -EBUSY; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 1243 int gid_index, union ib_gid *gid, 1244 const struct ib_gid_attr *attr) 1245 { 1246 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 1247 u32 *p; 1248 u32 val; 1249 1250 if (!gid || !attr) 1251 return -EINVAL; 1252 1253 if (attr->gid_type == IB_GID_TYPE_ROCE) 1254 sgid_type = GID_TYPE_FLAG_ROCE_V1; 1255 1256 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 1257 if (ipv6_addr_v4mapped((void *)gid)) 1258 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 1259 else 1260 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 1261 } 1262 1263 p = (u32 *)&gid->raw[0]; 1264 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG0_REG + 1265 0x20 * gid_index); 1266 1267 p = (u32 *)&gid->raw[4]; 1268 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG1_REG + 1269 0x20 * gid_index); 1270 1271 p = (u32 *)&gid->raw[8]; 1272 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG2_REG + 1273 0x20 * gid_index); 1274 1275 p = (u32 *)&gid->raw[0xc]; 1276 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG3_REG + 1277 0x20 * gid_index); 1278 1279 val = roce_read(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index); 1280 roce_set_field(val, ROCEE_VF_SGID_CFG4_SGID_TYPE_M, 1281 ROCEE_VF_SGID_CFG4_SGID_TYPE_S, sgid_type); 1282 1283 roce_write(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index, val); 1284 1285 return 0; 1286 } 1287 1288 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 1289 u8 *addr) 1290 { 1291 u16 reg_smac_h; 1292 u32 reg_smac_l; 1293 u32 val; 1294 1295 reg_smac_l = *(u32 *)(&addr[0]); 1296 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_VF_SMAC_CFG0_REG + 1297 0x08 * phy_port); 1298 val = roce_read(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port); 1299 1300 reg_smac_h = *(u16 *)(&addr[4]); 1301 roce_set_field(val, ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M, 1302 ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S, reg_smac_h); 1303 roce_write(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port, val); 1304 1305 return 0; 1306 } 1307 1308 static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, 1309 unsigned long mtpt_idx) 1310 { 1311 struct hns_roce_v2_mpt_entry *mpt_entry; 1312 struct scatterlist *sg; 1313 u64 page_addr; 1314 u64 *pages; 1315 int i, j; 1316 int len; 1317 int entry; 1318 1319 mpt_entry = mb_buf; 1320 memset(mpt_entry, 0, sizeof(*mpt_entry)); 1321 1322 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 1323 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 1324 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 1325 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == 1326 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); 1327 roce_set_field(mpt_entry->byte_4_pd_hop_st, 1328 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 1329 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, mr->pbl_ba_pg_sz); 1330 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1331 V2_MPT_BYTE_4_PD_S, mr->pd); 1332 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st); 1333 1334 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); 1335 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 1336 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0); 1337 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, 1338 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); 1339 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 0); 1340 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1341 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1342 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1343 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1344 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1345 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1346 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en); 1347 1348 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 1349 mr->type == MR_TYPE_MR ? 0 : 1); 1350 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa); 1351 1352 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 1353 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 1354 mpt_entry->lkey = cpu_to_le32(mr->key); 1355 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 1356 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 1357 1358 if (mr->type == MR_TYPE_DMA) 1359 return 0; 1360 1361 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1362 1363 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1364 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 1365 V2_MPT_BYTE_48_PBL_BA_H_S, 1366 upper_32_bits(mr->pbl_ba >> 3)); 1367 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba); 1368 1369 pages = (u64 *)__get_free_page(GFP_KERNEL); 1370 if (!pages) 1371 return -ENOMEM; 1372 1373 i = 0; 1374 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) { 1375 len = sg_dma_len(sg) >> PAGE_SHIFT; 1376 for (j = 0; j < len; ++j) { 1377 page_addr = sg_dma_address(sg) + 1378 (j << mr->umem->page_shift); 1379 pages[i] = page_addr >> 6; 1380 1381 /* Record the first 2 entry directly to MTPT table */ 1382 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) 1383 goto found; 1384 i++; 1385 } 1386 } 1387 1388 found: 1389 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 1390 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 1391 V2_MPT_BYTE_56_PA0_H_S, 1392 upper_32_bits(pages[0])); 1393 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h); 1394 1395 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 1396 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 1397 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 1398 1399 free_page((unsigned long)pages); 1400 1401 roce_set_field(mpt_entry->byte_64_buf_pa1, 1402 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 1403 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, mr->pbl_buf_pg_sz); 1404 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1); 1405 1406 return 0; 1407 } 1408 1409 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 1410 struct hns_roce_mr *mr, int flags, 1411 u32 pdn, int mr_access_flags, u64 iova, 1412 u64 size, void *mb_buf) 1413 { 1414 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 1415 1416 if (flags & IB_MR_REREG_PD) { 1417 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1418 V2_MPT_BYTE_4_PD_S, pdn); 1419 mr->pd = pdn; 1420 } 1421 1422 if (flags & IB_MR_REREG_ACCESS) { 1423 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1424 V2_MPT_BYTE_8_BIND_EN_S, 1425 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 1426 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1427 V2_MPT_BYTE_8_ATOMIC_EN_S, 1428 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0)); 1429 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1430 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1431 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1432 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1433 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1434 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1435 } 1436 1437 if (flags & IB_MR_REREG_TRANS) { 1438 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); 1439 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); 1440 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); 1441 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); 1442 1443 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1444 mpt_entry->pbl_ba_l = 1445 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1446 roce_set_field(mpt_entry->byte_48_mode_ba, 1447 V2_MPT_BYTE_48_PBL_BA_H_M, 1448 V2_MPT_BYTE_48_PBL_BA_H_S, 1449 upper_32_bits(mr->pbl_ba >> 3)); 1450 mpt_entry->byte_48_mode_ba = 1451 cpu_to_le32(mpt_entry->byte_48_mode_ba); 1452 1453 mr->iova = iova; 1454 mr->size = size; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1461 { 1462 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf, 1463 n * HNS_ROCE_V2_CQE_ENTRY_SIZE); 1464 } 1465 1466 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1467 { 1468 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 1469 1470 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 1471 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 1472 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL; 1473 } 1474 1475 static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq) 1476 { 1477 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 1478 } 1479 1480 static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) 1481 { 1482 struct hns_roce_v2_cq_db cq_db; 1483 1484 cq_db.byte_4 = 0; 1485 cq_db.parameter = 0; 1486 1487 roce_set_field(cq_db.byte_4, V2_CQ_DB_BYTE_4_TAG_M, 1488 V2_CQ_DB_BYTE_4_TAG_S, hr_cq->cqn); 1489 roce_set_field(cq_db.byte_4, V2_CQ_DB_BYTE_4_CMD_M, 1490 V2_CQ_DB_BYTE_4_CMD_S, HNS_ROCE_V2_CQ_DB_PTR); 1491 1492 roce_set_field(cq_db.parameter, V2_CQ_DB_PARAMETER_CONS_IDX_M, 1493 V2_CQ_DB_PARAMETER_CONS_IDX_S, 1494 cons_index & ((hr_cq->cq_depth << 1) - 1)); 1495 roce_set_field(cq_db.parameter, V2_CQ_DB_PARAMETER_CMD_SN_M, 1496 V2_CQ_DB_PARAMETER_CMD_SN_S, 1); 1497 1498 hns_roce_write64_k((__be32 *)&cq_db, hr_cq->cq_db_l); 1499 1500 } 1501 1502 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1503 struct hns_roce_srq *srq) 1504 { 1505 struct hns_roce_v2_cqe *cqe, *dest; 1506 u32 prod_index; 1507 int nfreed = 0; 1508 u8 owner_bit; 1509 1510 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 1511 ++prod_index) { 1512 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe) 1513 break; 1514 } 1515 1516 /* 1517 * Now backwards through the CQ, removing CQ entries 1518 * that match our QP by overwriting them with next entries. 1519 */ 1520 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 1521 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 1522 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 1523 V2_CQE_BYTE_16_LCL_QPN_S) & 1524 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 1525 /* In v1 engine, not support SRQ */ 1526 ++nfreed; 1527 } else if (nfreed) { 1528 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 1529 hr_cq->ib_cq.cqe); 1530 owner_bit = roce_get_bit(dest->byte_4, 1531 V2_CQE_BYTE_4_OWNER_S); 1532 memcpy(dest, cqe, sizeof(*cqe)); 1533 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 1534 owner_bit); 1535 } 1536 } 1537 1538 if (nfreed) { 1539 hr_cq->cons_index += nfreed; 1540 /* 1541 * Make sure update of buffer contents is done before 1542 * updating consumer index. 1543 */ 1544 wmb(); 1545 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 1546 } 1547 } 1548 1549 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1550 struct hns_roce_srq *srq) 1551 { 1552 spin_lock_irq(&hr_cq->lock); 1553 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 1554 spin_unlock_irq(&hr_cq->lock); 1555 } 1556 1557 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 1558 struct hns_roce_cq *hr_cq, void *mb_buf, 1559 u64 *mtts, dma_addr_t dma_handle, int nent, 1560 u32 vector) 1561 { 1562 struct hns_roce_v2_cq_context *cq_context; 1563 1564 cq_context = mb_buf; 1565 memset(cq_context, 0, sizeof(*cq_context)); 1566 1567 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 1568 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 1569 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 1570 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 1571 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 1572 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent)); 1573 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 1574 V2_CQC_BYTE_4_CEQN_S, vector); 1575 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn); 1576 1577 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 1578 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 1579 1580 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 1581 cq_context->cqe_cur_blk_addr = 1582 cpu_to_le32(cq_context->cqe_cur_blk_addr); 1583 1584 roce_set_field(cq_context->byte_16_hop_addr, 1585 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 1586 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 1587 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT))); 1588 roce_set_field(cq_context->byte_16_hop_addr, 1589 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 1590 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 1591 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 1592 1593 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT); 1594 roce_set_field(cq_context->byte_24_pgsz_addr, 1595 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 1596 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 1597 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT))); 1598 roce_set_field(cq_context->byte_24_pgsz_addr, 1599 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 1600 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 1601 hr_dev->caps.cqe_ba_pg_sz); 1602 roce_set_field(cq_context->byte_24_pgsz_addr, 1603 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 1604 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 1605 hr_dev->caps.cqe_buf_pg_sz); 1606 1607 cq_context->cqe_ba = (u32)(dma_handle >> 3); 1608 1609 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 1610 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 1611 1612 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1613 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 1614 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 1615 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 1616 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1617 V2_CQC_BYTE_56_CQ_PERIOD_M, 1618 V2_CQC_BYTE_56_CQ_PERIOD_S, 1619 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 1620 } 1621 1622 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 1623 enum ib_cq_notify_flags flags) 1624 { 1625 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 1626 u32 notification_flag; 1627 u32 doorbell[2]; 1628 1629 doorbell[0] = 0; 1630 doorbell[1] = 0; 1631 1632 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 1633 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 1634 /* 1635 * flags = 0; Notification Flag = 1, next 1636 * flags = 1; Notification Flag = 0, solocited 1637 */ 1638 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 1639 hr_cq->cqn); 1640 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 1641 HNS_ROCE_V2_CQ_DB_NTR); 1642 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 1643 V2_CQ_DB_PARAMETER_CONS_IDX_S, 1644 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1)); 1645 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 1646 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 1647 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 1648 notification_flag); 1649 1650 hns_roce_write64_k(doorbell, hr_cq->cq_db_l); 1651 1652 return 0; 1653 } 1654 1655 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 1656 struct hns_roce_qp **cur_qp, 1657 struct ib_wc *wc) 1658 { 1659 struct hns_roce_rinl_sge *sge_list; 1660 u32 wr_num, wr_cnt, sge_num; 1661 u32 sge_cnt, data_len, size; 1662 void *wqe_buf; 1663 1664 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 1665 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 1666 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 1667 1668 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 1669 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 1670 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt); 1671 data_len = wc->byte_len; 1672 1673 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 1674 size = min(sge_list[sge_cnt].len, data_len); 1675 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 1676 1677 data_len -= size; 1678 wqe_buf += size; 1679 } 1680 1681 if (data_len) { 1682 wc->status = IB_WC_LOC_LEN_ERR; 1683 return -EAGAIN; 1684 } 1685 1686 return 0; 1687 } 1688 1689 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 1690 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 1691 { 1692 struct hns_roce_dev *hr_dev; 1693 struct hns_roce_v2_cqe *cqe; 1694 struct hns_roce_qp *hr_qp; 1695 struct hns_roce_wq *wq; 1696 int is_send; 1697 u16 wqe_ctr; 1698 u32 opcode; 1699 u32 status; 1700 int qpn; 1701 int ret; 1702 1703 /* Find cqe according to consumer index */ 1704 cqe = next_cqe_sw_v2(hr_cq); 1705 if (!cqe) 1706 return -EAGAIN; 1707 1708 ++hr_cq->cons_index; 1709 /* Memory barrier */ 1710 rmb(); 1711 1712 /* 0->SQ, 1->RQ */ 1713 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 1714 1715 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 1716 V2_CQE_BYTE_16_LCL_QPN_S); 1717 1718 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 1719 hr_dev = to_hr_dev(hr_cq->ib_cq.device); 1720 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 1721 if (unlikely(!hr_qp)) { 1722 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n", 1723 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK)); 1724 return -EINVAL; 1725 } 1726 *cur_qp = hr_qp; 1727 } 1728 1729 wc->qp = &(*cur_qp)->ibqp; 1730 wc->vendor_err = 0; 1731 1732 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 1733 V2_CQE_BYTE_4_STATUS_S); 1734 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) { 1735 case HNS_ROCE_CQE_V2_SUCCESS: 1736 wc->status = IB_WC_SUCCESS; 1737 break; 1738 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR: 1739 wc->status = IB_WC_LOC_LEN_ERR; 1740 break; 1741 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR: 1742 wc->status = IB_WC_LOC_QP_OP_ERR; 1743 break; 1744 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR: 1745 wc->status = IB_WC_LOC_PROT_ERR; 1746 break; 1747 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR: 1748 wc->status = IB_WC_WR_FLUSH_ERR; 1749 break; 1750 case HNS_ROCE_CQE_V2_MW_BIND_ERR: 1751 wc->status = IB_WC_MW_BIND_ERR; 1752 break; 1753 case HNS_ROCE_CQE_V2_BAD_RESP_ERR: 1754 wc->status = IB_WC_BAD_RESP_ERR; 1755 break; 1756 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR: 1757 wc->status = IB_WC_LOC_ACCESS_ERR; 1758 break; 1759 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR: 1760 wc->status = IB_WC_REM_INV_REQ_ERR; 1761 break; 1762 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR: 1763 wc->status = IB_WC_REM_ACCESS_ERR; 1764 break; 1765 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR: 1766 wc->status = IB_WC_REM_OP_ERR; 1767 break; 1768 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR: 1769 wc->status = IB_WC_RETRY_EXC_ERR; 1770 break; 1771 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR: 1772 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 1773 break; 1774 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR: 1775 wc->status = IB_WC_REM_ABORT_ERR; 1776 break; 1777 default: 1778 wc->status = IB_WC_GENERAL_ERR; 1779 break; 1780 } 1781 1782 /* CQE status error, directly return */ 1783 if (wc->status != IB_WC_SUCCESS) 1784 return 0; 1785 1786 if (is_send) { 1787 wc->wc_flags = 0; 1788 /* SQ corresponding to CQE */ 1789 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 1790 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 1791 case HNS_ROCE_SQ_OPCODE_SEND: 1792 wc->opcode = IB_WC_SEND; 1793 break; 1794 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV: 1795 wc->opcode = IB_WC_SEND; 1796 break; 1797 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM: 1798 wc->opcode = IB_WC_SEND; 1799 wc->wc_flags |= IB_WC_WITH_IMM; 1800 break; 1801 case HNS_ROCE_SQ_OPCODE_RDMA_READ: 1802 wc->opcode = IB_WC_RDMA_READ; 1803 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 1804 break; 1805 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE: 1806 wc->opcode = IB_WC_RDMA_WRITE; 1807 break; 1808 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM: 1809 wc->opcode = IB_WC_RDMA_WRITE; 1810 wc->wc_flags |= IB_WC_WITH_IMM; 1811 break; 1812 case HNS_ROCE_SQ_OPCODE_LOCAL_INV: 1813 wc->opcode = IB_WC_LOCAL_INV; 1814 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 1815 break; 1816 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP: 1817 wc->opcode = IB_WC_COMP_SWAP; 1818 wc->byte_len = 8; 1819 break; 1820 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD: 1821 wc->opcode = IB_WC_FETCH_ADD; 1822 wc->byte_len = 8; 1823 break; 1824 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP: 1825 wc->opcode = IB_WC_MASKED_COMP_SWAP; 1826 wc->byte_len = 8; 1827 break; 1828 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD: 1829 wc->opcode = IB_WC_MASKED_FETCH_ADD; 1830 wc->byte_len = 8; 1831 break; 1832 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR: 1833 wc->opcode = IB_WC_REG_MR; 1834 break; 1835 case HNS_ROCE_SQ_OPCODE_BIND_MW: 1836 wc->opcode = IB_WC_REG_MR; 1837 break; 1838 default: 1839 wc->status = IB_WC_GENERAL_ERR; 1840 break; 1841 } 1842 1843 wq = &(*cur_qp)->sq; 1844 if ((*cur_qp)->sq_signal_bits) { 1845 /* 1846 * If sg_signal_bit is 1, 1847 * firstly tail pointer updated to wqe 1848 * which current cqe correspond to 1849 */ 1850 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 1851 V2_CQE_BYTE_4_WQE_INDX_M, 1852 V2_CQE_BYTE_4_WQE_INDX_S); 1853 wq->tail += (wqe_ctr - (u16)wq->tail) & 1854 (wq->wqe_cnt - 1); 1855 } 1856 1857 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 1858 ++wq->tail; 1859 } else { 1860 /* RQ correspond to CQE */ 1861 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 1862 1863 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 1864 V2_CQE_BYTE_4_OPCODE_S); 1865 switch (opcode & 0x1f) { 1866 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 1867 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 1868 wc->wc_flags = IB_WC_WITH_IMM; 1869 wc->ex.imm_data = cqe->immtdata; 1870 break; 1871 case HNS_ROCE_V2_OPCODE_SEND: 1872 wc->opcode = IB_WC_RECV; 1873 wc->wc_flags = 0; 1874 break; 1875 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 1876 wc->opcode = IB_WC_RECV; 1877 wc->wc_flags = IB_WC_WITH_IMM; 1878 wc->ex.imm_data = cqe->immtdata; 1879 break; 1880 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 1881 wc->opcode = IB_WC_RECV; 1882 wc->wc_flags = IB_WC_WITH_INVALIDATE; 1883 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 1884 break; 1885 default: 1886 wc->status = IB_WC_GENERAL_ERR; 1887 break; 1888 } 1889 1890 if ((wc->qp->qp_type == IB_QPT_RC || 1891 wc->qp->qp_type == IB_QPT_UC) && 1892 (opcode == HNS_ROCE_V2_OPCODE_SEND || 1893 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 1894 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 1895 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 1896 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 1897 if (ret) 1898 return -EAGAIN; 1899 } 1900 1901 /* Update tail pointer, record wr_id */ 1902 wq = &(*cur_qp)->rq; 1903 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 1904 ++wq->tail; 1905 1906 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 1907 V2_CQE_BYTE_32_SL_S); 1908 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 1909 V2_CQE_BYTE_32_RMT_QPN_M, 1910 V2_CQE_BYTE_32_RMT_QPN_S); 1911 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 1912 V2_CQE_BYTE_32_GRH_S) ? 1913 IB_WC_GRH : 0); 1914 wc->port_num = roce_get_field(cqe->byte_32, 1915 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 1916 wc->pkey_index = 0; 1917 memcpy(wc->smac, cqe->smac, 4); 1918 wc->smac[4] = roce_get_field(cqe->byte_28, 1919 V2_CQE_BYTE_28_SMAC_4_M, 1920 V2_CQE_BYTE_28_SMAC_4_S); 1921 wc->smac[5] = roce_get_field(cqe->byte_28, 1922 V2_CQE_BYTE_28_SMAC_5_M, 1923 V2_CQE_BYTE_28_SMAC_5_S); 1924 wc->vlan_id = 0xffff; 1925 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 1926 wc->network_hdr_type = roce_get_field(cqe->byte_28, 1927 V2_CQE_BYTE_28_PORT_TYPE_M, 1928 V2_CQE_BYTE_28_PORT_TYPE_S); 1929 } 1930 1931 return 0; 1932 } 1933 1934 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 1935 struct ib_wc *wc) 1936 { 1937 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 1938 struct hns_roce_qp *cur_qp = NULL; 1939 unsigned long flags; 1940 int npolled; 1941 1942 spin_lock_irqsave(&hr_cq->lock, flags); 1943 1944 for (npolled = 0; npolled < num_entries; ++npolled) { 1945 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 1946 break; 1947 } 1948 1949 if (npolled) { 1950 /* Memory barrier */ 1951 wmb(); 1952 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 1953 } 1954 1955 spin_unlock_irqrestore(&hr_cq->lock, flags); 1956 1957 return npolled; 1958 } 1959 1960 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 1961 struct hns_roce_hem_table *table, int obj, 1962 int step_idx) 1963 { 1964 struct device *dev = hr_dev->dev; 1965 struct hns_roce_cmd_mailbox *mailbox; 1966 struct hns_roce_hem_iter iter; 1967 struct hns_roce_hem_mhop mhop; 1968 struct hns_roce_hem *hem; 1969 unsigned long mhop_obj = obj; 1970 int i, j, k; 1971 int ret = 0; 1972 u64 hem_idx = 0; 1973 u64 l1_idx = 0; 1974 u64 bt_ba = 0; 1975 u32 chunk_ba_num; 1976 u32 hop_num; 1977 u16 op = 0xff; 1978 1979 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 1980 return 0; 1981 1982 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 1983 i = mhop.l0_idx; 1984 j = mhop.l1_idx; 1985 k = mhop.l2_idx; 1986 hop_num = mhop.hop_num; 1987 chunk_ba_num = mhop.bt_chunk_size / 8; 1988 1989 if (hop_num == 2) { 1990 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 1991 k; 1992 l1_idx = i * chunk_ba_num + j; 1993 } else if (hop_num == 1) { 1994 hem_idx = i * chunk_ba_num + j; 1995 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 1996 hem_idx = i; 1997 } 1998 1999 switch (table->type) { 2000 case HEM_TYPE_QPC: 2001 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 2002 break; 2003 case HEM_TYPE_MTPT: 2004 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 2005 break; 2006 case HEM_TYPE_CQC: 2007 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 2008 break; 2009 case HEM_TYPE_SRQC: 2010 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 2011 break; 2012 default: 2013 dev_warn(dev, "Table %d not to be written by mailbox!\n", 2014 table->type); 2015 return 0; 2016 } 2017 op += step_idx; 2018 2019 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2020 if (IS_ERR(mailbox)) 2021 return PTR_ERR(mailbox); 2022 2023 if (check_whether_last_step(hop_num, step_idx)) { 2024 hem = table->hem[hem_idx]; 2025 for (hns_roce_hem_first(hem, &iter); 2026 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 2027 bt_ba = hns_roce_hem_addr(&iter); 2028 2029 /* configure the ba, tag, and op */ 2030 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, 2031 obj, 0, op, 2032 HNS_ROCE_CMD_TIMEOUT_MSECS); 2033 } 2034 } else { 2035 if (step_idx == 0) 2036 bt_ba = table->bt_l0_dma_addr[i]; 2037 else if (step_idx == 1 && hop_num == 2) 2038 bt_ba = table->bt_l1_dma_addr[l1_idx]; 2039 2040 /* configure the ba, tag, and op */ 2041 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 2042 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 2043 } 2044 2045 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2046 return ret; 2047 } 2048 2049 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 2050 struct hns_roce_hem_table *table, int obj, 2051 int step_idx) 2052 { 2053 struct device *dev = hr_dev->dev; 2054 struct hns_roce_cmd_mailbox *mailbox; 2055 int ret = 0; 2056 u16 op = 0xff; 2057 2058 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 2059 return 0; 2060 2061 switch (table->type) { 2062 case HEM_TYPE_QPC: 2063 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 2064 break; 2065 case HEM_TYPE_MTPT: 2066 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 2067 break; 2068 case HEM_TYPE_CQC: 2069 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 2070 break; 2071 case HEM_TYPE_SRQC: 2072 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 2073 break; 2074 default: 2075 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", 2076 table->type); 2077 return 0; 2078 } 2079 op += step_idx; 2080 2081 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2082 if (IS_ERR(mailbox)) 2083 return PTR_ERR(mailbox); 2084 2085 /* configure the tag and op */ 2086 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 2087 HNS_ROCE_CMD_TIMEOUT_MSECS); 2088 2089 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2090 return ret; 2091 } 2092 2093 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 2094 struct hns_roce_mtt *mtt, 2095 enum ib_qp_state cur_state, 2096 enum ib_qp_state new_state, 2097 struct hns_roce_v2_qp_context *context, 2098 struct hns_roce_qp *hr_qp) 2099 { 2100 struct hns_roce_cmd_mailbox *mailbox; 2101 int ret; 2102 2103 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2104 if (IS_ERR(mailbox)) 2105 return PTR_ERR(mailbox); 2106 2107 memcpy(mailbox->buf, context, sizeof(*context) * 2); 2108 2109 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 2110 HNS_ROCE_CMD_MODIFY_QPC, 2111 HNS_ROCE_CMD_TIMEOUT_MSECS); 2112 2113 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2114 2115 return ret; 2116 } 2117 2118 static void set_access_flags(struct hns_roce_qp *hr_qp, 2119 struct hns_roce_v2_qp_context *context, 2120 struct hns_roce_v2_qp_context *qpc_mask, 2121 const struct ib_qp_attr *attr, int attr_mask) 2122 { 2123 u8 dest_rd_atomic; 2124 u32 access_flags; 2125 2126 dest_rd_atomic = !!(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 2127 attr->max_dest_rd_atomic : hr_qp->resp_depth; 2128 2129 access_flags = !!(attr_mask & IB_QP_ACCESS_FLAGS) ? 2130 attr->qp_access_flags : hr_qp->atomic_rd_en; 2131 2132 if (!dest_rd_atomic) 2133 access_flags &= IB_ACCESS_REMOTE_WRITE; 2134 2135 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2136 !!(access_flags & IB_ACCESS_REMOTE_READ)); 2137 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 2138 2139 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2140 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 2141 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 2142 2143 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2144 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2145 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 2146 } 2147 2148 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 2149 const struct ib_qp_attr *attr, 2150 int attr_mask, 2151 struct hns_roce_v2_qp_context *context, 2152 struct hns_roce_v2_qp_context *qpc_mask) 2153 { 2154 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2155 2156 /* 2157 * In v2 engine, software pass context and context mask to hardware 2158 * when modifying qp. If software need modify some fields in context, 2159 * we should set all bits of the relevant fields in context mask to 2160 * 0 at the same time, else set them to 0x1. 2161 */ 2162 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2163 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2164 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2165 V2_QPC_BYTE_4_TST_S, 0); 2166 2167 if (ibqp->qp_type == IB_QPT_GSI) 2168 roce_set_field(context->byte_4_sqpn_tst, 2169 V2_QPC_BYTE_4_SGE_SHIFT_M, 2170 V2_QPC_BYTE_4_SGE_SHIFT_S, 2171 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2172 else 2173 roce_set_field(context->byte_4_sqpn_tst, 2174 V2_QPC_BYTE_4_SGE_SHIFT_M, 2175 V2_QPC_BYTE_4_SGE_SHIFT_S, 2176 hr_qp->sq.max_gs > 2 ? 2177 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2178 2179 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2180 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2181 2182 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2183 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2184 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2185 V2_QPC_BYTE_4_SQPN_S, 0); 2186 2187 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2188 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2189 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2190 V2_QPC_BYTE_16_PD_S, 0); 2191 2192 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2193 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 2194 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2195 V2_QPC_BYTE_20_RQWS_S, 0); 2196 2197 roce_set_field(context->byte_20_smac_sgid_idx, 2198 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2199 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2200 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2201 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2202 2203 roce_set_field(context->byte_20_smac_sgid_idx, 2204 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2205 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2206 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2207 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2208 2209 /* No VLAN need to set 0xFFF */ 2210 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M, 2211 V2_QPC_BYTE_24_VLAN_IDX_S, 0xfff); 2212 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M, 2213 V2_QPC_BYTE_24_VLAN_IDX_S, 0); 2214 2215 /* 2216 * Set some fields in context to zero, Because the default values 2217 * of all fields in context are zero, we need not set them to 0 again. 2218 * but we should set the relevant fields of context mask to 0. 2219 */ 2220 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0); 2221 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0); 2222 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0); 2223 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0); 2224 2225 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M, 2226 V2_QPC_BYTE_60_MAPID_S, 0); 2227 2228 roce_set_bit(qpc_mask->byte_60_qpst_mapid, 2229 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0); 2230 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S, 2231 0); 2232 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S, 2233 0); 2234 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S, 2235 0); 2236 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S, 2237 0); 2238 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S, 2239 0); 2240 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0); 2241 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0); 2242 2243 if (attr_mask & IB_QP_QKEY) { 2244 context->qkey_xrcd = attr->qkey; 2245 qpc_mask->qkey_xrcd = 0; 2246 hr_qp->qkey = attr->qkey; 2247 } 2248 2249 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 1); 2250 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0); 2251 2252 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2253 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2254 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2255 V2_QPC_BYTE_80_RX_CQN_S, 0); 2256 if (ibqp->srq) { 2257 roce_set_field(context->byte_76_srqn_op_en, 2258 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2259 to_hr_srq(ibqp->srq)->srqn); 2260 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2261 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2262 roce_set_bit(context->byte_76_srqn_op_en, 2263 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2264 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2265 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2266 } 2267 2268 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2269 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2270 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 2271 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2272 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 2273 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 2274 2275 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M, 2276 V2_QPC_BYTE_92_SRQ_INFO_S, 0); 2277 2278 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 2279 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 2280 2281 roce_set_field(qpc_mask->byte_104_rq_sge, 2282 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M, 2283 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0); 2284 2285 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2286 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 2287 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2288 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 2289 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 2290 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2291 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0); 2292 2293 qpc_mask->rq_rnr_timer = 0; 2294 qpc_mask->rx_msg_len = 0; 2295 qpc_mask->rx_rkey_pkt_info = 0; 2296 qpc_mask->rx_va = 0; 2297 2298 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 2299 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 2300 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 2301 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 2302 2303 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0); 2304 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M, 2305 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0); 2306 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M, 2307 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0); 2308 2309 roce_set_field(qpc_mask->byte_144_raq, 2310 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M, 2311 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0); 2312 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S, 2313 0); 2314 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M, 2315 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0); 2316 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0); 2317 2318 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M, 2319 V2_QPC_BYTE_148_RQ_MSN_S, 0); 2320 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M, 2321 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0); 2322 2323 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2324 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 2325 roce_set_field(qpc_mask->byte_152_raq, 2326 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M, 2327 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0); 2328 2329 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M, 2330 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0); 2331 2332 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2333 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 2334 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 2335 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2336 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M, 2337 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0); 2338 2339 roce_set_field(context->byte_168_irrl_idx, 2340 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2341 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2342 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2343 roce_set_field(qpc_mask->byte_168_irrl_idx, 2344 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2345 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2346 2347 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2348 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0); 2349 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2350 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0); 2351 roce_set_field(qpc_mask->byte_168_irrl_idx, 2352 V2_QPC_BYTE_168_IRRL_IDX_LSB_M, 2353 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0); 2354 2355 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2356 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); 2357 roce_set_field(qpc_mask->byte_172_sq_psn, 2358 V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2359 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0); 2360 2361 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S, 2362 0); 2363 2364 roce_set_field(qpc_mask->byte_176_msg_pktn, 2365 V2_QPC_BYTE_176_MSG_USE_PKTN_M, 2366 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0); 2367 roce_set_field(qpc_mask->byte_176_msg_pktn, 2368 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M, 2369 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0); 2370 2371 roce_set_field(qpc_mask->byte_184_irrl_idx, 2372 V2_QPC_BYTE_184_IRRL_IDX_MSB_M, 2373 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0); 2374 2375 qpc_mask->cur_sge_offset = 0; 2376 2377 roce_set_field(qpc_mask->byte_192_ext_sge, 2378 V2_QPC_BYTE_192_CUR_SGE_IDX_M, 2379 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0); 2380 roce_set_field(qpc_mask->byte_192_ext_sge, 2381 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M, 2382 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0); 2383 2384 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 2385 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 2386 2387 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M, 2388 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0); 2389 roce_set_field(qpc_mask->byte_200_sq_max, 2390 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M, 2391 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0); 2392 2393 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0); 2394 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0); 2395 2396 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 2397 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 2398 2399 qpc_mask->sq_timer = 0; 2400 2401 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 2402 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 2403 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 2404 roce_set_field(qpc_mask->byte_232_irrl_sge, 2405 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 2406 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 2407 2408 qpc_mask->irrl_cur_sge_offset = 0; 2409 2410 roce_set_field(qpc_mask->byte_240_irrl_tail, 2411 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 2412 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 2413 roce_set_field(qpc_mask->byte_240_irrl_tail, 2414 V2_QPC_BYTE_240_IRRL_TAIL_RD_M, 2415 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0); 2416 roce_set_field(qpc_mask->byte_240_irrl_tail, 2417 V2_QPC_BYTE_240_RX_ACK_MSN_M, 2418 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 2419 2420 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M, 2421 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 2422 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S, 2423 0); 2424 roce_set_field(qpc_mask->byte_248_ack_psn, 2425 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 2426 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 2427 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 2428 0); 2429 roce_set_bit(qpc_mask->byte_248_ack_psn, 2430 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 2431 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S, 2432 0); 2433 2434 hr_qp->access_flags = attr->qp_access_flags; 2435 hr_qp->pkey_index = attr->pkey_index; 2436 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2437 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2438 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2439 V2_QPC_BYTE_252_TX_CQN_S, 0); 2440 2441 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M, 2442 V2_QPC_BYTE_252_ERR_TYPE_S, 0); 2443 2444 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2445 V2_QPC_BYTE_256_RQ_CQE_IDX_M, 2446 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0); 2447 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2448 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M, 2449 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0); 2450 } 2451 2452 static void modify_qp_init_to_init(struct ib_qp *ibqp, 2453 const struct ib_qp_attr *attr, int attr_mask, 2454 struct hns_roce_v2_qp_context *context, 2455 struct hns_roce_v2_qp_context *qpc_mask) 2456 { 2457 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2458 2459 /* 2460 * In v2 engine, software pass context and context mask to hardware 2461 * when modifying qp. If software need modify some fields in context, 2462 * we should set all bits of the relevant fields in context mask to 2463 * 0 at the same time, else set them to 0x1. 2464 */ 2465 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2466 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2467 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2468 V2_QPC_BYTE_4_TST_S, 0); 2469 2470 if (ibqp->qp_type == IB_QPT_GSI) 2471 roce_set_field(context->byte_4_sqpn_tst, 2472 V2_QPC_BYTE_4_SGE_SHIFT_M, 2473 V2_QPC_BYTE_4_SGE_SHIFT_S, 2474 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2475 else 2476 roce_set_field(context->byte_4_sqpn_tst, 2477 V2_QPC_BYTE_4_SGE_SHIFT_M, 2478 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ? 2479 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2480 2481 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2482 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2483 2484 if (attr_mask & IB_QP_ACCESS_FLAGS) { 2485 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2486 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); 2487 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2488 0); 2489 2490 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2491 !!(attr->qp_access_flags & 2492 IB_ACCESS_REMOTE_WRITE)); 2493 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2494 0); 2495 2496 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2497 !!(attr->qp_access_flags & 2498 IB_ACCESS_REMOTE_ATOMIC)); 2499 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2500 0); 2501 } else { 2502 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2503 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); 2504 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2505 0); 2506 2507 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2508 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); 2509 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2510 0); 2511 2512 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2513 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2514 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2515 0); 2516 } 2517 2518 roce_set_field(context->byte_20_smac_sgid_idx, 2519 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2520 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2521 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2522 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2523 2524 roce_set_field(context->byte_20_smac_sgid_idx, 2525 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2526 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2527 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2528 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2529 2530 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2531 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2532 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2533 V2_QPC_BYTE_16_PD_S, 0); 2534 2535 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2536 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2537 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2538 V2_QPC_BYTE_80_RX_CQN_S, 0); 2539 2540 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2541 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2542 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2543 V2_QPC_BYTE_252_TX_CQN_S, 0); 2544 2545 if (ibqp->srq) { 2546 roce_set_bit(context->byte_76_srqn_op_en, 2547 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2548 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2549 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2550 roce_set_field(context->byte_76_srqn_op_en, 2551 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2552 to_hr_srq(ibqp->srq)->srqn); 2553 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2554 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2555 } 2556 2557 if (attr_mask & IB_QP_QKEY) { 2558 context->qkey_xrcd = attr->qkey; 2559 qpc_mask->qkey_xrcd = 0; 2560 } 2561 2562 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2563 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2564 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2565 V2_QPC_BYTE_4_SQPN_S, 0); 2566 2567 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2568 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 2569 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2570 V2_QPC_BYTE_56_DQPN_S, 0); 2571 roce_set_field(context->byte_168_irrl_idx, 2572 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2573 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2574 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2575 roce_set_field(qpc_mask->byte_168_irrl_idx, 2576 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2577 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2578 } 2579 2580 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 2581 const struct ib_qp_attr *attr, int attr_mask, 2582 struct hns_roce_v2_qp_context *context, 2583 struct hns_roce_v2_qp_context *qpc_mask) 2584 { 2585 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 2586 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2587 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2588 struct device *dev = hr_dev->dev; 2589 dma_addr_t dma_handle_3; 2590 dma_addr_t dma_handle_2; 2591 dma_addr_t dma_handle; 2592 u32 page_size; 2593 u8 port_num; 2594 u64 *mtts_3; 2595 u64 *mtts_2; 2596 u64 *mtts; 2597 u8 *dmac; 2598 u8 *smac; 2599 int port; 2600 2601 /* Search qp buf's mtts */ 2602 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 2603 hr_qp->mtt.first_seg, &dma_handle); 2604 if (!mtts) { 2605 dev_err(dev, "qp buf pa find failed\n"); 2606 return -EINVAL; 2607 } 2608 2609 /* Search IRRL's mtts */ 2610 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 2611 hr_qp->qpn, &dma_handle_2); 2612 if (!mtts_2) { 2613 dev_err(dev, "qp irrl_table find failed\n"); 2614 return -EINVAL; 2615 } 2616 2617 /* Search TRRL's mtts */ 2618 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 2619 hr_qp->qpn, &dma_handle_3); 2620 if (!mtts_3) { 2621 dev_err(dev, "qp trrl_table find failed\n"); 2622 return -EINVAL; 2623 } 2624 2625 if ((attr_mask & IB_QP_ALT_PATH) || (attr_mask & IB_QP_ACCESS_FLAGS) || 2626 (attr_mask & IB_QP_PKEY_INDEX) || (attr_mask & IB_QP_QKEY)) { 2627 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask); 2628 return -EINVAL; 2629 } 2630 2631 dmac = (u8 *)attr->ah_attr.roce.dmac; 2632 context->wqe_sge_ba = (u32)(dma_handle >> 3); 2633 qpc_mask->wqe_sge_ba = 0; 2634 2635 /* 2636 * In v2 engine, software pass context and context mask to hardware 2637 * when modifying qp. If software need modify some fields in context, 2638 * we should set all bits of the relevant fields in context mask to 2639 * 0 at the same time, else set them to 0x1. 2640 */ 2641 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 2642 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3)); 2643 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 2644 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 2645 2646 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 2647 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 2648 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 2649 0 : hr_dev->caps.mtt_hop_num); 2650 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 2651 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 2652 2653 roce_set_field(context->byte_20_smac_sgid_idx, 2654 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 2655 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 2656 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2657 hr_dev->caps.mtt_hop_num : 0); 2658 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2659 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 2660 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 2661 2662 roce_set_field(context->byte_20_smac_sgid_idx, 2663 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 2664 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 2665 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 2666 0 : hr_dev->caps.mtt_hop_num); 2667 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2668 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 2669 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 2670 2671 roce_set_field(context->byte_16_buf_ba_pg_sz, 2672 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 2673 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 2674 hr_dev->caps.mtt_ba_pg_sz); 2675 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 2676 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 2677 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 2678 2679 roce_set_field(context->byte_16_buf_ba_pg_sz, 2680 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 2681 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 2682 hr_dev->caps.mtt_buf_pg_sz); 2683 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 2684 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 2685 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 2686 2687 roce_set_field(context->byte_80_rnr_rx_cqn, 2688 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 2689 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer); 2690 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 2691 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 2692 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 2693 2694 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 2695 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size] 2696 >> PAGE_ADDR_SHIFT); 2697 qpc_mask->rq_cur_blk_addr = 0; 2698 2699 roce_set_field(context->byte_92_srq_info, 2700 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 2701 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 2702 mtts[hr_qp->rq.offset / page_size] 2703 >> (32 + PAGE_ADDR_SHIFT)); 2704 roce_set_field(qpc_mask->byte_92_srq_info, 2705 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 2706 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 2707 2708 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1] 2709 >> PAGE_ADDR_SHIFT); 2710 qpc_mask->rq_nxt_blk_addr = 0; 2711 2712 roce_set_field(context->byte_104_rq_sge, 2713 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 2714 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 2715 mtts[hr_qp->rq.offset / page_size + 1] 2716 >> (32 + PAGE_ADDR_SHIFT)); 2717 roce_set_field(qpc_mask->byte_104_rq_sge, 2718 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 2719 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 2720 2721 roce_set_field(context->byte_108_rx_reqepsn, 2722 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 2723 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 2724 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2725 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 2726 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 2727 2728 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 2729 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4); 2730 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 2731 V2_QPC_BYTE_132_TRRL_BA_S, 0); 2732 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4)); 2733 qpc_mask->trrl_ba = 0; 2734 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 2735 V2_QPC_BYTE_140_TRRL_BA_S, 2736 (u32)(dma_handle_3 >> (32 + 16 + 4))); 2737 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 2738 V2_QPC_BYTE_140_TRRL_BA_S, 0); 2739 2740 context->irrl_ba = (u32)(dma_handle_2 >> 6); 2741 qpc_mask->irrl_ba = 0; 2742 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 2743 V2_QPC_BYTE_208_IRRL_BA_S, 2744 dma_handle_2 >> (32 + 6)); 2745 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 2746 V2_QPC_BYTE_208_IRRL_BA_S, 0); 2747 2748 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 2749 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 2750 2751 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 2752 hr_qp->sq_signal_bits); 2753 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 2754 0); 2755 2756 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 2757 2758 smac = (u8 *)hr_dev->dev_addr[port]; 2759 /* when dmac equals smac or loop_idc is 1, it should loopback */ 2760 if (ether_addr_equal_unaligned(dmac, smac) || 2761 hr_dev->loop_idc == 0x1) { 2762 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 2763 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 2764 } 2765 2766 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 2767 attr->max_dest_rd_atomic) { 2768 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 2769 V2_QPC_BYTE_140_RR_MAX_S, 2770 fls(attr->max_dest_rd_atomic - 1)); 2771 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 2772 V2_QPC_BYTE_140_RR_MAX_S, 0); 2773 } 2774 2775 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2776 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 2777 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2778 V2_QPC_BYTE_56_DQPN_S, 0); 2779 2780 /* Configure GID index */ 2781 port_num = rdma_ah_get_port_num(&attr->ah_attr); 2782 roce_set_field(context->byte_20_smac_sgid_idx, 2783 V2_QPC_BYTE_20_SGID_IDX_M, 2784 V2_QPC_BYTE_20_SGID_IDX_S, 2785 hns_get_gid_index(hr_dev, port_num - 1, 2786 grh->sgid_index)); 2787 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2788 V2_QPC_BYTE_20_SGID_IDX_M, 2789 V2_QPC_BYTE_20_SGID_IDX_S, 0); 2790 memcpy(&(context->dmac), dmac, 4); 2791 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 2792 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 2793 qpc_mask->dmac = 0; 2794 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 2795 V2_QPC_BYTE_52_DMAC_S, 0); 2796 2797 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 2798 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4); 2799 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 2800 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 2801 2802 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 2803 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 2804 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 2805 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 2806 2807 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 2808 V2_QPC_BYTE_28_FL_S, grh->flow_label); 2809 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 2810 V2_QPC_BYTE_28_FL_S, 0); 2811 2812 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 2813 V2_QPC_BYTE_24_TC_S, grh->traffic_class); 2814 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 2815 V2_QPC_BYTE_24_TC_S, 0); 2816 2817 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 2818 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2819 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096); 2820 else 2821 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2822 V2_QPC_BYTE_24_MTU_S, attr->path_mtu); 2823 2824 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2825 V2_QPC_BYTE_24_MTU_S, 0); 2826 2827 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 2828 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 2829 2830 roce_set_field(context->byte_84_rq_ci_pi, 2831 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2832 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 2833 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2834 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2835 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 2836 2837 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2838 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 2839 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 2840 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2841 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 2842 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 2843 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 2844 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2845 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 2846 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 2847 2848 context->rq_rnr_timer = 0; 2849 qpc_mask->rq_rnr_timer = 0; 2850 2851 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2852 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 2853 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2854 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 2855 2856 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 2857 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 2858 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 2859 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 2860 2861 roce_set_field(context->byte_168_irrl_idx, 2862 V2_QPC_BYTE_168_LP_SGEN_INI_M, 2863 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 2864 roce_set_field(qpc_mask->byte_168_irrl_idx, 2865 V2_QPC_BYTE_168_LP_SGEN_INI_M, 2866 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 2867 2868 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 2869 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr)); 2870 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 2871 V2_QPC_BYTE_28_SL_S, 0); 2872 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 2873 2874 return 0; 2875 } 2876 2877 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 2878 const struct ib_qp_attr *attr, int attr_mask, 2879 struct hns_roce_v2_qp_context *context, 2880 struct hns_roce_v2_qp_context *qpc_mask) 2881 { 2882 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2883 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2884 struct device *dev = hr_dev->dev; 2885 dma_addr_t dma_handle; 2886 u32 page_size; 2887 u64 *mtts; 2888 2889 /* Search qp buf's mtts */ 2890 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 2891 hr_qp->mtt.first_seg, &dma_handle); 2892 if (!mtts) { 2893 dev_err(dev, "qp buf pa find failed\n"); 2894 return -EINVAL; 2895 } 2896 2897 /* If exist optional param, return error */ 2898 if ((attr_mask & IB_QP_ALT_PATH) || (attr_mask & IB_QP_ACCESS_FLAGS) || 2899 (attr_mask & IB_QP_QKEY) || (attr_mask & IB_QP_PATH_MIG_STATE) || 2900 (attr_mask & IB_QP_CUR_STATE) || 2901 (attr_mask & IB_QP_MIN_RNR_TIMER)) { 2902 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 2903 return -EINVAL; 2904 } 2905 2906 /* 2907 * In v2 engine, software pass context and context mask to hardware 2908 * when modifying qp. If software need modify some fields in context, 2909 * we should set all bits of the relevant fields in context mask to 2910 * 0 at the same time, else set them to 0x1. 2911 */ 2912 roce_set_field(context->byte_60_qpst_mapid, 2913 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 2914 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt); 2915 roce_set_field(qpc_mask->byte_60_qpst_mapid, 2916 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 2917 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0); 2918 2919 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 2920 roce_set_field(context->byte_168_irrl_idx, 2921 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 2922 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 2923 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 2924 qpc_mask->sq_cur_blk_addr = 0; 2925 roce_set_field(qpc_mask->byte_168_irrl_idx, 2926 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 2927 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 2928 2929 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 2930 context->sq_cur_sge_blk_addr = 2931 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2932 ((u32)(mtts[hr_qp->sge.offset / page_size] 2933 >> PAGE_ADDR_SHIFT)) : 0; 2934 roce_set_field(context->byte_184_irrl_idx, 2935 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 2936 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 2937 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2938 (mtts[hr_qp->sge.offset / page_size] >> 2939 (32 + PAGE_ADDR_SHIFT)) : 0); 2940 qpc_mask->sq_cur_sge_blk_addr = 0; 2941 roce_set_field(qpc_mask->byte_184_irrl_idx, 2942 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 2943 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 2944 2945 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 2946 roce_set_field(context->byte_232_irrl_sge, 2947 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 2948 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 2949 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 2950 qpc_mask->rx_sq_cur_blk_addr = 0; 2951 roce_set_field(qpc_mask->byte_232_irrl_sge, 2952 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 2953 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 2954 2955 /* 2956 * Set some fields in context to zero, Because the default values 2957 * of all fields in context are zero, we need not set them to 0 again. 2958 * but we should set the relevant fields of context mask to 0. 2959 */ 2960 roce_set_field(qpc_mask->byte_232_irrl_sge, 2961 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 2962 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 2963 2964 roce_set_field(qpc_mask->byte_240_irrl_tail, 2965 V2_QPC_BYTE_240_RX_ACK_MSN_M, 2966 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 2967 2968 roce_set_field(context->byte_244_rnr_rxack, 2969 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 2970 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 2971 roce_set_field(qpc_mask->byte_244_rnr_rxack, 2972 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 2973 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 2974 2975 roce_set_field(qpc_mask->byte_248_ack_psn, 2976 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 2977 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 2978 roce_set_bit(qpc_mask->byte_248_ack_psn, 2979 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 2980 roce_set_field(qpc_mask->byte_248_ack_psn, 2981 V2_QPC_BYTE_248_IRRL_PSN_M, 2982 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 2983 2984 roce_set_field(qpc_mask->byte_240_irrl_tail, 2985 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 2986 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 2987 2988 roce_set_field(context->byte_220_retry_psn_msn, 2989 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 2990 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 2991 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 2992 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 2993 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 2994 2995 roce_set_field(context->byte_224_retry_msg, 2996 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 2997 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16); 2998 roce_set_field(qpc_mask->byte_224_retry_msg, 2999 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 3000 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 3001 3002 roce_set_field(context->byte_224_retry_msg, 3003 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3004 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn); 3005 roce_set_field(qpc_mask->byte_224_retry_msg, 3006 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3007 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 3008 3009 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 3010 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 3011 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 3012 3013 roce_set_bit(qpc_mask->byte_248_ack_psn, 3014 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 3015 3016 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 3017 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 3018 3019 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3020 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 3021 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3022 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 3023 3024 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3025 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt); 3026 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3027 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 3028 3029 roce_set_field(context->byte_244_rnr_rxack, 3030 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3031 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 3032 roce_set_field(qpc_mask->byte_244_rnr_rxack, 3033 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3034 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 3035 3036 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3037 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 3038 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3039 V2_QPC_BYTE_244_RNR_CNT_S, 0); 3040 3041 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3042 V2_QPC_BYTE_212_LSN_S, 0x100); 3043 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3044 V2_QPC_BYTE_212_LSN_S, 0); 3045 3046 if (attr_mask & IB_QP_TIMEOUT) { 3047 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3048 V2_QPC_BYTE_28_AT_S, attr->timeout); 3049 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3050 V2_QPC_BYTE_28_AT_S, 0); 3051 } 3052 3053 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3054 V2_QPC_BYTE_28_SL_S, 3055 rdma_ah_get_sl(&attr->ah_attr)); 3056 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3057 V2_QPC_BYTE_28_SL_S, 0); 3058 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 3059 3060 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3061 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 3062 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3063 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 3064 3065 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 3066 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 3067 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3068 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 3069 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3070 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 3071 3072 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 3073 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 3074 V2_QPC_BYTE_208_SR_MAX_S, 3075 fls(attr->max_rd_atomic - 1)); 3076 roce_set_field(qpc_mask->byte_208_irrl, 3077 V2_QPC_BYTE_208_SR_MAX_M, 3078 V2_QPC_BYTE_208_SR_MAX_S, 0); 3079 } 3080 return 0; 3081 } 3082 3083 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 3084 const struct ib_qp_attr *attr, 3085 int attr_mask, enum ib_qp_state cur_state, 3086 enum ib_qp_state new_state) 3087 { 3088 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3089 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3090 struct hns_roce_v2_qp_context *context; 3091 struct hns_roce_v2_qp_context *qpc_mask; 3092 struct device *dev = hr_dev->dev; 3093 int ret = -EINVAL; 3094 3095 context = kzalloc(2 * sizeof(*context), GFP_KERNEL); 3096 if (!context) 3097 return -ENOMEM; 3098 3099 qpc_mask = context + 1; 3100 /* 3101 * In v2 engine, software pass context and context mask to hardware 3102 * when modifying qp. If software need modify some fields in context, 3103 * we should set all bits of the relevant fields in context mask to 3104 * 0 at the same time, else set them to 0x1. 3105 */ 3106 memset(qpc_mask, 0xff, sizeof(*qpc_mask)); 3107 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3108 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 3109 qpc_mask); 3110 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3111 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 3112 qpc_mask); 3113 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3114 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 3115 qpc_mask); 3116 if (ret) 3117 goto out; 3118 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3119 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 3120 qpc_mask); 3121 if (ret) 3122 goto out; 3123 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) || 3124 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) || 3125 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) || 3126 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) || 3127 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) || 3128 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) || 3129 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) || 3130 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) || 3131 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) || 3132 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) || 3133 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) || 3134 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) || 3135 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) || 3136 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR)) { 3137 /* Nothing */ 3138 ; 3139 } else { 3140 dev_err(dev, "Illegal state for QP!\n"); 3141 goto out; 3142 } 3143 3144 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3145 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 3146 3147 /* Every status migrate must change state */ 3148 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3149 V2_QPC_BYTE_60_QP_ST_S, new_state); 3150 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3151 V2_QPC_BYTE_60_QP_ST_S, 0); 3152 3153 /* SW pass context to HW */ 3154 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state, 3155 context, hr_qp); 3156 if (ret) { 3157 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret); 3158 goto out; 3159 } 3160 3161 hr_qp->state = new_state; 3162 3163 if (attr_mask & IB_QP_ACCESS_FLAGS) 3164 hr_qp->atomic_rd_en = attr->qp_access_flags; 3165 3166 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3167 hr_qp->resp_depth = attr->max_dest_rd_atomic; 3168 if (attr_mask & IB_QP_PORT) { 3169 hr_qp->port = attr->port_num - 1; 3170 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 3171 } 3172 3173 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 3174 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 3175 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 3176 if (ibqp->send_cq != ibqp->recv_cq) 3177 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 3178 hr_qp->qpn, NULL); 3179 3180 hr_qp->rq.head = 0; 3181 hr_qp->rq.tail = 0; 3182 hr_qp->sq.head = 0; 3183 hr_qp->sq.tail = 0; 3184 hr_qp->sq_next_wqe = 0; 3185 hr_qp->next_sge = 0; 3186 } 3187 3188 out: 3189 kfree(context); 3190 return ret; 3191 } 3192 3193 static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state) 3194 { 3195 switch (state) { 3196 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET; 3197 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT; 3198 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR; 3199 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS; 3200 case HNS_ROCE_QP_ST_SQ_DRAINING: 3201 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD; 3202 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE; 3203 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR; 3204 default: return -1; 3205 } 3206 } 3207 3208 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 3209 struct hns_roce_qp *hr_qp, 3210 struct hns_roce_v2_qp_context *hr_context) 3211 { 3212 struct hns_roce_cmd_mailbox *mailbox; 3213 int ret; 3214 3215 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3216 if (IS_ERR(mailbox)) 3217 return PTR_ERR(mailbox); 3218 3219 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 3220 HNS_ROCE_CMD_QUERY_QPC, 3221 HNS_ROCE_CMD_TIMEOUT_MSECS); 3222 if (ret) { 3223 dev_err(hr_dev->dev, "QUERY QP cmd process error\n"); 3224 goto out; 3225 } 3226 3227 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 3228 3229 out: 3230 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3231 return ret; 3232 } 3233 3234 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 3235 int qp_attr_mask, 3236 struct ib_qp_init_attr *qp_init_attr) 3237 { 3238 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3239 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3240 struct hns_roce_v2_qp_context *context; 3241 struct device *dev = hr_dev->dev; 3242 int tmp_qp_state; 3243 int state; 3244 int ret; 3245 3246 context = kzalloc(sizeof(*context), GFP_KERNEL); 3247 if (!context) 3248 return -ENOMEM; 3249 3250 memset(qp_attr, 0, sizeof(*qp_attr)); 3251 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 3252 3253 mutex_lock(&hr_qp->mutex); 3254 3255 if (hr_qp->state == IB_QPS_RESET) { 3256 qp_attr->qp_state = IB_QPS_RESET; 3257 ret = 0; 3258 goto done; 3259 } 3260 3261 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context); 3262 if (ret) { 3263 dev_err(dev, "query qpc error\n"); 3264 ret = -EINVAL; 3265 goto out; 3266 } 3267 3268 state = roce_get_field(context->byte_60_qpst_mapid, 3269 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 3270 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 3271 if (tmp_qp_state == -1) { 3272 dev_err(dev, "Illegal ib_qp_state\n"); 3273 ret = -EINVAL; 3274 goto out; 3275 } 3276 hr_qp->state = (u8)tmp_qp_state; 3277 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 3278 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc, 3279 V2_QPC_BYTE_24_MTU_M, 3280 V2_QPC_BYTE_24_MTU_S); 3281 qp_attr->path_mig_state = IB_MIG_ARMED; 3282 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 3283 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 3284 qp_attr->qkey = V2_QKEY_VAL; 3285 3286 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn, 3287 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 3288 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 3289 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn, 3290 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3291 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 3292 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err, 3293 V2_QPC_BYTE_56_DQPN_M, 3294 V2_QPC_BYTE_56_DQPN_S); 3295 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en, 3296 V2_QPC_BYTE_76_RRE_S)) << 2) | 3297 ((roce_get_bit(context->byte_76_srqn_op_en, 3298 V2_QPC_BYTE_76_RWE_S)) << 1) | 3299 ((roce_get_bit(context->byte_76_srqn_op_en, 3300 V2_QPC_BYTE_76_ATE_S)) << 3); 3301 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 3302 hr_qp->ibqp.qp_type == IB_QPT_UC) { 3303 struct ib_global_route *grh = 3304 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 3305 3306 rdma_ah_set_sl(&qp_attr->ah_attr, 3307 roce_get_field(context->byte_28_at_fl, 3308 V2_QPC_BYTE_28_SL_M, 3309 V2_QPC_BYTE_28_SL_S)); 3310 grh->flow_label = roce_get_field(context->byte_28_at_fl, 3311 V2_QPC_BYTE_28_FL_M, 3312 V2_QPC_BYTE_28_FL_S); 3313 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx, 3314 V2_QPC_BYTE_20_SGID_IDX_M, 3315 V2_QPC_BYTE_20_SGID_IDX_S); 3316 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc, 3317 V2_QPC_BYTE_24_HOP_LIMIT_M, 3318 V2_QPC_BYTE_24_HOP_LIMIT_S); 3319 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc, 3320 V2_QPC_BYTE_24_TC_M, 3321 V2_QPC_BYTE_24_TC_S); 3322 3323 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw)); 3324 } 3325 3326 qp_attr->port_num = hr_qp->port + 1; 3327 qp_attr->sq_draining = 0; 3328 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl, 3329 V2_QPC_BYTE_208_SR_MAX_M, 3330 V2_QPC_BYTE_208_SR_MAX_S); 3331 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq, 3332 V2_QPC_BYTE_140_RR_MAX_M, 3333 V2_QPC_BYTE_140_RR_MAX_S); 3334 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn, 3335 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 3336 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 3337 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl, 3338 V2_QPC_BYTE_28_AT_M, 3339 V2_QPC_BYTE_28_AT_S); 3340 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn, 3341 V2_QPC_BYTE_212_RETRY_CNT_M, 3342 V2_QPC_BYTE_212_RETRY_CNT_S); 3343 qp_attr->rnr_retry = context->rq_rnr_timer; 3344 3345 done: 3346 qp_attr->cur_qp_state = qp_attr->qp_state; 3347 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 3348 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; 3349 3350 if (!ibqp->uobject) { 3351 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 3352 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 3353 } else { 3354 qp_attr->cap.max_send_wr = 0; 3355 qp_attr->cap.max_send_sge = 0; 3356 } 3357 3358 qp_init_attr->cap = qp_attr->cap; 3359 3360 out: 3361 mutex_unlock(&hr_qp->mutex); 3362 kfree(context); 3363 return ret; 3364 } 3365 3366 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 3367 struct hns_roce_qp *hr_qp, 3368 int is_user) 3369 { 3370 struct hns_roce_cq *send_cq, *recv_cq; 3371 struct device *dev = hr_dev->dev; 3372 int ret; 3373 3374 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { 3375 /* Modify qp to reset before destroying qp */ 3376 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 3377 hr_qp->state, IB_QPS_RESET); 3378 if (ret) { 3379 dev_err(dev, "modify QP %06lx to ERR failed.\n", 3380 hr_qp->qpn); 3381 return ret; 3382 } 3383 } 3384 3385 send_cq = to_hr_cq(hr_qp->ibqp.send_cq); 3386 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq); 3387 3388 hns_roce_lock_cqs(send_cq, recv_cq); 3389 3390 if (!is_user) { 3391 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ? 3392 to_hr_srq(hr_qp->ibqp.srq) : NULL); 3393 if (send_cq != recv_cq) 3394 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 3395 } 3396 3397 hns_roce_qp_remove(hr_dev, hr_qp); 3398 3399 hns_roce_unlock_cqs(send_cq, recv_cq); 3400 3401 hns_roce_qp_free(hr_dev, hr_qp); 3402 3403 /* Not special_QP, free their QPN */ 3404 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) || 3405 (hr_qp->ibqp.qp_type == IB_QPT_UC) || 3406 (hr_qp->ibqp.qp_type == IB_QPT_UD)) 3407 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1); 3408 3409 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt); 3410 3411 if (is_user) { 3412 ib_umem_release(hr_qp->umem); 3413 } else { 3414 kfree(hr_qp->sq.wrid); 3415 kfree(hr_qp->rq.wrid); 3416 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); 3417 } 3418 3419 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 3420 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); 3421 kfree(hr_qp->rq_inl_buf.wqe_list); 3422 } 3423 3424 return 0; 3425 } 3426 3427 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp) 3428 { 3429 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3430 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3431 int ret; 3432 3433 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject); 3434 if (ret) { 3435 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret); 3436 return ret; 3437 } 3438 3439 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 3440 kfree(hr_to_hr_sqp(hr_qp)); 3441 else 3442 kfree(hr_qp); 3443 3444 return 0; 3445 } 3446 3447 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 3448 { 3449 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 3450 struct hns_roce_v2_cq_context *cq_context; 3451 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 3452 struct hns_roce_v2_cq_context *cqc_mask; 3453 struct hns_roce_cmd_mailbox *mailbox; 3454 int ret; 3455 3456 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3457 if (IS_ERR(mailbox)) 3458 return PTR_ERR(mailbox); 3459 3460 cq_context = mailbox->buf; 3461 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 3462 3463 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 3464 3465 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3466 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3467 cq_count); 3468 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3469 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3470 0); 3471 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3472 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3473 cq_period); 3474 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3475 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3476 0); 3477 3478 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 3479 HNS_ROCE_CMD_MODIFY_CQC, 3480 HNS_ROCE_CMD_TIMEOUT_MSECS); 3481 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3482 if (ret) 3483 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n"); 3484 3485 return ret; 3486 } 3487 3488 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 3489 { 3490 u32 doorbell[2]; 3491 3492 doorbell[0] = 0; 3493 doorbell[1] = 0; 3494 3495 if (eq->type_flag == HNS_ROCE_AEQ) { 3496 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 3497 HNS_ROCE_V2_EQ_DB_CMD_S, 3498 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 3499 HNS_ROCE_EQ_DB_CMD_AEQ : 3500 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 3501 } else { 3502 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 3503 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 3504 3505 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 3506 HNS_ROCE_V2_EQ_DB_CMD_S, 3507 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 3508 HNS_ROCE_EQ_DB_CMD_CEQ : 3509 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 3510 } 3511 3512 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 3513 HNS_ROCE_V2_EQ_DB_PARA_S, 3514 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 3515 3516 hns_roce_write64_k(doorbell, eq->doorbell); 3517 } 3518 3519 static void hns_roce_v2_wq_catas_err_handle(struct hns_roce_dev *hr_dev, 3520 struct hns_roce_aeqe *aeqe, 3521 u32 qpn) 3522 { 3523 struct device *dev = hr_dev->dev; 3524 int sub_type; 3525 3526 dev_warn(dev, "Local work queue catastrophic error.\n"); 3527 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 3528 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 3529 switch (sub_type) { 3530 case HNS_ROCE_LWQCE_QPC_ERROR: 3531 dev_warn(dev, "QP %d, QPC error.\n", qpn); 3532 break; 3533 case HNS_ROCE_LWQCE_MTU_ERROR: 3534 dev_warn(dev, "QP %d, MTU error.\n", qpn); 3535 break; 3536 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR: 3537 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn); 3538 break; 3539 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR: 3540 dev_warn(dev, "QP %d, WQE addr error.\n", qpn); 3541 break; 3542 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR: 3543 dev_warn(dev, "QP %d, WQE shift error.\n", qpn); 3544 break; 3545 default: 3546 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 3547 break; 3548 } 3549 } 3550 3551 static void hns_roce_v2_local_wq_access_err_handle(struct hns_roce_dev *hr_dev, 3552 struct hns_roce_aeqe *aeqe, u32 qpn) 3553 { 3554 struct device *dev = hr_dev->dev; 3555 int sub_type; 3556 3557 dev_warn(dev, "Local access violation work queue error.\n"); 3558 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 3559 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 3560 switch (sub_type) { 3561 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION: 3562 dev_warn(dev, "QP %d, R_key violation.\n", qpn); 3563 break; 3564 case HNS_ROCE_LAVWQE_LENGTH_ERROR: 3565 dev_warn(dev, "QP %d, length error.\n", qpn); 3566 break; 3567 case HNS_ROCE_LAVWQE_VA_ERROR: 3568 dev_warn(dev, "QP %d, VA error.\n", qpn); 3569 break; 3570 case HNS_ROCE_LAVWQE_PD_ERROR: 3571 dev_err(dev, "QP %d, PD error.\n", qpn); 3572 break; 3573 case HNS_ROCE_LAVWQE_RW_ACC_ERROR: 3574 dev_warn(dev, "QP %d, rw acc error.\n", qpn); 3575 break; 3576 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR: 3577 dev_warn(dev, "QP %d, key state error.\n", qpn); 3578 break; 3579 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR: 3580 dev_warn(dev, "QP %d, MR operation error.\n", qpn); 3581 break; 3582 default: 3583 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 3584 break; 3585 } 3586 } 3587 3588 static void hns_roce_v2_qp_err_handle(struct hns_roce_dev *hr_dev, 3589 struct hns_roce_aeqe *aeqe, 3590 int event_type) 3591 { 3592 struct device *dev = hr_dev->dev; 3593 u32 qpn; 3594 3595 qpn = roce_get_field(aeqe->event.qp_event.qp, 3596 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 3597 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 3598 3599 switch (event_type) { 3600 case HNS_ROCE_EVENT_TYPE_COMM_EST: 3601 dev_warn(dev, "Communication established.\n"); 3602 break; 3603 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 3604 dev_warn(dev, "Send queue drained.\n"); 3605 break; 3606 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 3607 hns_roce_v2_wq_catas_err_handle(hr_dev, aeqe, qpn); 3608 break; 3609 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 3610 dev_warn(dev, "Invalid request local work queue error.\n"); 3611 break; 3612 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 3613 hns_roce_v2_local_wq_access_err_handle(hr_dev, aeqe, qpn); 3614 break; 3615 default: 3616 break; 3617 } 3618 3619 hns_roce_qp_event(hr_dev, qpn, event_type); 3620 } 3621 3622 static void hns_roce_v2_cq_err_handle(struct hns_roce_dev *hr_dev, 3623 struct hns_roce_aeqe *aeqe, 3624 int event_type) 3625 { 3626 struct device *dev = hr_dev->dev; 3627 u32 cqn; 3628 3629 cqn = roce_get_field(aeqe->event.cq_event.cq, 3630 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 3631 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 3632 3633 switch (event_type) { 3634 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 3635 dev_warn(dev, "CQ 0x%x access err.\n", cqn); 3636 break; 3637 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 3638 dev_warn(dev, "CQ 0x%x overflow\n", cqn); 3639 break; 3640 default: 3641 break; 3642 } 3643 3644 hns_roce_cq_event(hr_dev, cqn, event_type); 3645 } 3646 3647 static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry) 3648 { 3649 u32 buf_chk_sz; 3650 unsigned long off; 3651 3652 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3653 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 3654 3655 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) + 3656 off % buf_chk_sz); 3657 } 3658 3659 static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry) 3660 { 3661 u32 buf_chk_sz; 3662 unsigned long off; 3663 3664 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3665 3666 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 3667 3668 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 3669 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) + 3670 off % buf_chk_sz); 3671 else 3672 return (struct hns_roce_aeqe *)((u8 *) 3673 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz); 3674 } 3675 3676 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 3677 { 3678 struct hns_roce_aeqe *aeqe; 3679 3680 if (!eq->hop_num) 3681 aeqe = get_aeqe_v2(eq, eq->cons_index); 3682 else 3683 aeqe = mhop_get_aeqe(eq, eq->cons_index); 3684 3685 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 3686 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 3687 } 3688 3689 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 3690 struct hns_roce_eq *eq) 3691 { 3692 struct device *dev = hr_dev->dev; 3693 struct hns_roce_aeqe *aeqe; 3694 int aeqe_found = 0; 3695 int event_type; 3696 3697 while ((aeqe = next_aeqe_sw_v2(eq))) { 3698 3699 /* Make sure we read AEQ entry after we have checked the 3700 * ownership bit 3701 */ 3702 dma_rmb(); 3703 3704 event_type = roce_get_field(aeqe->asyn, 3705 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 3706 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 3707 3708 switch (event_type) { 3709 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 3710 dev_warn(dev, "Path migrated succeeded.\n"); 3711 break; 3712 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 3713 dev_warn(dev, "Path migration failed.\n"); 3714 break; 3715 case HNS_ROCE_EVENT_TYPE_COMM_EST: 3716 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 3717 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 3718 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 3719 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 3720 hns_roce_v2_qp_err_handle(hr_dev, aeqe, event_type); 3721 break; 3722 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 3723 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 3724 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 3725 dev_warn(dev, "SRQ not support.\n"); 3726 break; 3727 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 3728 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 3729 hns_roce_v2_cq_err_handle(hr_dev, aeqe, event_type); 3730 break; 3731 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 3732 dev_warn(dev, "DB overflow.\n"); 3733 break; 3734 case HNS_ROCE_EVENT_TYPE_MB: 3735 hns_roce_cmd_event(hr_dev, 3736 le16_to_cpu(aeqe->event.cmd.token), 3737 aeqe->event.cmd.status, 3738 le64_to_cpu(aeqe->event.cmd.out_param)); 3739 break; 3740 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: 3741 dev_warn(dev, "CEQ overflow.\n"); 3742 break; 3743 case HNS_ROCE_EVENT_TYPE_FLR: 3744 dev_warn(dev, "Function level reset.\n"); 3745 break; 3746 default: 3747 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 3748 event_type, eq->eqn, eq->cons_index); 3749 break; 3750 }; 3751 3752 ++eq->cons_index; 3753 aeqe_found = 1; 3754 3755 if (eq->cons_index > (2 * eq->entries - 1)) { 3756 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 3757 eq->cons_index = 0; 3758 } 3759 } 3760 3761 set_eq_cons_index_v2(eq); 3762 return aeqe_found; 3763 } 3764 3765 static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry) 3766 { 3767 u32 buf_chk_sz; 3768 unsigned long off; 3769 3770 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3771 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 3772 3773 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) + 3774 off % buf_chk_sz); 3775 } 3776 3777 static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry) 3778 { 3779 u32 buf_chk_sz; 3780 unsigned long off; 3781 3782 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3783 3784 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 3785 3786 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 3787 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) + 3788 off % buf_chk_sz); 3789 else 3790 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off / 3791 buf_chk_sz]) + off % buf_chk_sz); 3792 } 3793 3794 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 3795 { 3796 struct hns_roce_ceqe *ceqe; 3797 3798 if (!eq->hop_num) 3799 ceqe = get_ceqe_v2(eq, eq->cons_index); 3800 else 3801 ceqe = mhop_get_ceqe(eq, eq->cons_index); 3802 3803 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 3804 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 3805 } 3806 3807 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 3808 struct hns_roce_eq *eq) 3809 { 3810 struct device *dev = hr_dev->dev; 3811 struct hns_roce_ceqe *ceqe; 3812 int ceqe_found = 0; 3813 u32 cqn; 3814 3815 while ((ceqe = next_ceqe_sw_v2(eq))) { 3816 3817 /* Make sure we read CEQ entry after we have checked the 3818 * ownership bit 3819 */ 3820 dma_rmb(); 3821 3822 cqn = roce_get_field(ceqe->comp, 3823 HNS_ROCE_V2_CEQE_COMP_CQN_M, 3824 HNS_ROCE_V2_CEQE_COMP_CQN_S); 3825 3826 hns_roce_cq_completion(hr_dev, cqn); 3827 3828 ++eq->cons_index; 3829 ceqe_found = 1; 3830 3831 if (eq->cons_index > (2 * eq->entries - 1)) { 3832 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 3833 eq->cons_index = 0; 3834 } 3835 } 3836 3837 set_eq_cons_index_v2(eq); 3838 3839 return ceqe_found; 3840 } 3841 3842 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 3843 { 3844 struct hns_roce_eq *eq = eq_ptr; 3845 struct hns_roce_dev *hr_dev = eq->hr_dev; 3846 int int_work = 0; 3847 3848 if (eq->type_flag == HNS_ROCE_CEQ) 3849 /* Completion event interrupt */ 3850 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 3851 else 3852 /* Asychronous event interrupt */ 3853 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 3854 3855 return IRQ_RETVAL(int_work); 3856 } 3857 3858 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 3859 { 3860 struct hns_roce_dev *hr_dev = dev_id; 3861 struct device *dev = hr_dev->dev; 3862 int int_work = 0; 3863 u32 int_st; 3864 u32 int_en; 3865 3866 /* Abnormal interrupt */ 3867 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 3868 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 3869 3870 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 3871 dev_err(dev, "AEQ overflow!\n"); 3872 3873 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1); 3874 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3875 3876 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3877 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3878 3879 int_work = 1; 3880 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 3881 dev_err(dev, "BUS ERR!\n"); 3882 3883 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1); 3884 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3885 3886 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3887 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3888 3889 int_work = 1; 3890 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 3891 dev_err(dev, "OTHER ERR!\n"); 3892 3893 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1); 3894 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3895 3896 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3897 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3898 3899 int_work = 1; 3900 } else 3901 dev_err(dev, "There is no abnormal irq found!\n"); 3902 3903 return IRQ_RETVAL(int_work); 3904 } 3905 3906 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 3907 int eq_num, int enable_flag) 3908 { 3909 int i; 3910 3911 if (enable_flag == EQ_ENABLE) { 3912 for (i = 0; i < eq_num; i++) 3913 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 3914 i * EQ_REG_OFFSET, 3915 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 3916 3917 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 3918 HNS_ROCE_V2_VF_ABN_INT_EN_M); 3919 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 3920 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 3921 } else { 3922 for (i = 0; i < eq_num; i++) 3923 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 3924 i * EQ_REG_OFFSET, 3925 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 3926 3927 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 3928 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 3929 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 3930 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 3931 } 3932 } 3933 3934 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 3935 { 3936 struct device *dev = hr_dev->dev; 3937 int ret; 3938 3939 if (eqn < hr_dev->caps.num_comp_vectors) 3940 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 3941 0, HNS_ROCE_CMD_DESTROY_CEQC, 3942 HNS_ROCE_CMD_TIMEOUT_MSECS); 3943 else 3944 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 3945 0, HNS_ROCE_CMD_DESTROY_AEQC, 3946 HNS_ROCE_CMD_TIMEOUT_MSECS); 3947 if (ret) 3948 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 3949 } 3950 3951 static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev, 3952 struct hns_roce_eq *eq) 3953 { 3954 struct device *dev = hr_dev->dev; 3955 u64 idx; 3956 u64 size; 3957 u32 buf_chk_sz; 3958 u32 bt_chk_sz; 3959 u32 mhop_num; 3960 int eqe_alloc; 3961 int ba_num; 3962 int i = 0; 3963 int j = 0; 3964 3965 mhop_num = hr_dev->caps.eqe_hop_num; 3966 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 3967 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 3968 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1) / 3969 buf_chk_sz; 3970 3971 /* hop_num = 0 */ 3972 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 3973 dma_free_coherent(dev, (unsigned int)(eq->entries * 3974 eq->eqe_size), eq->bt_l0, eq->l0_dma); 3975 return; 3976 } 3977 3978 /* hop_num = 1 or hop = 2 */ 3979 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 3980 if (mhop_num == 1) { 3981 for (i = 0; i < eq->l0_last_num; i++) { 3982 if (i == eq->l0_last_num - 1) { 3983 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 3984 size = (eq->entries - eqe_alloc) * eq->eqe_size; 3985 dma_free_coherent(dev, size, eq->buf[i], 3986 eq->buf_dma[i]); 3987 break; 3988 } 3989 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 3990 eq->buf_dma[i]); 3991 } 3992 } else if (mhop_num == 2) { 3993 for (i = 0; i < eq->l0_last_num; i++) { 3994 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 3995 eq->l1_dma[i]); 3996 3997 for (j = 0; j < bt_chk_sz / 8; j++) { 3998 idx = i * (bt_chk_sz / 8) + j; 3999 if ((i == eq->l0_last_num - 1) 4000 && j == eq->l1_last_num - 1) { 4001 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4002 * idx; 4003 size = (eq->entries - eqe_alloc) 4004 * eq->eqe_size; 4005 dma_free_coherent(dev, size, 4006 eq->buf[idx], 4007 eq->buf_dma[idx]); 4008 break; 4009 } 4010 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4011 eq->buf_dma[idx]); 4012 } 4013 } 4014 } 4015 kfree(eq->buf_dma); 4016 kfree(eq->buf); 4017 kfree(eq->l1_dma); 4018 kfree(eq->bt_l1); 4019 eq->buf_dma = NULL; 4020 eq->buf = NULL; 4021 eq->l1_dma = NULL; 4022 eq->bt_l1 = NULL; 4023 } 4024 4025 static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev, 4026 struct hns_roce_eq *eq) 4027 { 4028 u32 buf_chk_sz; 4029 4030 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4031 4032 if (hr_dev->caps.eqe_hop_num) { 4033 hns_roce_mhop_free_eq(hr_dev, eq); 4034 return; 4035 } 4036 4037 if (eq->buf_list) 4038 dma_free_coherent(hr_dev->dev, buf_chk_sz, 4039 eq->buf_list->buf, eq->buf_list->map); 4040 } 4041 4042 static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev, 4043 struct hns_roce_eq *eq, 4044 void *mb_buf) 4045 { 4046 struct hns_roce_eq_context *eqc; 4047 4048 eqc = mb_buf; 4049 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 4050 4051 /* init eqc */ 4052 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 4053 eq->hop_num = hr_dev->caps.eqe_hop_num; 4054 eq->cons_index = 0; 4055 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 4056 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 4057 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 4058 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz; 4059 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz; 4060 eq->shift = ilog2((unsigned int)eq->entries); 4061 4062 if (!eq->hop_num) 4063 eq->eqe_ba = eq->buf_list->map; 4064 else 4065 eq->eqe_ba = eq->l0_dma; 4066 4067 /* set eqc state */ 4068 roce_set_field(eqc->byte_4, 4069 HNS_ROCE_EQC_EQ_ST_M, 4070 HNS_ROCE_EQC_EQ_ST_S, 4071 HNS_ROCE_V2_EQ_STATE_VALID); 4072 4073 /* set eqe hop num */ 4074 roce_set_field(eqc->byte_4, 4075 HNS_ROCE_EQC_HOP_NUM_M, 4076 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 4077 4078 /* set eqc over_ignore */ 4079 roce_set_field(eqc->byte_4, 4080 HNS_ROCE_EQC_OVER_IGNORE_M, 4081 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 4082 4083 /* set eqc coalesce */ 4084 roce_set_field(eqc->byte_4, 4085 HNS_ROCE_EQC_COALESCE_M, 4086 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 4087 4088 /* set eqc arm_state */ 4089 roce_set_field(eqc->byte_4, 4090 HNS_ROCE_EQC_ARM_ST_M, 4091 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 4092 4093 /* set eqn */ 4094 roce_set_field(eqc->byte_4, 4095 HNS_ROCE_EQC_EQN_M, 4096 HNS_ROCE_EQC_EQN_S, eq->eqn); 4097 4098 /* set eqe_cnt */ 4099 roce_set_field(eqc->byte_4, 4100 HNS_ROCE_EQC_EQE_CNT_M, 4101 HNS_ROCE_EQC_EQE_CNT_S, 4102 HNS_ROCE_EQ_INIT_EQE_CNT); 4103 4104 /* set eqe_ba_pg_sz */ 4105 roce_set_field(eqc->byte_8, 4106 HNS_ROCE_EQC_BA_PG_SZ_M, 4107 HNS_ROCE_EQC_BA_PG_SZ_S, eq->eqe_ba_pg_sz); 4108 4109 /* set eqe_buf_pg_sz */ 4110 roce_set_field(eqc->byte_8, 4111 HNS_ROCE_EQC_BUF_PG_SZ_M, 4112 HNS_ROCE_EQC_BUF_PG_SZ_S, eq->eqe_buf_pg_sz); 4113 4114 /* set eq_producer_idx */ 4115 roce_set_field(eqc->byte_8, 4116 HNS_ROCE_EQC_PROD_INDX_M, 4117 HNS_ROCE_EQC_PROD_INDX_S, 4118 HNS_ROCE_EQ_INIT_PROD_IDX); 4119 4120 /* set eq_max_cnt */ 4121 roce_set_field(eqc->byte_12, 4122 HNS_ROCE_EQC_MAX_CNT_M, 4123 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 4124 4125 /* set eq_period */ 4126 roce_set_field(eqc->byte_12, 4127 HNS_ROCE_EQC_PERIOD_M, 4128 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 4129 4130 /* set eqe_report_timer */ 4131 roce_set_field(eqc->eqe_report_timer, 4132 HNS_ROCE_EQC_REPORT_TIMER_M, 4133 HNS_ROCE_EQC_REPORT_TIMER_S, 4134 HNS_ROCE_EQ_INIT_REPORT_TIMER); 4135 4136 /* set eqe_ba [34:3] */ 4137 roce_set_field(eqc->eqe_ba0, 4138 HNS_ROCE_EQC_EQE_BA_L_M, 4139 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3); 4140 4141 /* set eqe_ba [64:35] */ 4142 roce_set_field(eqc->eqe_ba1, 4143 HNS_ROCE_EQC_EQE_BA_H_M, 4144 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35); 4145 4146 /* set eq shift */ 4147 roce_set_field(eqc->byte_28, 4148 HNS_ROCE_EQC_SHIFT_M, 4149 HNS_ROCE_EQC_SHIFT_S, eq->shift); 4150 4151 /* set eq MSI_IDX */ 4152 roce_set_field(eqc->byte_28, 4153 HNS_ROCE_EQC_MSI_INDX_M, 4154 HNS_ROCE_EQC_MSI_INDX_S, 4155 HNS_ROCE_EQ_INIT_MSI_IDX); 4156 4157 /* set cur_eqe_ba [27:12] */ 4158 roce_set_field(eqc->byte_28, 4159 HNS_ROCE_EQC_CUR_EQE_BA_L_M, 4160 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12); 4161 4162 /* set cur_eqe_ba [59:28] */ 4163 roce_set_field(eqc->byte_32, 4164 HNS_ROCE_EQC_CUR_EQE_BA_M_M, 4165 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28); 4166 4167 /* set cur_eqe_ba [63:60] */ 4168 roce_set_field(eqc->byte_36, 4169 HNS_ROCE_EQC_CUR_EQE_BA_H_M, 4170 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60); 4171 4172 /* set eq consumer idx */ 4173 roce_set_field(eqc->byte_36, 4174 HNS_ROCE_EQC_CONS_INDX_M, 4175 HNS_ROCE_EQC_CONS_INDX_S, 4176 HNS_ROCE_EQ_INIT_CONS_IDX); 4177 4178 /* set nex_eqe_ba[43:12] */ 4179 roce_set_field(eqc->nxt_eqe_ba0, 4180 HNS_ROCE_EQC_NXT_EQE_BA_L_M, 4181 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12); 4182 4183 /* set nex_eqe_ba[63:44] */ 4184 roce_set_field(eqc->nxt_eqe_ba1, 4185 HNS_ROCE_EQC_NXT_EQE_BA_H_M, 4186 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44); 4187 } 4188 4189 static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev, 4190 struct hns_roce_eq *eq) 4191 { 4192 struct device *dev = hr_dev->dev; 4193 int eq_alloc_done = 0; 4194 int eq_buf_cnt = 0; 4195 int eqe_alloc; 4196 u32 buf_chk_sz; 4197 u32 bt_chk_sz; 4198 u32 mhop_num; 4199 u64 size; 4200 u64 idx; 4201 int ba_num; 4202 int bt_num; 4203 int record_i; 4204 int record_j; 4205 int i = 0; 4206 int j = 0; 4207 4208 mhop_num = hr_dev->caps.eqe_hop_num; 4209 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4210 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 4211 4212 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1) 4213 / buf_chk_sz; 4214 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8); 4215 4216 /* hop_num = 0 */ 4217 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 4218 if (eq->entries > buf_chk_sz / eq->eqe_size) { 4219 dev_err(dev, "eq entries %d is larger than buf_pg_sz!", 4220 eq->entries); 4221 return -EINVAL; 4222 } 4223 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size, 4224 &(eq->l0_dma), GFP_KERNEL); 4225 if (!eq->bt_l0) 4226 return -ENOMEM; 4227 4228 eq->cur_eqe_ba = eq->l0_dma; 4229 eq->nxt_eqe_ba = 0; 4230 4231 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size); 4232 4233 return 0; 4234 } 4235 4236 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL); 4237 if (!eq->buf_dma) 4238 return -ENOMEM; 4239 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL); 4240 if (!eq->buf) 4241 goto err_kcalloc_buf; 4242 4243 if (mhop_num == 2) { 4244 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL); 4245 if (!eq->l1_dma) 4246 goto err_kcalloc_l1_dma; 4247 4248 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL); 4249 if (!eq->bt_l1) 4250 goto err_kcalloc_bt_l1; 4251 } 4252 4253 /* alloc L0 BT */ 4254 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL); 4255 if (!eq->bt_l0) 4256 goto err_dma_alloc_l0; 4257 4258 if (mhop_num == 1) { 4259 if (ba_num > (bt_chk_sz / 8)) 4260 dev_err(dev, "ba_num %d is too large for 1 hop\n", 4261 ba_num); 4262 4263 /* alloc buf */ 4264 for (i = 0; i < bt_chk_sz / 8; i++) { 4265 if (eq_buf_cnt + 1 < ba_num) { 4266 size = buf_chk_sz; 4267 } else { 4268 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 4269 size = (eq->entries - eqe_alloc) * eq->eqe_size; 4270 } 4271 eq->buf[i] = dma_alloc_coherent(dev, size, 4272 &(eq->buf_dma[i]), 4273 GFP_KERNEL); 4274 if (!eq->buf[i]) 4275 goto err_dma_alloc_buf; 4276 4277 memset(eq->buf[i], 0, size); 4278 *(eq->bt_l0 + i) = eq->buf_dma[i]; 4279 4280 eq_buf_cnt++; 4281 if (eq_buf_cnt >= ba_num) 4282 break; 4283 } 4284 eq->cur_eqe_ba = eq->buf_dma[0]; 4285 eq->nxt_eqe_ba = eq->buf_dma[1]; 4286 4287 } else if (mhop_num == 2) { 4288 /* alloc L1 BT and buf */ 4289 for (i = 0; i < bt_chk_sz / 8; i++) { 4290 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz, 4291 &(eq->l1_dma[i]), 4292 GFP_KERNEL); 4293 if (!eq->bt_l1[i]) 4294 goto err_dma_alloc_l1; 4295 *(eq->bt_l0 + i) = eq->l1_dma[i]; 4296 4297 for (j = 0; j < bt_chk_sz / 8; j++) { 4298 idx = i * bt_chk_sz / 8 + j; 4299 if (eq_buf_cnt + 1 < ba_num) { 4300 size = buf_chk_sz; 4301 } else { 4302 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4303 * idx; 4304 size = (eq->entries - eqe_alloc) 4305 * eq->eqe_size; 4306 } 4307 eq->buf[idx] = dma_alloc_coherent(dev, size, 4308 &(eq->buf_dma[idx]), 4309 GFP_KERNEL); 4310 if (!eq->buf[idx]) 4311 goto err_dma_alloc_buf; 4312 4313 memset(eq->buf[idx], 0, size); 4314 *(eq->bt_l1[i] + j) = eq->buf_dma[idx]; 4315 4316 eq_buf_cnt++; 4317 if (eq_buf_cnt >= ba_num) { 4318 eq_alloc_done = 1; 4319 break; 4320 } 4321 } 4322 4323 if (eq_alloc_done) 4324 break; 4325 } 4326 eq->cur_eqe_ba = eq->buf_dma[0]; 4327 eq->nxt_eqe_ba = eq->buf_dma[1]; 4328 } 4329 4330 eq->l0_last_num = i + 1; 4331 if (mhop_num == 2) 4332 eq->l1_last_num = j + 1; 4333 4334 return 0; 4335 4336 err_dma_alloc_l1: 4337 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4338 eq->bt_l0 = NULL; 4339 eq->l0_dma = 0; 4340 for (i -= 1; i >= 0; i--) { 4341 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4342 eq->l1_dma[i]); 4343 4344 for (j = 0; j < bt_chk_sz / 8; j++) { 4345 idx = i * bt_chk_sz / 8 + j; 4346 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4347 eq->buf_dma[idx]); 4348 } 4349 } 4350 goto err_dma_alloc_l0; 4351 4352 err_dma_alloc_buf: 4353 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4354 eq->bt_l0 = NULL; 4355 eq->l0_dma = 0; 4356 4357 if (mhop_num == 1) 4358 for (i -= i; i >= 0; i--) 4359 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 4360 eq->buf_dma[i]); 4361 else if (mhop_num == 2) { 4362 record_i = i; 4363 record_j = j; 4364 for (; i >= 0; i--) { 4365 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4366 eq->l1_dma[i]); 4367 4368 for (j = 0; j < bt_chk_sz / 8; j++) { 4369 if (i == record_i && j >= record_j) 4370 break; 4371 4372 idx = i * bt_chk_sz / 8 + j; 4373 dma_free_coherent(dev, buf_chk_sz, 4374 eq->buf[idx], 4375 eq->buf_dma[idx]); 4376 } 4377 } 4378 } 4379 4380 err_dma_alloc_l0: 4381 kfree(eq->bt_l1); 4382 eq->bt_l1 = NULL; 4383 4384 err_kcalloc_bt_l1: 4385 kfree(eq->l1_dma); 4386 eq->l1_dma = NULL; 4387 4388 err_kcalloc_l1_dma: 4389 kfree(eq->buf); 4390 eq->buf = NULL; 4391 4392 err_kcalloc_buf: 4393 kfree(eq->buf_dma); 4394 eq->buf_dma = NULL; 4395 4396 return -ENOMEM; 4397 } 4398 4399 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 4400 struct hns_roce_eq *eq, 4401 unsigned int eq_cmd) 4402 { 4403 struct device *dev = hr_dev->dev; 4404 struct hns_roce_cmd_mailbox *mailbox; 4405 u32 buf_chk_sz = 0; 4406 int ret; 4407 4408 /* Allocate mailbox memory */ 4409 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4410 if (IS_ERR(mailbox)) 4411 return PTR_ERR(mailbox); 4412 4413 if (!hr_dev->caps.eqe_hop_num) { 4414 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4415 4416 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list), 4417 GFP_KERNEL); 4418 if (!eq->buf_list) { 4419 ret = -ENOMEM; 4420 goto free_cmd_mbox; 4421 } 4422 4423 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz, 4424 &(eq->buf_list->map), 4425 GFP_KERNEL); 4426 if (!eq->buf_list->buf) { 4427 ret = -ENOMEM; 4428 goto err_alloc_buf; 4429 } 4430 4431 memset(eq->buf_list->buf, 0, buf_chk_sz); 4432 } else { 4433 ret = hns_roce_mhop_alloc_eq(hr_dev, eq); 4434 if (ret) { 4435 ret = -ENOMEM; 4436 goto free_cmd_mbox; 4437 } 4438 } 4439 4440 hns_roce_config_eqc(hr_dev, eq, mailbox->buf); 4441 4442 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 4443 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 4444 if (ret) { 4445 dev_err(dev, "[mailbox cmd] creat eqc failed.\n"); 4446 goto err_cmd_mbox; 4447 } 4448 4449 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4450 4451 return 0; 4452 4453 err_cmd_mbox: 4454 if (!hr_dev->caps.eqe_hop_num) 4455 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf, 4456 eq->buf_list->map); 4457 else { 4458 hns_roce_mhop_free_eq(hr_dev, eq); 4459 goto free_cmd_mbox; 4460 } 4461 4462 err_alloc_buf: 4463 kfree(eq->buf_list); 4464 4465 free_cmd_mbox: 4466 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4467 4468 return ret; 4469 } 4470 4471 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 4472 { 4473 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 4474 struct device *dev = hr_dev->dev; 4475 struct hns_roce_eq *eq; 4476 unsigned int eq_cmd; 4477 int irq_num; 4478 int eq_num; 4479 int other_num; 4480 int comp_num; 4481 int aeq_num; 4482 int i, j, k; 4483 int ret; 4484 4485 other_num = hr_dev->caps.num_other_vectors; 4486 comp_num = hr_dev->caps.num_comp_vectors; 4487 aeq_num = hr_dev->caps.num_aeq_vectors; 4488 4489 eq_num = comp_num + aeq_num; 4490 irq_num = eq_num + other_num; 4491 4492 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 4493 if (!eq_table->eq) 4494 return -ENOMEM; 4495 4496 for (i = 0; i < irq_num; i++) { 4497 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 4498 GFP_KERNEL); 4499 if (!hr_dev->irq_names[i]) { 4500 ret = -ENOMEM; 4501 goto err_failed_kzalloc; 4502 } 4503 } 4504 4505 /* create eq */ 4506 for (j = 0; j < eq_num; j++) { 4507 eq = &eq_table->eq[j]; 4508 eq->hr_dev = hr_dev; 4509 eq->eqn = j; 4510 if (j < comp_num) { 4511 /* CEQ */ 4512 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 4513 eq->type_flag = HNS_ROCE_CEQ; 4514 eq->entries = hr_dev->caps.ceqe_depth; 4515 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; 4516 eq->irq = hr_dev->irq[j + other_num + aeq_num]; 4517 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 4518 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 4519 } else { 4520 /* AEQ */ 4521 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 4522 eq->type_flag = HNS_ROCE_AEQ; 4523 eq->entries = hr_dev->caps.aeqe_depth; 4524 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; 4525 eq->irq = hr_dev->irq[j - comp_num + other_num]; 4526 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 4527 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 4528 } 4529 4530 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 4531 if (ret) { 4532 dev_err(dev, "eq create failed.\n"); 4533 goto err_create_eq_fail; 4534 } 4535 } 4536 4537 /* enable irq */ 4538 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 4539 4540 /* irq contains: abnormal + AEQ + CEQ*/ 4541 for (k = 0; k < irq_num; k++) 4542 if (k < other_num) 4543 snprintf((char *)hr_dev->irq_names[k], 4544 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k); 4545 else if (k < (other_num + aeq_num)) 4546 snprintf((char *)hr_dev->irq_names[k], 4547 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d", 4548 k - other_num); 4549 else 4550 snprintf((char *)hr_dev->irq_names[k], 4551 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d", 4552 k - other_num - aeq_num); 4553 4554 for (k = 0; k < irq_num; k++) { 4555 if (k < other_num) 4556 ret = request_irq(hr_dev->irq[k], 4557 hns_roce_v2_msix_interrupt_abn, 4558 0, hr_dev->irq_names[k], hr_dev); 4559 4560 else if (k < (other_num + comp_num)) 4561 ret = request_irq(eq_table->eq[k - other_num].irq, 4562 hns_roce_v2_msix_interrupt_eq, 4563 0, hr_dev->irq_names[k + aeq_num], 4564 &eq_table->eq[k - other_num]); 4565 else 4566 ret = request_irq(eq_table->eq[k - other_num].irq, 4567 hns_roce_v2_msix_interrupt_eq, 4568 0, hr_dev->irq_names[k - comp_num], 4569 &eq_table->eq[k - other_num]); 4570 if (ret) { 4571 dev_err(dev, "Request irq error!\n"); 4572 goto err_request_irq_fail; 4573 } 4574 } 4575 4576 return 0; 4577 4578 err_request_irq_fail: 4579 for (k -= 1; k >= 0; k--) 4580 if (k < other_num) 4581 free_irq(hr_dev->irq[k], hr_dev); 4582 else 4583 free_irq(eq_table->eq[k - other_num].irq, 4584 &eq_table->eq[k - other_num]); 4585 4586 err_create_eq_fail: 4587 for (j -= 1; j >= 0; j--) 4588 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]); 4589 4590 err_failed_kzalloc: 4591 for (i -= 1; i >= 0; i--) 4592 kfree(hr_dev->irq_names[i]); 4593 kfree(eq_table->eq); 4594 4595 return ret; 4596 } 4597 4598 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 4599 { 4600 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 4601 int irq_num; 4602 int eq_num; 4603 int i; 4604 4605 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 4606 irq_num = eq_num + hr_dev->caps.num_other_vectors; 4607 4608 /* Disable irq */ 4609 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 4610 4611 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 4612 free_irq(hr_dev->irq[i], hr_dev); 4613 4614 for (i = 0; i < eq_num; i++) { 4615 hns_roce_v2_destroy_eqc(hr_dev, i); 4616 4617 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]); 4618 4619 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]); 4620 } 4621 4622 for (i = 0; i < irq_num; i++) 4623 kfree(hr_dev->irq_names[i]); 4624 4625 kfree(eq_table->eq); 4626 } 4627 4628 static const struct hns_roce_hw hns_roce_hw_v2 = { 4629 .cmq_init = hns_roce_v2_cmq_init, 4630 .cmq_exit = hns_roce_v2_cmq_exit, 4631 .hw_profile = hns_roce_v2_profile, 4632 .post_mbox = hns_roce_v2_post_mbox, 4633 .chk_mbox = hns_roce_v2_chk_mbox, 4634 .set_gid = hns_roce_v2_set_gid, 4635 .set_mac = hns_roce_v2_set_mac, 4636 .write_mtpt = hns_roce_v2_write_mtpt, 4637 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 4638 .write_cqc = hns_roce_v2_write_cqc, 4639 .set_hem = hns_roce_v2_set_hem, 4640 .clear_hem = hns_roce_v2_clear_hem, 4641 .modify_qp = hns_roce_v2_modify_qp, 4642 .query_qp = hns_roce_v2_query_qp, 4643 .destroy_qp = hns_roce_v2_destroy_qp, 4644 .modify_cq = hns_roce_v2_modify_cq, 4645 .post_send = hns_roce_v2_post_send, 4646 .post_recv = hns_roce_v2_post_recv, 4647 .req_notify_cq = hns_roce_v2_req_notify_cq, 4648 .poll_cq = hns_roce_v2_poll_cq, 4649 .init_eq = hns_roce_v2_init_eq_table, 4650 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 4651 }; 4652 4653 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 4654 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 4655 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 4656 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 4657 /* required last entry */ 4658 {0, } 4659 }; 4660 4661 static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 4662 struct hnae3_handle *handle) 4663 { 4664 const struct pci_device_id *id; 4665 int i; 4666 4667 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 4668 if (!id) { 4669 dev_err(hr_dev->dev, "device is not compatible!\n"); 4670 return -ENXIO; 4671 } 4672 4673 hr_dev->hw = &hns_roce_hw_v2; 4674 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 4675 hr_dev->odb_offset = hr_dev->sdb_offset; 4676 4677 /* Get info from NIC driver. */ 4678 hr_dev->reg_base = handle->rinfo.roce_io_base; 4679 hr_dev->caps.num_ports = 1; 4680 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 4681 hr_dev->iboe.phy_port[0] = 0; 4682 4683 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 4684 hr_dev->iboe.netdevs[0]->dev_addr); 4685 4686 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 4687 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 4688 i + handle->rinfo.base_vector); 4689 4690 /* cmd issue mode: 0 is poll, 1 is event */ 4691 hr_dev->cmd_mod = 1; 4692 hr_dev->loop_idc = 0; 4693 4694 return 0; 4695 } 4696 4697 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 4698 { 4699 struct hns_roce_dev *hr_dev; 4700 int ret; 4701 4702 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev)); 4703 if (!hr_dev) 4704 return -ENOMEM; 4705 4706 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 4707 if (!hr_dev->priv) { 4708 ret = -ENOMEM; 4709 goto error_failed_kzalloc; 4710 } 4711 4712 hr_dev->pci_dev = handle->pdev; 4713 hr_dev->dev = &handle->pdev->dev; 4714 handle->priv = hr_dev; 4715 4716 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle); 4717 if (ret) { 4718 dev_err(hr_dev->dev, "Get Configuration failed!\n"); 4719 goto error_failed_get_cfg; 4720 } 4721 4722 ret = hns_roce_init(hr_dev); 4723 if (ret) { 4724 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 4725 goto error_failed_get_cfg; 4726 } 4727 4728 return 0; 4729 4730 error_failed_get_cfg: 4731 kfree(hr_dev->priv); 4732 4733 error_failed_kzalloc: 4734 ib_dealloc_device(&hr_dev->ib_dev); 4735 4736 return ret; 4737 } 4738 4739 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 4740 bool reset) 4741 { 4742 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 4743 4744 hns_roce_exit(hr_dev); 4745 kfree(hr_dev->priv); 4746 ib_dealloc_device(&hr_dev->ib_dev); 4747 } 4748 4749 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 4750 .init_instance = hns_roce_hw_v2_init_instance, 4751 .uninit_instance = hns_roce_hw_v2_uninit_instance, 4752 }; 4753 4754 static struct hnae3_client hns_roce_hw_v2_client = { 4755 .name = "hns_roce_hw_v2", 4756 .type = HNAE3_CLIENT_ROCE, 4757 .ops = &hns_roce_hw_v2_ops, 4758 }; 4759 4760 static int __init hns_roce_hw_v2_init(void) 4761 { 4762 return hnae3_register_client(&hns_roce_hw_v2_client); 4763 } 4764 4765 static void __exit hns_roce_hw_v2_exit(void) 4766 { 4767 hnae3_unregister_client(&hns_roce_hw_v2_client); 4768 } 4769 4770 module_init(hns_roce_hw_v2_init); 4771 module_exit(hns_roce_hw_v2_exit); 4772 4773 MODULE_LICENSE("Dual BSD/GPL"); 4774 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 4775 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 4776 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 4777 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 4778