1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 123 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 124 }; 125 126 static u32 to_hr_opcode(u32 ib_opcode) 127 { 128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 129 return HNS_ROCE_V2_WQE_OP_MASK; 130 131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 132 HNS_ROCE_V2_WQE_OP_MASK; 133 } 134 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 136 const struct ib_reg_wr *wr) 137 { 138 struct hns_roce_wqe_frmr_seg *fseg = 139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 140 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 141 u64 pbl_ba; 142 143 /* use ib_access_flags */ 144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 145 hr_reg_write_bool(fseg, FRMR_ATOMIC, 146 wr->access & IB_ACCESS_REMOTE_ATOMIC); 147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 150 151 /* Data structure reuse may lead to confusion */ 152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 155 156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 158 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 160 161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 164 hr_reg_clear(fseg, FRMR_BLK_MODE); 165 } 166 167 static void set_atomic_seg(const struct ib_send_wr *wr, 168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 169 unsigned int valid_num_sge) 170 { 171 struct hns_roce_v2_wqe_data_seg *dseg = 172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 173 struct hns_roce_wqe_atomic_seg *aseg = 174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 175 176 set_data_seg_v2(dseg, wr->sg_list); 177 178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 181 } else { 182 aseg->fetchadd_swap_data = 183 cpu_to_le64(atomic_wr(wr)->compare_add); 184 aseg->cmp_data = 0; 185 } 186 187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 188 } 189 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 191 const struct ib_send_wr *wr, 192 unsigned int *sge_idx, u32 msg_len) 193 { 194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 195 unsigned int left_len_in_pg; 196 unsigned int idx = *sge_idx; 197 unsigned int i = 0; 198 unsigned int len; 199 void *addr; 200 void *dseg; 201 202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 203 ibdev_err(ibdev, 204 "no enough extended sge space for inline data.\n"); 205 return -EINVAL; 206 } 207 208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 210 len = wr->sg_list[0].length; 211 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 212 213 /* When copying data to extended sge space, the left length in page may 214 * not long enough for current user's sge. So the data should be 215 * splited into several parts, one in the first page, and the others in 216 * the subsequent pages. 217 */ 218 while (1) { 219 if (len <= left_len_in_pg) { 220 memcpy(dseg, addr, len); 221 222 idx += len / HNS_ROCE_SGE_SIZE; 223 224 i++; 225 if (i >= wr->num_sge) 226 break; 227 228 left_len_in_pg -= len; 229 len = wr->sg_list[i].length; 230 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 231 dseg += len; 232 } else { 233 memcpy(dseg, addr, left_len_in_pg); 234 235 len -= left_len_in_pg; 236 addr += left_len_in_pg; 237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 238 dseg = hns_roce_get_extend_sge(qp, 239 idx & (qp->sge.sge_cnt - 1)); 240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 241 } 242 } 243 244 *sge_idx = idx; 245 246 return 0; 247 } 248 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 250 unsigned int *sge_ind, unsigned int cnt) 251 { 252 struct hns_roce_v2_wqe_data_seg *dseg; 253 unsigned int idx = *sge_ind; 254 255 while (cnt > 0) { 256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 257 if (likely(sge->length)) { 258 set_data_seg_v2(dseg, sge); 259 idx++; 260 cnt--; 261 } 262 sge++; 263 } 264 265 *sge_ind = idx; 266 } 267 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 269 { 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 274 ibdev_err(&hr_dev->ib_dev, 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 len, qp->max_inline_data, mtu); 277 return false; 278 } 279 280 return true; 281 } 282 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 285 unsigned int *sge_idx) 286 { 287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 289 struct ib_device *ibdev = &hr_dev->ib_dev; 290 unsigned int curr_idx = *sge_idx; 291 void *dseg = rc_sq_wqe; 292 unsigned int i; 293 int ret; 294 295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 296 ibdev_err(ibdev, "invalid inline parameters!\n"); 297 return -EINVAL; 298 } 299 300 if (!check_inl_data_len(qp, msg_len)) 301 return -EINVAL; 302 303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 304 305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 307 308 for (i = 0; i < wr->num_sge; i++) { 309 memcpy(dseg, ((void *)wr->sg_list[i].addr), 310 wr->sg_list[i].length); 311 dseg += wr->sg_list[i].length; 312 } 313 } else { 314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 317 if (ret) 318 return ret; 319 320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 321 } 322 323 *sge_idx = curr_idx; 324 325 return 0; 326 } 327 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 330 unsigned int *sge_ind, 331 unsigned int valid_num_sge) 332 { 333 struct hns_roce_v2_wqe_data_seg *dseg = 334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 335 struct hns_roce_qp *qp = to_hr_qp(ibqp); 336 int j = 0; 337 int i; 338 339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 340 (*sge_ind) & (qp->sge.sge_cnt - 1)); 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 343 !!(wr->send_flags & IB_SEND_INLINE)); 344 if (wr->send_flags & IB_SEND_INLINE) 345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 346 347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 348 for (i = 0; i < wr->num_sge; i++) { 349 if (likely(wr->sg_list[i].length)) { 350 set_data_seg_v2(dseg, wr->sg_list + i); 351 dseg++; 352 } 353 } 354 } else { 355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 356 if (likely(wr->sg_list[i].length)) { 357 set_data_seg_v2(dseg, wr->sg_list + i); 358 dseg++; 359 j++; 360 } 361 } 362 363 set_extend_sge(qp, wr->sg_list + i, sge_ind, 364 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 365 } 366 367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 368 369 return 0; 370 } 371 372 static int check_send_valid(struct hns_roce_dev *hr_dev, 373 struct hns_roce_qp *hr_qp) 374 { 375 struct ib_device *ibdev = &hr_dev->ib_dev; 376 377 if (unlikely(hr_qp->state == IB_QPS_RESET || 378 hr_qp->state == IB_QPS_INIT || 379 hr_qp->state == IB_QPS_RTR)) { 380 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 381 hr_qp->state); 382 return -EINVAL; 383 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 384 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 385 hr_dev->state); 386 return -EIO; 387 } 388 389 return 0; 390 } 391 392 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 393 unsigned int *sge_len) 394 { 395 unsigned int valid_num = 0; 396 unsigned int len = 0; 397 int i; 398 399 for (i = 0; i < wr->num_sge; i++) { 400 if (likely(wr->sg_list[i].length)) { 401 len += wr->sg_list[i].length; 402 valid_num++; 403 } 404 } 405 406 *sge_len = len; 407 return valid_num; 408 } 409 410 static __le32 get_immtdata(const struct ib_send_wr *wr) 411 { 412 switch (wr->opcode) { 413 case IB_WR_SEND_WITH_IMM: 414 case IB_WR_RDMA_WRITE_WITH_IMM: 415 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 416 default: 417 return 0; 418 } 419 } 420 421 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 422 const struct ib_send_wr *wr) 423 { 424 u32 ib_op = wr->opcode; 425 426 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 427 return -EINVAL; 428 429 ud_sq_wqe->immtdata = get_immtdata(wr); 430 431 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 432 433 return 0; 434 } 435 436 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 437 struct hns_roce_ah *ah) 438 { 439 struct ib_device *ib_dev = ah->ibah.device; 440 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 441 442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 445 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 446 447 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 448 return -EINVAL; 449 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 451 452 ud_sq_wqe->sgid_index = ah->av.gid_index; 453 454 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 455 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 456 457 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 458 return 0; 459 460 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 461 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 462 463 return 0; 464 } 465 466 static inline int set_ud_wqe(struct hns_roce_qp *qp, 467 const struct ib_send_wr *wr, 468 void *wqe, unsigned int *sge_idx, 469 unsigned int owner_bit) 470 { 471 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 472 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 473 unsigned int curr_idx = *sge_idx; 474 unsigned int valid_num_sge; 475 u32 msg_len = 0; 476 int ret; 477 478 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 479 480 ret = set_ud_opcode(ud_sq_wqe, wr); 481 if (WARN_ON(ret)) 482 return ret; 483 484 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 485 486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 487 !!(wr->send_flags & IB_SEND_SIGNALED)); 488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 489 !!(wr->send_flags & IB_SEND_SOLICITED)); 490 491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 494 curr_idx & (qp->sge.sge_cnt - 1)); 495 496 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 497 qp->qkey : ud_wr(wr)->remote_qkey); 498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 499 500 ret = fill_ud_av(ud_sq_wqe, ah); 501 if (ret) 502 return ret; 503 504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 505 506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 507 508 /* 509 * The pipeline can sequentially post all valid WQEs into WQ buffer, 510 * including new WQEs waiting for the doorbell to update the PI again. 511 * Therefore, the owner bit of WQE MUST be updated after all fields 512 * and extSGEs have been written into DDR instead of cache. 513 */ 514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 515 dma_wmb(); 516 517 *sge_idx = curr_idx; 518 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 519 520 return 0; 521 } 522 523 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 524 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 525 const struct ib_send_wr *wr) 526 { 527 u32 ib_op = wr->opcode; 528 int ret = 0; 529 530 rc_sq_wqe->immtdata = get_immtdata(wr); 531 532 switch (ib_op) { 533 case IB_WR_RDMA_READ: 534 case IB_WR_RDMA_WRITE: 535 case IB_WR_RDMA_WRITE_WITH_IMM: 536 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 537 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 538 break; 539 case IB_WR_SEND: 540 case IB_WR_SEND_WITH_IMM: 541 break; 542 case IB_WR_ATOMIC_CMP_AND_SWP: 543 case IB_WR_ATOMIC_FETCH_AND_ADD: 544 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 545 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 546 break; 547 case IB_WR_REG_MR: 548 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 549 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 550 else 551 ret = -EOPNOTSUPP; 552 break; 553 case IB_WR_SEND_WITH_INV: 554 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 555 break; 556 default: 557 ret = -EINVAL; 558 } 559 560 if (unlikely(ret)) 561 return ret; 562 563 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 564 565 return ret; 566 } 567 568 static inline int set_rc_wqe(struct hns_roce_qp *qp, 569 const struct ib_send_wr *wr, 570 void *wqe, unsigned int *sge_idx, 571 unsigned int owner_bit) 572 { 573 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 574 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 575 unsigned int curr_idx = *sge_idx; 576 unsigned int valid_num_sge; 577 u32 msg_len = 0; 578 int ret; 579 580 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 581 582 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 583 584 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 585 if (WARN_ON(ret)) 586 return ret; 587 588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 589 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 590 591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 592 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 593 594 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 595 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 596 597 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 598 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 599 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 600 else if (wr->opcode != IB_WR_REG_MR) 601 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 602 &curr_idx, valid_num_sge); 603 604 /* 605 * The pipeline can sequentially post all valid WQEs into WQ buffer, 606 * including new WQEs waiting for the doorbell to update the PI again. 607 * Therefore, the owner bit of WQE MUST be updated after all fields 608 * and extSGEs have been written into DDR instead of cache. 609 */ 610 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 611 dma_wmb(); 612 613 *sge_idx = curr_idx; 614 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 615 616 return ret; 617 } 618 619 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 620 struct hns_roce_qp *qp) 621 { 622 if (unlikely(qp->state == IB_QPS_ERR)) { 623 flush_cqe(hr_dev, qp); 624 } else { 625 struct hns_roce_v2_db sq_db = {}; 626 627 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 628 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 629 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 630 hr_reg_write(&sq_db, DB_SL, qp->sl); 631 632 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 633 } 634 } 635 636 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 637 struct hns_roce_qp *qp) 638 { 639 if (unlikely(qp->state == IB_QPS_ERR)) { 640 flush_cqe(hr_dev, qp); 641 } else { 642 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 643 *qp->rdb.db_record = 644 qp->rq.head & V2_DB_PRODUCER_IDX_M; 645 } else { 646 struct hns_roce_v2_db rq_db = {}; 647 648 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 649 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 650 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 651 652 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 653 qp->rq.db_reg); 654 } 655 } 656 } 657 658 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 659 u64 __iomem *dest) 660 { 661 #define HNS_ROCE_WRITE_TIMES 8 662 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 663 struct hnae3_handle *handle = priv->handle; 664 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 665 int i; 666 667 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 668 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 669 writeq_relaxed(*(val + i), dest + i); 670 } 671 672 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 673 void *wqe) 674 { 675 #define HNS_ROCE_SL_SHIFT 2 676 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 677 678 /* All kinds of DirectWQE have the same header field layout */ 679 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 680 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 682 qp->sl >> HNS_ROCE_SL_SHIFT); 683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 684 685 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 686 } 687 688 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 689 const struct ib_send_wr *wr, 690 const struct ib_send_wr **bad_wr) 691 { 692 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 693 struct ib_device *ibdev = &hr_dev->ib_dev; 694 struct hns_roce_qp *qp = to_hr_qp(ibqp); 695 unsigned long flags = 0; 696 unsigned int owner_bit; 697 unsigned int sge_idx; 698 unsigned int wqe_idx; 699 void *wqe = NULL; 700 u32 nreq; 701 int ret; 702 703 spin_lock_irqsave(&qp->sq.lock, flags); 704 705 ret = check_send_valid(hr_dev, qp); 706 if (unlikely(ret)) { 707 *bad_wr = wr; 708 nreq = 0; 709 goto out; 710 } 711 712 sge_idx = qp->next_sge; 713 714 for (nreq = 0; wr; ++nreq, wr = wr->next) { 715 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 716 ret = -ENOMEM; 717 *bad_wr = wr; 718 goto out; 719 } 720 721 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 722 723 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 724 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 725 wr->num_sge, qp->sq.max_gs); 726 ret = -EINVAL; 727 *bad_wr = wr; 728 goto out; 729 } 730 731 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 732 qp->sq.wrid[wqe_idx] = wr->wr_id; 733 owner_bit = 734 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 735 736 /* Corresponding to the QP type, wqe process separately */ 737 if (ibqp->qp_type == IB_QPT_RC) 738 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 739 else 740 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 741 742 if (unlikely(ret)) { 743 *bad_wr = wr; 744 goto out; 745 } 746 } 747 748 out: 749 if (likely(nreq)) { 750 qp->sq.head += nreq; 751 qp->next_sge = sge_idx; 752 753 if (nreq == 1 && !ret && 754 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 755 write_dwqe(hr_dev, qp, wqe); 756 else 757 update_sq_db(hr_dev, qp); 758 } 759 760 spin_unlock_irqrestore(&qp->sq.lock, flags); 761 762 return ret; 763 } 764 765 static int check_recv_valid(struct hns_roce_dev *hr_dev, 766 struct hns_roce_qp *hr_qp) 767 { 768 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 769 return -EIO; 770 771 if (hr_qp->state == IB_QPS_RESET) 772 return -EINVAL; 773 774 return 0; 775 } 776 777 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 778 u32 max_sge, bool rsv) 779 { 780 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 781 u32 i, cnt; 782 783 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 784 /* Skip zero-length sge */ 785 if (!wr->sg_list[i].length) 786 continue; 787 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 788 cnt++; 789 } 790 791 /* Fill a reserved sge to make hw stop reading remaining segments */ 792 if (rsv) { 793 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 794 dseg[cnt].addr = 0; 795 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 796 } else { 797 /* Clear remaining segments to make ROCEE ignore sges */ 798 if (cnt < max_sge) 799 memset(dseg + cnt, 0, 800 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 801 } 802 } 803 804 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 805 u32 wqe_idx, u32 max_sge) 806 { 807 void *wqe = NULL; 808 809 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 810 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 811 } 812 813 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 814 const struct ib_recv_wr *wr, 815 const struct ib_recv_wr **bad_wr) 816 { 817 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 818 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 819 struct ib_device *ibdev = &hr_dev->ib_dev; 820 u32 wqe_idx, nreq, max_sge; 821 unsigned long flags; 822 int ret; 823 824 spin_lock_irqsave(&hr_qp->rq.lock, flags); 825 826 ret = check_recv_valid(hr_dev, hr_qp); 827 if (unlikely(ret)) { 828 *bad_wr = wr; 829 nreq = 0; 830 goto out; 831 } 832 833 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 834 for (nreq = 0; wr; ++nreq, wr = wr->next) { 835 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 836 hr_qp->ibqp.recv_cq))) { 837 ret = -ENOMEM; 838 *bad_wr = wr; 839 goto out; 840 } 841 842 if (unlikely(wr->num_sge > max_sge)) { 843 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 844 wr->num_sge, max_sge); 845 ret = -EINVAL; 846 *bad_wr = wr; 847 goto out; 848 } 849 850 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 851 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 852 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 853 } 854 855 out: 856 if (likely(nreq)) { 857 hr_qp->rq.head += nreq; 858 859 update_rq_db(hr_dev, hr_qp); 860 } 861 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 862 863 return ret; 864 } 865 866 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 867 { 868 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 869 } 870 871 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 872 { 873 return hns_roce_buf_offset(idx_que->mtr.kmem, 874 n << idx_que->entry_shift); 875 } 876 877 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 878 { 879 /* always called with interrupts disabled. */ 880 spin_lock(&srq->lock); 881 882 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 883 srq->idx_que.tail++; 884 885 spin_unlock(&srq->lock); 886 } 887 888 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 889 { 890 struct hns_roce_idx_que *idx_que = &srq->idx_que; 891 892 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 893 } 894 895 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 896 const struct ib_recv_wr *wr) 897 { 898 struct ib_device *ib_dev = srq->ibsrq.device; 899 900 if (unlikely(wr->num_sge > max_sge)) { 901 ibdev_err(ib_dev, 902 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 903 wr->num_sge, max_sge); 904 return -EINVAL; 905 } 906 907 if (unlikely(hns_roce_srqwq_overflow(srq))) { 908 ibdev_err(ib_dev, 909 "failed to check srqwq status, srqwq is full.\n"); 910 return -ENOMEM; 911 } 912 913 return 0; 914 } 915 916 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 917 { 918 struct hns_roce_idx_que *idx_que = &srq->idx_que; 919 u32 pos; 920 921 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 922 if (unlikely(pos == srq->wqe_cnt)) 923 return -ENOSPC; 924 925 bitmap_set(idx_que->bitmap, pos, 1); 926 *wqe_idx = pos; 927 return 0; 928 } 929 930 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 931 { 932 struct hns_roce_idx_que *idx_que = &srq->idx_que; 933 unsigned int head; 934 __le32 *buf; 935 936 head = idx_que->head & (srq->wqe_cnt - 1); 937 938 buf = get_idx_buf(idx_que, head); 939 *buf = cpu_to_le32(wqe_idx); 940 941 idx_que->head++; 942 } 943 944 static void update_srq_db(struct hns_roce_srq *srq) 945 { 946 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 947 struct hns_roce_v2_db db; 948 949 hr_reg_write(&db, DB_TAG, srq->srqn); 950 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 951 hr_reg_write(&db, DB_PI, srq->idx_que.head); 952 953 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 954 } 955 956 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 957 const struct ib_recv_wr *wr, 958 const struct ib_recv_wr **bad_wr) 959 { 960 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 961 unsigned long flags; 962 int ret = 0; 963 u32 max_sge; 964 u32 wqe_idx; 965 void *wqe; 966 u32 nreq; 967 968 spin_lock_irqsave(&srq->lock, flags); 969 970 max_sge = srq->max_gs - srq->rsv_sge; 971 for (nreq = 0; wr; ++nreq, wr = wr->next) { 972 ret = check_post_srq_valid(srq, max_sge, wr); 973 if (ret) { 974 *bad_wr = wr; 975 break; 976 } 977 978 ret = get_srq_wqe_idx(srq, &wqe_idx); 979 if (unlikely(ret)) { 980 *bad_wr = wr; 981 break; 982 } 983 984 wqe = get_srq_wqe_buf(srq, wqe_idx); 985 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 986 fill_wqe_idx(srq, wqe_idx); 987 srq->wrid[wqe_idx] = wr->wr_id; 988 } 989 990 if (likely(nreq)) { 991 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 992 *srq->rdb.db_record = srq->idx_que.head & 993 V2_DB_PRODUCER_IDX_M; 994 else 995 update_srq_db(srq); 996 } 997 998 spin_unlock_irqrestore(&srq->lock, flags); 999 1000 return ret; 1001 } 1002 1003 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1004 unsigned long instance_stage, 1005 unsigned long reset_stage) 1006 { 1007 /* When hardware reset has been completed once or more, we should stop 1008 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1009 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1010 * stage of soft reset process, we should exit with error, and then 1011 * HNAE3_INIT_CLIENT related process can rollback the operation like 1012 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1013 * process will exit with error to notify NIC driver to reschedule soft 1014 * reset process once again. 1015 */ 1016 hr_dev->is_reset = true; 1017 hr_dev->dis_db = true; 1018 1019 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1020 instance_stage == HNS_ROCE_STATE_INIT) 1021 return CMD_RST_PRC_EBUSY; 1022 1023 return CMD_RST_PRC_SUCCESS; 1024 } 1025 1026 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1027 unsigned long instance_stage, 1028 unsigned long reset_stage) 1029 { 1030 #define HW_RESET_TIMEOUT_US 1000000 1031 #define HW_RESET_SLEEP_US 1000 1032 1033 struct hns_roce_v2_priv *priv = hr_dev->priv; 1034 struct hnae3_handle *handle = priv->handle; 1035 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1036 unsigned long val; 1037 int ret; 1038 1039 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1040 * doorbell to hardware. If now in .init_instance() function, we should 1041 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1042 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1043 * related process can rollback the operation like notifing hardware to 1044 * free resources, HNAE3_INIT_CLIENT related process will exit with 1045 * error to notify NIC driver to reschedule soft reset process once 1046 * again. 1047 */ 1048 hr_dev->dis_db = true; 1049 1050 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1051 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1052 HW_RESET_TIMEOUT_US, false, handle); 1053 if (!ret) 1054 hr_dev->is_reset = true; 1055 1056 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1057 instance_stage == HNS_ROCE_STATE_INIT) 1058 return CMD_RST_PRC_EBUSY; 1059 1060 return CMD_RST_PRC_SUCCESS; 1061 } 1062 1063 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1064 { 1065 struct hns_roce_v2_priv *priv = hr_dev->priv; 1066 struct hnae3_handle *handle = priv->handle; 1067 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1068 1069 /* When software reset is detected at .init_instance() function, we 1070 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1071 * with error. 1072 */ 1073 hr_dev->dis_db = true; 1074 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1075 hr_dev->is_reset = true; 1076 1077 return CMD_RST_PRC_EBUSY; 1078 } 1079 1080 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1081 struct hnae3_handle *handle) 1082 { 1083 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1084 unsigned long instance_stage; /* the current instance stage */ 1085 unsigned long reset_stage; /* the current reset stage */ 1086 unsigned long reset_cnt; 1087 bool sw_resetting; 1088 bool hw_resetting; 1089 1090 /* Get information about reset from NIC driver or RoCE driver itself, 1091 * the meaning of the following variables from NIC driver are described 1092 * as below: 1093 * reset_cnt -- The count value of completed hardware reset. 1094 * hw_resetting -- Whether hardware device is resetting now. 1095 * sw_resetting -- Whether NIC's software reset process is running now. 1096 */ 1097 instance_stage = handle->rinfo.instance_state; 1098 reset_stage = handle->rinfo.reset_state; 1099 reset_cnt = ops->ae_dev_reset_cnt(handle); 1100 if (reset_cnt != hr_dev->reset_cnt) 1101 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1102 reset_stage); 1103 1104 hw_resetting = ops->get_cmdq_stat(handle); 1105 if (hw_resetting) 1106 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1107 reset_stage); 1108 1109 sw_resetting = ops->ae_dev_resetting(handle); 1110 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1111 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1112 1113 return CMD_RST_PRC_OTHERS; 1114 } 1115 1116 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1117 { 1118 struct hns_roce_v2_priv *priv = hr_dev->priv; 1119 struct hnae3_handle *handle = priv->handle; 1120 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1121 1122 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1123 return true; 1124 1125 if (ops->get_hw_reset_stat(handle)) 1126 return true; 1127 1128 if (ops->ae_dev_resetting(handle)) 1129 return true; 1130 1131 return false; 1132 } 1133 1134 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1135 { 1136 struct hns_roce_v2_priv *priv = hr_dev->priv; 1137 u32 status; 1138 1139 if (hr_dev->is_reset) 1140 status = CMD_RST_PRC_SUCCESS; 1141 else 1142 status = check_aedev_reset_status(hr_dev, priv->handle); 1143 1144 *busy = (status == CMD_RST_PRC_EBUSY); 1145 1146 return status == CMD_RST_PRC_OTHERS; 1147 } 1148 1149 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1150 struct hns_roce_v2_cmq_ring *ring) 1151 { 1152 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1153 1154 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1155 &ring->desc_dma_addr, GFP_KERNEL); 1156 if (!ring->desc) 1157 return -ENOMEM; 1158 1159 return 0; 1160 } 1161 1162 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1163 struct hns_roce_v2_cmq_ring *ring) 1164 { 1165 dma_free_coherent(hr_dev->dev, 1166 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1167 ring->desc, ring->desc_dma_addr); 1168 1169 ring->desc_dma_addr = 0; 1170 } 1171 1172 static int init_csq(struct hns_roce_dev *hr_dev, 1173 struct hns_roce_v2_cmq_ring *csq) 1174 { 1175 dma_addr_t dma; 1176 int ret; 1177 1178 csq->desc_num = CMD_CSQ_DESC_NUM; 1179 spin_lock_init(&csq->lock); 1180 csq->flag = TYPE_CSQ; 1181 csq->head = 0; 1182 1183 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1184 if (ret) 1185 return ret; 1186 1187 dma = csq->desc_dma_addr; 1188 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1189 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1190 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1191 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1192 1193 /* Make sure to write CI first and then PI */ 1194 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1195 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1196 1197 return 0; 1198 } 1199 1200 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1201 { 1202 struct hns_roce_v2_priv *priv = hr_dev->priv; 1203 int ret; 1204 1205 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1206 1207 ret = init_csq(hr_dev, &priv->cmq.csq); 1208 if (ret) 1209 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1210 1211 return ret; 1212 } 1213 1214 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1215 { 1216 struct hns_roce_v2_priv *priv = hr_dev->priv; 1217 1218 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1219 } 1220 1221 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1222 enum hns_roce_opcode_type opcode, 1223 bool is_read) 1224 { 1225 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1226 desc->opcode = cpu_to_le16(opcode); 1227 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1228 if (is_read) 1229 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1230 else 1231 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1232 } 1233 1234 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1235 { 1236 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1237 struct hns_roce_v2_priv *priv = hr_dev->priv; 1238 1239 return tail == priv->cmq.csq.head; 1240 } 1241 1242 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1243 { 1244 struct hns_roce_v2_priv *priv = hr_dev->priv; 1245 struct hnae3_handle *handle = priv->handle; 1246 1247 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1248 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1249 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1250 } 1251 1252 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1253 { 1254 struct hns_roce_cmd_errcode errcode_table[] = { 1255 {CMD_EXEC_SUCCESS, 0}, 1256 {CMD_NO_AUTH, -EPERM}, 1257 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1258 {CMD_CRQ_FULL, -EXFULL}, 1259 {CMD_NEXT_ERR, -ENOSR}, 1260 {CMD_NOT_EXEC, -ENOTBLK}, 1261 {CMD_PARA_ERR, -EINVAL}, 1262 {CMD_RESULT_ERR, -ERANGE}, 1263 {CMD_TIMEOUT, -ETIME}, 1264 {CMD_HILINK_ERR, -ENOLINK}, 1265 {CMD_INFO_ILLEGAL, -ENXIO}, 1266 {CMD_INVALID, -EBADR}, 1267 }; 1268 u16 i; 1269 1270 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1271 if (desc_ret == errcode_table[i].return_status) 1272 return errcode_table[i].errno; 1273 return -EIO; 1274 } 1275 1276 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1277 struct hns_roce_cmq_desc *desc, int num) 1278 { 1279 struct hns_roce_v2_priv *priv = hr_dev->priv; 1280 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1281 u32 timeout = 0; 1282 u16 desc_ret; 1283 u32 tail; 1284 int ret; 1285 int i; 1286 1287 spin_lock_bh(&csq->lock); 1288 1289 tail = csq->head; 1290 1291 for (i = 0; i < num; i++) { 1292 csq->desc[csq->head++] = desc[i]; 1293 if (csq->head == csq->desc_num) 1294 csq->head = 0; 1295 } 1296 1297 /* Write to hardware */ 1298 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1299 1300 do { 1301 if (hns_roce_cmq_csq_done(hr_dev)) 1302 break; 1303 udelay(1); 1304 } while (++timeout < priv->cmq.tx_timeout); 1305 1306 if (hns_roce_cmq_csq_done(hr_dev)) { 1307 ret = 0; 1308 for (i = 0; i < num; i++) { 1309 /* check the result of hardware write back */ 1310 desc[i] = csq->desc[tail++]; 1311 if (tail == csq->desc_num) 1312 tail = 0; 1313 1314 desc_ret = le16_to_cpu(desc[i].retval); 1315 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1316 continue; 1317 1318 dev_err_ratelimited(hr_dev->dev, 1319 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1320 desc->opcode, desc_ret); 1321 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1322 } 1323 } else { 1324 /* FW/HW reset or incorrect number of desc */ 1325 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1326 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1327 csq->head, tail); 1328 csq->head = tail; 1329 1330 update_cmdq_status(hr_dev); 1331 1332 ret = -EAGAIN; 1333 } 1334 1335 spin_unlock_bh(&csq->lock); 1336 1337 return ret; 1338 } 1339 1340 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1341 struct hns_roce_cmq_desc *desc, int num) 1342 { 1343 bool busy; 1344 int ret; 1345 1346 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1347 return -EIO; 1348 1349 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1350 return busy ? -EBUSY : 0; 1351 1352 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1353 if (ret) { 1354 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1355 return busy ? -EBUSY : 0; 1356 } 1357 1358 return ret; 1359 } 1360 1361 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1362 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1363 { 1364 struct hns_roce_cmd_mailbox *mbox; 1365 int ret; 1366 1367 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1368 if (IS_ERR(mbox)) 1369 return PTR_ERR(mbox); 1370 1371 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1372 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1373 return ret; 1374 } 1375 1376 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1377 { 1378 struct hns_roce_query_version *resp; 1379 struct hns_roce_cmq_desc desc; 1380 int ret; 1381 1382 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1383 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1384 if (ret) 1385 return ret; 1386 1387 resp = (struct hns_roce_query_version *)desc.data; 1388 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1389 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1390 1391 return 0; 1392 } 1393 1394 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1395 struct hnae3_handle *handle) 1396 { 1397 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1398 unsigned long end; 1399 1400 hr_dev->dis_db = true; 1401 1402 dev_warn(hr_dev->dev, 1403 "func clear is pending, device in resetting state.\n"); 1404 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1405 while (end) { 1406 if (!ops->get_hw_reset_stat(handle)) { 1407 hr_dev->is_reset = true; 1408 dev_info(hr_dev->dev, 1409 "func clear success after reset.\n"); 1410 return; 1411 } 1412 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1413 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1414 } 1415 1416 dev_warn(hr_dev->dev, "func clear failed.\n"); 1417 } 1418 1419 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1420 struct hnae3_handle *handle) 1421 { 1422 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1423 unsigned long end; 1424 1425 hr_dev->dis_db = true; 1426 1427 dev_warn(hr_dev->dev, 1428 "func clear is pending, device in resetting state.\n"); 1429 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1430 while (end) { 1431 if (ops->ae_dev_reset_cnt(handle) != 1432 hr_dev->reset_cnt) { 1433 hr_dev->is_reset = true; 1434 dev_info(hr_dev->dev, 1435 "func clear success after sw reset\n"); 1436 return; 1437 } 1438 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1439 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1440 } 1441 1442 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1443 } 1444 1445 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1446 int flag) 1447 { 1448 struct hns_roce_v2_priv *priv = hr_dev->priv; 1449 struct hnae3_handle *handle = priv->handle; 1450 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1451 1452 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1453 hr_dev->dis_db = true; 1454 hr_dev->is_reset = true; 1455 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1456 return; 1457 } 1458 1459 if (ops->get_hw_reset_stat(handle)) { 1460 func_clr_hw_resetting_state(hr_dev, handle); 1461 return; 1462 } 1463 1464 if (ops->ae_dev_resetting(handle) && 1465 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1466 func_clr_sw_resetting_state(hr_dev, handle); 1467 return; 1468 } 1469 1470 if (retval && !flag) 1471 dev_warn(hr_dev->dev, 1472 "func clear read failed, ret = %d.\n", retval); 1473 1474 dev_warn(hr_dev->dev, "func clear failed.\n"); 1475 } 1476 1477 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1478 { 1479 bool fclr_write_fail_flag = false; 1480 struct hns_roce_func_clear *resp; 1481 struct hns_roce_cmq_desc desc; 1482 unsigned long end; 1483 int ret = 0; 1484 1485 if (check_device_is_in_reset(hr_dev)) 1486 goto out; 1487 1488 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1489 resp = (struct hns_roce_func_clear *)desc.data; 1490 resp->rst_funcid_en = cpu_to_le32(vf_id); 1491 1492 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1493 if (ret) { 1494 fclr_write_fail_flag = true; 1495 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1496 ret); 1497 goto out; 1498 } 1499 1500 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1501 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1502 while (end) { 1503 if (check_device_is_in_reset(hr_dev)) 1504 goto out; 1505 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1506 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1507 1508 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1509 true); 1510 1511 resp->rst_funcid_en = cpu_to_le32(vf_id); 1512 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1513 if (ret) 1514 continue; 1515 1516 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1517 if (vf_id == 0) 1518 hr_dev->is_reset = true; 1519 return; 1520 } 1521 } 1522 1523 out: 1524 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1525 } 1526 1527 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1528 { 1529 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1530 struct hns_roce_cmq_desc desc[2]; 1531 struct hns_roce_cmq_req *req_a; 1532 1533 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1534 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1535 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1536 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1537 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1538 1539 return hns_roce_cmq_send(hr_dev, desc, 2); 1540 } 1541 1542 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1543 { 1544 int ret; 1545 int i; 1546 1547 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1548 return; 1549 1550 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1551 __hns_roce_function_clear(hr_dev, i); 1552 1553 if (i == 0) 1554 continue; 1555 1556 ret = hns_roce_free_vf_resource(hr_dev, i); 1557 if (ret) 1558 ibdev_err(&hr_dev->ib_dev, 1559 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1560 i, ret); 1561 } 1562 } 1563 1564 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1565 { 1566 struct hns_roce_cmq_desc desc; 1567 int ret; 1568 1569 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1570 false); 1571 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1572 if (ret) 1573 ibdev_err(&hr_dev->ib_dev, 1574 "failed to clear extended doorbell info, ret = %d.\n", 1575 ret); 1576 1577 return ret; 1578 } 1579 1580 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1581 { 1582 struct hns_roce_query_fw_info *resp; 1583 struct hns_roce_cmq_desc desc; 1584 int ret; 1585 1586 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1587 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1588 if (ret) 1589 return ret; 1590 1591 resp = (struct hns_roce_query_fw_info *)desc.data; 1592 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1593 1594 return 0; 1595 } 1596 1597 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1598 { 1599 struct hns_roce_cmq_desc desc; 1600 int ret; 1601 1602 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1603 hr_dev->func_num = 1; 1604 return 0; 1605 } 1606 1607 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1608 true); 1609 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1610 if (ret) { 1611 hr_dev->func_num = 1; 1612 return ret; 1613 } 1614 1615 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1616 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1617 1618 return 0; 1619 } 1620 1621 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1622 u64 *stats, u32 port, int *num_counters) 1623 { 1624 #define CNT_PER_DESC 3 1625 struct hns_roce_cmq_desc *desc; 1626 int bd_idx, cnt_idx; 1627 __le64 *cnt_data; 1628 int desc_num; 1629 int ret; 1630 int i; 1631 1632 if (port > hr_dev->caps.num_ports) 1633 return -EINVAL; 1634 1635 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1636 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1637 if (!desc) 1638 return -ENOMEM; 1639 1640 for (i = 0; i < desc_num; i++) { 1641 hns_roce_cmq_setup_basic_desc(&desc[i], 1642 HNS_ROCE_OPC_QUERY_COUNTER, true); 1643 if (i != desc_num - 1) 1644 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1645 } 1646 1647 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1648 if (ret) { 1649 ibdev_err(&hr_dev->ib_dev, 1650 "failed to get counter, ret = %d.\n", ret); 1651 goto err_out; 1652 } 1653 1654 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1655 bd_idx = i / CNT_PER_DESC; 1656 if (!(desc[bd_idx].flag & HNS_ROCE_CMD_FLAG_NEXT) && 1657 bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC) 1658 break; 1659 1660 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1661 cnt_idx = i % CNT_PER_DESC; 1662 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1663 } 1664 *num_counters = i; 1665 1666 err_out: 1667 kfree(desc); 1668 return ret; 1669 } 1670 1671 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1672 { 1673 struct hns_roce_cmq_desc desc; 1674 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1675 u32 clock_cycles_of_1us; 1676 1677 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1678 false); 1679 1680 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1681 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1682 else 1683 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1684 1685 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1686 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1687 1688 return hns_roce_cmq_send(hr_dev, &desc, 1); 1689 } 1690 1691 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1692 { 1693 struct hns_roce_cmq_desc desc[2]; 1694 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1695 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1696 struct hns_roce_caps *caps = &hr_dev->caps; 1697 enum hns_roce_opcode_type opcode; 1698 u32 func_num; 1699 int ret; 1700 1701 if (is_vf) { 1702 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1703 func_num = 1; 1704 } else { 1705 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1706 func_num = hr_dev->func_num; 1707 } 1708 1709 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1710 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1711 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1712 1713 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1714 if (ret) 1715 return ret; 1716 1717 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1718 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1719 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1720 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1721 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1722 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1723 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1724 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1725 1726 if (is_vf) { 1727 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1728 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1729 func_num; 1730 } else { 1731 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1732 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1733 func_num; 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1740 { 1741 struct hns_roce_cmq_desc desc; 1742 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1743 struct hns_roce_caps *caps = &hr_dev->caps; 1744 int ret; 1745 1746 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1747 true); 1748 1749 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1750 if (ret) 1751 return ret; 1752 1753 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1754 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1755 1756 return 0; 1757 } 1758 1759 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1760 { 1761 struct device *dev = hr_dev->dev; 1762 int ret; 1763 1764 ret = load_func_res_caps(hr_dev, false); 1765 if (ret) { 1766 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1767 return ret; 1768 } 1769 1770 ret = load_pf_timer_res_caps(hr_dev); 1771 if (ret) 1772 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1773 ret); 1774 1775 return ret; 1776 } 1777 1778 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1779 { 1780 struct device *dev = hr_dev->dev; 1781 int ret; 1782 1783 ret = load_func_res_caps(hr_dev, true); 1784 if (ret) 1785 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1786 1787 return ret; 1788 } 1789 1790 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1791 u32 vf_id) 1792 { 1793 struct hns_roce_vf_switch *swt; 1794 struct hns_roce_cmq_desc desc; 1795 int ret; 1796 1797 swt = (struct hns_roce_vf_switch *)desc.data; 1798 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1799 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1800 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1801 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1802 if (ret) 1803 return ret; 1804 1805 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1806 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1807 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1808 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1809 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1810 1811 return hns_roce_cmq_send(hr_dev, &desc, 1); 1812 } 1813 1814 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1815 { 1816 u32 vf_id; 1817 int ret; 1818 1819 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1820 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1821 if (ret) 1822 return ret; 1823 } 1824 return 0; 1825 } 1826 1827 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1828 { 1829 struct hns_roce_cmq_desc desc[2]; 1830 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1831 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1832 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1833 struct hns_roce_caps *caps = &hr_dev->caps; 1834 1835 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1836 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1837 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1838 1839 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1840 1841 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1842 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1843 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1844 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1845 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1846 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1847 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1848 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1849 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1850 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1851 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1852 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1853 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1854 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1855 1856 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1857 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1858 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1859 vf_id * caps->gmv_bt_num); 1860 } else { 1861 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1862 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1863 vf_id * caps->sgid_bt_num); 1864 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1865 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1866 vf_id * caps->smac_bt_num); 1867 } 1868 1869 return hns_roce_cmq_send(hr_dev, desc, 2); 1870 } 1871 1872 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1873 { 1874 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1875 u32 vf_id; 1876 int ret; 1877 1878 for (vf_id = 0; vf_id < func_num; vf_id++) { 1879 ret = config_vf_hem_resource(hr_dev, vf_id); 1880 if (ret) { 1881 dev_err(hr_dev->dev, 1882 "failed to config vf-%u hem res, ret = %d.\n", 1883 vf_id, ret); 1884 return ret; 1885 } 1886 } 1887 1888 return 0; 1889 } 1890 1891 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1892 { 1893 struct hns_roce_cmq_desc desc; 1894 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1895 struct hns_roce_caps *caps = &hr_dev->caps; 1896 1897 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1898 1899 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1900 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1901 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1902 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1903 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1904 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1905 1906 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1907 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1908 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1909 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1910 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1911 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1912 1913 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1914 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1915 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1916 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1917 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1918 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1919 1920 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1921 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1922 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1923 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1924 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1925 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1926 1927 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1928 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1929 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1930 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1931 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1932 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1933 1934 return hns_roce_cmq_send(hr_dev, &desc, 1); 1935 } 1936 1937 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1938 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1939 { 1940 u64 obj_per_chunk; 1941 u64 bt_chunk_size = PAGE_SIZE; 1942 u64 buf_chunk_size = PAGE_SIZE; 1943 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1944 1945 *buf_page_size = 0; 1946 *bt_page_size = 0; 1947 1948 switch (hop_num) { 1949 case 3: 1950 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1951 (bt_chunk_size / BA_BYTE_LEN) * 1952 (bt_chunk_size / BA_BYTE_LEN) * 1953 obj_per_chunk_default; 1954 break; 1955 case 2: 1956 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1957 (bt_chunk_size / BA_BYTE_LEN) * 1958 obj_per_chunk_default; 1959 break; 1960 case 1: 1961 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1962 obj_per_chunk_default; 1963 break; 1964 case HNS_ROCE_HOP_NUM_0: 1965 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1966 break; 1967 default: 1968 pr_err("table %u not support hop_num = %u!\n", hem_type, 1969 hop_num); 1970 return; 1971 } 1972 1973 if (hem_type >= HEM_TYPE_MTT) 1974 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1975 else 1976 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1977 } 1978 1979 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 1980 { 1981 struct hns_roce_caps *caps = &hr_dev->caps; 1982 1983 /* EQ */ 1984 caps->eqe_ba_pg_sz = 0; 1985 caps->eqe_buf_pg_sz = 0; 1986 1987 /* Link Table */ 1988 caps->llm_buf_pg_sz = 0; 1989 1990 /* MR */ 1991 caps->mpt_ba_pg_sz = 0; 1992 caps->mpt_buf_pg_sz = 0; 1993 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 1994 caps->pbl_buf_pg_sz = 0; 1995 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 1996 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 1997 HEM_TYPE_MTPT); 1998 1999 /* QP */ 2000 caps->qpc_ba_pg_sz = 0; 2001 caps->qpc_buf_pg_sz = 0; 2002 caps->qpc_timer_ba_pg_sz = 0; 2003 caps->qpc_timer_buf_pg_sz = 0; 2004 caps->sccc_ba_pg_sz = 0; 2005 caps->sccc_buf_pg_sz = 0; 2006 caps->mtt_ba_pg_sz = 0; 2007 caps->mtt_buf_pg_sz = 0; 2008 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2009 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2010 HEM_TYPE_QPC); 2011 2012 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2013 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2014 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2015 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2016 2017 /* CQ */ 2018 caps->cqc_ba_pg_sz = 0; 2019 caps->cqc_buf_pg_sz = 0; 2020 caps->cqc_timer_ba_pg_sz = 0; 2021 caps->cqc_timer_buf_pg_sz = 0; 2022 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2023 caps->cqe_buf_pg_sz = 0; 2024 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2025 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2026 HEM_TYPE_CQC); 2027 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2028 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2029 2030 /* SRQ */ 2031 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2032 caps->srqc_ba_pg_sz = 0; 2033 caps->srqc_buf_pg_sz = 0; 2034 caps->srqwqe_ba_pg_sz = 0; 2035 caps->srqwqe_buf_pg_sz = 0; 2036 caps->idx_ba_pg_sz = 0; 2037 caps->idx_buf_pg_sz = 0; 2038 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2039 caps->srqc_hop_num, caps->srqc_bt_num, 2040 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2041 HEM_TYPE_SRQC); 2042 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2043 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2044 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2045 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2046 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2047 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2048 } 2049 2050 /* GMV */ 2051 caps->gmv_ba_pg_sz = 0; 2052 caps->gmv_buf_pg_sz = 0; 2053 } 2054 2055 /* Apply all loaded caps before setting to hardware */ 2056 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2057 { 2058 struct hns_roce_caps *caps = &hr_dev->caps; 2059 struct hns_roce_v2_priv *priv = hr_dev->priv; 2060 2061 /* The following configurations don't need to be got from firmware. */ 2062 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2063 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2064 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2065 2066 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2067 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2068 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2069 2070 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2071 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2072 2073 if (!caps->num_comp_vectors) 2074 caps->num_comp_vectors = 2075 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2076 (u32)priv->handle->rinfo.num_vectors - 2077 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2078 2079 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2080 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2081 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2082 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2083 2084 /* The following configurations will be overwritten */ 2085 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2086 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2087 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2088 2089 /* The following configurations are not got from firmware */ 2090 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2091 2092 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2093 caps->gid_table_len[0] = caps->gmv_bt_num * 2094 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2095 2096 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2097 caps->gmv_entry_sz); 2098 } else { 2099 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2100 2101 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2102 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2103 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2104 caps->gid_table_len[0] /= func_num; 2105 } 2106 2107 if (hr_dev->is_vf) { 2108 caps->default_aeq_arm_st = 0x3; 2109 caps->default_ceq_arm_st = 0x3; 2110 caps->default_ceq_max_cnt = 0x1; 2111 caps->default_ceq_period = 0x10; 2112 caps->default_aeq_max_cnt = 0x1; 2113 caps->default_aeq_period = 0x10; 2114 } 2115 2116 set_hem_page_size(hr_dev); 2117 } 2118 2119 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2120 { 2121 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2122 struct hns_roce_caps *caps = &hr_dev->caps; 2123 struct hns_roce_query_pf_caps_a *resp_a; 2124 struct hns_roce_query_pf_caps_b *resp_b; 2125 struct hns_roce_query_pf_caps_c *resp_c; 2126 struct hns_roce_query_pf_caps_d *resp_d; 2127 struct hns_roce_query_pf_caps_e *resp_e; 2128 enum hns_roce_opcode_type cmd; 2129 int ctx_hop_num; 2130 int pbl_hop_num; 2131 int ret; 2132 int i; 2133 2134 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2135 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2136 2137 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2138 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2139 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2140 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2141 else 2142 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2143 } 2144 2145 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2146 if (ret) 2147 return ret; 2148 2149 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2150 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2151 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2152 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2153 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2154 2155 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2156 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2157 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2158 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2159 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2160 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2161 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2162 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2163 caps->num_other_vectors = resp_a->num_other_vectors; 2164 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2165 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2166 2167 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2168 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2169 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2170 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2171 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2172 caps->idx_entry_sz = resp_b->idx_entry_sz; 2173 caps->sccc_sz = resp_b->sccc_sz; 2174 caps->max_mtu = resp_b->max_mtu; 2175 caps->min_cqes = resp_b->min_cqes; 2176 caps->min_wqes = resp_b->min_wqes; 2177 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2178 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2179 caps->phy_num_uars = resp_b->phy_num_uars; 2180 ctx_hop_num = resp_b->ctx_hop_num; 2181 pbl_hop_num = resp_b->pbl_hop_num; 2182 2183 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2184 2185 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2186 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2187 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2188 2189 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2190 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2191 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2192 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2193 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2194 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2195 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2196 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2197 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2198 2199 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2200 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2201 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2202 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2203 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2204 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2205 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2206 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2207 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2208 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2209 2210 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2211 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2212 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2213 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2214 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2215 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2216 2217 caps->qpc_hop_num = ctx_hop_num; 2218 caps->sccc_hop_num = ctx_hop_num; 2219 caps->srqc_hop_num = ctx_hop_num; 2220 caps->cqc_hop_num = ctx_hop_num; 2221 caps->mpt_hop_num = ctx_hop_num; 2222 caps->mtt_hop_num = pbl_hop_num; 2223 caps->cqe_hop_num = pbl_hop_num; 2224 caps->srqwqe_hop_num = pbl_hop_num; 2225 caps->idx_hop_num = pbl_hop_num; 2226 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2227 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2228 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2229 2230 if (!(caps->page_size_cap & PAGE_SIZE)) 2231 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2232 2233 if (!hr_dev->is_vf) { 2234 caps->cqe_sz = resp_a->cqe_sz; 2235 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2236 caps->default_aeq_arm_st = 2237 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2238 caps->default_ceq_arm_st = 2239 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2240 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2241 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2242 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2243 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2244 } 2245 2246 return 0; 2247 } 2248 2249 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2250 { 2251 struct hns_roce_cmq_desc desc; 2252 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2253 2254 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2255 false); 2256 2257 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2258 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2259 2260 return hns_roce_cmq_send(hr_dev, &desc, 1); 2261 } 2262 2263 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2264 { 2265 struct hns_roce_caps *caps = &hr_dev->caps; 2266 int ret; 2267 2268 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2269 return 0; 2270 2271 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2272 caps->qpc_sz); 2273 if (ret) { 2274 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2275 return ret; 2276 } 2277 2278 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2279 caps->sccc_sz); 2280 if (ret) 2281 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2282 2283 return ret; 2284 } 2285 2286 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2287 { 2288 struct device *dev = hr_dev->dev; 2289 int ret; 2290 2291 hr_dev->func_num = 1; 2292 2293 ret = hns_roce_query_caps(hr_dev); 2294 if (ret) { 2295 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2296 return ret; 2297 } 2298 2299 ret = hns_roce_query_vf_resource(hr_dev); 2300 if (ret) { 2301 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2302 return ret; 2303 } 2304 2305 apply_func_caps(hr_dev); 2306 2307 ret = hns_roce_v2_set_bt(hr_dev); 2308 if (ret) 2309 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2310 2311 return ret; 2312 } 2313 2314 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2315 { 2316 struct device *dev = hr_dev->dev; 2317 int ret; 2318 2319 ret = hns_roce_query_func_info(hr_dev); 2320 if (ret) { 2321 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2322 return ret; 2323 } 2324 2325 ret = hns_roce_config_global_param(hr_dev); 2326 if (ret) { 2327 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2328 return ret; 2329 } 2330 2331 ret = hns_roce_set_vf_switch_param(hr_dev); 2332 if (ret) { 2333 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2334 return ret; 2335 } 2336 2337 ret = hns_roce_query_caps(hr_dev); 2338 if (ret) { 2339 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2340 return ret; 2341 } 2342 2343 ret = hns_roce_query_pf_resource(hr_dev); 2344 if (ret) { 2345 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2346 return ret; 2347 } 2348 2349 apply_func_caps(hr_dev); 2350 2351 ret = hns_roce_alloc_vf_resource(hr_dev); 2352 if (ret) { 2353 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2354 return ret; 2355 } 2356 2357 ret = hns_roce_v2_set_bt(hr_dev); 2358 if (ret) { 2359 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2360 return ret; 2361 } 2362 2363 /* Configure the size of QPC, SCCC, etc. */ 2364 return hns_roce_config_entry_size(hr_dev); 2365 } 2366 2367 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2368 { 2369 struct device *dev = hr_dev->dev; 2370 int ret; 2371 2372 ret = hns_roce_cmq_query_hw_info(hr_dev); 2373 if (ret) { 2374 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2375 return ret; 2376 } 2377 2378 ret = hns_roce_query_fw_ver(hr_dev); 2379 if (ret) { 2380 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2381 return ret; 2382 } 2383 2384 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2385 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2386 2387 if (hr_dev->is_vf) 2388 return hns_roce_v2_vf_profile(hr_dev); 2389 else 2390 return hns_roce_v2_pf_profile(hr_dev); 2391 } 2392 2393 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2394 { 2395 u32 i, next_ptr, page_num; 2396 __le64 *entry = cfg_buf; 2397 dma_addr_t addr; 2398 u64 val; 2399 2400 page_num = data_buf->npages; 2401 for (i = 0; i < page_num; i++) { 2402 addr = hns_roce_buf_page(data_buf, i); 2403 if (i == (page_num - 1)) 2404 next_ptr = 0; 2405 else 2406 next_ptr = i + 1; 2407 2408 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2409 entry[i] = cpu_to_le64(val); 2410 } 2411 } 2412 2413 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2414 struct hns_roce_link_table *table) 2415 { 2416 struct hns_roce_cmq_desc desc[2]; 2417 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2418 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2419 struct hns_roce_buf *buf = table->buf; 2420 enum hns_roce_opcode_type opcode; 2421 dma_addr_t addr; 2422 2423 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2424 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2425 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2426 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2427 2428 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2429 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2430 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2431 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2432 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2433 2434 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2435 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2436 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2437 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2438 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2439 2440 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2441 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2442 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2443 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2444 2445 return hns_roce_cmq_send(hr_dev, desc, 2); 2446 } 2447 2448 static struct hns_roce_link_table * 2449 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2450 { 2451 struct hns_roce_v2_priv *priv = hr_dev->priv; 2452 struct hns_roce_link_table *link_tbl; 2453 u32 pg_shift, size, min_size; 2454 2455 link_tbl = &priv->ext_llm; 2456 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2457 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2458 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2459 2460 /* Alloc data table */ 2461 size = max(size, min_size); 2462 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2463 if (IS_ERR(link_tbl->buf)) 2464 return ERR_PTR(-ENOMEM); 2465 2466 /* Alloc config table */ 2467 size = link_tbl->buf->npages * sizeof(u64); 2468 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2469 &link_tbl->table.map, 2470 GFP_KERNEL); 2471 if (!link_tbl->table.buf) { 2472 hns_roce_buf_free(hr_dev, link_tbl->buf); 2473 return ERR_PTR(-ENOMEM); 2474 } 2475 2476 return link_tbl; 2477 } 2478 2479 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2480 struct hns_roce_link_table *tbl) 2481 { 2482 if (tbl->buf) { 2483 u32 size = tbl->buf->npages * sizeof(u64); 2484 2485 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2486 tbl->table.map); 2487 } 2488 2489 hns_roce_buf_free(hr_dev, tbl->buf); 2490 } 2491 2492 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2493 { 2494 struct hns_roce_link_table *link_tbl; 2495 int ret; 2496 2497 link_tbl = alloc_link_table_buf(hr_dev); 2498 if (IS_ERR(link_tbl)) 2499 return -ENOMEM; 2500 2501 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2502 ret = -EINVAL; 2503 goto err_alloc; 2504 } 2505 2506 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2507 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2508 if (ret) 2509 goto err_alloc; 2510 2511 return 0; 2512 2513 err_alloc: 2514 free_link_table_buf(hr_dev, link_tbl); 2515 return ret; 2516 } 2517 2518 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2519 { 2520 struct hns_roce_v2_priv *priv = hr_dev->priv; 2521 2522 free_link_table_buf(hr_dev, &priv->ext_llm); 2523 } 2524 2525 static void free_dip_list(struct hns_roce_dev *hr_dev) 2526 { 2527 struct hns_roce_dip *hr_dip; 2528 struct hns_roce_dip *tmp; 2529 unsigned long flags; 2530 2531 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2532 2533 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2534 list_del(&hr_dip->node); 2535 kfree(hr_dip); 2536 } 2537 2538 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2539 } 2540 2541 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2542 { 2543 struct hns_roce_v2_priv *priv = hr_dev->priv; 2544 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2545 struct ib_device *ibdev = &hr_dev->ib_dev; 2546 struct hns_roce_pd *hr_pd; 2547 struct ib_pd *pd; 2548 2549 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2550 if (ZERO_OR_NULL_PTR(hr_pd)) 2551 return NULL; 2552 pd = &hr_pd->ibpd; 2553 pd->device = ibdev; 2554 2555 if (hns_roce_alloc_pd(pd, NULL)) { 2556 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2557 kfree(hr_pd); 2558 return NULL; 2559 } 2560 free_mr->rsv_pd = to_hr_pd(pd); 2561 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2562 free_mr->rsv_pd->ibpd.uobject = NULL; 2563 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2564 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2565 2566 return pd; 2567 } 2568 2569 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2570 { 2571 struct hns_roce_v2_priv *priv = hr_dev->priv; 2572 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2573 struct ib_device *ibdev = &hr_dev->ib_dev; 2574 struct ib_cq_init_attr cq_init_attr = {}; 2575 struct hns_roce_cq *hr_cq; 2576 struct ib_cq *cq; 2577 2578 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2579 2580 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2581 if (ZERO_OR_NULL_PTR(hr_cq)) 2582 return NULL; 2583 2584 cq = &hr_cq->ib_cq; 2585 cq->device = ibdev; 2586 2587 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2588 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2589 kfree(hr_cq); 2590 return NULL; 2591 } 2592 free_mr->rsv_cq = to_hr_cq(cq); 2593 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2594 free_mr->rsv_cq->ib_cq.uobject = NULL; 2595 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2596 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2597 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2598 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2599 2600 return cq; 2601 } 2602 2603 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2604 struct ib_qp_init_attr *init_attr, int i) 2605 { 2606 struct hns_roce_v2_priv *priv = hr_dev->priv; 2607 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2608 struct ib_device *ibdev = &hr_dev->ib_dev; 2609 struct hns_roce_qp *hr_qp; 2610 struct ib_qp *qp; 2611 int ret; 2612 2613 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2614 if (ZERO_OR_NULL_PTR(hr_qp)) 2615 return -ENOMEM; 2616 2617 qp = &hr_qp->ibqp; 2618 qp->device = ibdev; 2619 2620 ret = hns_roce_create_qp(qp, init_attr, NULL); 2621 if (ret) { 2622 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2623 kfree(hr_qp); 2624 return ret; 2625 } 2626 2627 free_mr->rsv_qp[i] = hr_qp; 2628 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2629 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2630 2631 return 0; 2632 } 2633 2634 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2635 { 2636 struct hns_roce_v2_priv *priv = hr_dev->priv; 2637 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2638 struct ib_qp *qp; 2639 int i; 2640 2641 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2642 if (free_mr->rsv_qp[i]) { 2643 qp = &free_mr->rsv_qp[i]->ibqp; 2644 hns_roce_v2_destroy_qp(qp, NULL); 2645 kfree(free_mr->rsv_qp[i]); 2646 free_mr->rsv_qp[i] = NULL; 2647 } 2648 } 2649 2650 if (free_mr->rsv_cq) { 2651 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2652 kfree(free_mr->rsv_cq); 2653 free_mr->rsv_cq = NULL; 2654 } 2655 2656 if (free_mr->rsv_pd) { 2657 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2658 kfree(free_mr->rsv_pd); 2659 free_mr->rsv_pd = NULL; 2660 } 2661 } 2662 2663 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2664 { 2665 struct hns_roce_v2_priv *priv = hr_dev->priv; 2666 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2667 struct ib_qp_init_attr qp_init_attr = {}; 2668 struct ib_pd *pd; 2669 struct ib_cq *cq; 2670 int ret; 2671 int i; 2672 2673 pd = free_mr_init_pd(hr_dev); 2674 if (!pd) 2675 return -ENOMEM; 2676 2677 cq = free_mr_init_cq(hr_dev); 2678 if (!cq) { 2679 ret = -ENOMEM; 2680 goto create_failed_cq; 2681 } 2682 2683 qp_init_attr.qp_type = IB_QPT_RC; 2684 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2685 qp_init_attr.send_cq = cq; 2686 qp_init_attr.recv_cq = cq; 2687 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2688 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2689 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2690 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2691 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2692 2693 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2694 if (ret) 2695 goto create_failed_qp; 2696 } 2697 2698 return 0; 2699 2700 create_failed_qp: 2701 hns_roce_destroy_cq(cq, NULL); 2702 kfree(cq); 2703 2704 create_failed_cq: 2705 hns_roce_dealloc_pd(pd, NULL); 2706 kfree(pd); 2707 2708 return ret; 2709 } 2710 2711 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2712 struct ib_qp_attr *attr, int sl_num) 2713 { 2714 struct hns_roce_v2_priv *priv = hr_dev->priv; 2715 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2716 struct ib_device *ibdev = &hr_dev->ib_dev; 2717 struct hns_roce_qp *hr_qp; 2718 int loopback; 2719 int mask; 2720 int ret; 2721 2722 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2723 hr_qp->free_mr_en = 1; 2724 hr_qp->ibqp.device = ibdev; 2725 hr_qp->ibqp.qp_type = IB_QPT_RC; 2726 2727 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2728 attr->qp_state = IB_QPS_INIT; 2729 attr->port_num = 1; 2730 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2731 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2732 IB_QPS_INIT, NULL); 2733 if (ret) { 2734 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2735 ret); 2736 return ret; 2737 } 2738 2739 loopback = hr_dev->loop_idc; 2740 /* Set qpc lbi = 1 incidate loopback IO */ 2741 hr_dev->loop_idc = 1; 2742 2743 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2744 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2745 attr->qp_state = IB_QPS_RTR; 2746 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2747 attr->path_mtu = IB_MTU_256; 2748 attr->dest_qp_num = hr_qp->qpn; 2749 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2750 2751 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2752 2753 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2754 IB_QPS_RTR, NULL); 2755 hr_dev->loop_idc = loopback; 2756 if (ret) { 2757 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2758 ret); 2759 return ret; 2760 } 2761 2762 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2763 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2764 attr->qp_state = IB_QPS_RTS; 2765 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2766 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2767 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2768 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2769 IB_QPS_RTS, NULL); 2770 if (ret) 2771 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2772 ret); 2773 2774 return ret; 2775 } 2776 2777 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2778 { 2779 struct hns_roce_v2_priv *priv = hr_dev->priv; 2780 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2781 struct ib_qp_attr attr = {}; 2782 int ret; 2783 int i; 2784 2785 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2786 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2787 rdma_ah_set_port_num(&attr.ah_attr, 1); 2788 2789 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2790 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2791 if (ret) 2792 return ret; 2793 } 2794 2795 return 0; 2796 } 2797 2798 static int free_mr_init(struct hns_roce_dev *hr_dev) 2799 { 2800 struct hns_roce_v2_priv *priv = hr_dev->priv; 2801 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2802 int ret; 2803 2804 mutex_init(&free_mr->mutex); 2805 2806 ret = free_mr_alloc_res(hr_dev); 2807 if (ret) 2808 return ret; 2809 2810 ret = free_mr_modify_qp(hr_dev); 2811 if (ret) 2812 goto err_modify_qp; 2813 2814 return 0; 2815 2816 err_modify_qp: 2817 free_mr_exit(hr_dev); 2818 2819 return ret; 2820 } 2821 2822 static int get_hem_table(struct hns_roce_dev *hr_dev) 2823 { 2824 unsigned int qpc_count; 2825 unsigned int cqc_count; 2826 unsigned int gmv_count; 2827 int ret; 2828 int i; 2829 2830 /* Alloc memory for source address table buffer space chunk */ 2831 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2832 gmv_count++) { 2833 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2834 if (ret) 2835 goto err_gmv_failed; 2836 } 2837 2838 if (hr_dev->is_vf) 2839 return 0; 2840 2841 /* Alloc memory for QPC Timer buffer space chunk */ 2842 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2843 qpc_count++) { 2844 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2845 qpc_count); 2846 if (ret) { 2847 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2848 goto err_qpc_timer_failed; 2849 } 2850 } 2851 2852 /* Alloc memory for CQC Timer buffer space chunk */ 2853 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2854 cqc_count++) { 2855 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2856 cqc_count); 2857 if (ret) { 2858 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2859 goto err_cqc_timer_failed; 2860 } 2861 } 2862 2863 return 0; 2864 2865 err_cqc_timer_failed: 2866 for (i = 0; i < cqc_count; i++) 2867 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2868 2869 err_qpc_timer_failed: 2870 for (i = 0; i < qpc_count; i++) 2871 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2872 2873 err_gmv_failed: 2874 for (i = 0; i < gmv_count; i++) 2875 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2876 2877 return ret; 2878 } 2879 2880 static void put_hem_table(struct hns_roce_dev *hr_dev) 2881 { 2882 int i; 2883 2884 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2885 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2886 2887 if (hr_dev->is_vf) 2888 return; 2889 2890 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2891 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2892 2893 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2894 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2895 } 2896 2897 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2898 { 2899 int ret; 2900 2901 /* The hns ROCEE requires the extdb info to be cleared before using */ 2902 ret = hns_roce_clear_extdb_list_info(hr_dev); 2903 if (ret) 2904 return ret; 2905 2906 ret = get_hem_table(hr_dev); 2907 if (ret) 2908 return ret; 2909 2910 if (hr_dev->is_vf) 2911 return 0; 2912 2913 ret = hns_roce_init_link_table(hr_dev); 2914 if (ret) { 2915 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2916 goto err_llm_init_failed; 2917 } 2918 2919 return 0; 2920 2921 err_llm_init_failed: 2922 put_hem_table(hr_dev); 2923 2924 return ret; 2925 } 2926 2927 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2928 { 2929 hns_roce_function_clear(hr_dev); 2930 2931 if (!hr_dev->is_vf) 2932 hns_roce_free_link_table(hr_dev); 2933 2934 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2935 free_dip_list(hr_dev); 2936 } 2937 2938 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2939 struct hns_roce_mbox_msg *mbox_msg) 2940 { 2941 struct hns_roce_cmq_desc desc; 2942 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2943 2944 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2945 2946 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2947 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2948 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2949 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2950 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2951 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2952 mbox_msg->token); 2953 2954 return hns_roce_cmq_send(hr_dev, &desc, 1); 2955 } 2956 2957 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2958 u8 *complete_status) 2959 { 2960 struct hns_roce_mbox_status *mb_st; 2961 struct hns_roce_cmq_desc desc; 2962 unsigned long end; 2963 int ret = -EBUSY; 2964 u32 status; 2965 bool busy; 2966 2967 mb_st = (struct hns_roce_mbox_status *)desc.data; 2968 end = msecs_to_jiffies(timeout) + jiffies; 2969 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2970 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2971 return -EIO; 2972 2973 status = 0; 2974 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2975 true); 2976 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2977 if (!ret) { 2978 status = le32_to_cpu(mb_st->mb_status_hw_run); 2979 /* No pending message exists in ROCEE mbox. */ 2980 if (!(status & MB_ST_HW_RUN_M)) 2981 break; 2982 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2983 break; 2984 } 2985 2986 if (time_after(jiffies, end)) { 2987 dev_err_ratelimited(hr_dev->dev, 2988 "failed to wait mbox status 0x%x\n", 2989 status); 2990 return -ETIMEDOUT; 2991 } 2992 2993 cond_resched(); 2994 ret = -EBUSY; 2995 } 2996 2997 if (!ret) { 2998 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 2999 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3000 /* Ignore all errors if the mbox is unavailable. */ 3001 ret = 0; 3002 *complete_status = MB_ST_COMPLETE_M; 3003 } 3004 3005 return ret; 3006 } 3007 3008 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3009 struct hns_roce_mbox_msg *mbox_msg) 3010 { 3011 u8 status = 0; 3012 int ret; 3013 3014 /* Waiting for the mbox to be idle */ 3015 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3016 &status); 3017 if (unlikely(ret)) { 3018 dev_err_ratelimited(hr_dev->dev, 3019 "failed to check post mbox status = 0x%x, ret = %d.\n", 3020 status, ret); 3021 return ret; 3022 } 3023 3024 /* Post new message to mbox */ 3025 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3026 if (ret) 3027 dev_err_ratelimited(hr_dev->dev, 3028 "failed to post mailbox, ret = %d.\n", ret); 3029 3030 return ret; 3031 } 3032 3033 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3034 { 3035 u8 status = 0; 3036 int ret; 3037 3038 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3039 &status); 3040 if (!ret) { 3041 if (status != MB_ST_COMPLETE_SUCC) 3042 return -EBUSY; 3043 } else { 3044 dev_err_ratelimited(hr_dev->dev, 3045 "failed to check mbox status = 0x%x, ret = %d.\n", 3046 status, ret); 3047 } 3048 3049 return ret; 3050 } 3051 3052 static void copy_gid(void *dest, const union ib_gid *gid) 3053 { 3054 #define GID_SIZE 4 3055 const union ib_gid *src = gid; 3056 __le32 (*p)[GID_SIZE] = dest; 3057 int i; 3058 3059 if (!gid) 3060 src = &zgid; 3061 3062 for (i = 0; i < GID_SIZE; i++) 3063 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3064 } 3065 3066 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3067 int gid_index, const union ib_gid *gid, 3068 enum hns_roce_sgid_type sgid_type) 3069 { 3070 struct hns_roce_cmq_desc desc; 3071 struct hns_roce_cfg_sgid_tb *sgid_tb = 3072 (struct hns_roce_cfg_sgid_tb *)desc.data; 3073 3074 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3075 3076 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3077 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3078 3079 copy_gid(&sgid_tb->vf_sgid_l, gid); 3080 3081 return hns_roce_cmq_send(hr_dev, &desc, 1); 3082 } 3083 3084 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3085 int gid_index, const union ib_gid *gid, 3086 enum hns_roce_sgid_type sgid_type, 3087 const struct ib_gid_attr *attr) 3088 { 3089 struct hns_roce_cmq_desc desc[2]; 3090 struct hns_roce_cfg_gmv_tb_a *tb_a = 3091 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3092 struct hns_roce_cfg_gmv_tb_b *tb_b = 3093 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3094 3095 u16 vlan_id = VLAN_CFI_MASK; 3096 u8 mac[ETH_ALEN] = {}; 3097 int ret; 3098 3099 if (gid) { 3100 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3101 if (ret) 3102 return ret; 3103 } 3104 3105 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3106 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3107 3108 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3109 3110 copy_gid(&tb_a->vf_sgid_l, gid); 3111 3112 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3113 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3114 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3115 3116 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3117 3118 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3119 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3120 3121 return hns_roce_cmq_send(hr_dev, desc, 2); 3122 } 3123 3124 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3125 const union ib_gid *gid, 3126 const struct ib_gid_attr *attr) 3127 { 3128 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3129 int ret; 3130 3131 if (gid) { 3132 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3133 if (ipv6_addr_v4mapped((void *)gid)) 3134 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3135 else 3136 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3137 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3138 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3139 } 3140 } 3141 3142 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3143 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3144 else 3145 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3146 3147 if (ret) 3148 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3149 ret); 3150 3151 return ret; 3152 } 3153 3154 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3155 const u8 *addr) 3156 { 3157 struct hns_roce_cmq_desc desc; 3158 struct hns_roce_cfg_smac_tb *smac_tb = 3159 (struct hns_roce_cfg_smac_tb *)desc.data; 3160 u16 reg_smac_h; 3161 u32 reg_smac_l; 3162 3163 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3164 3165 reg_smac_l = *(u32 *)(&addr[0]); 3166 reg_smac_h = *(u16 *)(&addr[4]); 3167 3168 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3169 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3170 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3171 3172 return hns_roce_cmq_send(hr_dev, &desc, 1); 3173 } 3174 3175 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3176 struct hns_roce_v2_mpt_entry *mpt_entry, 3177 struct hns_roce_mr *mr) 3178 { 3179 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3180 struct ib_device *ibdev = &hr_dev->ib_dev; 3181 dma_addr_t pbl_ba; 3182 int i, count; 3183 3184 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3185 min_t(int, ARRAY_SIZE(pages), mr->npages), 3186 &pbl_ba); 3187 if (count < 1) { 3188 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3189 count); 3190 return -ENOBUFS; 3191 } 3192 3193 /* Aligned to the hardware address access unit */ 3194 for (i = 0; i < count; i++) 3195 pages[i] >>= 6; 3196 3197 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3198 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3199 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3200 3201 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3202 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3203 3204 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3205 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3206 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3207 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3208 3209 return 0; 3210 } 3211 3212 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3213 void *mb_buf, struct hns_roce_mr *mr) 3214 { 3215 struct hns_roce_v2_mpt_entry *mpt_entry; 3216 3217 mpt_entry = mb_buf; 3218 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3219 3220 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3221 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3222 3223 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3224 mr->access & IB_ACCESS_MW_BIND); 3225 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3226 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3227 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3228 mr->access & IB_ACCESS_REMOTE_READ); 3229 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3230 mr->access & IB_ACCESS_REMOTE_WRITE); 3231 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3232 mr->access & IB_ACCESS_LOCAL_WRITE); 3233 3234 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3235 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3236 mpt_entry->lkey = cpu_to_le32(mr->key); 3237 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3238 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3239 3240 if (mr->type != MR_TYPE_MR) 3241 hr_reg_enable(mpt_entry, MPT_PA); 3242 3243 if (mr->type == MR_TYPE_DMA) 3244 return 0; 3245 3246 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3247 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3248 3249 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3250 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3251 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3252 3253 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3254 } 3255 3256 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3257 struct hns_roce_mr *mr, int flags, 3258 void *mb_buf) 3259 { 3260 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3261 u32 mr_access_flags = mr->access; 3262 int ret = 0; 3263 3264 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3265 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3266 3267 if (flags & IB_MR_REREG_ACCESS) { 3268 hr_reg_write(mpt_entry, MPT_BIND_EN, 3269 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3270 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3271 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3272 hr_reg_write(mpt_entry, MPT_RR_EN, 3273 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3274 hr_reg_write(mpt_entry, MPT_RW_EN, 3275 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3276 hr_reg_write(mpt_entry, MPT_LW_EN, 3277 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3278 } 3279 3280 if (flags & IB_MR_REREG_TRANS) { 3281 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3282 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3283 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3284 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3285 3286 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3287 } 3288 3289 return ret; 3290 } 3291 3292 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3293 void *mb_buf, struct hns_roce_mr *mr) 3294 { 3295 struct ib_device *ibdev = &hr_dev->ib_dev; 3296 struct hns_roce_v2_mpt_entry *mpt_entry; 3297 dma_addr_t pbl_ba = 0; 3298 3299 mpt_entry = mb_buf; 3300 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3301 3302 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3303 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3304 return -ENOBUFS; 3305 } 3306 3307 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3308 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3309 3310 hr_reg_enable(mpt_entry, MPT_RA_EN); 3311 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3312 3313 hr_reg_enable(mpt_entry, MPT_FRE); 3314 hr_reg_clear(mpt_entry, MPT_MR_MW); 3315 hr_reg_enable(mpt_entry, MPT_BPD); 3316 hr_reg_clear(mpt_entry, MPT_PA); 3317 3318 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3319 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3320 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3321 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3322 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3323 3324 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3325 3326 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3327 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3328 3329 return 0; 3330 } 3331 3332 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3333 { 3334 struct hns_roce_v2_mpt_entry *mpt_entry; 3335 3336 mpt_entry = mb_buf; 3337 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3338 3339 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3340 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3341 3342 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3343 hr_reg_enable(mpt_entry, MPT_LW_EN); 3344 3345 hr_reg_enable(mpt_entry, MPT_MR_MW); 3346 hr_reg_enable(mpt_entry, MPT_BPD); 3347 hr_reg_clear(mpt_entry, MPT_PA); 3348 hr_reg_write(mpt_entry, MPT_BQP, 3349 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3350 3351 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3352 3353 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3354 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3355 mw->pbl_hop_num); 3356 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3357 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3358 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3359 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3360 3361 return 0; 3362 } 3363 3364 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3365 { 3366 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3367 struct ib_device *ibdev = &hr_dev->ib_dev; 3368 const struct ib_send_wr *bad_wr; 3369 struct ib_rdma_wr rdma_wr = {}; 3370 struct ib_send_wr *send_wr; 3371 int ret; 3372 3373 send_wr = &rdma_wr.wr; 3374 send_wr->opcode = IB_WR_RDMA_WRITE; 3375 3376 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3377 if (ret) { 3378 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3379 ret); 3380 return ret; 3381 } 3382 3383 return 0; 3384 } 3385 3386 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3387 struct ib_wc *wc); 3388 3389 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3390 { 3391 struct hns_roce_v2_priv *priv = hr_dev->priv; 3392 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3393 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3394 struct ib_device *ibdev = &hr_dev->ib_dev; 3395 struct hns_roce_qp *hr_qp; 3396 unsigned long end; 3397 int cqe_cnt = 0; 3398 int npolled; 3399 int ret; 3400 int i; 3401 3402 /* 3403 * If the device initialization is not complete or in the uninstall 3404 * process, then there is no need to execute free mr. 3405 */ 3406 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3407 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3408 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3409 return; 3410 3411 mutex_lock(&free_mr->mutex); 3412 3413 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3414 hr_qp = free_mr->rsv_qp[i]; 3415 3416 ret = free_mr_post_send_lp_wqe(hr_qp); 3417 if (ret) { 3418 ibdev_err(ibdev, 3419 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3420 hr_qp->qpn, ret); 3421 break; 3422 } 3423 3424 cqe_cnt++; 3425 } 3426 3427 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3428 while (cqe_cnt) { 3429 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3430 if (npolled < 0) { 3431 ibdev_err(ibdev, 3432 "failed to poll cqe for free mr, remain %d cqe.\n", 3433 cqe_cnt); 3434 goto out; 3435 } 3436 3437 if (time_after(jiffies, end)) { 3438 ibdev_err(ibdev, 3439 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3440 cqe_cnt); 3441 goto out; 3442 } 3443 cqe_cnt -= npolled; 3444 } 3445 3446 out: 3447 mutex_unlock(&free_mr->mutex); 3448 } 3449 3450 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3451 { 3452 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3453 free_mr_send_cmd_to_hw(hr_dev); 3454 } 3455 3456 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3457 { 3458 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3459 } 3460 3461 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3462 { 3463 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3464 3465 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3466 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3467 NULL; 3468 } 3469 3470 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3471 struct hns_roce_cq *hr_cq) 3472 { 3473 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3474 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3475 } else { 3476 struct hns_roce_v2_db cq_db = {}; 3477 3478 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3479 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3480 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3481 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3482 3483 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3484 } 3485 } 3486 3487 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3488 struct hns_roce_srq *srq) 3489 { 3490 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3491 struct hns_roce_v2_cqe *cqe, *dest; 3492 u32 prod_index; 3493 int nfreed = 0; 3494 int wqe_index; 3495 u8 owner_bit; 3496 3497 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3498 ++prod_index) { 3499 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3500 break; 3501 } 3502 3503 /* 3504 * Now backwards through the CQ, removing CQ entries 3505 * that match our QP by overwriting them with next entries. 3506 */ 3507 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3508 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3509 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3510 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3511 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3512 hns_roce_free_srq_wqe(srq, wqe_index); 3513 } 3514 ++nfreed; 3515 } else if (nfreed) { 3516 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3517 hr_cq->ib_cq.cqe); 3518 owner_bit = hr_reg_read(dest, CQE_OWNER); 3519 memcpy(dest, cqe, hr_cq->cqe_size); 3520 hr_reg_write(dest, CQE_OWNER, owner_bit); 3521 } 3522 } 3523 3524 if (nfreed) { 3525 hr_cq->cons_index += nfreed; 3526 update_cq_db(hr_dev, hr_cq); 3527 } 3528 } 3529 3530 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3531 struct hns_roce_srq *srq) 3532 { 3533 spin_lock_irq(&hr_cq->lock); 3534 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3535 spin_unlock_irq(&hr_cq->lock); 3536 } 3537 3538 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3539 struct hns_roce_cq *hr_cq, void *mb_buf, 3540 u64 *mtts, dma_addr_t dma_handle) 3541 { 3542 struct hns_roce_v2_cq_context *cq_context; 3543 3544 cq_context = mb_buf; 3545 memset(cq_context, 0, sizeof(*cq_context)); 3546 3547 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3548 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3549 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3550 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3551 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3552 3553 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3554 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3555 3556 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3557 hr_reg_enable(cq_context, CQC_STASH); 3558 3559 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3560 to_hr_hw_page_addr(mtts[0])); 3561 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3562 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3563 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3564 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3565 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3566 to_hr_hw_page_addr(mtts[1])); 3567 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3568 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3569 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3570 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3571 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3572 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3573 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3574 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3575 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3576 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3577 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3578 ((u32)hr_cq->db.dma) >> 1); 3579 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3580 hr_cq->db.dma >> 32); 3581 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3582 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3583 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3584 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3585 } 3586 3587 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3588 enum ib_cq_notify_flags flags) 3589 { 3590 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3591 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3592 struct hns_roce_v2_db cq_db = {}; 3593 u32 notify_flag; 3594 3595 /* 3596 * flags = 0, then notify_flag : next 3597 * flags = 1, then notify flag : solocited 3598 */ 3599 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3600 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3601 3602 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3603 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3604 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3605 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3606 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3607 3608 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3609 3610 return 0; 3611 } 3612 3613 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3614 int num_entries, struct ib_wc *wc) 3615 { 3616 unsigned int left; 3617 int npolled = 0; 3618 3619 left = wq->head - wq->tail; 3620 if (left == 0) 3621 return 0; 3622 3623 left = min_t(unsigned int, (unsigned int)num_entries, left); 3624 while (npolled < left) { 3625 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3626 wc->status = IB_WC_WR_FLUSH_ERR; 3627 wc->vendor_err = 0; 3628 wc->qp = &hr_qp->ibqp; 3629 3630 wq->tail++; 3631 wc++; 3632 npolled++; 3633 } 3634 3635 return npolled; 3636 } 3637 3638 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3639 struct ib_wc *wc) 3640 { 3641 struct hns_roce_qp *hr_qp; 3642 int npolled = 0; 3643 3644 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3645 npolled += sw_comp(hr_qp, &hr_qp->sq, 3646 num_entries - npolled, wc + npolled); 3647 if (npolled >= num_entries) 3648 goto out; 3649 } 3650 3651 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3652 npolled += sw_comp(hr_qp, &hr_qp->rq, 3653 num_entries - npolled, wc + npolled); 3654 if (npolled >= num_entries) 3655 goto out; 3656 } 3657 3658 out: 3659 return npolled; 3660 } 3661 3662 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3663 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3664 struct ib_wc *wc) 3665 { 3666 static const struct { 3667 u32 cqe_status; 3668 enum ib_wc_status wc_status; 3669 } map[] = { 3670 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3671 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3672 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3673 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3674 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3675 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3676 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3677 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3678 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3679 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3680 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3681 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3682 IB_WC_RETRY_EXC_ERR }, 3683 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3684 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3685 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3686 }; 3687 3688 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3689 int i; 3690 3691 wc->status = IB_WC_GENERAL_ERR; 3692 for (i = 0; i < ARRAY_SIZE(map); i++) 3693 if (cqe_status == map[i].cqe_status) { 3694 wc->status = map[i].wc_status; 3695 break; 3696 } 3697 3698 if (likely(wc->status == IB_WC_SUCCESS || 3699 wc->status == IB_WC_WR_FLUSH_ERR)) 3700 return; 3701 3702 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3703 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3704 cq->cqe_size, false); 3705 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3706 3707 /* 3708 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3709 * the standard protocol, the driver must ignore it and needn't to set 3710 * the QP to an error state. 3711 */ 3712 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3713 return; 3714 3715 flush_cqe(hr_dev, qp); 3716 } 3717 3718 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3719 struct hns_roce_qp **cur_qp) 3720 { 3721 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3722 struct hns_roce_qp *hr_qp = *cur_qp; 3723 u32 qpn; 3724 3725 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3726 3727 if (!hr_qp || qpn != hr_qp->qpn) { 3728 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3729 if (unlikely(!hr_qp)) { 3730 ibdev_err(&hr_dev->ib_dev, 3731 "CQ %06lx with entry for unknown QPN %06x\n", 3732 hr_cq->cqn, qpn); 3733 return -EINVAL; 3734 } 3735 *cur_qp = hr_qp; 3736 } 3737 3738 return 0; 3739 } 3740 3741 /* 3742 * mapped-value = 1 + real-value 3743 * The ib wc opcode's real value is start from 0, In order to distinguish 3744 * between initialized and uninitialized map values, we plus 1 to the actual 3745 * value when defining the mapping, so that the validity can be identified by 3746 * checking whether the mapped value is greater than 0. 3747 */ 3748 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3749 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3750 3751 static const u32 wc_send_op_map[] = { 3752 HR_WC_OP_MAP(SEND, SEND), 3753 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3754 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3755 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3756 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3757 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3758 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3759 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3760 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3761 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3762 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3763 HR_WC_OP_MAP(BIND_MW, REG_MR), 3764 }; 3765 3766 static int to_ib_wc_send_op(u32 hr_opcode) 3767 { 3768 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3769 return -EINVAL; 3770 3771 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3772 -EINVAL; 3773 } 3774 3775 static const u32 wc_recv_op_map[] = { 3776 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3777 HR_WC_OP_MAP(SEND, RECV), 3778 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3779 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3780 }; 3781 3782 static int to_ib_wc_recv_op(u32 hr_opcode) 3783 { 3784 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3785 return -EINVAL; 3786 3787 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3788 -EINVAL; 3789 } 3790 3791 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3792 { 3793 u32 hr_opcode; 3794 int ib_opcode; 3795 3796 wc->wc_flags = 0; 3797 3798 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3799 switch (hr_opcode) { 3800 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3801 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3802 break; 3803 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3804 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3805 wc->wc_flags |= IB_WC_WITH_IMM; 3806 break; 3807 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3808 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3809 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3810 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3811 wc->byte_len = 8; 3812 break; 3813 default: 3814 break; 3815 } 3816 3817 ib_opcode = to_ib_wc_send_op(hr_opcode); 3818 if (ib_opcode < 0) 3819 wc->status = IB_WC_GENERAL_ERR; 3820 else 3821 wc->opcode = ib_opcode; 3822 } 3823 3824 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3825 { 3826 u32 hr_opcode; 3827 int ib_opcode; 3828 3829 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3830 3831 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3832 switch (hr_opcode) { 3833 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3834 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3835 wc->wc_flags = IB_WC_WITH_IMM; 3836 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3837 break; 3838 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3839 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3840 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3841 break; 3842 default: 3843 wc->wc_flags = 0; 3844 } 3845 3846 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3847 if (ib_opcode < 0) 3848 wc->status = IB_WC_GENERAL_ERR; 3849 else 3850 wc->opcode = ib_opcode; 3851 3852 wc->sl = hr_reg_read(cqe, CQE_SL); 3853 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3854 wc->slid = 0; 3855 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3856 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3857 wc->pkey_index = 0; 3858 3859 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3860 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3861 wc->wc_flags |= IB_WC_WITH_VLAN; 3862 } else { 3863 wc->vlan_id = 0xffff; 3864 } 3865 3866 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3867 3868 return 0; 3869 } 3870 3871 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3872 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3873 { 3874 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3875 struct hns_roce_qp *qp = *cur_qp; 3876 struct hns_roce_srq *srq = NULL; 3877 struct hns_roce_v2_cqe *cqe; 3878 struct hns_roce_wq *wq; 3879 int is_send; 3880 u16 wqe_idx; 3881 int ret; 3882 3883 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3884 if (!cqe) 3885 return -EAGAIN; 3886 3887 ++hr_cq->cons_index; 3888 /* Memory barrier */ 3889 rmb(); 3890 3891 ret = get_cur_qp(hr_cq, cqe, &qp); 3892 if (ret) 3893 return ret; 3894 3895 wc->qp = &qp->ibqp; 3896 wc->vendor_err = 0; 3897 3898 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3899 3900 is_send = !hr_reg_read(cqe, CQE_S_R); 3901 if (is_send) { 3902 wq = &qp->sq; 3903 3904 /* If sg_signal_bit is set, tail pointer will be updated to 3905 * the WQE corresponding to the current CQE. 3906 */ 3907 if (qp->sq_signal_bits) 3908 wq->tail += (wqe_idx - (u16)wq->tail) & 3909 (wq->wqe_cnt - 1); 3910 3911 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3912 ++wq->tail; 3913 3914 fill_send_wc(wc, cqe); 3915 } else { 3916 if (qp->ibqp.srq) { 3917 srq = to_hr_srq(qp->ibqp.srq); 3918 wc->wr_id = srq->wrid[wqe_idx]; 3919 hns_roce_free_srq_wqe(srq, wqe_idx); 3920 } else { 3921 wq = &qp->rq; 3922 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3923 ++wq->tail; 3924 } 3925 3926 ret = fill_recv_wc(wc, cqe); 3927 } 3928 3929 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3930 if (unlikely(wc->status != IB_WC_SUCCESS)) 3931 return 0; 3932 3933 return ret; 3934 } 3935 3936 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3937 struct ib_wc *wc) 3938 { 3939 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3940 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3941 struct hns_roce_qp *cur_qp = NULL; 3942 unsigned long flags; 3943 int npolled; 3944 3945 spin_lock_irqsave(&hr_cq->lock, flags); 3946 3947 /* 3948 * When the device starts to reset, the state is RST_DOWN. At this time, 3949 * there may still be some valid CQEs in the hardware that are not 3950 * polled. Therefore, it is not allowed to switch to the software mode 3951 * immediately. When the state changes to UNINIT, CQE no longer exists 3952 * in the hardware, and then switch to software mode. 3953 */ 3954 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3955 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3956 goto out; 3957 } 3958 3959 for (npolled = 0; npolled < num_entries; ++npolled) { 3960 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3961 break; 3962 } 3963 3964 if (npolled) 3965 update_cq_db(hr_dev, hr_cq); 3966 3967 out: 3968 spin_unlock_irqrestore(&hr_cq->lock, flags); 3969 3970 return npolled; 3971 } 3972 3973 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3974 u32 step_idx, u8 *mbox_cmd) 3975 { 3976 u8 cmd; 3977 3978 switch (type) { 3979 case HEM_TYPE_QPC: 3980 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 3981 break; 3982 case HEM_TYPE_MTPT: 3983 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 3984 break; 3985 case HEM_TYPE_CQC: 3986 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 3987 break; 3988 case HEM_TYPE_SRQC: 3989 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3990 break; 3991 case HEM_TYPE_SCCC: 3992 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3993 break; 3994 case HEM_TYPE_QPC_TIMER: 3995 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3996 break; 3997 case HEM_TYPE_CQC_TIMER: 3998 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3999 break; 4000 default: 4001 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4002 return -EINVAL; 4003 } 4004 4005 *mbox_cmd = cmd + step_idx; 4006 4007 return 0; 4008 } 4009 4010 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4011 dma_addr_t base_addr) 4012 { 4013 struct hns_roce_cmq_desc desc; 4014 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4015 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4016 u64 addr = to_hr_hw_page_addr(base_addr); 4017 4018 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4019 4020 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4021 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4022 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4023 4024 return hns_roce_cmq_send(hr_dev, &desc, 1); 4025 } 4026 4027 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4028 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4029 { 4030 int ret; 4031 u8 cmd; 4032 4033 if (unlikely(hem_type == HEM_TYPE_GMV)) 4034 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4035 4036 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4037 return 0; 4038 4039 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4040 if (ret < 0) 4041 return ret; 4042 4043 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4044 } 4045 4046 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4047 struct hns_roce_hem_table *table, int obj, 4048 u32 step_idx) 4049 { 4050 struct hns_roce_hem_iter iter; 4051 struct hns_roce_hem_mhop mhop; 4052 struct hns_roce_hem *hem; 4053 unsigned long mhop_obj = obj; 4054 int i, j, k; 4055 int ret = 0; 4056 u64 hem_idx = 0; 4057 u64 l1_idx = 0; 4058 u64 bt_ba = 0; 4059 u32 chunk_ba_num; 4060 u32 hop_num; 4061 4062 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4063 return 0; 4064 4065 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4066 i = mhop.l0_idx; 4067 j = mhop.l1_idx; 4068 k = mhop.l2_idx; 4069 hop_num = mhop.hop_num; 4070 chunk_ba_num = mhop.bt_chunk_size / 8; 4071 4072 if (hop_num == 2) { 4073 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4074 k; 4075 l1_idx = i * chunk_ba_num + j; 4076 } else if (hop_num == 1) { 4077 hem_idx = i * chunk_ba_num + j; 4078 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4079 hem_idx = i; 4080 } 4081 4082 if (table->type == HEM_TYPE_SCCC) 4083 obj = mhop.l0_idx; 4084 4085 if (check_whether_last_step(hop_num, step_idx)) { 4086 hem = table->hem[hem_idx]; 4087 for (hns_roce_hem_first(hem, &iter); 4088 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4089 bt_ba = hns_roce_hem_addr(&iter); 4090 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4091 step_idx); 4092 } 4093 } else { 4094 if (step_idx == 0) 4095 bt_ba = table->bt_l0_dma_addr[i]; 4096 else if (step_idx == 1 && hop_num == 2) 4097 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4098 4099 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4100 } 4101 4102 return ret; 4103 } 4104 4105 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4106 struct hns_roce_hem_table *table, 4107 int tag, u32 step_idx) 4108 { 4109 struct hns_roce_cmd_mailbox *mailbox; 4110 struct device *dev = hr_dev->dev; 4111 u8 cmd = 0xff; 4112 int ret; 4113 4114 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4115 return 0; 4116 4117 switch (table->type) { 4118 case HEM_TYPE_QPC: 4119 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4120 break; 4121 case HEM_TYPE_MTPT: 4122 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4123 break; 4124 case HEM_TYPE_CQC: 4125 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4126 break; 4127 case HEM_TYPE_SRQC: 4128 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4129 break; 4130 case HEM_TYPE_SCCC: 4131 case HEM_TYPE_QPC_TIMER: 4132 case HEM_TYPE_CQC_TIMER: 4133 case HEM_TYPE_GMV: 4134 return 0; 4135 default: 4136 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4137 table->type); 4138 return 0; 4139 } 4140 4141 cmd += step_idx; 4142 4143 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4144 if (IS_ERR(mailbox)) 4145 return PTR_ERR(mailbox); 4146 4147 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4148 4149 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4150 return ret; 4151 } 4152 4153 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4154 struct hns_roce_v2_qp_context *context, 4155 struct hns_roce_v2_qp_context *qpc_mask, 4156 struct hns_roce_qp *hr_qp) 4157 { 4158 struct hns_roce_cmd_mailbox *mailbox; 4159 int qpc_size; 4160 int ret; 4161 4162 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4163 if (IS_ERR(mailbox)) 4164 return PTR_ERR(mailbox); 4165 4166 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4167 qpc_size = hr_dev->caps.qpc_sz; 4168 memcpy(mailbox->buf, context, qpc_size); 4169 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4170 4171 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4172 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4173 4174 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4175 4176 return ret; 4177 } 4178 4179 static void set_access_flags(struct hns_roce_qp *hr_qp, 4180 struct hns_roce_v2_qp_context *context, 4181 struct hns_roce_v2_qp_context *qpc_mask, 4182 const struct ib_qp_attr *attr, int attr_mask) 4183 { 4184 u8 dest_rd_atomic; 4185 u32 access_flags; 4186 4187 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4188 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4189 4190 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4191 attr->qp_access_flags : hr_qp->atomic_rd_en; 4192 4193 if (!dest_rd_atomic) 4194 access_flags &= IB_ACCESS_REMOTE_WRITE; 4195 4196 hr_reg_write_bool(context, QPC_RRE, 4197 access_flags & IB_ACCESS_REMOTE_READ); 4198 hr_reg_clear(qpc_mask, QPC_RRE); 4199 4200 hr_reg_write_bool(context, QPC_RWE, 4201 access_flags & IB_ACCESS_REMOTE_WRITE); 4202 hr_reg_clear(qpc_mask, QPC_RWE); 4203 4204 hr_reg_write_bool(context, QPC_ATE, 4205 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4206 hr_reg_clear(qpc_mask, QPC_ATE); 4207 hr_reg_write_bool(context, QPC_EXT_ATE, 4208 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4209 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4210 } 4211 4212 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4213 struct hns_roce_v2_qp_context *context, 4214 struct hns_roce_v2_qp_context *qpc_mask) 4215 { 4216 hr_reg_write(context, QPC_SGE_SHIFT, 4217 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4218 hr_qp->sge.sge_shift)); 4219 4220 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4221 4222 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4223 } 4224 4225 static inline int get_cqn(struct ib_cq *ib_cq) 4226 { 4227 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4228 } 4229 4230 static inline int get_pdn(struct ib_pd *ib_pd) 4231 { 4232 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4233 } 4234 4235 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4236 const struct ib_qp_attr *attr, 4237 struct hns_roce_v2_qp_context *context, 4238 struct hns_roce_v2_qp_context *qpc_mask) 4239 { 4240 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4241 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4242 4243 /* 4244 * In v2 engine, software pass context and context mask to hardware 4245 * when modifying qp. If software need modify some fields in context, 4246 * we should set all bits of the relevant fields in context mask to 4247 * 0 at the same time, else set them to 0x1. 4248 */ 4249 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4250 4251 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4252 4253 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4254 4255 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4256 4257 /* No VLAN need to set 0xFFF */ 4258 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4259 4260 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4261 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4262 4263 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4264 } 4265 4266 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4267 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4268 4269 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4270 hr_reg_enable(context, QPC_OWNER_MODE); 4271 4272 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4273 lower_32_bits(hr_qp->rdb.dma) >> 1); 4274 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4275 upper_32_bits(hr_qp->rdb.dma)); 4276 4277 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4278 4279 if (ibqp->srq) { 4280 hr_reg_enable(context, QPC_SRQ_EN); 4281 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4282 } 4283 4284 hr_reg_enable(context, QPC_FRE); 4285 4286 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4287 4288 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4289 return; 4290 4291 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4292 hr_reg_enable(&context->ext, QPCEX_STASH); 4293 } 4294 4295 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4296 const struct ib_qp_attr *attr, 4297 struct hns_roce_v2_qp_context *context, 4298 struct hns_roce_v2_qp_context *qpc_mask) 4299 { 4300 /* 4301 * In v2 engine, software pass context and context mask to hardware 4302 * when modifying qp. If software need modify some fields in context, 4303 * we should set all bits of the relevant fields in context mask to 4304 * 0 at the same time, else set them to 0x1. 4305 */ 4306 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4307 hr_reg_clear(qpc_mask, QPC_TST); 4308 4309 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4310 hr_reg_clear(qpc_mask, QPC_PD); 4311 4312 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4313 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4314 4315 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4316 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4317 4318 if (ibqp->srq) { 4319 hr_reg_enable(context, QPC_SRQ_EN); 4320 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4321 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4322 hr_reg_clear(qpc_mask, QPC_SRQN); 4323 } 4324 } 4325 4326 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4327 struct hns_roce_qp *hr_qp, 4328 struct hns_roce_v2_qp_context *context, 4329 struct hns_roce_v2_qp_context *qpc_mask) 4330 { 4331 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4332 u64 wqe_sge_ba; 4333 int count; 4334 4335 /* Search qp buf's mtts */ 4336 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4337 MTT_MIN_COUNT, &wqe_sge_ba); 4338 if (hr_qp->rq.wqe_cnt && count < 1) { 4339 ibdev_err(&hr_dev->ib_dev, 4340 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4341 return -EINVAL; 4342 } 4343 4344 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4345 qpc_mask->wqe_sge_ba = 0; 4346 4347 /* 4348 * In v2 engine, software pass context and context mask to hardware 4349 * when modifying qp. If software need modify some fields in context, 4350 * we should set all bits of the relevant fields in context mask to 4351 * 0 at the same time, else set them to 0x1. 4352 */ 4353 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4354 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4355 4356 hr_reg_write(context, QPC_SQ_HOP_NUM, 4357 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4358 hr_qp->sq.wqe_cnt)); 4359 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4360 4361 hr_reg_write(context, QPC_SGE_HOP_NUM, 4362 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4363 hr_qp->sge.sge_cnt)); 4364 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4365 4366 hr_reg_write(context, QPC_RQ_HOP_NUM, 4367 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4368 hr_qp->rq.wqe_cnt)); 4369 4370 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4371 4372 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4373 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4374 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4375 4376 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4377 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4378 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4379 4380 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4381 qpc_mask->rq_cur_blk_addr = 0; 4382 4383 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4384 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4385 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4386 4387 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4388 qpc_mask->rq_nxt_blk_addr = 0; 4389 4390 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4391 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4392 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4393 4394 return 0; 4395 } 4396 4397 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4398 struct hns_roce_qp *hr_qp, 4399 struct hns_roce_v2_qp_context *context, 4400 struct hns_roce_v2_qp_context *qpc_mask) 4401 { 4402 struct ib_device *ibdev = &hr_dev->ib_dev; 4403 u64 sge_cur_blk = 0; 4404 u64 sq_cur_blk = 0; 4405 int count; 4406 4407 /* search qp buf's mtts */ 4408 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4409 if (count < 1) { 4410 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4411 hr_qp->qpn); 4412 return -EINVAL; 4413 } 4414 if (hr_qp->sge.sge_cnt > 0) { 4415 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4416 hr_qp->sge.offset, 4417 &sge_cur_blk, 1, NULL); 4418 if (count < 1) { 4419 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4420 hr_qp->qpn); 4421 return -EINVAL; 4422 } 4423 } 4424 4425 /* 4426 * In v2 engine, software pass context and context mask to hardware 4427 * when modifying qp. If software need modify some fields in context, 4428 * we should set all bits of the relevant fields in context mask to 4429 * 0 at the same time, else set them to 0x1. 4430 */ 4431 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4432 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4433 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4434 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4435 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4436 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4437 4438 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4439 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4440 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4441 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4442 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4443 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4444 4445 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4446 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4447 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4448 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4449 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4450 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4451 4452 return 0; 4453 } 4454 4455 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4456 const struct ib_qp_attr *attr) 4457 { 4458 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4459 return IB_MTU_4096; 4460 4461 return attr->path_mtu; 4462 } 4463 4464 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4465 const struct ib_qp_attr *attr, int attr_mask, 4466 struct hns_roce_v2_qp_context *context, 4467 struct hns_roce_v2_qp_context *qpc_mask, 4468 struct ib_udata *udata) 4469 { 4470 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4471 struct hns_roce_ucontext, ibucontext); 4472 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4473 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4474 struct ib_device *ibdev = &hr_dev->ib_dev; 4475 dma_addr_t trrl_ba; 4476 dma_addr_t irrl_ba; 4477 enum ib_mtu ib_mtu; 4478 const u8 *smac; 4479 u8 lp_pktn_ini; 4480 u64 *mtts; 4481 u8 *dmac; 4482 u32 port; 4483 int mtu; 4484 int ret; 4485 4486 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4487 if (ret) { 4488 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4489 return ret; 4490 } 4491 4492 /* Search IRRL's mtts */ 4493 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4494 hr_qp->qpn, &irrl_ba); 4495 if (!mtts) { 4496 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4497 return -EINVAL; 4498 } 4499 4500 /* Search TRRL's mtts */ 4501 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4502 hr_qp->qpn, &trrl_ba); 4503 if (!mtts) { 4504 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4505 return -EINVAL; 4506 } 4507 4508 if (attr_mask & IB_QP_ALT_PATH) { 4509 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4510 attr_mask); 4511 return -EINVAL; 4512 } 4513 4514 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4515 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4516 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4517 qpc_mask->trrl_ba = 0; 4518 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4519 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4520 4521 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4522 qpc_mask->irrl_ba = 0; 4523 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4524 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4525 4526 hr_reg_enable(context, QPC_RMT_E2E); 4527 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4528 4529 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4530 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4531 4532 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4533 4534 smac = (const u8 *)hr_dev->dev_addr[port]; 4535 dmac = (u8 *)attr->ah_attr.roce.dmac; 4536 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4537 if (ether_addr_equal_unaligned(dmac, smac) || 4538 hr_dev->loop_idc == 0x1) { 4539 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4540 hr_reg_clear(qpc_mask, QPC_LBI); 4541 } 4542 4543 if (attr_mask & IB_QP_DEST_QPN) { 4544 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4545 hr_reg_clear(qpc_mask, QPC_DQPN); 4546 } 4547 4548 memcpy(&context->dmac, dmac, sizeof(u32)); 4549 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4550 qpc_mask->dmac = 0; 4551 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4552 4553 ib_mtu = get_mtu(ibqp, attr); 4554 hr_qp->path_mtu = ib_mtu; 4555 4556 mtu = ib_mtu_enum_to_int(ib_mtu); 4557 if (WARN_ON(mtu <= 0)) 4558 return -EINVAL; 4559 #define MIN_LP_MSG_LEN 1024 4560 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4561 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4562 4563 if (attr_mask & IB_QP_PATH_MTU) { 4564 hr_reg_write(context, QPC_MTU, ib_mtu); 4565 hr_reg_clear(qpc_mask, QPC_MTU); 4566 } 4567 4568 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4569 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4570 4571 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4572 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4573 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4574 4575 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4576 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4577 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4578 4579 context->rq_rnr_timer = 0; 4580 qpc_mask->rq_rnr_timer = 0; 4581 4582 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4583 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4584 4585 /* rocee send 2^lp_sgen_ini segs every time */ 4586 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4587 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4588 4589 if (udata && ibqp->qp_type == IB_QPT_RC && 4590 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4591 hr_reg_write_bool(context, QPC_RQIE, 4592 hr_dev->caps.flags & 4593 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4594 hr_reg_clear(qpc_mask, QPC_RQIE); 4595 } 4596 4597 if (udata && 4598 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4599 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4600 hr_reg_write_bool(context, QPC_CQEIE, 4601 hr_dev->caps.flags & 4602 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4603 hr_reg_clear(qpc_mask, QPC_CQEIE); 4604 4605 hr_reg_write(context, QPC_CQEIS, 0); 4606 hr_reg_clear(qpc_mask, QPC_CQEIS); 4607 } 4608 4609 return 0; 4610 } 4611 4612 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4613 const struct ib_qp_attr *attr, int attr_mask, 4614 struct hns_roce_v2_qp_context *context, 4615 struct hns_roce_v2_qp_context *qpc_mask) 4616 { 4617 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4618 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4619 struct ib_device *ibdev = &hr_dev->ib_dev; 4620 int ret; 4621 4622 /* Not support alternate path and path migration */ 4623 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4624 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4625 return -EINVAL; 4626 } 4627 4628 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4629 if (ret) { 4630 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4631 return ret; 4632 } 4633 4634 /* 4635 * Set some fields in context to zero, Because the default values 4636 * of all fields in context are zero, we need not set them to 0 again. 4637 * but we should set the relevant fields of context mask to 0. 4638 */ 4639 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4640 4641 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4642 4643 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4644 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4645 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4646 4647 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4648 4649 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4650 4651 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4652 4653 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4654 4655 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4656 4657 return 0; 4658 } 4659 4660 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4661 u32 *dip_idx) 4662 { 4663 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4664 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4665 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4666 u32 *head = &hr_dev->qp_table.idx_table.head; 4667 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4668 struct hns_roce_dip *hr_dip; 4669 unsigned long flags; 4670 int ret = 0; 4671 4672 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4673 4674 spare_idx[*tail] = ibqp->qp_num; 4675 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4676 4677 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4678 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4679 *dip_idx = hr_dip->dip_idx; 4680 goto out; 4681 } 4682 } 4683 4684 /* If no dgid is found, a new dip and a mapping between dgid and 4685 * dip_idx will be created. 4686 */ 4687 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4688 if (!hr_dip) { 4689 ret = -ENOMEM; 4690 goto out; 4691 } 4692 4693 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4694 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4695 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4696 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4697 4698 out: 4699 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4700 return ret; 4701 } 4702 4703 enum { 4704 CONG_DCQCN, 4705 CONG_WINDOW, 4706 }; 4707 4708 enum { 4709 UNSUPPORT_CONG_LEVEL, 4710 SUPPORT_CONG_LEVEL, 4711 }; 4712 4713 enum { 4714 CONG_LDCP, 4715 CONG_HC3, 4716 }; 4717 4718 enum { 4719 DIP_INVALID, 4720 DIP_VALID, 4721 }; 4722 4723 enum { 4724 WND_LIMIT, 4725 WND_UNLIMIT, 4726 }; 4727 4728 static int check_cong_type(struct ib_qp *ibqp, 4729 struct hns_roce_congestion_algorithm *cong_alg) 4730 { 4731 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4732 4733 if (ibqp->qp_type == IB_QPT_UD) 4734 hr_dev->caps.cong_type = CONG_TYPE_DCQCN; 4735 4736 /* different congestion types match different configurations */ 4737 switch (hr_dev->caps.cong_type) { 4738 case CONG_TYPE_DCQCN: 4739 cong_alg->alg_sel = CONG_DCQCN; 4740 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4741 cong_alg->dip_vld = DIP_INVALID; 4742 cong_alg->wnd_mode_sel = WND_LIMIT; 4743 break; 4744 case CONG_TYPE_LDCP: 4745 cong_alg->alg_sel = CONG_WINDOW; 4746 cong_alg->alg_sub_sel = CONG_LDCP; 4747 cong_alg->dip_vld = DIP_INVALID; 4748 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4749 break; 4750 case CONG_TYPE_HC3: 4751 cong_alg->alg_sel = CONG_WINDOW; 4752 cong_alg->alg_sub_sel = CONG_HC3; 4753 cong_alg->dip_vld = DIP_INVALID; 4754 cong_alg->wnd_mode_sel = WND_LIMIT; 4755 break; 4756 case CONG_TYPE_DIP: 4757 cong_alg->alg_sel = CONG_DCQCN; 4758 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4759 cong_alg->dip_vld = DIP_VALID; 4760 cong_alg->wnd_mode_sel = WND_LIMIT; 4761 break; 4762 default: 4763 ibdev_err(&hr_dev->ib_dev, 4764 "error type(%u) for congestion selection.\n", 4765 hr_dev->caps.cong_type); 4766 return -EINVAL; 4767 } 4768 4769 return 0; 4770 } 4771 4772 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4773 struct hns_roce_v2_qp_context *context, 4774 struct hns_roce_v2_qp_context *qpc_mask) 4775 { 4776 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4777 struct hns_roce_congestion_algorithm cong_field; 4778 struct ib_device *ibdev = ibqp->device; 4779 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4780 u32 dip_idx = 0; 4781 int ret; 4782 4783 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4784 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4785 return 0; 4786 4787 ret = check_cong_type(ibqp, &cong_field); 4788 if (ret) 4789 return ret; 4790 4791 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4792 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4793 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4794 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4795 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4796 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4797 cong_field.alg_sub_sel); 4798 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4799 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4800 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4801 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4802 cong_field.wnd_mode_sel); 4803 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4804 4805 /* if dip is disabled, there is no need to set dip idx */ 4806 if (cong_field.dip_vld == 0) 4807 return 0; 4808 4809 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4810 if (ret) { 4811 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4812 return ret; 4813 } 4814 4815 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4816 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4817 4818 return 0; 4819 } 4820 4821 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4822 const struct ib_qp_attr *attr, 4823 int attr_mask, 4824 struct hns_roce_v2_qp_context *context, 4825 struct hns_roce_v2_qp_context *qpc_mask) 4826 { 4827 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4828 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4829 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4830 struct ib_device *ibdev = &hr_dev->ib_dev; 4831 const struct ib_gid_attr *gid_attr = NULL; 4832 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4833 int is_roce_protocol; 4834 u16 vlan_id = 0xffff; 4835 bool is_udp = false; 4836 u32 max_sl; 4837 u8 ib_port; 4838 u8 hr_port; 4839 int ret; 4840 4841 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4842 if (unlikely(sl > max_sl)) { 4843 ibdev_err_ratelimited(ibdev, 4844 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n", 4845 sl, max_sl); 4846 return -EINVAL; 4847 } 4848 4849 /* 4850 * If free_mr_en of qp is set, it means that this qp comes from 4851 * free mr. This qp will perform the loopback operation. 4852 * In the loopback scenario, only sl needs to be set. 4853 */ 4854 if (hr_qp->free_mr_en) { 4855 hr_reg_write(context, QPC_SL, sl); 4856 hr_reg_clear(qpc_mask, QPC_SL); 4857 hr_qp->sl = sl; 4858 return 0; 4859 } 4860 4861 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4862 hr_port = ib_port - 1; 4863 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4864 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4865 4866 if (is_roce_protocol) { 4867 gid_attr = attr->ah_attr.grh.sgid_attr; 4868 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4869 if (ret) 4870 return ret; 4871 4872 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4873 } 4874 4875 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4876 if (vlan_id < VLAN_N_VID && 4877 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4878 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4879 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4880 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4881 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4882 } 4883 4884 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4885 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4886 4887 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4888 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4889 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4890 return -EINVAL; 4891 } 4892 4893 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4894 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4895 return -EINVAL; 4896 } 4897 4898 hr_reg_write(context, QPC_UDPSPN, 4899 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4900 attr->dest_qp_num) : 4901 0); 4902 4903 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4904 4905 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4906 4907 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4908 4909 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4910 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4911 4912 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4913 if (ret) 4914 return ret; 4915 4916 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4917 hr_reg_clear(qpc_mask, QPC_TC); 4918 4919 hr_reg_write(context, QPC_FL, grh->flow_label); 4920 hr_reg_clear(qpc_mask, QPC_FL); 4921 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4922 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4923 4924 hr_qp->sl = sl; 4925 hr_reg_write(context, QPC_SL, hr_qp->sl); 4926 hr_reg_clear(qpc_mask, QPC_SL); 4927 4928 return 0; 4929 } 4930 4931 static bool check_qp_state(enum ib_qp_state cur_state, 4932 enum ib_qp_state new_state) 4933 { 4934 static const bool sm[][IB_QPS_ERR + 1] = { 4935 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4936 [IB_QPS_INIT] = true }, 4937 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4938 [IB_QPS_INIT] = true, 4939 [IB_QPS_RTR] = true, 4940 [IB_QPS_ERR] = true }, 4941 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4942 [IB_QPS_RTS] = true, 4943 [IB_QPS_ERR] = true }, 4944 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4945 [IB_QPS_RTS] = true, 4946 [IB_QPS_ERR] = true }, 4947 [IB_QPS_SQD] = {}, 4948 [IB_QPS_SQE] = {}, 4949 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4950 [IB_QPS_ERR] = true } 4951 }; 4952 4953 return sm[cur_state][new_state]; 4954 } 4955 4956 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4957 const struct ib_qp_attr *attr, 4958 int attr_mask, 4959 enum ib_qp_state cur_state, 4960 enum ib_qp_state new_state, 4961 struct hns_roce_v2_qp_context *context, 4962 struct hns_roce_v2_qp_context *qpc_mask, 4963 struct ib_udata *udata) 4964 { 4965 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4966 int ret = 0; 4967 4968 if (!check_qp_state(cur_state, new_state)) { 4969 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4970 return -EINVAL; 4971 } 4972 4973 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4974 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4975 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 4976 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4977 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 4978 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4979 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4980 qpc_mask, udata); 4981 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4982 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4983 qpc_mask); 4984 } 4985 4986 return ret; 4987 } 4988 4989 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 4990 { 4991 #define QP_ACK_TIMEOUT_MAX_HIP08 20 4992 #define QP_ACK_TIMEOUT_MAX 31 4993 4994 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4995 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 4996 ibdev_warn(&hr_dev->ib_dev, 4997 "local ACK timeout shall be 0 to 20.\n"); 4998 return false; 4999 } 5000 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5001 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5002 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5003 ibdev_warn(&hr_dev->ib_dev, 5004 "local ACK timeout shall be 0 to 31.\n"); 5005 return false; 5006 } 5007 } 5008 5009 return true; 5010 } 5011 5012 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5013 const struct ib_qp_attr *attr, 5014 int attr_mask, 5015 struct hns_roce_v2_qp_context *context, 5016 struct hns_roce_v2_qp_context *qpc_mask) 5017 { 5018 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5019 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5020 int ret = 0; 5021 u8 timeout; 5022 5023 if (attr_mask & IB_QP_AV) { 5024 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5025 qpc_mask); 5026 if (ret) 5027 return ret; 5028 } 5029 5030 if (attr_mask & IB_QP_TIMEOUT) { 5031 timeout = attr->timeout; 5032 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5033 hr_reg_write(context, QPC_AT, timeout); 5034 hr_reg_clear(qpc_mask, QPC_AT); 5035 } 5036 } 5037 5038 if (attr_mask & IB_QP_RETRY_CNT) { 5039 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5040 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5041 5042 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5043 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5044 } 5045 5046 if (attr_mask & IB_QP_RNR_RETRY) { 5047 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5048 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5049 5050 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5051 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5052 } 5053 5054 if (attr_mask & IB_QP_SQ_PSN) { 5055 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5056 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5057 5058 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5059 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5060 5061 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5062 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5063 5064 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5065 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5066 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5067 5068 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5069 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5070 5071 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5072 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5073 } 5074 5075 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5076 attr->max_dest_rd_atomic) { 5077 hr_reg_write(context, QPC_RR_MAX, 5078 fls(attr->max_dest_rd_atomic - 1)); 5079 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5080 } 5081 5082 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5083 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5084 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5085 } 5086 5087 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5088 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5089 5090 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5091 hr_reg_write(context, QPC_MIN_RNR_TIME, 5092 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5093 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5094 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5095 } 5096 5097 if (attr_mask & IB_QP_RQ_PSN) { 5098 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5099 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5100 5101 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5102 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5103 } 5104 5105 if (attr_mask & IB_QP_QKEY) { 5106 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5107 qpc_mask->qkey_xrcd = 0; 5108 hr_qp->qkey = attr->qkey; 5109 } 5110 5111 return ret; 5112 } 5113 5114 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5115 const struct ib_qp_attr *attr, 5116 int attr_mask) 5117 { 5118 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5119 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5120 5121 if (attr_mask & IB_QP_ACCESS_FLAGS) 5122 hr_qp->atomic_rd_en = attr->qp_access_flags; 5123 5124 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5125 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5126 if (attr_mask & IB_QP_PORT) { 5127 hr_qp->port = attr->port_num - 1; 5128 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5129 } 5130 } 5131 5132 static void clear_qp(struct hns_roce_qp *hr_qp) 5133 { 5134 struct ib_qp *ibqp = &hr_qp->ibqp; 5135 5136 if (ibqp->send_cq) 5137 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5138 hr_qp->qpn, NULL); 5139 5140 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5141 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5142 hr_qp->qpn, ibqp->srq ? 5143 to_hr_srq(ibqp->srq) : NULL); 5144 5145 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5146 *hr_qp->rdb.db_record = 0; 5147 5148 hr_qp->rq.head = 0; 5149 hr_qp->rq.tail = 0; 5150 hr_qp->sq.head = 0; 5151 hr_qp->sq.tail = 0; 5152 hr_qp->next_sge = 0; 5153 } 5154 5155 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5156 struct hns_roce_v2_qp_context *context, 5157 struct hns_roce_v2_qp_context *qpc_mask) 5158 { 5159 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5160 unsigned long sq_flag = 0; 5161 unsigned long rq_flag = 0; 5162 5163 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5164 return; 5165 5166 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5167 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5168 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5169 hr_qp->state = IB_QPS_ERR; 5170 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5171 5172 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5173 return; 5174 5175 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5176 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5177 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5178 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5179 } 5180 5181 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5182 const struct ib_qp_attr *attr, 5183 int attr_mask, enum ib_qp_state cur_state, 5184 enum ib_qp_state new_state, struct ib_udata *udata) 5185 { 5186 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5187 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5188 struct hns_roce_v2_qp_context ctx[2]; 5189 struct hns_roce_v2_qp_context *context = ctx; 5190 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5191 struct ib_device *ibdev = &hr_dev->ib_dev; 5192 int ret; 5193 5194 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5195 return -EOPNOTSUPP; 5196 5197 /* 5198 * In v2 engine, software pass context and context mask to hardware 5199 * when modifying qp. If software need modify some fields in context, 5200 * we should set all bits of the relevant fields in context mask to 5201 * 0 at the same time, else set them to 0x1. 5202 */ 5203 memset(context, 0, hr_dev->caps.qpc_sz); 5204 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5205 5206 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5207 new_state, context, qpc_mask, udata); 5208 if (ret) 5209 goto out; 5210 5211 /* When QP state is err, SQ and RQ WQE should be flushed */ 5212 if (new_state == IB_QPS_ERR) 5213 v2_set_flushed_fields(ibqp, context, qpc_mask); 5214 5215 /* Configure the optional fields */ 5216 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5217 qpc_mask); 5218 if (ret) 5219 goto out; 5220 5221 hr_reg_write_bool(context, QPC_INV_CREDIT, 5222 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5223 ibqp->srq); 5224 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5225 5226 /* Every status migrate must change state */ 5227 hr_reg_write(context, QPC_QP_ST, new_state); 5228 hr_reg_clear(qpc_mask, QPC_QP_ST); 5229 5230 /* SW pass context to HW */ 5231 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5232 if (ret) { 5233 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5234 goto out; 5235 } 5236 5237 hr_qp->state = new_state; 5238 5239 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5240 5241 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5242 clear_qp(hr_qp); 5243 5244 out: 5245 return ret; 5246 } 5247 5248 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5249 { 5250 static const enum ib_qp_state map[] = { 5251 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5252 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5253 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5254 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5255 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5256 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5257 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5258 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5259 }; 5260 5261 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5262 } 5263 5264 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5265 void *buffer) 5266 { 5267 struct hns_roce_cmd_mailbox *mailbox; 5268 int ret; 5269 5270 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5271 if (IS_ERR(mailbox)) 5272 return PTR_ERR(mailbox); 5273 5274 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5275 qpn); 5276 if (ret) 5277 goto out; 5278 5279 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5280 5281 out: 5282 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5283 return ret; 5284 } 5285 5286 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5287 void *buffer) 5288 { 5289 struct hns_roce_srq_context *context; 5290 struct hns_roce_cmd_mailbox *mailbox; 5291 int ret; 5292 5293 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5294 if (IS_ERR(mailbox)) 5295 return PTR_ERR(mailbox); 5296 5297 context = mailbox->buf; 5298 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5299 srqn); 5300 if (ret) 5301 goto out; 5302 5303 memcpy(buffer, context, sizeof(*context)); 5304 5305 out: 5306 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5307 return ret; 5308 } 5309 5310 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5311 struct hns_roce_v2_qp_context *context) 5312 { 5313 u8 timeout; 5314 5315 timeout = (u8)hr_reg_read(context, QPC_AT); 5316 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5317 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5318 5319 return timeout; 5320 } 5321 5322 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5323 int qp_attr_mask, 5324 struct ib_qp_init_attr *qp_init_attr) 5325 { 5326 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5327 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5328 struct hns_roce_v2_qp_context context = {}; 5329 struct ib_device *ibdev = &hr_dev->ib_dev; 5330 int tmp_qp_state; 5331 int state; 5332 int ret; 5333 5334 memset(qp_attr, 0, sizeof(*qp_attr)); 5335 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5336 5337 mutex_lock(&hr_qp->mutex); 5338 5339 if (hr_qp->state == IB_QPS_RESET) { 5340 qp_attr->qp_state = IB_QPS_RESET; 5341 ret = 0; 5342 goto done; 5343 } 5344 5345 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5346 if (ret) { 5347 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5348 ret = -EINVAL; 5349 goto out; 5350 } 5351 5352 state = hr_reg_read(&context, QPC_QP_ST); 5353 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5354 if (tmp_qp_state == -1) { 5355 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5356 ret = -EINVAL; 5357 goto out; 5358 } 5359 hr_qp->state = (u8)tmp_qp_state; 5360 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5361 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5362 qp_attr->path_mig_state = IB_MIG_ARMED; 5363 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5364 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5365 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5366 5367 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5368 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5369 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5370 qp_attr->qp_access_flags = 5371 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5372 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5373 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5374 5375 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5376 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5377 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5378 struct ib_global_route *grh = 5379 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5380 5381 rdma_ah_set_sl(&qp_attr->ah_attr, 5382 hr_reg_read(&context, QPC_SL)); 5383 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5384 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5385 grh->flow_label = hr_reg_read(&context, QPC_FL); 5386 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5387 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5388 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5389 5390 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5391 } 5392 5393 qp_attr->port_num = hr_qp->port + 1; 5394 qp_attr->sq_draining = 0; 5395 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5396 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5397 5398 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5399 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5400 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5401 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5402 5403 done: 5404 qp_attr->cur_qp_state = qp_attr->qp_state; 5405 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5406 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5407 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5408 5409 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5410 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5411 5412 qp_init_attr->qp_context = ibqp->qp_context; 5413 qp_init_attr->qp_type = ibqp->qp_type; 5414 qp_init_attr->recv_cq = ibqp->recv_cq; 5415 qp_init_attr->send_cq = ibqp->send_cq; 5416 qp_init_attr->srq = ibqp->srq; 5417 qp_init_attr->cap = qp_attr->cap; 5418 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5419 5420 out: 5421 mutex_unlock(&hr_qp->mutex); 5422 return ret; 5423 } 5424 5425 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5426 { 5427 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5428 hr_qp->ibqp.qp_type == IB_QPT_UD || 5429 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5430 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5431 hr_qp->state != IB_QPS_RESET); 5432 } 5433 5434 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5435 struct hns_roce_qp *hr_qp, 5436 struct ib_udata *udata) 5437 { 5438 struct ib_device *ibdev = &hr_dev->ib_dev; 5439 struct hns_roce_cq *send_cq, *recv_cq; 5440 unsigned long flags; 5441 int ret = 0; 5442 5443 if (modify_qp_is_ok(hr_qp)) { 5444 /* Modify qp to reset before destroying qp */ 5445 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5446 hr_qp->state, IB_QPS_RESET, udata); 5447 if (ret) 5448 ibdev_err(ibdev, 5449 "failed to modify QP to RST, ret = %d.\n", 5450 ret); 5451 } 5452 5453 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5454 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5455 5456 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5457 hns_roce_lock_cqs(send_cq, recv_cq); 5458 5459 if (!udata) { 5460 if (recv_cq) 5461 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5462 (hr_qp->ibqp.srq ? 5463 to_hr_srq(hr_qp->ibqp.srq) : 5464 NULL)); 5465 5466 if (send_cq && send_cq != recv_cq) 5467 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5468 } 5469 5470 hns_roce_qp_remove(hr_dev, hr_qp); 5471 5472 hns_roce_unlock_cqs(send_cq, recv_cq); 5473 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5474 5475 return ret; 5476 } 5477 5478 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5479 { 5480 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5481 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5482 int ret; 5483 5484 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5485 if (ret) 5486 ibdev_err(&hr_dev->ib_dev, 5487 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5488 hr_qp->qpn, ret); 5489 5490 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5491 5492 return 0; 5493 } 5494 5495 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5496 struct hns_roce_qp *hr_qp) 5497 { 5498 struct ib_device *ibdev = &hr_dev->ib_dev; 5499 struct hns_roce_sccc_clr_done *resp; 5500 struct hns_roce_sccc_clr *clr; 5501 struct hns_roce_cmq_desc desc; 5502 int ret, i; 5503 5504 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5505 return 0; 5506 5507 mutex_lock(&hr_dev->qp_table.scc_mutex); 5508 5509 /* set scc ctx clear done flag */ 5510 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5511 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5512 if (ret) { 5513 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5514 goto out; 5515 } 5516 5517 /* clear scc context */ 5518 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5519 clr = (struct hns_roce_sccc_clr *)desc.data; 5520 clr->qpn = cpu_to_le32(hr_qp->qpn); 5521 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5522 if (ret) { 5523 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5524 goto out; 5525 } 5526 5527 /* query scc context clear is done or not */ 5528 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5529 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5530 hns_roce_cmq_setup_basic_desc(&desc, 5531 HNS_ROCE_OPC_QUERY_SCCC, true); 5532 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5533 if (ret) { 5534 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5535 ret); 5536 goto out; 5537 } 5538 5539 if (resp->clr_done) 5540 goto out; 5541 5542 msleep(20); 5543 } 5544 5545 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5546 ret = -ETIMEDOUT; 5547 5548 out: 5549 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5550 return ret; 5551 } 5552 5553 #define DMA_IDX_SHIFT 3 5554 #define DMA_WQE_SHIFT 3 5555 5556 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5557 struct hns_roce_srq_context *ctx) 5558 { 5559 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5560 struct ib_device *ibdev = srq->ibsrq.device; 5561 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5562 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5563 dma_addr_t dma_handle_idx = 0; 5564 int ret; 5565 5566 /* Get physical address of idx que buf */ 5567 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5568 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5569 if (ret < 1) { 5570 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5571 ret); 5572 return -ENOBUFS; 5573 } 5574 5575 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5576 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5577 5578 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5579 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5580 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5581 5582 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5583 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5584 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5585 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5586 5587 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5588 to_hr_hw_page_addr(mtts_idx[0])); 5589 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5590 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5591 5592 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5593 to_hr_hw_page_addr(mtts_idx[1])); 5594 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5595 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5596 5597 return 0; 5598 } 5599 5600 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5601 { 5602 struct ib_device *ibdev = srq->ibsrq.device; 5603 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5604 struct hns_roce_srq_context *ctx = mb_buf; 5605 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5606 dma_addr_t dma_handle_wqe = 0; 5607 int ret; 5608 5609 memset(ctx, 0, sizeof(*ctx)); 5610 5611 /* Get the physical address of srq buf */ 5612 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5613 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5614 if (ret < 1) { 5615 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5616 ret); 5617 return -ENOBUFS; 5618 } 5619 5620 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5621 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5622 srq->ibsrq.srq_type == IB_SRQT_XRC); 5623 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5624 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5625 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5626 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5627 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5628 hr_reg_write(ctx, SRQC_RQWS, 5629 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5630 5631 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5632 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5633 srq->wqe_cnt)); 5634 5635 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5636 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5637 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5638 5639 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5640 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5641 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5642 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5643 5644 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5645 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5646 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5647 lower_32_bits(srq->rdb.dma) >> 1); 5648 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5649 upper_32_bits(srq->rdb.dma)); 5650 } 5651 5652 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5653 } 5654 5655 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5656 struct ib_srq_attr *srq_attr, 5657 enum ib_srq_attr_mask srq_attr_mask, 5658 struct ib_udata *udata) 5659 { 5660 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5661 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5662 struct hns_roce_srq_context *srq_context; 5663 struct hns_roce_srq_context *srqc_mask; 5664 struct hns_roce_cmd_mailbox *mailbox; 5665 int ret; 5666 5667 /* Resizing SRQs is not supported yet */ 5668 if (srq_attr_mask & IB_SRQ_MAX_WR) 5669 return -EINVAL; 5670 5671 if (srq_attr_mask & IB_SRQ_LIMIT) { 5672 if (srq_attr->srq_limit > srq->wqe_cnt) 5673 return -EINVAL; 5674 5675 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5676 if (IS_ERR(mailbox)) 5677 return PTR_ERR(mailbox); 5678 5679 srq_context = mailbox->buf; 5680 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5681 5682 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5683 5684 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5685 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5686 5687 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5688 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5689 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5690 if (ret) { 5691 ibdev_err(&hr_dev->ib_dev, 5692 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5693 ret); 5694 return ret; 5695 } 5696 } 5697 5698 return 0; 5699 } 5700 5701 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5702 { 5703 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5704 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5705 struct hns_roce_srq_context *srq_context; 5706 struct hns_roce_cmd_mailbox *mailbox; 5707 int ret; 5708 5709 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5710 if (IS_ERR(mailbox)) 5711 return PTR_ERR(mailbox); 5712 5713 srq_context = mailbox->buf; 5714 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5715 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5716 if (ret) { 5717 ibdev_err(&hr_dev->ib_dev, 5718 "failed to process cmd of querying SRQ, ret = %d.\n", 5719 ret); 5720 goto out; 5721 } 5722 5723 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5724 attr->max_wr = srq->wqe_cnt; 5725 attr->max_sge = srq->max_gs - srq->rsv_sge; 5726 5727 out: 5728 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5729 return ret; 5730 } 5731 5732 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5733 { 5734 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5735 struct hns_roce_v2_cq_context *cq_context; 5736 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5737 struct hns_roce_v2_cq_context *cqc_mask; 5738 struct hns_roce_cmd_mailbox *mailbox; 5739 int ret; 5740 5741 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5742 if (IS_ERR(mailbox)) 5743 return PTR_ERR(mailbox); 5744 5745 cq_context = mailbox->buf; 5746 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5747 5748 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5749 5750 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5751 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5752 5753 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5754 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5755 dev_info(hr_dev->dev, 5756 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5757 cq_period); 5758 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5759 } 5760 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5761 } 5762 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5763 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5764 5765 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5766 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5767 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5768 if (ret) 5769 ibdev_err(&hr_dev->ib_dev, 5770 "failed to process cmd when modifying CQ, ret = %d.\n", 5771 ret); 5772 5773 return ret; 5774 } 5775 5776 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5777 void *buffer) 5778 { 5779 struct hns_roce_v2_cq_context *context; 5780 struct hns_roce_cmd_mailbox *mailbox; 5781 int ret; 5782 5783 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5784 if (IS_ERR(mailbox)) 5785 return PTR_ERR(mailbox); 5786 5787 context = mailbox->buf; 5788 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5789 HNS_ROCE_CMD_QUERY_CQC, cqn); 5790 if (ret) { 5791 ibdev_err(&hr_dev->ib_dev, 5792 "failed to process cmd when querying CQ, ret = %d.\n", 5793 ret); 5794 goto err_mailbox; 5795 } 5796 5797 memcpy(buffer, context, sizeof(*context)); 5798 5799 err_mailbox: 5800 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5801 5802 return ret; 5803 } 5804 5805 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5806 void *buffer) 5807 { 5808 struct hns_roce_v2_mpt_entry *context; 5809 struct hns_roce_cmd_mailbox *mailbox; 5810 int ret; 5811 5812 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5813 if (IS_ERR(mailbox)) 5814 return PTR_ERR(mailbox); 5815 5816 context = mailbox->buf; 5817 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5818 key_to_hw_index(key)); 5819 if (ret) { 5820 ibdev_err(&hr_dev->ib_dev, 5821 "failed to process cmd when querying MPT, ret = %d.\n", 5822 ret); 5823 goto err_mailbox; 5824 } 5825 5826 memcpy(buffer, context, sizeof(*context)); 5827 5828 err_mailbox: 5829 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5830 5831 return ret; 5832 } 5833 5834 static void hns_roce_irq_work_handle(struct work_struct *work) 5835 { 5836 struct hns_roce_work *irq_work = 5837 container_of(work, struct hns_roce_work, work); 5838 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5839 5840 switch (irq_work->event_type) { 5841 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5842 ibdev_info(ibdev, "path migrated succeeded.\n"); 5843 break; 5844 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5845 ibdev_warn(ibdev, "path migration failed.\n"); 5846 break; 5847 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5848 break; 5849 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5850 ibdev_dbg(ibdev, "send queue drained.\n"); 5851 break; 5852 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5853 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5854 irq_work->queue_num, irq_work->sub_type); 5855 break; 5856 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5857 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5858 irq_work->queue_num); 5859 break; 5860 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5861 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5862 irq_work->queue_num, irq_work->sub_type); 5863 break; 5864 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5865 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 5866 break; 5867 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5868 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 5869 break; 5870 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5871 ibdev_err(ibdev, "SRQ catas error.\n"); 5872 break; 5873 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5874 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5875 break; 5876 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5877 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5878 break; 5879 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5880 ibdev_warn(ibdev, "DB overflow.\n"); 5881 break; 5882 case HNS_ROCE_EVENT_TYPE_FLR: 5883 ibdev_warn(ibdev, "function level reset.\n"); 5884 break; 5885 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5886 ibdev_err(ibdev, "xrc domain violation error.\n"); 5887 break; 5888 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5889 ibdev_err(ibdev, "invalid xrceth error.\n"); 5890 break; 5891 default: 5892 break; 5893 } 5894 5895 kfree(irq_work); 5896 } 5897 5898 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5899 struct hns_roce_eq *eq, u32 queue_num) 5900 { 5901 struct hns_roce_work *irq_work; 5902 5903 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5904 if (!irq_work) 5905 return; 5906 5907 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5908 irq_work->hr_dev = hr_dev; 5909 irq_work->event_type = eq->event_type; 5910 irq_work->sub_type = eq->sub_type; 5911 irq_work->queue_num = queue_num; 5912 queue_work(hr_dev->irq_workq, &irq_work->work); 5913 } 5914 5915 static void update_eq_db(struct hns_roce_eq *eq) 5916 { 5917 struct hns_roce_dev *hr_dev = eq->hr_dev; 5918 struct hns_roce_v2_db eq_db = {}; 5919 5920 if (eq->type_flag == HNS_ROCE_AEQ) { 5921 hr_reg_write(&eq_db, EQ_DB_CMD, 5922 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5923 HNS_ROCE_EQ_DB_CMD_AEQ : 5924 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5925 } else { 5926 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5927 5928 hr_reg_write(&eq_db, EQ_DB_CMD, 5929 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5930 HNS_ROCE_EQ_DB_CMD_CEQ : 5931 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5932 } 5933 5934 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5935 5936 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5937 } 5938 5939 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5940 { 5941 struct hns_roce_aeqe *aeqe; 5942 5943 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5944 (eq->cons_index & (eq->entries - 1)) * 5945 eq->eqe_size); 5946 5947 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5948 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5949 } 5950 5951 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5952 struct hns_roce_eq *eq) 5953 { 5954 struct device *dev = hr_dev->dev; 5955 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5956 irqreturn_t aeqe_found = IRQ_NONE; 5957 int event_type; 5958 u32 queue_num; 5959 int sub_type; 5960 5961 while (aeqe) { 5962 /* Make sure we read AEQ entry after we have checked the 5963 * ownership bit 5964 */ 5965 dma_rmb(); 5966 5967 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 5968 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 5969 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 5970 5971 switch (event_type) { 5972 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5973 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5974 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5975 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5976 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5977 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5978 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5979 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5980 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5981 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5982 hns_roce_qp_event(hr_dev, queue_num, event_type); 5983 break; 5984 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5985 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5986 hns_roce_srq_event(hr_dev, queue_num, event_type); 5987 break; 5988 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5989 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5990 hns_roce_cq_event(hr_dev, queue_num, event_type); 5991 break; 5992 case HNS_ROCE_EVENT_TYPE_MB: 5993 hns_roce_cmd_event(hr_dev, 5994 le16_to_cpu(aeqe->event.cmd.token), 5995 aeqe->event.cmd.status, 5996 le64_to_cpu(aeqe->event.cmd.out_param)); 5997 break; 5998 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5999 case HNS_ROCE_EVENT_TYPE_FLR: 6000 break; 6001 default: 6002 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 6003 event_type, eq->eqn, eq->cons_index); 6004 break; 6005 } 6006 6007 eq->event_type = event_type; 6008 eq->sub_type = sub_type; 6009 ++eq->cons_index; 6010 aeqe_found = IRQ_HANDLED; 6011 6012 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6013 6014 aeqe = next_aeqe_sw_v2(eq); 6015 } 6016 6017 update_eq_db(eq); 6018 6019 return IRQ_RETVAL(aeqe_found); 6020 } 6021 6022 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6023 { 6024 struct hns_roce_ceqe *ceqe; 6025 6026 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6027 (eq->cons_index & (eq->entries - 1)) * 6028 eq->eqe_size); 6029 6030 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6031 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6032 } 6033 6034 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6035 struct hns_roce_eq *eq) 6036 { 6037 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6038 irqreturn_t ceqe_found = IRQ_NONE; 6039 u32 cqn; 6040 6041 while (ceqe) { 6042 /* Make sure we read CEQ entry after we have checked the 6043 * ownership bit 6044 */ 6045 dma_rmb(); 6046 6047 cqn = hr_reg_read(ceqe, CEQE_CQN); 6048 6049 hns_roce_cq_completion(hr_dev, cqn); 6050 6051 ++eq->cons_index; 6052 ceqe_found = IRQ_HANDLED; 6053 6054 ceqe = next_ceqe_sw_v2(eq); 6055 } 6056 6057 update_eq_db(eq); 6058 6059 return IRQ_RETVAL(ceqe_found); 6060 } 6061 6062 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6063 { 6064 struct hns_roce_eq *eq = eq_ptr; 6065 struct hns_roce_dev *hr_dev = eq->hr_dev; 6066 irqreturn_t int_work; 6067 6068 if (eq->type_flag == HNS_ROCE_CEQ) 6069 /* Completion event interrupt */ 6070 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6071 else 6072 /* Asynchronous event interrupt */ 6073 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6074 6075 return IRQ_RETVAL(int_work); 6076 } 6077 6078 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6079 u32 int_st) 6080 { 6081 struct pci_dev *pdev = hr_dev->pci_dev; 6082 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6083 const struct hnae3_ae_ops *ops = ae_dev->ops; 6084 irqreturn_t int_work = IRQ_NONE; 6085 u32 int_en; 6086 6087 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6088 6089 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6090 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6091 6092 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6093 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6094 6095 /* Set reset level for reset_event() */ 6096 if (ops->set_default_reset_request) 6097 ops->set_default_reset_request(ae_dev, 6098 HNAE3_FUNC_RESET); 6099 if (ops->reset_event) 6100 ops->reset_event(pdev, NULL); 6101 6102 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6103 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6104 6105 int_work = IRQ_HANDLED; 6106 } else { 6107 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6108 } 6109 6110 return IRQ_RETVAL(int_work); 6111 } 6112 6113 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6114 struct fmea_ram_ecc *ecc_info) 6115 { 6116 struct hns_roce_cmq_desc desc; 6117 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6118 int ret; 6119 6120 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6121 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6122 if (ret) 6123 return ret; 6124 6125 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6126 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6127 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6128 6129 return 0; 6130 } 6131 6132 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6133 { 6134 struct hns_roce_cmq_desc desc; 6135 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6136 u32 addr_upper; 6137 u32 addr_low; 6138 int ret; 6139 6140 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6141 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6142 6143 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6144 if (ret) { 6145 dev_err(hr_dev->dev, 6146 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6147 return ret; 6148 } 6149 6150 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6151 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6152 6153 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6154 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6155 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6156 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6157 6158 return hns_roce_cmq_send(hr_dev, &desc, 1); 6159 } 6160 6161 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6162 { 6163 if (res_type == ECC_RESOURCE_QPC_TIMER || 6164 res_type == ECC_RESOURCE_CQC_TIMER || 6165 res_type == ECC_RESOURCE_SCCC) 6166 return le64_to_cpu(*data); 6167 6168 return le64_to_cpu(*data) << PAGE_SHIFT; 6169 } 6170 6171 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6172 u32 index) 6173 { 6174 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6175 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6176 struct hns_roce_cmd_mailbox *mailbox; 6177 u64 addr; 6178 int ret; 6179 6180 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6181 if (IS_ERR(mailbox)) 6182 return PTR_ERR(mailbox); 6183 6184 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6185 if (ret) { 6186 dev_err(hr_dev->dev, 6187 "failed to execute cmd to read fmea ram, ret = %d.\n", 6188 ret); 6189 goto out; 6190 } 6191 6192 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6193 6194 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6195 if (ret) 6196 dev_err(hr_dev->dev, 6197 "failed to execute cmd to write fmea ram, ret = %d.\n", 6198 ret); 6199 6200 out: 6201 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6202 return ret; 6203 } 6204 6205 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6206 struct fmea_ram_ecc *ecc_info) 6207 { 6208 u32 res_type = ecc_info->res_type; 6209 u32 index = ecc_info->index; 6210 int ret; 6211 6212 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6213 6214 if (res_type >= ECC_RESOURCE_COUNT) { 6215 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6216 res_type); 6217 return; 6218 } 6219 6220 if (res_type == ECC_RESOURCE_GMV) 6221 ret = fmea_recover_gmv(hr_dev, index); 6222 else 6223 ret = fmea_recover_others(hr_dev, res_type, index); 6224 if (ret) 6225 dev_err(hr_dev->dev, 6226 "failed to recover %s, index = %u, ret = %d.\n", 6227 fmea_ram_res[res_type].name, index, ret); 6228 } 6229 6230 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6231 { 6232 struct hns_roce_dev *hr_dev = 6233 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6234 struct fmea_ram_ecc ecc_info = {}; 6235 6236 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6237 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6238 return; 6239 } 6240 6241 if (!ecc_info.is_ecc_err) { 6242 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6243 return; 6244 } 6245 6246 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6247 } 6248 6249 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6250 { 6251 struct hns_roce_dev *hr_dev = dev_id; 6252 irqreturn_t int_work = IRQ_NONE; 6253 u32 int_st; 6254 6255 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6256 6257 if (int_st) { 6258 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6259 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6260 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6261 int_work = IRQ_HANDLED; 6262 } else { 6263 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6264 } 6265 6266 return IRQ_RETVAL(int_work); 6267 } 6268 6269 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6270 int eq_num, u32 enable_flag) 6271 { 6272 int i; 6273 6274 for (i = 0; i < eq_num; i++) 6275 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6276 i * EQ_REG_OFFSET, enable_flag); 6277 6278 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6279 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6280 } 6281 6282 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6283 { 6284 struct device *dev = hr_dev->dev; 6285 int ret; 6286 u8 cmd; 6287 6288 if (eqn < hr_dev->caps.num_comp_vectors) 6289 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6290 else 6291 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6292 6293 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6294 if (ret) 6295 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6296 } 6297 6298 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6299 { 6300 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6301 } 6302 6303 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6304 { 6305 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6306 eq->cons_index = 0; 6307 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6308 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6309 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6310 eq->shift = ilog2((unsigned int)eq->entries); 6311 } 6312 6313 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6314 void *mb_buf) 6315 { 6316 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6317 struct hns_roce_eq_context *eqc; 6318 u64 bt_ba = 0; 6319 int count; 6320 6321 eqc = mb_buf; 6322 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6323 6324 init_eq_config(hr_dev, eq); 6325 6326 /* if not multi-hop, eqe buffer only use one trunk */ 6327 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6328 &bt_ba); 6329 if (count < 1) { 6330 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6331 return -ENOBUFS; 6332 } 6333 6334 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6335 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6336 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6337 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6338 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6339 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6340 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6341 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6342 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6343 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6344 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6345 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6346 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6347 6348 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6349 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6350 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6351 eq->eq_period); 6352 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6353 } 6354 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6355 } 6356 6357 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6358 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6359 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6360 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6361 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6362 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6363 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6364 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6365 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6366 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6367 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6368 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6369 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6370 6371 return 0; 6372 } 6373 6374 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6375 { 6376 struct hns_roce_buf_attr buf_attr = {}; 6377 int err; 6378 6379 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6380 eq->hop_num = 0; 6381 else 6382 eq->hop_num = hr_dev->caps.eqe_hop_num; 6383 6384 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6385 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6386 buf_attr.region[0].hopnum = eq->hop_num; 6387 buf_attr.region_count = 1; 6388 6389 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6390 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6391 0); 6392 if (err) 6393 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6394 6395 return err; 6396 } 6397 6398 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6399 struct hns_roce_eq *eq, u8 eq_cmd) 6400 { 6401 struct hns_roce_cmd_mailbox *mailbox; 6402 int ret; 6403 6404 /* Allocate mailbox memory */ 6405 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6406 if (IS_ERR(mailbox)) 6407 return PTR_ERR(mailbox); 6408 6409 ret = alloc_eq_buf(hr_dev, eq); 6410 if (ret) 6411 goto free_cmd_mbox; 6412 6413 ret = config_eqc(hr_dev, eq, mailbox->buf); 6414 if (ret) 6415 goto err_cmd_mbox; 6416 6417 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6418 if (ret) { 6419 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6420 goto err_cmd_mbox; 6421 } 6422 6423 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6424 6425 return 0; 6426 6427 err_cmd_mbox: 6428 free_eq_buf(hr_dev, eq); 6429 6430 free_cmd_mbox: 6431 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6432 6433 return ret; 6434 } 6435 6436 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6437 int comp_num, int aeq_num, int other_num) 6438 { 6439 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6440 int i, j; 6441 int ret; 6442 6443 for (i = 0; i < irq_num; i++) { 6444 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6445 GFP_KERNEL); 6446 if (!hr_dev->irq_names[i]) { 6447 ret = -ENOMEM; 6448 goto err_kzalloc_failed; 6449 } 6450 } 6451 6452 /* irq contains: abnormal + AEQ + CEQ */ 6453 for (j = 0; j < other_num; j++) 6454 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6455 "hns-abn-%d", j); 6456 6457 for (j = other_num; j < (other_num + aeq_num); j++) 6458 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6459 "hns-aeq-%d", j - other_num); 6460 6461 for (j = (other_num + aeq_num); j < irq_num; j++) 6462 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6463 "hns-ceq-%d", j - other_num - aeq_num); 6464 6465 for (j = 0; j < irq_num; j++) { 6466 if (j < other_num) 6467 ret = request_irq(hr_dev->irq[j], 6468 hns_roce_v2_msix_interrupt_abn, 6469 0, hr_dev->irq_names[j], hr_dev); 6470 6471 else if (j < (other_num + comp_num)) 6472 ret = request_irq(eq_table->eq[j - other_num].irq, 6473 hns_roce_v2_msix_interrupt_eq, 6474 0, hr_dev->irq_names[j + aeq_num], 6475 &eq_table->eq[j - other_num]); 6476 else 6477 ret = request_irq(eq_table->eq[j - other_num].irq, 6478 hns_roce_v2_msix_interrupt_eq, 6479 0, hr_dev->irq_names[j - comp_num], 6480 &eq_table->eq[j - other_num]); 6481 if (ret) { 6482 dev_err(hr_dev->dev, "request irq error!\n"); 6483 goto err_request_failed; 6484 } 6485 } 6486 6487 return 0; 6488 6489 err_request_failed: 6490 for (j -= 1; j >= 0; j--) 6491 if (j < other_num) 6492 free_irq(hr_dev->irq[j], hr_dev); 6493 else 6494 free_irq(eq_table->eq[j - other_num].irq, 6495 &eq_table->eq[j - other_num]); 6496 6497 err_kzalloc_failed: 6498 for (i -= 1; i >= 0; i--) 6499 kfree(hr_dev->irq_names[i]); 6500 6501 return ret; 6502 } 6503 6504 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6505 { 6506 int irq_num; 6507 int eq_num; 6508 int i; 6509 6510 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6511 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6512 6513 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6514 free_irq(hr_dev->irq[i], hr_dev); 6515 6516 for (i = 0; i < eq_num; i++) 6517 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6518 6519 for (i = 0; i < irq_num; i++) 6520 kfree(hr_dev->irq_names[i]); 6521 } 6522 6523 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6524 { 6525 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6526 struct device *dev = hr_dev->dev; 6527 struct hns_roce_eq *eq; 6528 int other_num; 6529 int comp_num; 6530 int aeq_num; 6531 int irq_num; 6532 int eq_num; 6533 u8 eq_cmd; 6534 int ret; 6535 int i; 6536 6537 other_num = hr_dev->caps.num_other_vectors; 6538 comp_num = hr_dev->caps.num_comp_vectors; 6539 aeq_num = hr_dev->caps.num_aeq_vectors; 6540 6541 eq_num = comp_num + aeq_num; 6542 irq_num = eq_num + other_num; 6543 6544 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6545 if (!eq_table->eq) 6546 return -ENOMEM; 6547 6548 /* create eq */ 6549 for (i = 0; i < eq_num; i++) { 6550 eq = &eq_table->eq[i]; 6551 eq->hr_dev = hr_dev; 6552 eq->eqn = i; 6553 if (i < comp_num) { 6554 /* CEQ */ 6555 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6556 eq->type_flag = HNS_ROCE_CEQ; 6557 eq->entries = hr_dev->caps.ceqe_depth; 6558 eq->eqe_size = hr_dev->caps.ceqe_size; 6559 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6560 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6561 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6562 } else { 6563 /* AEQ */ 6564 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6565 eq->type_flag = HNS_ROCE_AEQ; 6566 eq->entries = hr_dev->caps.aeqe_depth; 6567 eq->eqe_size = hr_dev->caps.aeqe_size; 6568 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6569 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6570 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6571 } 6572 6573 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6574 if (ret) { 6575 dev_err(dev, "failed to create eq.\n"); 6576 goto err_create_eq_fail; 6577 } 6578 } 6579 6580 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6581 6582 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6583 if (!hr_dev->irq_workq) { 6584 dev_err(dev, "failed to create irq workqueue.\n"); 6585 ret = -ENOMEM; 6586 goto err_create_eq_fail; 6587 } 6588 6589 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6590 other_num); 6591 if (ret) { 6592 dev_err(dev, "failed to request irq.\n"); 6593 goto err_request_irq_fail; 6594 } 6595 6596 /* enable irq */ 6597 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6598 6599 return 0; 6600 6601 err_request_irq_fail: 6602 destroy_workqueue(hr_dev->irq_workq); 6603 6604 err_create_eq_fail: 6605 for (i -= 1; i >= 0; i--) 6606 free_eq_buf(hr_dev, &eq_table->eq[i]); 6607 kfree(eq_table->eq); 6608 6609 return ret; 6610 } 6611 6612 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6613 { 6614 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6615 int eq_num; 6616 int i; 6617 6618 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6619 6620 /* Disable irq */ 6621 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6622 6623 __hns_roce_free_irq(hr_dev); 6624 destroy_workqueue(hr_dev->irq_workq); 6625 6626 for (i = 0; i < eq_num; i++) { 6627 hns_roce_v2_destroy_eqc(hr_dev, i); 6628 6629 free_eq_buf(hr_dev, &eq_table->eq[i]); 6630 } 6631 6632 kfree(eq_table->eq); 6633 } 6634 6635 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6636 .destroy_qp = hns_roce_v2_destroy_qp, 6637 .modify_cq = hns_roce_v2_modify_cq, 6638 .poll_cq = hns_roce_v2_poll_cq, 6639 .post_recv = hns_roce_v2_post_recv, 6640 .post_send = hns_roce_v2_post_send, 6641 .query_qp = hns_roce_v2_query_qp, 6642 .req_notify_cq = hns_roce_v2_req_notify_cq, 6643 }; 6644 6645 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6646 .modify_srq = hns_roce_v2_modify_srq, 6647 .post_srq_recv = hns_roce_v2_post_srq_recv, 6648 .query_srq = hns_roce_v2_query_srq, 6649 }; 6650 6651 static const struct hns_roce_hw hns_roce_hw_v2 = { 6652 .cmq_init = hns_roce_v2_cmq_init, 6653 .cmq_exit = hns_roce_v2_cmq_exit, 6654 .hw_profile = hns_roce_v2_profile, 6655 .hw_init = hns_roce_v2_init, 6656 .hw_exit = hns_roce_v2_exit, 6657 .post_mbox = v2_post_mbox, 6658 .poll_mbox_done = v2_poll_mbox_done, 6659 .chk_mbox_avail = v2_chk_mbox_is_avail, 6660 .set_gid = hns_roce_v2_set_gid, 6661 .set_mac = hns_roce_v2_set_mac, 6662 .write_mtpt = hns_roce_v2_write_mtpt, 6663 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6664 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6665 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6666 .write_cqc = hns_roce_v2_write_cqc, 6667 .set_hem = hns_roce_v2_set_hem, 6668 .clear_hem = hns_roce_v2_clear_hem, 6669 .modify_qp = hns_roce_v2_modify_qp, 6670 .dereg_mr = hns_roce_v2_dereg_mr, 6671 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6672 .init_eq = hns_roce_v2_init_eq_table, 6673 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6674 .write_srqc = hns_roce_v2_write_srqc, 6675 .query_cqc = hns_roce_v2_query_cqc, 6676 .query_qpc = hns_roce_v2_query_qpc, 6677 .query_mpt = hns_roce_v2_query_mpt, 6678 .query_srqc = hns_roce_v2_query_srqc, 6679 .query_hw_counter = hns_roce_hw_v2_query_counter, 6680 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6681 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6682 }; 6683 6684 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6685 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6686 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6687 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6688 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6689 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6690 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6691 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6692 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6693 /* required last entry */ 6694 {0, } 6695 }; 6696 6697 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6698 6699 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6700 struct hnae3_handle *handle) 6701 { 6702 struct hns_roce_v2_priv *priv = hr_dev->priv; 6703 const struct pci_device_id *id; 6704 int i; 6705 6706 hr_dev->pci_dev = handle->pdev; 6707 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6708 hr_dev->is_vf = id->driver_data; 6709 hr_dev->dev = &handle->pdev->dev; 6710 hr_dev->hw = &hns_roce_hw_v2; 6711 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6712 hr_dev->odb_offset = hr_dev->sdb_offset; 6713 6714 /* Get info from NIC driver. */ 6715 hr_dev->reg_base = handle->rinfo.roce_io_base; 6716 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6717 hr_dev->caps.num_ports = 1; 6718 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6719 hr_dev->iboe.phy_port[0] = 0; 6720 6721 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6722 hr_dev->iboe.netdevs[0]->dev_addr); 6723 6724 for (i = 0; i < handle->rinfo.num_vectors; i++) 6725 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6726 i + handle->rinfo.base_vector); 6727 6728 /* cmd issue mode: 0 is poll, 1 is event */ 6729 hr_dev->cmd_mod = 1; 6730 hr_dev->loop_idc = 0; 6731 6732 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6733 priv->handle = handle; 6734 } 6735 6736 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6737 { 6738 struct hns_roce_dev *hr_dev; 6739 int ret; 6740 6741 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6742 if (!hr_dev) 6743 return -ENOMEM; 6744 6745 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6746 if (!hr_dev->priv) { 6747 ret = -ENOMEM; 6748 goto error_failed_kzalloc; 6749 } 6750 6751 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6752 6753 ret = hns_roce_init(hr_dev); 6754 if (ret) { 6755 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6756 goto error_failed_roce_init; 6757 } 6758 6759 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6760 ret = free_mr_init(hr_dev); 6761 if (ret) { 6762 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6763 goto error_failed_free_mr_init; 6764 } 6765 } 6766 6767 handle->priv = hr_dev; 6768 6769 return 0; 6770 6771 error_failed_free_mr_init: 6772 hns_roce_exit(hr_dev); 6773 6774 error_failed_roce_init: 6775 kfree(hr_dev->priv); 6776 6777 error_failed_kzalloc: 6778 ib_dealloc_device(&hr_dev->ib_dev); 6779 6780 return ret; 6781 } 6782 6783 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6784 bool reset) 6785 { 6786 struct hns_roce_dev *hr_dev = handle->priv; 6787 6788 if (!hr_dev) 6789 return; 6790 6791 handle->priv = NULL; 6792 6793 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6794 hns_roce_handle_device_err(hr_dev); 6795 6796 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6797 free_mr_exit(hr_dev); 6798 6799 hns_roce_exit(hr_dev); 6800 kfree(hr_dev->priv); 6801 ib_dealloc_device(&hr_dev->ib_dev); 6802 } 6803 6804 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6805 { 6806 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6807 const struct pci_device_id *id; 6808 struct device *dev = &handle->pdev->dev; 6809 int ret; 6810 6811 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6812 6813 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6814 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6815 goto reset_chk_err; 6816 } 6817 6818 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6819 if (!id) 6820 return 0; 6821 6822 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6823 return 0; 6824 6825 ret = __hns_roce_hw_v2_init_instance(handle); 6826 if (ret) { 6827 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6828 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6829 if (ops->ae_dev_resetting(handle) || 6830 ops->get_hw_reset_stat(handle)) 6831 goto reset_chk_err; 6832 else 6833 return ret; 6834 } 6835 6836 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6837 6838 return 0; 6839 6840 reset_chk_err: 6841 dev_err(dev, "Device is busy in resetting state.\n" 6842 "please retry later.\n"); 6843 6844 return -EBUSY; 6845 } 6846 6847 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6848 bool reset) 6849 { 6850 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6851 return; 6852 6853 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6854 6855 __hns_roce_hw_v2_uninit_instance(handle, reset); 6856 6857 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6858 } 6859 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6860 { 6861 struct hns_roce_dev *hr_dev; 6862 6863 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6864 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6865 return 0; 6866 } 6867 6868 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6869 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6870 6871 hr_dev = handle->priv; 6872 if (!hr_dev) 6873 return 0; 6874 6875 hr_dev->active = false; 6876 hr_dev->dis_db = true; 6877 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6878 6879 return 0; 6880 } 6881 6882 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6883 { 6884 struct device *dev = &handle->pdev->dev; 6885 int ret; 6886 6887 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6888 &handle->rinfo.state)) { 6889 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6890 return 0; 6891 } 6892 6893 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6894 6895 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6896 ret = __hns_roce_hw_v2_init_instance(handle); 6897 if (ret) { 6898 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6899 * callback function, RoCE Engine reinitialize. If RoCE reinit 6900 * failed, we should inform NIC driver. 6901 */ 6902 handle->priv = NULL; 6903 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6904 } else { 6905 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6906 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6907 } 6908 6909 return ret; 6910 } 6911 6912 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6913 { 6914 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6915 return 0; 6916 6917 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6918 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6919 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6920 __hns_roce_hw_v2_uninit_instance(handle, false); 6921 6922 return 0; 6923 } 6924 6925 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6926 enum hnae3_reset_notify_type type) 6927 { 6928 int ret = 0; 6929 6930 switch (type) { 6931 case HNAE3_DOWN_CLIENT: 6932 ret = hns_roce_hw_v2_reset_notify_down(handle); 6933 break; 6934 case HNAE3_INIT_CLIENT: 6935 ret = hns_roce_hw_v2_reset_notify_init(handle); 6936 break; 6937 case HNAE3_UNINIT_CLIENT: 6938 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6939 break; 6940 default: 6941 break; 6942 } 6943 6944 return ret; 6945 } 6946 6947 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6948 .init_instance = hns_roce_hw_v2_init_instance, 6949 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6950 .reset_notify = hns_roce_hw_v2_reset_notify, 6951 }; 6952 6953 static struct hnae3_client hns_roce_hw_v2_client = { 6954 .name = "hns_roce_hw_v2", 6955 .type = HNAE3_CLIENT_ROCE, 6956 .ops = &hns_roce_hw_v2_ops, 6957 }; 6958 6959 static int __init hns_roce_hw_v2_init(void) 6960 { 6961 return hnae3_register_client(&hns_roce_hw_v2_client); 6962 } 6963 6964 static void __exit hns_roce_hw_v2_exit(void) 6965 { 6966 hnae3_unregister_client(&hns_roce_hw_v2_client); 6967 } 6968 6969 module_init(hns_roce_hw_v2_init); 6970 module_exit(hns_roce_hw_v2_exit); 6971 6972 MODULE_LICENSE("Dual BSD/GPL"); 6973 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6974 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6975 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6976 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6977