1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 123 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 124 }; 125 126 static u32 to_hr_opcode(u32 ib_opcode) 127 { 128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 129 return HNS_ROCE_V2_WQE_OP_MASK; 130 131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 132 HNS_ROCE_V2_WQE_OP_MASK; 133 } 134 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 136 const struct ib_reg_wr *wr) 137 { 138 struct hns_roce_wqe_frmr_seg *fseg = 139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 140 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 141 u64 pbl_ba; 142 143 /* use ib_access_flags */ 144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 145 hr_reg_write_bool(fseg, FRMR_ATOMIC, 146 wr->access & IB_ACCESS_REMOTE_ATOMIC); 147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 150 151 /* Data structure reuse may lead to confusion */ 152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 155 156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 158 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 160 161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 164 hr_reg_clear(fseg, FRMR_BLK_MODE); 165 } 166 167 static void set_atomic_seg(const struct ib_send_wr *wr, 168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 169 unsigned int valid_num_sge) 170 { 171 struct hns_roce_v2_wqe_data_seg *dseg = 172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 173 struct hns_roce_wqe_atomic_seg *aseg = 174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 175 176 set_data_seg_v2(dseg, wr->sg_list); 177 178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 181 } else { 182 aseg->fetchadd_swap_data = 183 cpu_to_le64(atomic_wr(wr)->compare_add); 184 aseg->cmp_data = 0; 185 } 186 187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 188 } 189 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 191 const struct ib_send_wr *wr, 192 unsigned int *sge_idx, u32 msg_len) 193 { 194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 195 unsigned int left_len_in_pg; 196 unsigned int idx = *sge_idx; 197 unsigned int i = 0; 198 unsigned int len; 199 void *addr; 200 void *dseg; 201 202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 203 ibdev_err(ibdev, 204 "no enough extended sge space for inline data.\n"); 205 return -EINVAL; 206 } 207 208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 210 len = wr->sg_list[0].length; 211 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 212 213 /* When copying data to extended sge space, the left length in page may 214 * not long enough for current user's sge. So the data should be 215 * splited into several parts, one in the first page, and the others in 216 * the subsequent pages. 217 */ 218 while (1) { 219 if (len <= left_len_in_pg) { 220 memcpy(dseg, addr, len); 221 222 idx += len / HNS_ROCE_SGE_SIZE; 223 224 i++; 225 if (i >= wr->num_sge) 226 break; 227 228 left_len_in_pg -= len; 229 len = wr->sg_list[i].length; 230 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 231 dseg += len; 232 } else { 233 memcpy(dseg, addr, left_len_in_pg); 234 235 len -= left_len_in_pg; 236 addr += left_len_in_pg; 237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 238 dseg = hns_roce_get_extend_sge(qp, 239 idx & (qp->sge.sge_cnt - 1)); 240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 241 } 242 } 243 244 *sge_idx = idx; 245 246 return 0; 247 } 248 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 250 unsigned int *sge_ind, unsigned int cnt) 251 { 252 struct hns_roce_v2_wqe_data_seg *dseg; 253 unsigned int idx = *sge_ind; 254 255 while (cnt > 0) { 256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 257 if (likely(sge->length)) { 258 set_data_seg_v2(dseg, sge); 259 idx++; 260 cnt--; 261 } 262 sge++; 263 } 264 265 *sge_ind = idx; 266 } 267 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 269 { 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 274 ibdev_err(&hr_dev->ib_dev, 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 len, qp->max_inline_data, mtu); 277 return false; 278 } 279 280 return true; 281 } 282 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 285 unsigned int *sge_idx) 286 { 287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 289 struct ib_device *ibdev = &hr_dev->ib_dev; 290 unsigned int curr_idx = *sge_idx; 291 void *dseg = rc_sq_wqe; 292 unsigned int i; 293 int ret; 294 295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 296 ibdev_err(ibdev, "invalid inline parameters!\n"); 297 return -EINVAL; 298 } 299 300 if (!check_inl_data_len(qp, msg_len)) 301 return -EINVAL; 302 303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 304 305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 307 308 for (i = 0; i < wr->num_sge; i++) { 309 memcpy(dseg, ((void *)wr->sg_list[i].addr), 310 wr->sg_list[i].length); 311 dseg += wr->sg_list[i].length; 312 } 313 } else { 314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 317 if (ret) 318 return ret; 319 320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 321 } 322 323 *sge_idx = curr_idx; 324 325 return 0; 326 } 327 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 330 unsigned int *sge_ind, 331 unsigned int valid_num_sge) 332 { 333 struct hns_roce_v2_wqe_data_seg *dseg = 334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 335 struct hns_roce_qp *qp = to_hr_qp(ibqp); 336 int j = 0; 337 int i; 338 339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 340 (*sge_ind) & (qp->sge.sge_cnt - 1)); 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 343 !!(wr->send_flags & IB_SEND_INLINE)); 344 if (wr->send_flags & IB_SEND_INLINE) 345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 346 347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 348 for (i = 0; i < wr->num_sge; i++) { 349 if (likely(wr->sg_list[i].length)) { 350 set_data_seg_v2(dseg, wr->sg_list + i); 351 dseg++; 352 } 353 } 354 } else { 355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 356 if (likely(wr->sg_list[i].length)) { 357 set_data_seg_v2(dseg, wr->sg_list + i); 358 dseg++; 359 j++; 360 } 361 } 362 363 set_extend_sge(qp, wr->sg_list + i, sge_ind, 364 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 365 } 366 367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 368 369 return 0; 370 } 371 372 static int check_send_valid(struct hns_roce_dev *hr_dev, 373 struct hns_roce_qp *hr_qp) 374 { 375 struct ib_device *ibdev = &hr_dev->ib_dev; 376 377 if (unlikely(hr_qp->state == IB_QPS_RESET || 378 hr_qp->state == IB_QPS_INIT || 379 hr_qp->state == IB_QPS_RTR)) { 380 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 381 hr_qp->state); 382 return -EINVAL; 383 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 384 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 385 hr_dev->state); 386 return -EIO; 387 } 388 389 return 0; 390 } 391 392 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 393 unsigned int *sge_len) 394 { 395 unsigned int valid_num = 0; 396 unsigned int len = 0; 397 int i; 398 399 for (i = 0; i < wr->num_sge; i++) { 400 if (likely(wr->sg_list[i].length)) { 401 len += wr->sg_list[i].length; 402 valid_num++; 403 } 404 } 405 406 *sge_len = len; 407 return valid_num; 408 } 409 410 static __le32 get_immtdata(const struct ib_send_wr *wr) 411 { 412 switch (wr->opcode) { 413 case IB_WR_SEND_WITH_IMM: 414 case IB_WR_RDMA_WRITE_WITH_IMM: 415 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 416 default: 417 return 0; 418 } 419 } 420 421 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 422 const struct ib_send_wr *wr) 423 { 424 u32 ib_op = wr->opcode; 425 426 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 427 return -EINVAL; 428 429 ud_sq_wqe->immtdata = get_immtdata(wr); 430 431 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 432 433 return 0; 434 } 435 436 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 437 struct hns_roce_ah *ah) 438 { 439 struct ib_device *ib_dev = ah->ibah.device; 440 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 441 442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 445 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 446 447 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 448 return -EINVAL; 449 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 451 452 ud_sq_wqe->sgid_index = ah->av.gid_index; 453 454 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 455 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 456 457 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 458 return 0; 459 460 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 461 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 462 463 return 0; 464 } 465 466 static inline int set_ud_wqe(struct hns_roce_qp *qp, 467 const struct ib_send_wr *wr, 468 void *wqe, unsigned int *sge_idx, 469 unsigned int owner_bit) 470 { 471 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 472 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 473 unsigned int curr_idx = *sge_idx; 474 unsigned int valid_num_sge; 475 u32 msg_len = 0; 476 int ret; 477 478 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 479 480 ret = set_ud_opcode(ud_sq_wqe, wr); 481 if (WARN_ON(ret)) 482 return ret; 483 484 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 485 486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 487 !!(wr->send_flags & IB_SEND_SIGNALED)); 488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 489 !!(wr->send_flags & IB_SEND_SOLICITED)); 490 491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 494 curr_idx & (qp->sge.sge_cnt - 1)); 495 496 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 497 qp->qkey : ud_wr(wr)->remote_qkey); 498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 499 500 ret = fill_ud_av(ud_sq_wqe, ah); 501 if (ret) 502 return ret; 503 504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 505 506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 507 508 /* 509 * The pipeline can sequentially post all valid WQEs into WQ buffer, 510 * including new WQEs waiting for the doorbell to update the PI again. 511 * Therefore, the owner bit of WQE MUST be updated after all fields 512 * and extSGEs have been written into DDR instead of cache. 513 */ 514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 515 dma_wmb(); 516 517 *sge_idx = curr_idx; 518 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 519 520 return 0; 521 } 522 523 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 524 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 525 const struct ib_send_wr *wr) 526 { 527 u32 ib_op = wr->opcode; 528 int ret = 0; 529 530 rc_sq_wqe->immtdata = get_immtdata(wr); 531 532 switch (ib_op) { 533 case IB_WR_RDMA_READ: 534 case IB_WR_RDMA_WRITE: 535 case IB_WR_RDMA_WRITE_WITH_IMM: 536 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 537 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 538 break; 539 case IB_WR_SEND: 540 case IB_WR_SEND_WITH_IMM: 541 break; 542 case IB_WR_ATOMIC_CMP_AND_SWP: 543 case IB_WR_ATOMIC_FETCH_AND_ADD: 544 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 545 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 546 break; 547 case IB_WR_REG_MR: 548 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 549 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 550 else 551 ret = -EOPNOTSUPP; 552 break; 553 case IB_WR_SEND_WITH_INV: 554 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 555 break; 556 default: 557 ret = -EINVAL; 558 } 559 560 if (unlikely(ret)) 561 return ret; 562 563 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 564 565 return ret; 566 } 567 568 static inline int set_rc_wqe(struct hns_roce_qp *qp, 569 const struct ib_send_wr *wr, 570 void *wqe, unsigned int *sge_idx, 571 unsigned int owner_bit) 572 { 573 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 574 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 575 unsigned int curr_idx = *sge_idx; 576 unsigned int valid_num_sge; 577 u32 msg_len = 0; 578 int ret; 579 580 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 581 582 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 583 584 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 585 if (WARN_ON(ret)) 586 return ret; 587 588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 589 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 590 591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 592 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 593 594 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 595 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 596 597 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 598 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 599 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 600 else if (wr->opcode != IB_WR_REG_MR) 601 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 602 &curr_idx, valid_num_sge); 603 604 /* 605 * The pipeline can sequentially post all valid WQEs into WQ buffer, 606 * including new WQEs waiting for the doorbell to update the PI again. 607 * Therefore, the owner bit of WQE MUST be updated after all fields 608 * and extSGEs have been written into DDR instead of cache. 609 */ 610 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 611 dma_wmb(); 612 613 *sge_idx = curr_idx; 614 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 615 616 return ret; 617 } 618 619 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 620 struct hns_roce_qp *qp) 621 { 622 if (unlikely(qp->state == IB_QPS_ERR)) { 623 flush_cqe(hr_dev, qp); 624 } else { 625 struct hns_roce_v2_db sq_db = {}; 626 627 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 628 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 629 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 630 hr_reg_write(&sq_db, DB_SL, qp->sl); 631 632 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 633 } 634 } 635 636 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 637 struct hns_roce_qp *qp) 638 { 639 if (unlikely(qp->state == IB_QPS_ERR)) { 640 flush_cqe(hr_dev, qp); 641 } else { 642 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 643 *qp->rdb.db_record = 644 qp->rq.head & V2_DB_PRODUCER_IDX_M; 645 } else { 646 struct hns_roce_v2_db rq_db = {}; 647 648 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 649 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 650 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 651 652 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 653 qp->rq.db_reg); 654 } 655 } 656 } 657 658 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 659 u64 __iomem *dest) 660 { 661 #define HNS_ROCE_WRITE_TIMES 8 662 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 663 struct hnae3_handle *handle = priv->handle; 664 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 665 int i; 666 667 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 668 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 669 writeq_relaxed(*(val + i), dest + i); 670 } 671 672 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 673 void *wqe) 674 { 675 #define HNS_ROCE_SL_SHIFT 2 676 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 677 678 /* All kinds of DirectWQE have the same header field layout */ 679 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 680 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 682 qp->sl >> HNS_ROCE_SL_SHIFT); 683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 684 685 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 686 } 687 688 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 689 const struct ib_send_wr *wr, 690 const struct ib_send_wr **bad_wr) 691 { 692 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 693 struct ib_device *ibdev = &hr_dev->ib_dev; 694 struct hns_roce_qp *qp = to_hr_qp(ibqp); 695 unsigned long flags = 0; 696 unsigned int owner_bit; 697 unsigned int sge_idx; 698 unsigned int wqe_idx; 699 void *wqe = NULL; 700 u32 nreq; 701 int ret; 702 703 spin_lock_irqsave(&qp->sq.lock, flags); 704 705 ret = check_send_valid(hr_dev, qp); 706 if (unlikely(ret)) { 707 *bad_wr = wr; 708 nreq = 0; 709 goto out; 710 } 711 712 sge_idx = qp->next_sge; 713 714 for (nreq = 0; wr; ++nreq, wr = wr->next) { 715 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 716 ret = -ENOMEM; 717 *bad_wr = wr; 718 goto out; 719 } 720 721 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 722 723 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 724 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 725 wr->num_sge, qp->sq.max_gs); 726 ret = -EINVAL; 727 *bad_wr = wr; 728 goto out; 729 } 730 731 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 732 qp->sq.wrid[wqe_idx] = wr->wr_id; 733 owner_bit = 734 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 735 736 /* Corresponding to the QP type, wqe process separately */ 737 if (ibqp->qp_type == IB_QPT_RC) 738 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 739 else 740 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 741 742 if (unlikely(ret)) { 743 *bad_wr = wr; 744 goto out; 745 } 746 } 747 748 out: 749 if (likely(nreq)) { 750 qp->sq.head += nreq; 751 qp->next_sge = sge_idx; 752 753 if (nreq == 1 && !ret && 754 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 755 write_dwqe(hr_dev, qp, wqe); 756 else 757 update_sq_db(hr_dev, qp); 758 } 759 760 spin_unlock_irqrestore(&qp->sq.lock, flags); 761 762 return ret; 763 } 764 765 static int check_recv_valid(struct hns_roce_dev *hr_dev, 766 struct hns_roce_qp *hr_qp) 767 { 768 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 769 return -EIO; 770 771 if (hr_qp->state == IB_QPS_RESET) 772 return -EINVAL; 773 774 return 0; 775 } 776 777 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 778 u32 max_sge, bool rsv) 779 { 780 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 781 u32 i, cnt; 782 783 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 784 /* Skip zero-length sge */ 785 if (!wr->sg_list[i].length) 786 continue; 787 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 788 cnt++; 789 } 790 791 /* Fill a reserved sge to make hw stop reading remaining segments */ 792 if (rsv) { 793 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 794 dseg[cnt].addr = 0; 795 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 796 } else { 797 /* Clear remaining segments to make ROCEE ignore sges */ 798 if (cnt < max_sge) 799 memset(dseg + cnt, 0, 800 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 801 } 802 } 803 804 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 805 u32 wqe_idx, u32 max_sge) 806 { 807 void *wqe = NULL; 808 809 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 810 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 811 } 812 813 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 814 const struct ib_recv_wr *wr, 815 const struct ib_recv_wr **bad_wr) 816 { 817 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 818 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 819 struct ib_device *ibdev = &hr_dev->ib_dev; 820 u32 wqe_idx, nreq, max_sge; 821 unsigned long flags; 822 int ret; 823 824 spin_lock_irqsave(&hr_qp->rq.lock, flags); 825 826 ret = check_recv_valid(hr_dev, hr_qp); 827 if (unlikely(ret)) { 828 *bad_wr = wr; 829 nreq = 0; 830 goto out; 831 } 832 833 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 834 for (nreq = 0; wr; ++nreq, wr = wr->next) { 835 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 836 hr_qp->ibqp.recv_cq))) { 837 ret = -ENOMEM; 838 *bad_wr = wr; 839 goto out; 840 } 841 842 if (unlikely(wr->num_sge > max_sge)) { 843 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 844 wr->num_sge, max_sge); 845 ret = -EINVAL; 846 *bad_wr = wr; 847 goto out; 848 } 849 850 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 851 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 852 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 853 } 854 855 out: 856 if (likely(nreq)) { 857 hr_qp->rq.head += nreq; 858 859 update_rq_db(hr_dev, hr_qp); 860 } 861 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 862 863 return ret; 864 } 865 866 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 867 { 868 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 869 } 870 871 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 872 { 873 return hns_roce_buf_offset(idx_que->mtr.kmem, 874 n << idx_que->entry_shift); 875 } 876 877 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 878 { 879 /* always called with interrupts disabled. */ 880 spin_lock(&srq->lock); 881 882 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 883 srq->idx_que.tail++; 884 885 spin_unlock(&srq->lock); 886 } 887 888 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 889 { 890 struct hns_roce_idx_que *idx_que = &srq->idx_que; 891 892 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 893 } 894 895 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 896 const struct ib_recv_wr *wr) 897 { 898 struct ib_device *ib_dev = srq->ibsrq.device; 899 900 if (unlikely(wr->num_sge > max_sge)) { 901 ibdev_err(ib_dev, 902 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 903 wr->num_sge, max_sge); 904 return -EINVAL; 905 } 906 907 if (unlikely(hns_roce_srqwq_overflow(srq))) { 908 ibdev_err(ib_dev, 909 "failed to check srqwq status, srqwq is full.\n"); 910 return -ENOMEM; 911 } 912 913 return 0; 914 } 915 916 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 917 { 918 struct hns_roce_idx_que *idx_que = &srq->idx_que; 919 u32 pos; 920 921 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 922 if (unlikely(pos == srq->wqe_cnt)) 923 return -ENOSPC; 924 925 bitmap_set(idx_que->bitmap, pos, 1); 926 *wqe_idx = pos; 927 return 0; 928 } 929 930 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 931 { 932 struct hns_roce_idx_que *idx_que = &srq->idx_que; 933 unsigned int head; 934 __le32 *buf; 935 936 head = idx_que->head & (srq->wqe_cnt - 1); 937 938 buf = get_idx_buf(idx_que, head); 939 *buf = cpu_to_le32(wqe_idx); 940 941 idx_que->head++; 942 } 943 944 static void update_srq_db(struct hns_roce_srq *srq) 945 { 946 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 947 struct hns_roce_v2_db db; 948 949 hr_reg_write(&db, DB_TAG, srq->srqn); 950 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 951 hr_reg_write(&db, DB_PI, srq->idx_que.head); 952 953 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 954 } 955 956 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 957 const struct ib_recv_wr *wr, 958 const struct ib_recv_wr **bad_wr) 959 { 960 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 961 unsigned long flags; 962 int ret = 0; 963 u32 max_sge; 964 u32 wqe_idx; 965 void *wqe; 966 u32 nreq; 967 968 spin_lock_irqsave(&srq->lock, flags); 969 970 max_sge = srq->max_gs - srq->rsv_sge; 971 for (nreq = 0; wr; ++nreq, wr = wr->next) { 972 ret = check_post_srq_valid(srq, max_sge, wr); 973 if (ret) { 974 *bad_wr = wr; 975 break; 976 } 977 978 ret = get_srq_wqe_idx(srq, &wqe_idx); 979 if (unlikely(ret)) { 980 *bad_wr = wr; 981 break; 982 } 983 984 wqe = get_srq_wqe_buf(srq, wqe_idx); 985 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 986 fill_wqe_idx(srq, wqe_idx); 987 srq->wrid[wqe_idx] = wr->wr_id; 988 } 989 990 if (likely(nreq)) { 991 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 992 *srq->rdb.db_record = srq->idx_que.head & 993 V2_DB_PRODUCER_IDX_M; 994 else 995 update_srq_db(srq); 996 } 997 998 spin_unlock_irqrestore(&srq->lock, flags); 999 1000 return ret; 1001 } 1002 1003 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1004 unsigned long instance_stage, 1005 unsigned long reset_stage) 1006 { 1007 /* When hardware reset has been completed once or more, we should stop 1008 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1009 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1010 * stage of soft reset process, we should exit with error, and then 1011 * HNAE3_INIT_CLIENT related process can rollback the operation like 1012 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1013 * process will exit with error to notify NIC driver to reschedule soft 1014 * reset process once again. 1015 */ 1016 hr_dev->is_reset = true; 1017 hr_dev->dis_db = true; 1018 1019 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1020 instance_stage == HNS_ROCE_STATE_INIT) 1021 return CMD_RST_PRC_EBUSY; 1022 1023 return CMD_RST_PRC_SUCCESS; 1024 } 1025 1026 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1027 unsigned long instance_stage, 1028 unsigned long reset_stage) 1029 { 1030 #define HW_RESET_TIMEOUT_US 1000000 1031 #define HW_RESET_SLEEP_US 1000 1032 1033 struct hns_roce_v2_priv *priv = hr_dev->priv; 1034 struct hnae3_handle *handle = priv->handle; 1035 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1036 unsigned long val; 1037 int ret; 1038 1039 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1040 * doorbell to hardware. If now in .init_instance() function, we should 1041 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1042 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1043 * related process can rollback the operation like notifing hardware to 1044 * free resources, HNAE3_INIT_CLIENT related process will exit with 1045 * error to notify NIC driver to reschedule soft reset process once 1046 * again. 1047 */ 1048 hr_dev->dis_db = true; 1049 1050 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1051 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1052 HW_RESET_TIMEOUT_US, false, handle); 1053 if (!ret) 1054 hr_dev->is_reset = true; 1055 1056 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1057 instance_stage == HNS_ROCE_STATE_INIT) 1058 return CMD_RST_PRC_EBUSY; 1059 1060 return CMD_RST_PRC_SUCCESS; 1061 } 1062 1063 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1064 { 1065 struct hns_roce_v2_priv *priv = hr_dev->priv; 1066 struct hnae3_handle *handle = priv->handle; 1067 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1068 1069 /* When software reset is detected at .init_instance() function, we 1070 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1071 * with error. 1072 */ 1073 hr_dev->dis_db = true; 1074 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1075 hr_dev->is_reset = true; 1076 1077 return CMD_RST_PRC_EBUSY; 1078 } 1079 1080 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1081 struct hnae3_handle *handle) 1082 { 1083 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1084 unsigned long instance_stage; /* the current instance stage */ 1085 unsigned long reset_stage; /* the current reset stage */ 1086 unsigned long reset_cnt; 1087 bool sw_resetting; 1088 bool hw_resetting; 1089 1090 /* Get information about reset from NIC driver or RoCE driver itself, 1091 * the meaning of the following variables from NIC driver are described 1092 * as below: 1093 * reset_cnt -- The count value of completed hardware reset. 1094 * hw_resetting -- Whether hardware device is resetting now. 1095 * sw_resetting -- Whether NIC's software reset process is running now. 1096 */ 1097 instance_stage = handle->rinfo.instance_state; 1098 reset_stage = handle->rinfo.reset_state; 1099 reset_cnt = ops->ae_dev_reset_cnt(handle); 1100 if (reset_cnt != hr_dev->reset_cnt) 1101 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1102 reset_stage); 1103 1104 hw_resetting = ops->get_cmdq_stat(handle); 1105 if (hw_resetting) 1106 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1107 reset_stage); 1108 1109 sw_resetting = ops->ae_dev_resetting(handle); 1110 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1111 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1112 1113 return CMD_RST_PRC_OTHERS; 1114 } 1115 1116 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1117 { 1118 struct hns_roce_v2_priv *priv = hr_dev->priv; 1119 struct hnae3_handle *handle = priv->handle; 1120 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1121 1122 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1123 return true; 1124 1125 if (ops->get_hw_reset_stat(handle)) 1126 return true; 1127 1128 if (ops->ae_dev_resetting(handle)) 1129 return true; 1130 1131 return false; 1132 } 1133 1134 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1135 { 1136 struct hns_roce_v2_priv *priv = hr_dev->priv; 1137 u32 status; 1138 1139 if (hr_dev->is_reset) 1140 status = CMD_RST_PRC_SUCCESS; 1141 else 1142 status = check_aedev_reset_status(hr_dev, priv->handle); 1143 1144 *busy = (status == CMD_RST_PRC_EBUSY); 1145 1146 return status == CMD_RST_PRC_OTHERS; 1147 } 1148 1149 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1150 struct hns_roce_v2_cmq_ring *ring) 1151 { 1152 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1153 1154 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1155 &ring->desc_dma_addr, GFP_KERNEL); 1156 if (!ring->desc) 1157 return -ENOMEM; 1158 1159 return 0; 1160 } 1161 1162 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1163 struct hns_roce_v2_cmq_ring *ring) 1164 { 1165 dma_free_coherent(hr_dev->dev, 1166 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1167 ring->desc, ring->desc_dma_addr); 1168 1169 ring->desc_dma_addr = 0; 1170 } 1171 1172 static int init_csq(struct hns_roce_dev *hr_dev, 1173 struct hns_roce_v2_cmq_ring *csq) 1174 { 1175 dma_addr_t dma; 1176 int ret; 1177 1178 csq->desc_num = CMD_CSQ_DESC_NUM; 1179 spin_lock_init(&csq->lock); 1180 csq->flag = TYPE_CSQ; 1181 csq->head = 0; 1182 1183 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1184 if (ret) 1185 return ret; 1186 1187 dma = csq->desc_dma_addr; 1188 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1189 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1190 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1191 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1192 1193 /* Make sure to write CI first and then PI */ 1194 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1195 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1196 1197 return 0; 1198 } 1199 1200 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1201 { 1202 struct hns_roce_v2_priv *priv = hr_dev->priv; 1203 int ret; 1204 1205 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1206 1207 ret = init_csq(hr_dev, &priv->cmq.csq); 1208 if (ret) 1209 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1210 1211 return ret; 1212 } 1213 1214 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1215 { 1216 struct hns_roce_v2_priv *priv = hr_dev->priv; 1217 1218 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1219 } 1220 1221 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1222 enum hns_roce_opcode_type opcode, 1223 bool is_read) 1224 { 1225 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1226 desc->opcode = cpu_to_le16(opcode); 1227 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1228 if (is_read) 1229 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1230 else 1231 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1232 } 1233 1234 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1235 { 1236 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1237 struct hns_roce_v2_priv *priv = hr_dev->priv; 1238 1239 return tail == priv->cmq.csq.head; 1240 } 1241 1242 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1243 { 1244 struct hns_roce_v2_priv *priv = hr_dev->priv; 1245 struct hnae3_handle *handle = priv->handle; 1246 1247 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1248 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1249 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1250 } 1251 1252 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1253 { 1254 struct hns_roce_cmd_errcode errcode_table[] = { 1255 {CMD_EXEC_SUCCESS, 0}, 1256 {CMD_NO_AUTH, -EPERM}, 1257 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1258 {CMD_CRQ_FULL, -EXFULL}, 1259 {CMD_NEXT_ERR, -ENOSR}, 1260 {CMD_NOT_EXEC, -ENOTBLK}, 1261 {CMD_PARA_ERR, -EINVAL}, 1262 {CMD_RESULT_ERR, -ERANGE}, 1263 {CMD_TIMEOUT, -ETIME}, 1264 {CMD_HILINK_ERR, -ENOLINK}, 1265 {CMD_INFO_ILLEGAL, -ENXIO}, 1266 {CMD_INVALID, -EBADR}, 1267 }; 1268 u16 i; 1269 1270 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1271 if (desc_ret == errcode_table[i].return_status) 1272 return errcode_table[i].errno; 1273 return -EIO; 1274 } 1275 1276 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1277 struct hns_roce_cmq_desc *desc, int num) 1278 { 1279 struct hns_roce_v2_priv *priv = hr_dev->priv; 1280 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1281 u32 timeout = 0; 1282 u16 desc_ret; 1283 u32 tail; 1284 int ret; 1285 int i; 1286 1287 spin_lock_bh(&csq->lock); 1288 1289 tail = csq->head; 1290 1291 for (i = 0; i < num; i++) { 1292 csq->desc[csq->head++] = desc[i]; 1293 if (csq->head == csq->desc_num) 1294 csq->head = 0; 1295 } 1296 1297 /* Write to hardware */ 1298 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1299 1300 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1301 1302 do { 1303 if (hns_roce_cmq_csq_done(hr_dev)) 1304 break; 1305 udelay(1); 1306 } while (++timeout < priv->cmq.tx_timeout); 1307 1308 if (hns_roce_cmq_csq_done(hr_dev)) { 1309 ret = 0; 1310 for (i = 0; i < num; i++) { 1311 /* check the result of hardware write back */ 1312 desc[i] = csq->desc[tail++]; 1313 if (tail == csq->desc_num) 1314 tail = 0; 1315 1316 desc_ret = le16_to_cpu(desc[i].retval); 1317 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1318 continue; 1319 1320 dev_err_ratelimited(hr_dev->dev, 1321 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1322 desc->opcode, desc_ret); 1323 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1324 } 1325 } else { 1326 /* FW/HW reset or incorrect number of desc */ 1327 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1328 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1329 csq->head, tail); 1330 csq->head = tail; 1331 1332 update_cmdq_status(hr_dev); 1333 1334 ret = -EAGAIN; 1335 } 1336 1337 spin_unlock_bh(&csq->lock); 1338 1339 if (ret) 1340 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1341 1342 return ret; 1343 } 1344 1345 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1346 struct hns_roce_cmq_desc *desc, int num) 1347 { 1348 bool busy; 1349 int ret; 1350 1351 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1352 return -EIO; 1353 1354 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1355 return busy ? -EBUSY : 0; 1356 1357 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1358 if (ret) { 1359 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1360 return busy ? -EBUSY : 0; 1361 } 1362 1363 return ret; 1364 } 1365 1366 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1367 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1368 { 1369 struct hns_roce_cmd_mailbox *mbox; 1370 int ret; 1371 1372 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1373 if (IS_ERR(mbox)) 1374 return PTR_ERR(mbox); 1375 1376 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1377 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1378 return ret; 1379 } 1380 1381 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1382 { 1383 struct hns_roce_query_version *resp; 1384 struct hns_roce_cmq_desc desc; 1385 int ret; 1386 1387 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1388 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1389 if (ret) 1390 return ret; 1391 1392 resp = (struct hns_roce_query_version *)desc.data; 1393 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1394 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1395 1396 return 0; 1397 } 1398 1399 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1400 struct hnae3_handle *handle) 1401 { 1402 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1403 unsigned long end; 1404 1405 hr_dev->dis_db = true; 1406 1407 dev_warn(hr_dev->dev, 1408 "func clear is pending, device in resetting state.\n"); 1409 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1410 while (end) { 1411 if (!ops->get_hw_reset_stat(handle)) { 1412 hr_dev->is_reset = true; 1413 dev_info(hr_dev->dev, 1414 "func clear success after reset.\n"); 1415 return; 1416 } 1417 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1418 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1419 } 1420 1421 dev_warn(hr_dev->dev, "func clear failed.\n"); 1422 } 1423 1424 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1425 struct hnae3_handle *handle) 1426 { 1427 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1428 unsigned long end; 1429 1430 hr_dev->dis_db = true; 1431 1432 dev_warn(hr_dev->dev, 1433 "func clear is pending, device in resetting state.\n"); 1434 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1435 while (end) { 1436 if (ops->ae_dev_reset_cnt(handle) != 1437 hr_dev->reset_cnt) { 1438 hr_dev->is_reset = true; 1439 dev_info(hr_dev->dev, 1440 "func clear success after sw reset\n"); 1441 return; 1442 } 1443 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1444 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1445 } 1446 1447 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1448 } 1449 1450 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1451 int flag) 1452 { 1453 struct hns_roce_v2_priv *priv = hr_dev->priv; 1454 struct hnae3_handle *handle = priv->handle; 1455 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1456 1457 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1458 hr_dev->dis_db = true; 1459 hr_dev->is_reset = true; 1460 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1461 return; 1462 } 1463 1464 if (ops->get_hw_reset_stat(handle)) { 1465 func_clr_hw_resetting_state(hr_dev, handle); 1466 return; 1467 } 1468 1469 if (ops->ae_dev_resetting(handle) && 1470 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1471 func_clr_sw_resetting_state(hr_dev, handle); 1472 return; 1473 } 1474 1475 if (retval && !flag) 1476 dev_warn(hr_dev->dev, 1477 "func clear read failed, ret = %d.\n", retval); 1478 1479 dev_warn(hr_dev->dev, "func clear failed.\n"); 1480 } 1481 1482 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1483 { 1484 bool fclr_write_fail_flag = false; 1485 struct hns_roce_func_clear *resp; 1486 struct hns_roce_cmq_desc desc; 1487 unsigned long end; 1488 int ret = 0; 1489 1490 if (check_device_is_in_reset(hr_dev)) 1491 goto out; 1492 1493 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1494 resp = (struct hns_roce_func_clear *)desc.data; 1495 resp->rst_funcid_en = cpu_to_le32(vf_id); 1496 1497 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1498 if (ret) { 1499 fclr_write_fail_flag = true; 1500 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1501 ret); 1502 goto out; 1503 } 1504 1505 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1506 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1507 while (end) { 1508 if (check_device_is_in_reset(hr_dev)) 1509 goto out; 1510 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1511 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1512 1513 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1514 true); 1515 1516 resp->rst_funcid_en = cpu_to_le32(vf_id); 1517 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1518 if (ret) 1519 continue; 1520 1521 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1522 if (vf_id == 0) 1523 hr_dev->is_reset = true; 1524 return; 1525 } 1526 } 1527 1528 out: 1529 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1530 } 1531 1532 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1533 { 1534 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1535 struct hns_roce_cmq_desc desc[2]; 1536 struct hns_roce_cmq_req *req_a; 1537 1538 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1539 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1540 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1541 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1542 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1543 1544 return hns_roce_cmq_send(hr_dev, desc, 2); 1545 } 1546 1547 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1548 { 1549 int ret; 1550 int i; 1551 1552 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1553 return; 1554 1555 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1556 __hns_roce_function_clear(hr_dev, i); 1557 1558 if (i == 0) 1559 continue; 1560 1561 ret = hns_roce_free_vf_resource(hr_dev, i); 1562 if (ret) 1563 ibdev_err(&hr_dev->ib_dev, 1564 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1565 i, ret); 1566 } 1567 } 1568 1569 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1570 { 1571 struct hns_roce_cmq_desc desc; 1572 int ret; 1573 1574 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1575 false); 1576 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1577 if (ret) 1578 ibdev_err(&hr_dev->ib_dev, 1579 "failed to clear extended doorbell info, ret = %d.\n", 1580 ret); 1581 1582 return ret; 1583 } 1584 1585 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1586 { 1587 struct hns_roce_query_fw_info *resp; 1588 struct hns_roce_cmq_desc desc; 1589 int ret; 1590 1591 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1592 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1593 if (ret) 1594 return ret; 1595 1596 resp = (struct hns_roce_query_fw_info *)desc.data; 1597 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1598 1599 return 0; 1600 } 1601 1602 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1603 { 1604 struct hns_roce_cmq_desc desc; 1605 int ret; 1606 1607 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1608 hr_dev->func_num = 1; 1609 return 0; 1610 } 1611 1612 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1613 true); 1614 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1615 if (ret) { 1616 hr_dev->func_num = 1; 1617 return ret; 1618 } 1619 1620 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1621 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1622 1623 return 0; 1624 } 1625 1626 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1627 u64 *stats, u32 port, int *num_counters) 1628 { 1629 #define CNT_PER_DESC 3 1630 struct hns_roce_cmq_desc *desc; 1631 int bd_idx, cnt_idx; 1632 __le64 *cnt_data; 1633 int desc_num; 1634 int ret; 1635 int i; 1636 1637 if (port > hr_dev->caps.num_ports) 1638 return -EINVAL; 1639 1640 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1641 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1642 if (!desc) 1643 return -ENOMEM; 1644 1645 for (i = 0; i < desc_num; i++) { 1646 hns_roce_cmq_setup_basic_desc(&desc[i], 1647 HNS_ROCE_OPC_QUERY_COUNTER, true); 1648 if (i != desc_num - 1) 1649 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1650 } 1651 1652 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1653 if (ret) { 1654 ibdev_err(&hr_dev->ib_dev, 1655 "failed to get counter, ret = %d.\n", ret); 1656 goto err_out; 1657 } 1658 1659 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1660 bd_idx = i / CNT_PER_DESC; 1661 if (!(desc[bd_idx].flag & HNS_ROCE_CMD_FLAG_NEXT) && 1662 bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC) 1663 break; 1664 1665 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1666 cnt_idx = i % CNT_PER_DESC; 1667 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1668 } 1669 *num_counters = i; 1670 1671 err_out: 1672 kfree(desc); 1673 return ret; 1674 } 1675 1676 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1677 { 1678 struct hns_roce_cmq_desc desc; 1679 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1680 u32 clock_cycles_of_1us; 1681 1682 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1683 false); 1684 1685 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1686 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1687 else 1688 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1689 1690 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1691 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1692 1693 return hns_roce_cmq_send(hr_dev, &desc, 1); 1694 } 1695 1696 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1697 { 1698 struct hns_roce_cmq_desc desc[2]; 1699 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1700 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1701 struct hns_roce_caps *caps = &hr_dev->caps; 1702 enum hns_roce_opcode_type opcode; 1703 u32 func_num; 1704 int ret; 1705 1706 if (is_vf) { 1707 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1708 func_num = 1; 1709 } else { 1710 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1711 func_num = hr_dev->func_num; 1712 } 1713 1714 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1715 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1716 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1717 1718 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1719 if (ret) 1720 return ret; 1721 1722 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1723 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1724 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1725 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1726 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1727 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1728 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1729 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1730 1731 if (is_vf) { 1732 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1733 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1734 func_num; 1735 } else { 1736 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1737 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1738 func_num; 1739 } 1740 1741 return 0; 1742 } 1743 1744 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1745 { 1746 struct hns_roce_cmq_desc desc; 1747 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1748 struct hns_roce_caps *caps = &hr_dev->caps; 1749 int ret; 1750 1751 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1752 true); 1753 1754 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1755 if (ret) 1756 return ret; 1757 1758 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1759 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1760 1761 return 0; 1762 } 1763 1764 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1765 { 1766 struct device *dev = hr_dev->dev; 1767 int ret; 1768 1769 ret = load_func_res_caps(hr_dev, false); 1770 if (ret) { 1771 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1772 return ret; 1773 } 1774 1775 ret = load_pf_timer_res_caps(hr_dev); 1776 if (ret) 1777 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1778 ret); 1779 1780 return ret; 1781 } 1782 1783 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1784 { 1785 struct device *dev = hr_dev->dev; 1786 int ret; 1787 1788 ret = load_func_res_caps(hr_dev, true); 1789 if (ret) 1790 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1791 1792 return ret; 1793 } 1794 1795 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1796 u32 vf_id) 1797 { 1798 struct hns_roce_vf_switch *swt; 1799 struct hns_roce_cmq_desc desc; 1800 int ret; 1801 1802 swt = (struct hns_roce_vf_switch *)desc.data; 1803 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1804 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1805 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1806 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1807 if (ret) 1808 return ret; 1809 1810 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1811 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1812 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1813 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1814 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1815 1816 return hns_roce_cmq_send(hr_dev, &desc, 1); 1817 } 1818 1819 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1820 { 1821 u32 vf_id; 1822 int ret; 1823 1824 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1825 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1826 if (ret) 1827 return ret; 1828 } 1829 return 0; 1830 } 1831 1832 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1833 { 1834 struct hns_roce_cmq_desc desc[2]; 1835 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1836 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1837 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1838 struct hns_roce_caps *caps = &hr_dev->caps; 1839 1840 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1841 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1842 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1843 1844 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1845 1846 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1847 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1848 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1849 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1850 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1851 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1852 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1853 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1854 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1855 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1856 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1857 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1858 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1859 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1860 1861 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1862 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1863 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1864 vf_id * caps->gmv_bt_num); 1865 } else { 1866 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1867 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1868 vf_id * caps->sgid_bt_num); 1869 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1870 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1871 vf_id * caps->smac_bt_num); 1872 } 1873 1874 return hns_roce_cmq_send(hr_dev, desc, 2); 1875 } 1876 1877 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1878 { 1879 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1880 u32 vf_id; 1881 int ret; 1882 1883 for (vf_id = 0; vf_id < func_num; vf_id++) { 1884 ret = config_vf_hem_resource(hr_dev, vf_id); 1885 if (ret) { 1886 dev_err(hr_dev->dev, 1887 "failed to config vf-%u hem res, ret = %d.\n", 1888 vf_id, ret); 1889 return ret; 1890 } 1891 } 1892 1893 return 0; 1894 } 1895 1896 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1897 { 1898 struct hns_roce_cmq_desc desc; 1899 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1900 struct hns_roce_caps *caps = &hr_dev->caps; 1901 1902 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1903 1904 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1905 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1906 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1907 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1908 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1909 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1910 1911 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1912 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1913 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1914 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1915 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1916 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1917 1918 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1919 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1920 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1921 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1922 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1923 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1924 1925 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1926 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1927 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1928 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1929 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1930 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1931 1932 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1933 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1934 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1935 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1936 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1937 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1938 1939 return hns_roce_cmq_send(hr_dev, &desc, 1); 1940 } 1941 1942 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1943 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1944 { 1945 u64 obj_per_chunk; 1946 u64 bt_chunk_size = PAGE_SIZE; 1947 u64 buf_chunk_size = PAGE_SIZE; 1948 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1949 1950 *buf_page_size = 0; 1951 *bt_page_size = 0; 1952 1953 switch (hop_num) { 1954 case 3: 1955 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1956 (bt_chunk_size / BA_BYTE_LEN) * 1957 (bt_chunk_size / BA_BYTE_LEN) * 1958 obj_per_chunk_default; 1959 break; 1960 case 2: 1961 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1962 (bt_chunk_size / BA_BYTE_LEN) * 1963 obj_per_chunk_default; 1964 break; 1965 case 1: 1966 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1967 obj_per_chunk_default; 1968 break; 1969 case HNS_ROCE_HOP_NUM_0: 1970 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1971 break; 1972 default: 1973 pr_err("table %u not support hop_num = %u!\n", hem_type, 1974 hop_num); 1975 return; 1976 } 1977 1978 if (hem_type >= HEM_TYPE_MTT) 1979 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1980 else 1981 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1982 } 1983 1984 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 1985 { 1986 struct hns_roce_caps *caps = &hr_dev->caps; 1987 1988 /* EQ */ 1989 caps->eqe_ba_pg_sz = 0; 1990 caps->eqe_buf_pg_sz = 0; 1991 1992 /* Link Table */ 1993 caps->llm_buf_pg_sz = 0; 1994 1995 /* MR */ 1996 caps->mpt_ba_pg_sz = 0; 1997 caps->mpt_buf_pg_sz = 0; 1998 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 1999 caps->pbl_buf_pg_sz = 0; 2000 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2001 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2002 HEM_TYPE_MTPT); 2003 2004 /* QP */ 2005 caps->qpc_ba_pg_sz = 0; 2006 caps->qpc_buf_pg_sz = 0; 2007 caps->qpc_timer_ba_pg_sz = 0; 2008 caps->qpc_timer_buf_pg_sz = 0; 2009 caps->sccc_ba_pg_sz = 0; 2010 caps->sccc_buf_pg_sz = 0; 2011 caps->mtt_ba_pg_sz = 0; 2012 caps->mtt_buf_pg_sz = 0; 2013 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2014 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2015 HEM_TYPE_QPC); 2016 2017 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2018 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2019 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2020 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2021 2022 /* CQ */ 2023 caps->cqc_ba_pg_sz = 0; 2024 caps->cqc_buf_pg_sz = 0; 2025 caps->cqc_timer_ba_pg_sz = 0; 2026 caps->cqc_timer_buf_pg_sz = 0; 2027 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2028 caps->cqe_buf_pg_sz = 0; 2029 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2030 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2031 HEM_TYPE_CQC); 2032 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2033 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2034 2035 /* SRQ */ 2036 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2037 caps->srqc_ba_pg_sz = 0; 2038 caps->srqc_buf_pg_sz = 0; 2039 caps->srqwqe_ba_pg_sz = 0; 2040 caps->srqwqe_buf_pg_sz = 0; 2041 caps->idx_ba_pg_sz = 0; 2042 caps->idx_buf_pg_sz = 0; 2043 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2044 caps->srqc_hop_num, caps->srqc_bt_num, 2045 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2046 HEM_TYPE_SRQC); 2047 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2048 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2049 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2050 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2051 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2052 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2053 } 2054 2055 /* GMV */ 2056 caps->gmv_ba_pg_sz = 0; 2057 caps->gmv_buf_pg_sz = 0; 2058 } 2059 2060 /* Apply all loaded caps before setting to hardware */ 2061 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2062 { 2063 #define MAX_GID_TBL_LEN 256 2064 struct hns_roce_caps *caps = &hr_dev->caps; 2065 struct hns_roce_v2_priv *priv = hr_dev->priv; 2066 2067 /* The following configurations don't need to be got from firmware. */ 2068 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2069 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2070 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2071 2072 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2073 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2074 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2075 2076 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2077 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2078 2079 if (!caps->num_comp_vectors) 2080 caps->num_comp_vectors = 2081 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2082 (u32)priv->handle->rinfo.num_vectors - 2083 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2084 2085 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2086 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2087 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2088 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2089 2090 /* The following configurations will be overwritten */ 2091 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2092 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2093 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2094 2095 /* The following configurations are not got from firmware */ 2096 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2097 2098 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2099 2100 /* It's meaningless to support excessively large gid_table_len, 2101 * as the type of sgid_index in kernel struct ib_global_route 2102 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2103 */ 2104 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2105 caps->gmv_bt_num * 2106 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2107 2108 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2109 caps->gmv_entry_sz); 2110 } else { 2111 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2112 2113 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2114 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2115 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2116 caps->gid_table_len[0] /= func_num; 2117 } 2118 2119 if (hr_dev->is_vf) { 2120 caps->default_aeq_arm_st = 0x3; 2121 caps->default_ceq_arm_st = 0x3; 2122 caps->default_ceq_max_cnt = 0x1; 2123 caps->default_ceq_period = 0x10; 2124 caps->default_aeq_max_cnt = 0x1; 2125 caps->default_aeq_period = 0x10; 2126 } 2127 2128 set_hem_page_size(hr_dev); 2129 } 2130 2131 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2132 { 2133 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2134 struct hns_roce_caps *caps = &hr_dev->caps; 2135 struct hns_roce_query_pf_caps_a *resp_a; 2136 struct hns_roce_query_pf_caps_b *resp_b; 2137 struct hns_roce_query_pf_caps_c *resp_c; 2138 struct hns_roce_query_pf_caps_d *resp_d; 2139 struct hns_roce_query_pf_caps_e *resp_e; 2140 enum hns_roce_opcode_type cmd; 2141 int ctx_hop_num; 2142 int pbl_hop_num; 2143 int ret; 2144 int i; 2145 2146 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2147 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2148 2149 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2150 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2151 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2152 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2153 else 2154 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2155 } 2156 2157 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2158 if (ret) 2159 return ret; 2160 2161 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2162 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2163 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2164 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2165 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2166 2167 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2168 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2169 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2170 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2171 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2172 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2173 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2174 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2175 caps->num_other_vectors = resp_a->num_other_vectors; 2176 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2177 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2178 2179 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2180 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2181 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2182 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2183 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2184 caps->idx_entry_sz = resp_b->idx_entry_sz; 2185 caps->sccc_sz = resp_b->sccc_sz; 2186 caps->max_mtu = resp_b->max_mtu; 2187 caps->min_cqes = resp_b->min_cqes; 2188 caps->min_wqes = resp_b->min_wqes; 2189 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2190 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2191 caps->phy_num_uars = resp_b->phy_num_uars; 2192 ctx_hop_num = resp_b->ctx_hop_num; 2193 pbl_hop_num = resp_b->pbl_hop_num; 2194 2195 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2196 2197 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2198 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2199 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2200 2201 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2202 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2203 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2204 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2205 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2206 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2207 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2208 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2209 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2210 2211 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2212 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2213 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2214 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2215 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2216 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2217 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2218 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2219 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2220 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2221 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2222 2223 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2224 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2225 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2226 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2227 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2228 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2229 2230 caps->qpc_hop_num = ctx_hop_num; 2231 caps->sccc_hop_num = ctx_hop_num; 2232 caps->srqc_hop_num = ctx_hop_num; 2233 caps->cqc_hop_num = ctx_hop_num; 2234 caps->mpt_hop_num = ctx_hop_num; 2235 caps->mtt_hop_num = pbl_hop_num; 2236 caps->cqe_hop_num = pbl_hop_num; 2237 caps->srqwqe_hop_num = pbl_hop_num; 2238 caps->idx_hop_num = pbl_hop_num; 2239 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2240 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2241 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2242 2243 if (!(caps->page_size_cap & PAGE_SIZE)) 2244 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2245 2246 if (!hr_dev->is_vf) { 2247 caps->cqe_sz = resp_a->cqe_sz; 2248 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2249 caps->default_aeq_arm_st = 2250 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2251 caps->default_ceq_arm_st = 2252 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2253 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2254 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2255 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2256 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2257 } 2258 2259 return 0; 2260 } 2261 2262 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2263 { 2264 struct hns_roce_cmq_desc desc; 2265 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2266 2267 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2268 false); 2269 2270 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2271 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2272 2273 return hns_roce_cmq_send(hr_dev, &desc, 1); 2274 } 2275 2276 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2277 { 2278 struct hns_roce_caps *caps = &hr_dev->caps; 2279 int ret; 2280 2281 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2282 return 0; 2283 2284 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2285 caps->qpc_sz); 2286 if (ret) { 2287 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2288 return ret; 2289 } 2290 2291 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2292 caps->sccc_sz); 2293 if (ret) 2294 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2295 2296 return ret; 2297 } 2298 2299 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2300 { 2301 struct device *dev = hr_dev->dev; 2302 int ret; 2303 2304 hr_dev->func_num = 1; 2305 2306 ret = hns_roce_query_caps(hr_dev); 2307 if (ret) { 2308 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2309 return ret; 2310 } 2311 2312 ret = hns_roce_query_vf_resource(hr_dev); 2313 if (ret) { 2314 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2315 return ret; 2316 } 2317 2318 apply_func_caps(hr_dev); 2319 2320 ret = hns_roce_v2_set_bt(hr_dev); 2321 if (ret) 2322 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2323 2324 return ret; 2325 } 2326 2327 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2328 { 2329 struct device *dev = hr_dev->dev; 2330 int ret; 2331 2332 ret = hns_roce_query_func_info(hr_dev); 2333 if (ret) { 2334 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2335 return ret; 2336 } 2337 2338 ret = hns_roce_config_global_param(hr_dev); 2339 if (ret) { 2340 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2341 return ret; 2342 } 2343 2344 ret = hns_roce_set_vf_switch_param(hr_dev); 2345 if (ret) { 2346 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2347 return ret; 2348 } 2349 2350 ret = hns_roce_query_caps(hr_dev); 2351 if (ret) { 2352 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2353 return ret; 2354 } 2355 2356 ret = hns_roce_query_pf_resource(hr_dev); 2357 if (ret) { 2358 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2359 return ret; 2360 } 2361 2362 apply_func_caps(hr_dev); 2363 2364 ret = hns_roce_alloc_vf_resource(hr_dev); 2365 if (ret) { 2366 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2367 return ret; 2368 } 2369 2370 ret = hns_roce_v2_set_bt(hr_dev); 2371 if (ret) { 2372 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2373 return ret; 2374 } 2375 2376 /* Configure the size of QPC, SCCC, etc. */ 2377 return hns_roce_config_entry_size(hr_dev); 2378 } 2379 2380 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2381 { 2382 struct device *dev = hr_dev->dev; 2383 int ret; 2384 2385 ret = hns_roce_cmq_query_hw_info(hr_dev); 2386 if (ret) { 2387 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2388 return ret; 2389 } 2390 2391 ret = hns_roce_query_fw_ver(hr_dev); 2392 if (ret) { 2393 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2394 return ret; 2395 } 2396 2397 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2398 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2399 2400 if (hr_dev->is_vf) 2401 return hns_roce_v2_vf_profile(hr_dev); 2402 else 2403 return hns_roce_v2_pf_profile(hr_dev); 2404 } 2405 2406 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2407 { 2408 u32 i, next_ptr, page_num; 2409 __le64 *entry = cfg_buf; 2410 dma_addr_t addr; 2411 u64 val; 2412 2413 page_num = data_buf->npages; 2414 for (i = 0; i < page_num; i++) { 2415 addr = hns_roce_buf_page(data_buf, i); 2416 if (i == (page_num - 1)) 2417 next_ptr = 0; 2418 else 2419 next_ptr = i + 1; 2420 2421 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2422 entry[i] = cpu_to_le64(val); 2423 } 2424 } 2425 2426 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2427 struct hns_roce_link_table *table) 2428 { 2429 struct hns_roce_cmq_desc desc[2]; 2430 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2431 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2432 struct hns_roce_buf *buf = table->buf; 2433 enum hns_roce_opcode_type opcode; 2434 dma_addr_t addr; 2435 2436 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2437 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2438 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2439 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2440 2441 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2442 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2443 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2444 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2445 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2446 2447 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2448 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2449 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2450 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2451 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2452 2453 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2454 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2455 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2456 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2457 2458 return hns_roce_cmq_send(hr_dev, desc, 2); 2459 } 2460 2461 static struct hns_roce_link_table * 2462 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2463 { 2464 struct hns_roce_v2_priv *priv = hr_dev->priv; 2465 struct hns_roce_link_table *link_tbl; 2466 u32 pg_shift, size, min_size; 2467 2468 link_tbl = &priv->ext_llm; 2469 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2470 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2471 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2472 2473 /* Alloc data table */ 2474 size = max(size, min_size); 2475 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2476 if (IS_ERR(link_tbl->buf)) 2477 return ERR_PTR(-ENOMEM); 2478 2479 /* Alloc config table */ 2480 size = link_tbl->buf->npages * sizeof(u64); 2481 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2482 &link_tbl->table.map, 2483 GFP_KERNEL); 2484 if (!link_tbl->table.buf) { 2485 hns_roce_buf_free(hr_dev, link_tbl->buf); 2486 return ERR_PTR(-ENOMEM); 2487 } 2488 2489 return link_tbl; 2490 } 2491 2492 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2493 struct hns_roce_link_table *tbl) 2494 { 2495 if (tbl->buf) { 2496 u32 size = tbl->buf->npages * sizeof(u64); 2497 2498 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2499 tbl->table.map); 2500 } 2501 2502 hns_roce_buf_free(hr_dev, tbl->buf); 2503 } 2504 2505 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2506 { 2507 struct hns_roce_link_table *link_tbl; 2508 int ret; 2509 2510 link_tbl = alloc_link_table_buf(hr_dev); 2511 if (IS_ERR(link_tbl)) 2512 return -ENOMEM; 2513 2514 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2515 ret = -EINVAL; 2516 goto err_alloc; 2517 } 2518 2519 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2520 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2521 if (ret) 2522 goto err_alloc; 2523 2524 return 0; 2525 2526 err_alloc: 2527 free_link_table_buf(hr_dev, link_tbl); 2528 return ret; 2529 } 2530 2531 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2532 { 2533 struct hns_roce_v2_priv *priv = hr_dev->priv; 2534 2535 free_link_table_buf(hr_dev, &priv->ext_llm); 2536 } 2537 2538 static void free_dip_list(struct hns_roce_dev *hr_dev) 2539 { 2540 struct hns_roce_dip *hr_dip; 2541 struct hns_roce_dip *tmp; 2542 unsigned long flags; 2543 2544 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2545 2546 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2547 list_del(&hr_dip->node); 2548 kfree(hr_dip); 2549 } 2550 2551 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2552 } 2553 2554 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2555 { 2556 struct hns_roce_v2_priv *priv = hr_dev->priv; 2557 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2558 struct ib_device *ibdev = &hr_dev->ib_dev; 2559 struct hns_roce_pd *hr_pd; 2560 struct ib_pd *pd; 2561 2562 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2563 if (ZERO_OR_NULL_PTR(hr_pd)) 2564 return NULL; 2565 pd = &hr_pd->ibpd; 2566 pd->device = ibdev; 2567 2568 if (hns_roce_alloc_pd(pd, NULL)) { 2569 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2570 kfree(hr_pd); 2571 return NULL; 2572 } 2573 free_mr->rsv_pd = to_hr_pd(pd); 2574 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2575 free_mr->rsv_pd->ibpd.uobject = NULL; 2576 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2577 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2578 2579 return pd; 2580 } 2581 2582 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2583 { 2584 struct hns_roce_v2_priv *priv = hr_dev->priv; 2585 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2586 struct ib_device *ibdev = &hr_dev->ib_dev; 2587 struct ib_cq_init_attr cq_init_attr = {}; 2588 struct hns_roce_cq *hr_cq; 2589 struct ib_cq *cq; 2590 2591 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2592 2593 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2594 if (ZERO_OR_NULL_PTR(hr_cq)) 2595 return NULL; 2596 2597 cq = &hr_cq->ib_cq; 2598 cq->device = ibdev; 2599 2600 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2601 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2602 kfree(hr_cq); 2603 return NULL; 2604 } 2605 free_mr->rsv_cq = to_hr_cq(cq); 2606 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2607 free_mr->rsv_cq->ib_cq.uobject = NULL; 2608 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2609 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2610 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2611 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2612 2613 return cq; 2614 } 2615 2616 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2617 struct ib_qp_init_attr *init_attr, int i) 2618 { 2619 struct hns_roce_v2_priv *priv = hr_dev->priv; 2620 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2621 struct ib_device *ibdev = &hr_dev->ib_dev; 2622 struct hns_roce_qp *hr_qp; 2623 struct ib_qp *qp; 2624 int ret; 2625 2626 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2627 if (ZERO_OR_NULL_PTR(hr_qp)) 2628 return -ENOMEM; 2629 2630 qp = &hr_qp->ibqp; 2631 qp->device = ibdev; 2632 2633 ret = hns_roce_create_qp(qp, init_attr, NULL); 2634 if (ret) { 2635 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2636 kfree(hr_qp); 2637 return ret; 2638 } 2639 2640 free_mr->rsv_qp[i] = hr_qp; 2641 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2642 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2643 2644 return 0; 2645 } 2646 2647 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2648 { 2649 struct hns_roce_v2_priv *priv = hr_dev->priv; 2650 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2651 struct ib_qp *qp; 2652 int i; 2653 2654 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2655 if (free_mr->rsv_qp[i]) { 2656 qp = &free_mr->rsv_qp[i]->ibqp; 2657 hns_roce_v2_destroy_qp(qp, NULL); 2658 kfree(free_mr->rsv_qp[i]); 2659 free_mr->rsv_qp[i] = NULL; 2660 } 2661 } 2662 2663 if (free_mr->rsv_cq) { 2664 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2665 kfree(free_mr->rsv_cq); 2666 free_mr->rsv_cq = NULL; 2667 } 2668 2669 if (free_mr->rsv_pd) { 2670 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2671 kfree(free_mr->rsv_pd); 2672 free_mr->rsv_pd = NULL; 2673 } 2674 } 2675 2676 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2677 { 2678 struct hns_roce_v2_priv *priv = hr_dev->priv; 2679 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2680 struct ib_qp_init_attr qp_init_attr = {}; 2681 struct ib_pd *pd; 2682 struct ib_cq *cq; 2683 int ret; 2684 int i; 2685 2686 pd = free_mr_init_pd(hr_dev); 2687 if (!pd) 2688 return -ENOMEM; 2689 2690 cq = free_mr_init_cq(hr_dev); 2691 if (!cq) { 2692 ret = -ENOMEM; 2693 goto create_failed_cq; 2694 } 2695 2696 qp_init_attr.qp_type = IB_QPT_RC; 2697 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2698 qp_init_attr.send_cq = cq; 2699 qp_init_attr.recv_cq = cq; 2700 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2701 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2702 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2703 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2704 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2705 2706 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2707 if (ret) 2708 goto create_failed_qp; 2709 } 2710 2711 return 0; 2712 2713 create_failed_qp: 2714 for (i--; i >= 0; i--) { 2715 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 2716 kfree(free_mr->rsv_qp[i]); 2717 } 2718 hns_roce_destroy_cq(cq, NULL); 2719 kfree(cq); 2720 2721 create_failed_cq: 2722 hns_roce_dealloc_pd(pd, NULL); 2723 kfree(pd); 2724 2725 return ret; 2726 } 2727 2728 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2729 struct ib_qp_attr *attr, int sl_num) 2730 { 2731 struct hns_roce_v2_priv *priv = hr_dev->priv; 2732 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2733 struct ib_device *ibdev = &hr_dev->ib_dev; 2734 struct hns_roce_qp *hr_qp; 2735 int loopback; 2736 int mask; 2737 int ret; 2738 2739 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2740 hr_qp->free_mr_en = 1; 2741 hr_qp->ibqp.device = ibdev; 2742 hr_qp->ibqp.qp_type = IB_QPT_RC; 2743 2744 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2745 attr->qp_state = IB_QPS_INIT; 2746 attr->port_num = 1; 2747 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2748 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2749 IB_QPS_INIT, NULL); 2750 if (ret) { 2751 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2752 ret); 2753 return ret; 2754 } 2755 2756 loopback = hr_dev->loop_idc; 2757 /* Set qpc lbi = 1 incidate loopback IO */ 2758 hr_dev->loop_idc = 1; 2759 2760 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2761 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2762 attr->qp_state = IB_QPS_RTR; 2763 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2764 attr->path_mtu = IB_MTU_256; 2765 attr->dest_qp_num = hr_qp->qpn; 2766 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2767 2768 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2769 2770 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2771 IB_QPS_RTR, NULL); 2772 hr_dev->loop_idc = loopback; 2773 if (ret) { 2774 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2775 ret); 2776 return ret; 2777 } 2778 2779 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2780 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2781 attr->qp_state = IB_QPS_RTS; 2782 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2783 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2784 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2785 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2786 IB_QPS_RTS, NULL); 2787 if (ret) 2788 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2789 ret); 2790 2791 return ret; 2792 } 2793 2794 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2795 { 2796 struct hns_roce_v2_priv *priv = hr_dev->priv; 2797 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2798 struct ib_qp_attr attr = {}; 2799 int ret; 2800 int i; 2801 2802 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2803 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2804 rdma_ah_set_port_num(&attr.ah_attr, 1); 2805 2806 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2807 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2808 if (ret) 2809 return ret; 2810 } 2811 2812 return 0; 2813 } 2814 2815 static int free_mr_init(struct hns_roce_dev *hr_dev) 2816 { 2817 struct hns_roce_v2_priv *priv = hr_dev->priv; 2818 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2819 int ret; 2820 2821 mutex_init(&free_mr->mutex); 2822 2823 ret = free_mr_alloc_res(hr_dev); 2824 if (ret) 2825 return ret; 2826 2827 ret = free_mr_modify_qp(hr_dev); 2828 if (ret) 2829 goto err_modify_qp; 2830 2831 return 0; 2832 2833 err_modify_qp: 2834 free_mr_exit(hr_dev); 2835 2836 return ret; 2837 } 2838 2839 static int get_hem_table(struct hns_roce_dev *hr_dev) 2840 { 2841 unsigned int qpc_count; 2842 unsigned int cqc_count; 2843 unsigned int gmv_count; 2844 int ret; 2845 int i; 2846 2847 /* Alloc memory for source address table buffer space chunk */ 2848 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2849 gmv_count++) { 2850 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2851 if (ret) 2852 goto err_gmv_failed; 2853 } 2854 2855 if (hr_dev->is_vf) 2856 return 0; 2857 2858 /* Alloc memory for QPC Timer buffer space chunk */ 2859 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2860 qpc_count++) { 2861 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2862 qpc_count); 2863 if (ret) { 2864 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2865 goto err_qpc_timer_failed; 2866 } 2867 } 2868 2869 /* Alloc memory for CQC Timer buffer space chunk */ 2870 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2871 cqc_count++) { 2872 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2873 cqc_count); 2874 if (ret) { 2875 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2876 goto err_cqc_timer_failed; 2877 } 2878 } 2879 2880 return 0; 2881 2882 err_cqc_timer_failed: 2883 for (i = 0; i < cqc_count; i++) 2884 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2885 2886 err_qpc_timer_failed: 2887 for (i = 0; i < qpc_count; i++) 2888 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2889 2890 err_gmv_failed: 2891 for (i = 0; i < gmv_count; i++) 2892 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2893 2894 return ret; 2895 } 2896 2897 static void put_hem_table(struct hns_roce_dev *hr_dev) 2898 { 2899 int i; 2900 2901 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2902 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2903 2904 if (hr_dev->is_vf) 2905 return; 2906 2907 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2908 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2909 2910 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2911 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2912 } 2913 2914 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2915 { 2916 int ret; 2917 2918 /* The hns ROCEE requires the extdb info to be cleared before using */ 2919 ret = hns_roce_clear_extdb_list_info(hr_dev); 2920 if (ret) 2921 return ret; 2922 2923 ret = get_hem_table(hr_dev); 2924 if (ret) 2925 return ret; 2926 2927 if (hr_dev->is_vf) 2928 return 0; 2929 2930 ret = hns_roce_init_link_table(hr_dev); 2931 if (ret) { 2932 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2933 goto err_llm_init_failed; 2934 } 2935 2936 return 0; 2937 2938 err_llm_init_failed: 2939 put_hem_table(hr_dev); 2940 2941 return ret; 2942 } 2943 2944 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2945 { 2946 hns_roce_function_clear(hr_dev); 2947 2948 if (!hr_dev->is_vf) 2949 hns_roce_free_link_table(hr_dev); 2950 2951 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2952 free_dip_list(hr_dev); 2953 } 2954 2955 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2956 struct hns_roce_mbox_msg *mbox_msg) 2957 { 2958 struct hns_roce_cmq_desc desc; 2959 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2960 2961 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2962 2963 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2964 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2965 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2966 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2967 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2968 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2969 mbox_msg->token); 2970 2971 return hns_roce_cmq_send(hr_dev, &desc, 1); 2972 } 2973 2974 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2975 u8 *complete_status) 2976 { 2977 struct hns_roce_mbox_status *mb_st; 2978 struct hns_roce_cmq_desc desc; 2979 unsigned long end; 2980 int ret = -EBUSY; 2981 u32 status; 2982 bool busy; 2983 2984 mb_st = (struct hns_roce_mbox_status *)desc.data; 2985 end = msecs_to_jiffies(timeout) + jiffies; 2986 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2987 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2988 return -EIO; 2989 2990 status = 0; 2991 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2992 true); 2993 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2994 if (!ret) { 2995 status = le32_to_cpu(mb_st->mb_status_hw_run); 2996 /* No pending message exists in ROCEE mbox. */ 2997 if (!(status & MB_ST_HW_RUN_M)) 2998 break; 2999 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3000 break; 3001 } 3002 3003 if (time_after(jiffies, end)) { 3004 dev_err_ratelimited(hr_dev->dev, 3005 "failed to wait mbox status 0x%x\n", 3006 status); 3007 return -ETIMEDOUT; 3008 } 3009 3010 cond_resched(); 3011 ret = -EBUSY; 3012 } 3013 3014 if (!ret) { 3015 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3016 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3017 /* Ignore all errors if the mbox is unavailable. */ 3018 ret = 0; 3019 *complete_status = MB_ST_COMPLETE_M; 3020 } 3021 3022 return ret; 3023 } 3024 3025 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3026 struct hns_roce_mbox_msg *mbox_msg) 3027 { 3028 u8 status = 0; 3029 int ret; 3030 3031 /* Waiting for the mbox to be idle */ 3032 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3033 &status); 3034 if (unlikely(ret)) { 3035 dev_err_ratelimited(hr_dev->dev, 3036 "failed to check post mbox status = 0x%x, ret = %d.\n", 3037 status, ret); 3038 return ret; 3039 } 3040 3041 /* Post new message to mbox */ 3042 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3043 if (ret) 3044 dev_err_ratelimited(hr_dev->dev, 3045 "failed to post mailbox, ret = %d.\n", ret); 3046 3047 return ret; 3048 } 3049 3050 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3051 { 3052 u8 status = 0; 3053 int ret; 3054 3055 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3056 &status); 3057 if (!ret) { 3058 if (status != MB_ST_COMPLETE_SUCC) 3059 return -EBUSY; 3060 } else { 3061 dev_err_ratelimited(hr_dev->dev, 3062 "failed to check mbox status = 0x%x, ret = %d.\n", 3063 status, ret); 3064 } 3065 3066 return ret; 3067 } 3068 3069 static void copy_gid(void *dest, const union ib_gid *gid) 3070 { 3071 #define GID_SIZE 4 3072 const union ib_gid *src = gid; 3073 __le32 (*p)[GID_SIZE] = dest; 3074 int i; 3075 3076 if (!gid) 3077 src = &zgid; 3078 3079 for (i = 0; i < GID_SIZE; i++) 3080 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3081 } 3082 3083 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3084 int gid_index, const union ib_gid *gid, 3085 enum hns_roce_sgid_type sgid_type) 3086 { 3087 struct hns_roce_cmq_desc desc; 3088 struct hns_roce_cfg_sgid_tb *sgid_tb = 3089 (struct hns_roce_cfg_sgid_tb *)desc.data; 3090 3091 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3092 3093 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3094 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3095 3096 copy_gid(&sgid_tb->vf_sgid_l, gid); 3097 3098 return hns_roce_cmq_send(hr_dev, &desc, 1); 3099 } 3100 3101 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3102 int gid_index, const union ib_gid *gid, 3103 enum hns_roce_sgid_type sgid_type, 3104 const struct ib_gid_attr *attr) 3105 { 3106 struct hns_roce_cmq_desc desc[2]; 3107 struct hns_roce_cfg_gmv_tb_a *tb_a = 3108 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3109 struct hns_roce_cfg_gmv_tb_b *tb_b = 3110 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3111 3112 u16 vlan_id = VLAN_CFI_MASK; 3113 u8 mac[ETH_ALEN] = {}; 3114 int ret; 3115 3116 if (gid) { 3117 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3118 if (ret) 3119 return ret; 3120 } 3121 3122 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3123 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3124 3125 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3126 3127 copy_gid(&tb_a->vf_sgid_l, gid); 3128 3129 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3130 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3131 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3132 3133 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3134 3135 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3136 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3137 3138 return hns_roce_cmq_send(hr_dev, desc, 2); 3139 } 3140 3141 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3142 const union ib_gid *gid, 3143 const struct ib_gid_attr *attr) 3144 { 3145 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3146 int ret; 3147 3148 if (gid) { 3149 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3150 if (ipv6_addr_v4mapped((void *)gid)) 3151 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3152 else 3153 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3154 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3155 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3156 } 3157 } 3158 3159 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3160 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3161 else 3162 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3163 3164 if (ret) 3165 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3166 ret); 3167 3168 return ret; 3169 } 3170 3171 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3172 const u8 *addr) 3173 { 3174 struct hns_roce_cmq_desc desc; 3175 struct hns_roce_cfg_smac_tb *smac_tb = 3176 (struct hns_roce_cfg_smac_tb *)desc.data; 3177 u16 reg_smac_h; 3178 u32 reg_smac_l; 3179 3180 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3181 3182 reg_smac_l = *(u32 *)(&addr[0]); 3183 reg_smac_h = *(u16 *)(&addr[4]); 3184 3185 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3186 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3187 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3188 3189 return hns_roce_cmq_send(hr_dev, &desc, 1); 3190 } 3191 3192 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3193 struct hns_roce_v2_mpt_entry *mpt_entry, 3194 struct hns_roce_mr *mr) 3195 { 3196 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3197 struct ib_device *ibdev = &hr_dev->ib_dev; 3198 dma_addr_t pbl_ba; 3199 int ret; 3200 int i; 3201 3202 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3203 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3204 if (ret) { 3205 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3206 return ret; 3207 } 3208 3209 /* Aligned to the hardware address access unit */ 3210 for (i = 0; i < ARRAY_SIZE(pages); i++) 3211 pages[i] >>= 6; 3212 3213 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3214 3215 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3216 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3217 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3218 3219 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3220 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3221 3222 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3223 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3224 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3225 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3226 3227 return 0; 3228 } 3229 3230 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3231 void *mb_buf, struct hns_roce_mr *mr) 3232 { 3233 struct hns_roce_v2_mpt_entry *mpt_entry; 3234 3235 mpt_entry = mb_buf; 3236 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3237 3238 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3239 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3240 3241 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3242 mr->access & IB_ACCESS_MW_BIND); 3243 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3244 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3245 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3246 mr->access & IB_ACCESS_REMOTE_READ); 3247 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3248 mr->access & IB_ACCESS_REMOTE_WRITE); 3249 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3250 mr->access & IB_ACCESS_LOCAL_WRITE); 3251 3252 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3253 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3254 mpt_entry->lkey = cpu_to_le32(mr->key); 3255 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3256 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3257 3258 if (mr->type != MR_TYPE_MR) 3259 hr_reg_enable(mpt_entry, MPT_PA); 3260 3261 if (mr->type == MR_TYPE_DMA) 3262 return 0; 3263 3264 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3265 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3266 3267 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3268 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3269 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3270 3271 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3272 } 3273 3274 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3275 struct hns_roce_mr *mr, int flags, 3276 void *mb_buf) 3277 { 3278 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3279 u32 mr_access_flags = mr->access; 3280 int ret = 0; 3281 3282 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3283 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3284 3285 if (flags & IB_MR_REREG_ACCESS) { 3286 hr_reg_write(mpt_entry, MPT_BIND_EN, 3287 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3288 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3289 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3290 hr_reg_write(mpt_entry, MPT_RR_EN, 3291 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3292 hr_reg_write(mpt_entry, MPT_RW_EN, 3293 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3294 hr_reg_write(mpt_entry, MPT_LW_EN, 3295 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3296 } 3297 3298 if (flags & IB_MR_REREG_TRANS) { 3299 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3300 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3301 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3302 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3303 3304 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3305 } 3306 3307 return ret; 3308 } 3309 3310 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3311 void *mb_buf, struct hns_roce_mr *mr) 3312 { 3313 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3314 struct hns_roce_v2_mpt_entry *mpt_entry; 3315 3316 mpt_entry = mb_buf; 3317 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3318 3319 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3320 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3321 3322 hr_reg_enable(mpt_entry, MPT_RA_EN); 3323 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3324 3325 hr_reg_enable(mpt_entry, MPT_FRE); 3326 hr_reg_clear(mpt_entry, MPT_MR_MW); 3327 hr_reg_enable(mpt_entry, MPT_BPD); 3328 hr_reg_clear(mpt_entry, MPT_PA); 3329 3330 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3331 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3332 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3333 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3334 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3335 3336 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3337 3338 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3339 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3340 3341 return 0; 3342 } 3343 3344 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3345 { 3346 struct hns_roce_v2_mpt_entry *mpt_entry; 3347 3348 mpt_entry = mb_buf; 3349 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3350 3351 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3352 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3353 3354 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3355 hr_reg_enable(mpt_entry, MPT_LW_EN); 3356 3357 hr_reg_enable(mpt_entry, MPT_MR_MW); 3358 hr_reg_enable(mpt_entry, MPT_BPD); 3359 hr_reg_clear(mpt_entry, MPT_PA); 3360 hr_reg_write(mpt_entry, MPT_BQP, 3361 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3362 3363 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3364 3365 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3366 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3367 mw->pbl_hop_num); 3368 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3369 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3370 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3371 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3372 3373 return 0; 3374 } 3375 3376 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3377 { 3378 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3379 struct ib_device *ibdev = &hr_dev->ib_dev; 3380 const struct ib_send_wr *bad_wr; 3381 struct ib_rdma_wr rdma_wr = {}; 3382 struct ib_send_wr *send_wr; 3383 int ret; 3384 3385 send_wr = &rdma_wr.wr; 3386 send_wr->opcode = IB_WR_RDMA_WRITE; 3387 3388 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3389 if (ret) { 3390 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3391 ret); 3392 return ret; 3393 } 3394 3395 return 0; 3396 } 3397 3398 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3399 struct ib_wc *wc); 3400 3401 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3402 { 3403 struct hns_roce_v2_priv *priv = hr_dev->priv; 3404 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3405 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3406 struct ib_device *ibdev = &hr_dev->ib_dev; 3407 struct hns_roce_qp *hr_qp; 3408 unsigned long end; 3409 int cqe_cnt = 0; 3410 int npolled; 3411 int ret; 3412 int i; 3413 3414 /* 3415 * If the device initialization is not complete or in the uninstall 3416 * process, then there is no need to execute free mr. 3417 */ 3418 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3419 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3420 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3421 return; 3422 3423 mutex_lock(&free_mr->mutex); 3424 3425 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3426 hr_qp = free_mr->rsv_qp[i]; 3427 3428 ret = free_mr_post_send_lp_wqe(hr_qp); 3429 if (ret) { 3430 ibdev_err(ibdev, 3431 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3432 hr_qp->qpn, ret); 3433 break; 3434 } 3435 3436 cqe_cnt++; 3437 } 3438 3439 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3440 while (cqe_cnt) { 3441 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3442 if (npolled < 0) { 3443 ibdev_err(ibdev, 3444 "failed to poll cqe for free mr, remain %d cqe.\n", 3445 cqe_cnt); 3446 goto out; 3447 } 3448 3449 if (time_after(jiffies, end)) { 3450 ibdev_err(ibdev, 3451 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3452 cqe_cnt); 3453 goto out; 3454 } 3455 cqe_cnt -= npolled; 3456 } 3457 3458 out: 3459 mutex_unlock(&free_mr->mutex); 3460 } 3461 3462 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3463 { 3464 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3465 free_mr_send_cmd_to_hw(hr_dev); 3466 } 3467 3468 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3469 { 3470 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3471 } 3472 3473 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3474 { 3475 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3476 3477 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3478 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3479 NULL; 3480 } 3481 3482 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3483 struct hns_roce_cq *hr_cq) 3484 { 3485 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3486 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3487 } else { 3488 struct hns_roce_v2_db cq_db = {}; 3489 3490 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3491 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3492 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3493 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3494 3495 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3496 } 3497 } 3498 3499 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3500 struct hns_roce_srq *srq) 3501 { 3502 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3503 struct hns_roce_v2_cqe *cqe, *dest; 3504 u32 prod_index; 3505 int nfreed = 0; 3506 int wqe_index; 3507 u8 owner_bit; 3508 3509 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3510 ++prod_index) { 3511 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3512 break; 3513 } 3514 3515 /* 3516 * Now backwards through the CQ, removing CQ entries 3517 * that match our QP by overwriting them with next entries. 3518 */ 3519 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3520 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3521 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3522 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3523 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3524 hns_roce_free_srq_wqe(srq, wqe_index); 3525 } 3526 ++nfreed; 3527 } else if (nfreed) { 3528 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3529 hr_cq->ib_cq.cqe); 3530 owner_bit = hr_reg_read(dest, CQE_OWNER); 3531 memcpy(dest, cqe, hr_cq->cqe_size); 3532 hr_reg_write(dest, CQE_OWNER, owner_bit); 3533 } 3534 } 3535 3536 if (nfreed) { 3537 hr_cq->cons_index += nfreed; 3538 update_cq_db(hr_dev, hr_cq); 3539 } 3540 } 3541 3542 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3543 struct hns_roce_srq *srq) 3544 { 3545 spin_lock_irq(&hr_cq->lock); 3546 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3547 spin_unlock_irq(&hr_cq->lock); 3548 } 3549 3550 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3551 struct hns_roce_cq *hr_cq, void *mb_buf, 3552 u64 *mtts, dma_addr_t dma_handle) 3553 { 3554 struct hns_roce_v2_cq_context *cq_context; 3555 3556 cq_context = mb_buf; 3557 memset(cq_context, 0, sizeof(*cq_context)); 3558 3559 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3560 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3561 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3562 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3563 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3564 3565 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3566 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3567 3568 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3569 hr_reg_enable(cq_context, CQC_STASH); 3570 3571 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3572 to_hr_hw_page_addr(mtts[0])); 3573 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3574 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3575 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3576 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3577 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3578 to_hr_hw_page_addr(mtts[1])); 3579 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3580 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3581 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3582 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3583 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3584 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3585 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3586 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3587 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3588 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3589 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3590 ((u32)hr_cq->db.dma) >> 1); 3591 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3592 hr_cq->db.dma >> 32); 3593 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3594 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3595 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3596 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3597 } 3598 3599 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3600 enum ib_cq_notify_flags flags) 3601 { 3602 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3603 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3604 struct hns_roce_v2_db cq_db = {}; 3605 u32 notify_flag; 3606 3607 /* 3608 * flags = 0, then notify_flag : next 3609 * flags = 1, then notify flag : solocited 3610 */ 3611 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3612 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3613 3614 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3615 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3616 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3617 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3618 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3619 3620 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3621 3622 return 0; 3623 } 3624 3625 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3626 int num_entries, struct ib_wc *wc) 3627 { 3628 unsigned int left; 3629 int npolled = 0; 3630 3631 left = wq->head - wq->tail; 3632 if (left == 0) 3633 return 0; 3634 3635 left = min_t(unsigned int, (unsigned int)num_entries, left); 3636 while (npolled < left) { 3637 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3638 wc->status = IB_WC_WR_FLUSH_ERR; 3639 wc->vendor_err = 0; 3640 wc->qp = &hr_qp->ibqp; 3641 3642 wq->tail++; 3643 wc++; 3644 npolled++; 3645 } 3646 3647 return npolled; 3648 } 3649 3650 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3651 struct ib_wc *wc) 3652 { 3653 struct hns_roce_qp *hr_qp; 3654 int npolled = 0; 3655 3656 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3657 npolled += sw_comp(hr_qp, &hr_qp->sq, 3658 num_entries - npolled, wc + npolled); 3659 if (npolled >= num_entries) 3660 goto out; 3661 } 3662 3663 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3664 npolled += sw_comp(hr_qp, &hr_qp->rq, 3665 num_entries - npolled, wc + npolled); 3666 if (npolled >= num_entries) 3667 goto out; 3668 } 3669 3670 out: 3671 return npolled; 3672 } 3673 3674 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3675 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3676 struct ib_wc *wc) 3677 { 3678 static const struct { 3679 u32 cqe_status; 3680 enum ib_wc_status wc_status; 3681 } map[] = { 3682 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3683 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3684 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3685 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3686 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3687 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3688 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3689 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3690 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3691 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3692 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3693 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3694 IB_WC_RETRY_EXC_ERR }, 3695 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3696 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3697 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3698 }; 3699 3700 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3701 int i; 3702 3703 wc->status = IB_WC_GENERAL_ERR; 3704 for (i = 0; i < ARRAY_SIZE(map); i++) 3705 if (cqe_status == map[i].cqe_status) { 3706 wc->status = map[i].wc_status; 3707 break; 3708 } 3709 3710 if (likely(wc->status == IB_WC_SUCCESS || 3711 wc->status == IB_WC_WR_FLUSH_ERR)) 3712 return; 3713 3714 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3715 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3716 cq->cqe_size, false); 3717 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3718 3719 /* 3720 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3721 * the standard protocol, the driver must ignore it and needn't to set 3722 * the QP to an error state. 3723 */ 3724 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3725 return; 3726 3727 flush_cqe(hr_dev, qp); 3728 } 3729 3730 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3731 struct hns_roce_qp **cur_qp) 3732 { 3733 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3734 struct hns_roce_qp *hr_qp = *cur_qp; 3735 u32 qpn; 3736 3737 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3738 3739 if (!hr_qp || qpn != hr_qp->qpn) { 3740 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3741 if (unlikely(!hr_qp)) { 3742 ibdev_err(&hr_dev->ib_dev, 3743 "CQ %06lx with entry for unknown QPN %06x\n", 3744 hr_cq->cqn, qpn); 3745 return -EINVAL; 3746 } 3747 *cur_qp = hr_qp; 3748 } 3749 3750 return 0; 3751 } 3752 3753 /* 3754 * mapped-value = 1 + real-value 3755 * The ib wc opcode's real value is start from 0, In order to distinguish 3756 * between initialized and uninitialized map values, we plus 1 to the actual 3757 * value when defining the mapping, so that the validity can be identified by 3758 * checking whether the mapped value is greater than 0. 3759 */ 3760 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3761 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3762 3763 static const u32 wc_send_op_map[] = { 3764 HR_WC_OP_MAP(SEND, SEND), 3765 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3766 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3767 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3768 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3769 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3770 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3771 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3772 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3773 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3774 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3775 HR_WC_OP_MAP(BIND_MW, REG_MR), 3776 }; 3777 3778 static int to_ib_wc_send_op(u32 hr_opcode) 3779 { 3780 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3781 return -EINVAL; 3782 3783 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3784 -EINVAL; 3785 } 3786 3787 static const u32 wc_recv_op_map[] = { 3788 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3789 HR_WC_OP_MAP(SEND, RECV), 3790 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3791 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3792 }; 3793 3794 static int to_ib_wc_recv_op(u32 hr_opcode) 3795 { 3796 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3797 return -EINVAL; 3798 3799 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3800 -EINVAL; 3801 } 3802 3803 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3804 { 3805 u32 hr_opcode; 3806 int ib_opcode; 3807 3808 wc->wc_flags = 0; 3809 3810 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3811 switch (hr_opcode) { 3812 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3813 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3814 break; 3815 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3816 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3817 wc->wc_flags |= IB_WC_WITH_IMM; 3818 break; 3819 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3820 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3821 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3822 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3823 wc->byte_len = 8; 3824 break; 3825 default: 3826 break; 3827 } 3828 3829 ib_opcode = to_ib_wc_send_op(hr_opcode); 3830 if (ib_opcode < 0) 3831 wc->status = IB_WC_GENERAL_ERR; 3832 else 3833 wc->opcode = ib_opcode; 3834 } 3835 3836 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3837 { 3838 u32 hr_opcode; 3839 int ib_opcode; 3840 3841 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3842 3843 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3844 switch (hr_opcode) { 3845 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3846 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3847 wc->wc_flags = IB_WC_WITH_IMM; 3848 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3849 break; 3850 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3851 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3852 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3853 break; 3854 default: 3855 wc->wc_flags = 0; 3856 } 3857 3858 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3859 if (ib_opcode < 0) 3860 wc->status = IB_WC_GENERAL_ERR; 3861 else 3862 wc->opcode = ib_opcode; 3863 3864 wc->sl = hr_reg_read(cqe, CQE_SL); 3865 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3866 wc->slid = 0; 3867 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3868 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3869 wc->pkey_index = 0; 3870 3871 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3872 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3873 wc->wc_flags |= IB_WC_WITH_VLAN; 3874 } else { 3875 wc->vlan_id = 0xffff; 3876 } 3877 3878 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3879 3880 return 0; 3881 } 3882 3883 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3884 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3885 { 3886 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3887 struct hns_roce_qp *qp = *cur_qp; 3888 struct hns_roce_srq *srq = NULL; 3889 struct hns_roce_v2_cqe *cqe; 3890 struct hns_roce_wq *wq; 3891 int is_send; 3892 u16 wqe_idx; 3893 int ret; 3894 3895 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3896 if (!cqe) 3897 return -EAGAIN; 3898 3899 ++hr_cq->cons_index; 3900 /* Memory barrier */ 3901 rmb(); 3902 3903 ret = get_cur_qp(hr_cq, cqe, &qp); 3904 if (ret) 3905 return ret; 3906 3907 wc->qp = &qp->ibqp; 3908 wc->vendor_err = 0; 3909 3910 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3911 3912 is_send = !hr_reg_read(cqe, CQE_S_R); 3913 if (is_send) { 3914 wq = &qp->sq; 3915 3916 /* If sg_signal_bit is set, tail pointer will be updated to 3917 * the WQE corresponding to the current CQE. 3918 */ 3919 if (qp->sq_signal_bits) 3920 wq->tail += (wqe_idx - (u16)wq->tail) & 3921 (wq->wqe_cnt - 1); 3922 3923 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3924 ++wq->tail; 3925 3926 fill_send_wc(wc, cqe); 3927 } else { 3928 if (qp->ibqp.srq) { 3929 srq = to_hr_srq(qp->ibqp.srq); 3930 wc->wr_id = srq->wrid[wqe_idx]; 3931 hns_roce_free_srq_wqe(srq, wqe_idx); 3932 } else { 3933 wq = &qp->rq; 3934 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3935 ++wq->tail; 3936 } 3937 3938 ret = fill_recv_wc(wc, cqe); 3939 } 3940 3941 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3942 if (unlikely(wc->status != IB_WC_SUCCESS)) 3943 return 0; 3944 3945 return ret; 3946 } 3947 3948 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3949 struct ib_wc *wc) 3950 { 3951 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3952 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3953 struct hns_roce_qp *cur_qp = NULL; 3954 unsigned long flags; 3955 int npolled; 3956 3957 spin_lock_irqsave(&hr_cq->lock, flags); 3958 3959 /* 3960 * When the device starts to reset, the state is RST_DOWN. At this time, 3961 * there may still be some valid CQEs in the hardware that are not 3962 * polled. Therefore, it is not allowed to switch to the software mode 3963 * immediately. When the state changes to UNINIT, CQE no longer exists 3964 * in the hardware, and then switch to software mode. 3965 */ 3966 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3967 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3968 goto out; 3969 } 3970 3971 for (npolled = 0; npolled < num_entries; ++npolled) { 3972 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3973 break; 3974 } 3975 3976 if (npolled) 3977 update_cq_db(hr_dev, hr_cq); 3978 3979 out: 3980 spin_unlock_irqrestore(&hr_cq->lock, flags); 3981 3982 return npolled; 3983 } 3984 3985 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3986 u32 step_idx, u8 *mbox_cmd) 3987 { 3988 u8 cmd; 3989 3990 switch (type) { 3991 case HEM_TYPE_QPC: 3992 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 3993 break; 3994 case HEM_TYPE_MTPT: 3995 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 3996 break; 3997 case HEM_TYPE_CQC: 3998 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 3999 break; 4000 case HEM_TYPE_SRQC: 4001 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4002 break; 4003 case HEM_TYPE_SCCC: 4004 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4005 break; 4006 case HEM_TYPE_QPC_TIMER: 4007 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4008 break; 4009 case HEM_TYPE_CQC_TIMER: 4010 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4011 break; 4012 default: 4013 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4014 return -EINVAL; 4015 } 4016 4017 *mbox_cmd = cmd + step_idx; 4018 4019 return 0; 4020 } 4021 4022 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4023 dma_addr_t base_addr) 4024 { 4025 struct hns_roce_cmq_desc desc; 4026 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4027 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4028 u64 addr = to_hr_hw_page_addr(base_addr); 4029 4030 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4031 4032 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4033 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4034 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4035 4036 return hns_roce_cmq_send(hr_dev, &desc, 1); 4037 } 4038 4039 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4040 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4041 { 4042 int ret; 4043 u8 cmd; 4044 4045 if (unlikely(hem_type == HEM_TYPE_GMV)) 4046 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4047 4048 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4049 return 0; 4050 4051 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4052 if (ret < 0) 4053 return ret; 4054 4055 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4056 } 4057 4058 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4059 struct hns_roce_hem_table *table, int obj, 4060 u32 step_idx) 4061 { 4062 struct hns_roce_hem_mhop mhop; 4063 struct hns_roce_hem *hem; 4064 unsigned long mhop_obj = obj; 4065 int i, j, k; 4066 int ret = 0; 4067 u64 hem_idx = 0; 4068 u64 l1_idx = 0; 4069 u64 bt_ba = 0; 4070 u32 chunk_ba_num; 4071 u32 hop_num; 4072 4073 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4074 return 0; 4075 4076 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4077 i = mhop.l0_idx; 4078 j = mhop.l1_idx; 4079 k = mhop.l2_idx; 4080 hop_num = mhop.hop_num; 4081 chunk_ba_num = mhop.bt_chunk_size / 8; 4082 4083 if (hop_num == 2) { 4084 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4085 k; 4086 l1_idx = i * chunk_ba_num + j; 4087 } else if (hop_num == 1) { 4088 hem_idx = i * chunk_ba_num + j; 4089 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4090 hem_idx = i; 4091 } 4092 4093 if (table->type == HEM_TYPE_SCCC) 4094 obj = mhop.l0_idx; 4095 4096 if (check_whether_last_step(hop_num, step_idx)) { 4097 hem = table->hem[hem_idx]; 4098 4099 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4100 } else { 4101 if (step_idx == 0) 4102 bt_ba = table->bt_l0_dma_addr[i]; 4103 else if (step_idx == 1 && hop_num == 2) 4104 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4105 4106 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4107 } 4108 4109 return ret; 4110 } 4111 4112 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4113 struct hns_roce_hem_table *table, 4114 int tag, u32 step_idx) 4115 { 4116 struct hns_roce_cmd_mailbox *mailbox; 4117 struct device *dev = hr_dev->dev; 4118 u8 cmd = 0xff; 4119 int ret; 4120 4121 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4122 return 0; 4123 4124 switch (table->type) { 4125 case HEM_TYPE_QPC: 4126 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4127 break; 4128 case HEM_TYPE_MTPT: 4129 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4130 break; 4131 case HEM_TYPE_CQC: 4132 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4133 break; 4134 case HEM_TYPE_SRQC: 4135 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4136 break; 4137 case HEM_TYPE_SCCC: 4138 case HEM_TYPE_QPC_TIMER: 4139 case HEM_TYPE_CQC_TIMER: 4140 case HEM_TYPE_GMV: 4141 return 0; 4142 default: 4143 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4144 table->type); 4145 return 0; 4146 } 4147 4148 cmd += step_idx; 4149 4150 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4151 if (IS_ERR(mailbox)) 4152 return PTR_ERR(mailbox); 4153 4154 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4155 4156 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4157 return ret; 4158 } 4159 4160 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4161 struct hns_roce_v2_qp_context *context, 4162 struct hns_roce_v2_qp_context *qpc_mask, 4163 struct hns_roce_qp *hr_qp) 4164 { 4165 struct hns_roce_cmd_mailbox *mailbox; 4166 int qpc_size; 4167 int ret; 4168 4169 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4170 if (IS_ERR(mailbox)) 4171 return PTR_ERR(mailbox); 4172 4173 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4174 qpc_size = hr_dev->caps.qpc_sz; 4175 memcpy(mailbox->buf, context, qpc_size); 4176 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4177 4178 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4179 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4180 4181 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4182 4183 return ret; 4184 } 4185 4186 static void set_access_flags(struct hns_roce_qp *hr_qp, 4187 struct hns_roce_v2_qp_context *context, 4188 struct hns_roce_v2_qp_context *qpc_mask, 4189 const struct ib_qp_attr *attr, int attr_mask) 4190 { 4191 u8 dest_rd_atomic; 4192 u32 access_flags; 4193 4194 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4195 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4196 4197 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4198 attr->qp_access_flags : hr_qp->atomic_rd_en; 4199 4200 if (!dest_rd_atomic) 4201 access_flags &= IB_ACCESS_REMOTE_WRITE; 4202 4203 hr_reg_write_bool(context, QPC_RRE, 4204 access_flags & IB_ACCESS_REMOTE_READ); 4205 hr_reg_clear(qpc_mask, QPC_RRE); 4206 4207 hr_reg_write_bool(context, QPC_RWE, 4208 access_flags & IB_ACCESS_REMOTE_WRITE); 4209 hr_reg_clear(qpc_mask, QPC_RWE); 4210 4211 hr_reg_write_bool(context, QPC_ATE, 4212 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4213 hr_reg_clear(qpc_mask, QPC_ATE); 4214 hr_reg_write_bool(context, QPC_EXT_ATE, 4215 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4216 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4217 } 4218 4219 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4220 struct hns_roce_v2_qp_context *context, 4221 struct hns_roce_v2_qp_context *qpc_mask) 4222 { 4223 hr_reg_write(context, QPC_SGE_SHIFT, 4224 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4225 hr_qp->sge.sge_shift)); 4226 4227 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4228 4229 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4230 } 4231 4232 static inline int get_cqn(struct ib_cq *ib_cq) 4233 { 4234 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4235 } 4236 4237 static inline int get_pdn(struct ib_pd *ib_pd) 4238 { 4239 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4240 } 4241 4242 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4243 const struct ib_qp_attr *attr, 4244 struct hns_roce_v2_qp_context *context, 4245 struct hns_roce_v2_qp_context *qpc_mask) 4246 { 4247 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4248 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4249 4250 /* 4251 * In v2 engine, software pass context and context mask to hardware 4252 * when modifying qp. If software need modify some fields in context, 4253 * we should set all bits of the relevant fields in context mask to 4254 * 0 at the same time, else set them to 0x1. 4255 */ 4256 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4257 4258 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4259 4260 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4261 4262 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4263 4264 /* No VLAN need to set 0xFFF */ 4265 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4266 4267 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4268 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4269 4270 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4271 } 4272 4273 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4274 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4275 4276 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4277 hr_reg_enable(context, QPC_OWNER_MODE); 4278 4279 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4280 lower_32_bits(hr_qp->rdb.dma) >> 1); 4281 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4282 upper_32_bits(hr_qp->rdb.dma)); 4283 4284 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4285 4286 if (ibqp->srq) { 4287 hr_reg_enable(context, QPC_SRQ_EN); 4288 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4289 } 4290 4291 hr_reg_enable(context, QPC_FRE); 4292 4293 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4294 4295 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4296 return; 4297 4298 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4299 hr_reg_enable(&context->ext, QPCEX_STASH); 4300 } 4301 4302 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4303 const struct ib_qp_attr *attr, 4304 struct hns_roce_v2_qp_context *context, 4305 struct hns_roce_v2_qp_context *qpc_mask) 4306 { 4307 /* 4308 * In v2 engine, software pass context and context mask to hardware 4309 * when modifying qp. If software need modify some fields in context, 4310 * we should set all bits of the relevant fields in context mask to 4311 * 0 at the same time, else set them to 0x1. 4312 */ 4313 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4314 hr_reg_clear(qpc_mask, QPC_TST); 4315 4316 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4317 hr_reg_clear(qpc_mask, QPC_PD); 4318 4319 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4320 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4321 4322 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4323 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4324 4325 if (ibqp->srq) { 4326 hr_reg_enable(context, QPC_SRQ_EN); 4327 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4328 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4329 hr_reg_clear(qpc_mask, QPC_SRQN); 4330 } 4331 } 4332 4333 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4334 struct hns_roce_qp *hr_qp, 4335 struct hns_roce_v2_qp_context *context, 4336 struct hns_roce_v2_qp_context *qpc_mask) 4337 { 4338 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4339 u64 wqe_sge_ba; 4340 int ret; 4341 4342 /* Search qp buf's mtts */ 4343 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4344 MTT_MIN_COUNT); 4345 if (hr_qp->rq.wqe_cnt && ret) { 4346 ibdev_err(&hr_dev->ib_dev, 4347 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4348 hr_qp->qpn, ret); 4349 return ret; 4350 } 4351 4352 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4353 4354 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4355 qpc_mask->wqe_sge_ba = 0; 4356 4357 /* 4358 * In v2 engine, software pass context and context mask to hardware 4359 * when modifying qp. If software need modify some fields in context, 4360 * we should set all bits of the relevant fields in context mask to 4361 * 0 at the same time, else set them to 0x1. 4362 */ 4363 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4364 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4365 4366 hr_reg_write(context, QPC_SQ_HOP_NUM, 4367 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4368 hr_qp->sq.wqe_cnt)); 4369 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4370 4371 hr_reg_write(context, QPC_SGE_HOP_NUM, 4372 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4373 hr_qp->sge.sge_cnt)); 4374 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4375 4376 hr_reg_write(context, QPC_RQ_HOP_NUM, 4377 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4378 hr_qp->rq.wqe_cnt)); 4379 4380 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4381 4382 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4383 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4384 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4385 4386 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4387 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4388 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4389 4390 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4391 qpc_mask->rq_cur_blk_addr = 0; 4392 4393 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4394 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4395 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4396 4397 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4398 qpc_mask->rq_nxt_blk_addr = 0; 4399 4400 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4401 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4402 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4403 4404 return 0; 4405 } 4406 4407 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4408 struct hns_roce_qp *hr_qp, 4409 struct hns_roce_v2_qp_context *context, 4410 struct hns_roce_v2_qp_context *qpc_mask) 4411 { 4412 struct ib_device *ibdev = &hr_dev->ib_dev; 4413 u64 sge_cur_blk = 0; 4414 u64 sq_cur_blk = 0; 4415 int ret; 4416 4417 /* search qp buf's mtts */ 4418 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4419 &sq_cur_blk, 1); 4420 if (ret) { 4421 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4422 hr_qp->qpn, ret); 4423 return ret; 4424 } 4425 if (hr_qp->sge.sge_cnt > 0) { 4426 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4427 hr_qp->sge.offset, &sge_cur_blk, 1); 4428 if (ret) { 4429 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4430 hr_qp->qpn, ret); 4431 return ret; 4432 } 4433 } 4434 4435 /* 4436 * In v2 engine, software pass context and context mask to hardware 4437 * when modifying qp. If software need modify some fields in context, 4438 * we should set all bits of the relevant fields in context mask to 4439 * 0 at the same time, else set them to 0x1. 4440 */ 4441 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4442 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4443 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4444 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4445 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4446 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4447 4448 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4449 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4450 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4451 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4452 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4453 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4454 4455 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4456 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4457 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4458 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4459 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4460 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4461 4462 return 0; 4463 } 4464 4465 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4466 const struct ib_qp_attr *attr) 4467 { 4468 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4469 return IB_MTU_4096; 4470 4471 return attr->path_mtu; 4472 } 4473 4474 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4475 const struct ib_qp_attr *attr, int attr_mask, 4476 struct hns_roce_v2_qp_context *context, 4477 struct hns_roce_v2_qp_context *qpc_mask, 4478 struct ib_udata *udata) 4479 { 4480 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4481 struct hns_roce_ucontext, ibucontext); 4482 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4483 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4484 struct ib_device *ibdev = &hr_dev->ib_dev; 4485 dma_addr_t trrl_ba; 4486 dma_addr_t irrl_ba; 4487 enum ib_mtu ib_mtu; 4488 const u8 *smac; 4489 u8 lp_pktn_ini; 4490 u64 *mtts; 4491 u8 *dmac; 4492 u32 port; 4493 int mtu; 4494 int ret; 4495 4496 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4497 if (ret) { 4498 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4499 return ret; 4500 } 4501 4502 /* Search IRRL's mtts */ 4503 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4504 hr_qp->qpn, &irrl_ba); 4505 if (!mtts) { 4506 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4507 return -EINVAL; 4508 } 4509 4510 /* Search TRRL's mtts */ 4511 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4512 hr_qp->qpn, &trrl_ba); 4513 if (!mtts) { 4514 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4515 return -EINVAL; 4516 } 4517 4518 if (attr_mask & IB_QP_ALT_PATH) { 4519 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4520 attr_mask); 4521 return -EINVAL; 4522 } 4523 4524 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4525 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4526 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4527 qpc_mask->trrl_ba = 0; 4528 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4529 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4530 4531 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4532 qpc_mask->irrl_ba = 0; 4533 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4534 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4535 4536 hr_reg_enable(context, QPC_RMT_E2E); 4537 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4538 4539 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4540 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4541 4542 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4543 4544 smac = (const u8 *)hr_dev->dev_addr[port]; 4545 dmac = (u8 *)attr->ah_attr.roce.dmac; 4546 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4547 if (ether_addr_equal_unaligned(dmac, smac) || 4548 hr_dev->loop_idc == 0x1) { 4549 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4550 hr_reg_clear(qpc_mask, QPC_LBI); 4551 } 4552 4553 if (attr_mask & IB_QP_DEST_QPN) { 4554 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4555 hr_reg_clear(qpc_mask, QPC_DQPN); 4556 } 4557 4558 memcpy(&context->dmac, dmac, sizeof(u32)); 4559 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4560 qpc_mask->dmac = 0; 4561 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4562 4563 ib_mtu = get_mtu(ibqp, attr); 4564 hr_qp->path_mtu = ib_mtu; 4565 4566 mtu = ib_mtu_enum_to_int(ib_mtu); 4567 if (WARN_ON(mtu <= 0)) 4568 return -EINVAL; 4569 #define MIN_LP_MSG_LEN 1024 4570 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4571 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4572 4573 if (attr_mask & IB_QP_PATH_MTU) { 4574 hr_reg_write(context, QPC_MTU, ib_mtu); 4575 hr_reg_clear(qpc_mask, QPC_MTU); 4576 } 4577 4578 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4579 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4580 4581 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4582 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4583 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4584 4585 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4586 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4587 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4588 4589 context->rq_rnr_timer = 0; 4590 qpc_mask->rq_rnr_timer = 0; 4591 4592 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4593 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4594 4595 /* rocee send 2^lp_sgen_ini segs every time */ 4596 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4597 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4598 4599 if (udata && ibqp->qp_type == IB_QPT_RC && 4600 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4601 hr_reg_write_bool(context, QPC_RQIE, 4602 hr_dev->caps.flags & 4603 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4604 hr_reg_clear(qpc_mask, QPC_RQIE); 4605 } 4606 4607 if (udata && 4608 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4609 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4610 hr_reg_write_bool(context, QPC_CQEIE, 4611 hr_dev->caps.flags & 4612 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4613 hr_reg_clear(qpc_mask, QPC_CQEIE); 4614 4615 hr_reg_write(context, QPC_CQEIS, 0); 4616 hr_reg_clear(qpc_mask, QPC_CQEIS); 4617 } 4618 4619 return 0; 4620 } 4621 4622 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4623 const struct ib_qp_attr *attr, int attr_mask, 4624 struct hns_roce_v2_qp_context *context, 4625 struct hns_roce_v2_qp_context *qpc_mask) 4626 { 4627 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4628 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4629 struct ib_device *ibdev = &hr_dev->ib_dev; 4630 int ret; 4631 4632 /* Not support alternate path and path migration */ 4633 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4634 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4635 return -EINVAL; 4636 } 4637 4638 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4639 if (ret) { 4640 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4641 return ret; 4642 } 4643 4644 /* 4645 * Set some fields in context to zero, Because the default values 4646 * of all fields in context are zero, we need not set them to 0 again. 4647 * but we should set the relevant fields of context mask to 0. 4648 */ 4649 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4650 4651 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4652 4653 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4654 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4655 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4656 4657 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4658 4659 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4660 4661 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4662 4663 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4664 4665 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4666 4667 return 0; 4668 } 4669 4670 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4671 u32 *dip_idx) 4672 { 4673 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4674 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4675 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4676 u32 *head = &hr_dev->qp_table.idx_table.head; 4677 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4678 struct hns_roce_dip *hr_dip; 4679 unsigned long flags; 4680 int ret = 0; 4681 4682 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4683 4684 spare_idx[*tail] = ibqp->qp_num; 4685 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4686 4687 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4688 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4689 *dip_idx = hr_dip->dip_idx; 4690 goto out; 4691 } 4692 } 4693 4694 /* If no dgid is found, a new dip and a mapping between dgid and 4695 * dip_idx will be created. 4696 */ 4697 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4698 if (!hr_dip) { 4699 ret = -ENOMEM; 4700 goto out; 4701 } 4702 4703 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4704 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4705 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4706 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4707 4708 out: 4709 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4710 return ret; 4711 } 4712 4713 enum { 4714 CONG_DCQCN, 4715 CONG_WINDOW, 4716 }; 4717 4718 enum { 4719 UNSUPPORT_CONG_LEVEL, 4720 SUPPORT_CONG_LEVEL, 4721 }; 4722 4723 enum { 4724 CONG_LDCP, 4725 CONG_HC3, 4726 }; 4727 4728 enum { 4729 DIP_INVALID, 4730 DIP_VALID, 4731 }; 4732 4733 enum { 4734 WND_LIMIT, 4735 WND_UNLIMIT, 4736 }; 4737 4738 static int check_cong_type(struct ib_qp *ibqp, 4739 struct hns_roce_congestion_algorithm *cong_alg) 4740 { 4741 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4742 4743 /* different congestion types match different configurations */ 4744 switch (hr_qp->cong_type) { 4745 case CONG_TYPE_DCQCN: 4746 cong_alg->alg_sel = CONG_DCQCN; 4747 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4748 cong_alg->dip_vld = DIP_INVALID; 4749 cong_alg->wnd_mode_sel = WND_LIMIT; 4750 break; 4751 case CONG_TYPE_LDCP: 4752 cong_alg->alg_sel = CONG_WINDOW; 4753 cong_alg->alg_sub_sel = CONG_LDCP; 4754 cong_alg->dip_vld = DIP_INVALID; 4755 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4756 break; 4757 case CONG_TYPE_HC3: 4758 cong_alg->alg_sel = CONG_WINDOW; 4759 cong_alg->alg_sub_sel = CONG_HC3; 4760 cong_alg->dip_vld = DIP_INVALID; 4761 cong_alg->wnd_mode_sel = WND_LIMIT; 4762 break; 4763 case CONG_TYPE_DIP: 4764 cong_alg->alg_sel = CONG_DCQCN; 4765 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4766 cong_alg->dip_vld = DIP_VALID; 4767 cong_alg->wnd_mode_sel = WND_LIMIT; 4768 break; 4769 default: 4770 hr_qp->cong_type = CONG_TYPE_DCQCN; 4771 cong_alg->alg_sel = CONG_DCQCN; 4772 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4773 cong_alg->dip_vld = DIP_INVALID; 4774 cong_alg->wnd_mode_sel = WND_LIMIT; 4775 break; 4776 } 4777 4778 return 0; 4779 } 4780 4781 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4782 struct hns_roce_v2_qp_context *context, 4783 struct hns_roce_v2_qp_context *qpc_mask) 4784 { 4785 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4786 struct hns_roce_congestion_algorithm cong_field; 4787 struct ib_device *ibdev = ibqp->device; 4788 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4789 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4790 u32 dip_idx = 0; 4791 int ret; 4792 4793 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4794 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4795 return 0; 4796 4797 ret = check_cong_type(ibqp, &cong_field); 4798 if (ret) 4799 return ret; 4800 4801 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4802 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 4803 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4804 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4805 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4806 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4807 cong_field.alg_sub_sel); 4808 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4809 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4810 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4811 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4812 cong_field.wnd_mode_sel); 4813 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4814 4815 /* if dip is disabled, there is no need to set dip idx */ 4816 if (cong_field.dip_vld == 0) 4817 return 0; 4818 4819 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4820 if (ret) { 4821 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4822 return ret; 4823 } 4824 4825 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4826 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4827 4828 return 0; 4829 } 4830 4831 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4832 const struct ib_qp_attr *attr, 4833 int attr_mask, 4834 struct hns_roce_v2_qp_context *context, 4835 struct hns_roce_v2_qp_context *qpc_mask) 4836 { 4837 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4838 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4839 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4840 struct ib_device *ibdev = &hr_dev->ib_dev; 4841 const struct ib_gid_attr *gid_attr = NULL; 4842 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4843 int is_roce_protocol; 4844 u16 vlan_id = 0xffff; 4845 bool is_udp = false; 4846 u32 max_sl; 4847 u8 ib_port; 4848 u8 hr_port; 4849 int ret; 4850 4851 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4852 if (unlikely(sl > max_sl)) { 4853 ibdev_err_ratelimited(ibdev, 4854 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n", 4855 sl, max_sl); 4856 return -EINVAL; 4857 } 4858 4859 /* 4860 * If free_mr_en of qp is set, it means that this qp comes from 4861 * free mr. This qp will perform the loopback operation. 4862 * In the loopback scenario, only sl needs to be set. 4863 */ 4864 if (hr_qp->free_mr_en) { 4865 hr_reg_write(context, QPC_SL, sl); 4866 hr_reg_clear(qpc_mask, QPC_SL); 4867 hr_qp->sl = sl; 4868 return 0; 4869 } 4870 4871 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4872 hr_port = ib_port - 1; 4873 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4874 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4875 4876 if (is_roce_protocol) { 4877 gid_attr = attr->ah_attr.grh.sgid_attr; 4878 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4879 if (ret) 4880 return ret; 4881 4882 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4883 } 4884 4885 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4886 if (vlan_id < VLAN_N_VID && 4887 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4888 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4889 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4890 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4891 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4892 } 4893 4894 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4895 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4896 4897 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4898 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4899 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4900 return -EINVAL; 4901 } 4902 4903 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4904 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4905 return -EINVAL; 4906 } 4907 4908 hr_reg_write(context, QPC_UDPSPN, 4909 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4910 attr->dest_qp_num) : 4911 0); 4912 4913 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4914 4915 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4916 4917 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4918 4919 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4920 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4921 4922 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4923 if (ret) 4924 return ret; 4925 4926 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4927 hr_reg_clear(qpc_mask, QPC_TC); 4928 4929 hr_reg_write(context, QPC_FL, grh->flow_label); 4930 hr_reg_clear(qpc_mask, QPC_FL); 4931 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4932 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4933 4934 hr_qp->sl = sl; 4935 hr_reg_write(context, QPC_SL, hr_qp->sl); 4936 hr_reg_clear(qpc_mask, QPC_SL); 4937 4938 return 0; 4939 } 4940 4941 static bool check_qp_state(enum ib_qp_state cur_state, 4942 enum ib_qp_state new_state) 4943 { 4944 static const bool sm[][IB_QPS_ERR + 1] = { 4945 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4946 [IB_QPS_INIT] = true }, 4947 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4948 [IB_QPS_INIT] = true, 4949 [IB_QPS_RTR] = true, 4950 [IB_QPS_ERR] = true }, 4951 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4952 [IB_QPS_RTS] = true, 4953 [IB_QPS_ERR] = true }, 4954 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4955 [IB_QPS_RTS] = true, 4956 [IB_QPS_ERR] = true }, 4957 [IB_QPS_SQD] = {}, 4958 [IB_QPS_SQE] = {}, 4959 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4960 [IB_QPS_ERR] = true } 4961 }; 4962 4963 return sm[cur_state][new_state]; 4964 } 4965 4966 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4967 const struct ib_qp_attr *attr, 4968 int attr_mask, 4969 enum ib_qp_state cur_state, 4970 enum ib_qp_state new_state, 4971 struct hns_roce_v2_qp_context *context, 4972 struct hns_roce_v2_qp_context *qpc_mask, 4973 struct ib_udata *udata) 4974 { 4975 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4976 int ret = 0; 4977 4978 if (!check_qp_state(cur_state, new_state)) { 4979 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4980 return -EINVAL; 4981 } 4982 4983 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4984 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4985 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 4986 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4987 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 4988 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4989 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4990 qpc_mask, udata); 4991 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4992 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4993 qpc_mask); 4994 } 4995 4996 return ret; 4997 } 4998 4999 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5000 { 5001 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5002 #define QP_ACK_TIMEOUT_MAX 31 5003 5004 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5005 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5006 ibdev_warn(&hr_dev->ib_dev, 5007 "local ACK timeout shall be 0 to 20.\n"); 5008 return false; 5009 } 5010 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5011 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5012 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5013 ibdev_warn(&hr_dev->ib_dev, 5014 "local ACK timeout shall be 0 to 31.\n"); 5015 return false; 5016 } 5017 } 5018 5019 return true; 5020 } 5021 5022 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5023 const struct ib_qp_attr *attr, 5024 int attr_mask, 5025 struct hns_roce_v2_qp_context *context, 5026 struct hns_roce_v2_qp_context *qpc_mask) 5027 { 5028 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5029 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5030 int ret = 0; 5031 u8 timeout; 5032 5033 if (attr_mask & IB_QP_AV) { 5034 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5035 qpc_mask); 5036 if (ret) 5037 return ret; 5038 } 5039 5040 if (attr_mask & IB_QP_TIMEOUT) { 5041 timeout = attr->timeout; 5042 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5043 hr_reg_write(context, QPC_AT, timeout); 5044 hr_reg_clear(qpc_mask, QPC_AT); 5045 } 5046 } 5047 5048 if (attr_mask & IB_QP_RETRY_CNT) { 5049 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5050 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5051 5052 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5053 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5054 } 5055 5056 if (attr_mask & IB_QP_RNR_RETRY) { 5057 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5058 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5059 5060 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5061 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5062 } 5063 5064 if (attr_mask & IB_QP_SQ_PSN) { 5065 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5066 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5067 5068 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5069 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5070 5071 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5072 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5073 5074 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5075 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5076 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5077 5078 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5079 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5080 5081 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5082 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5083 } 5084 5085 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5086 attr->max_dest_rd_atomic) { 5087 hr_reg_write(context, QPC_RR_MAX, 5088 fls(attr->max_dest_rd_atomic - 1)); 5089 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5090 } 5091 5092 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5093 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5094 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5095 } 5096 5097 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5098 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5099 5100 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5101 hr_reg_write(context, QPC_MIN_RNR_TIME, 5102 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5103 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5104 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5105 } 5106 5107 if (attr_mask & IB_QP_RQ_PSN) { 5108 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5109 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5110 5111 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5112 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5113 } 5114 5115 if (attr_mask & IB_QP_QKEY) { 5116 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5117 qpc_mask->qkey_xrcd = 0; 5118 hr_qp->qkey = attr->qkey; 5119 } 5120 5121 return ret; 5122 } 5123 5124 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5125 const struct ib_qp_attr *attr, 5126 int attr_mask) 5127 { 5128 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5129 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5130 5131 if (attr_mask & IB_QP_ACCESS_FLAGS) 5132 hr_qp->atomic_rd_en = attr->qp_access_flags; 5133 5134 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5135 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5136 if (attr_mask & IB_QP_PORT) { 5137 hr_qp->port = attr->port_num - 1; 5138 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5139 } 5140 } 5141 5142 static void clear_qp(struct hns_roce_qp *hr_qp) 5143 { 5144 struct ib_qp *ibqp = &hr_qp->ibqp; 5145 5146 if (ibqp->send_cq) 5147 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5148 hr_qp->qpn, NULL); 5149 5150 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5151 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5152 hr_qp->qpn, ibqp->srq ? 5153 to_hr_srq(ibqp->srq) : NULL); 5154 5155 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5156 *hr_qp->rdb.db_record = 0; 5157 5158 hr_qp->rq.head = 0; 5159 hr_qp->rq.tail = 0; 5160 hr_qp->sq.head = 0; 5161 hr_qp->sq.tail = 0; 5162 hr_qp->next_sge = 0; 5163 } 5164 5165 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5166 struct hns_roce_v2_qp_context *context, 5167 struct hns_roce_v2_qp_context *qpc_mask) 5168 { 5169 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5170 unsigned long sq_flag = 0; 5171 unsigned long rq_flag = 0; 5172 5173 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5174 return; 5175 5176 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5177 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5178 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5179 hr_qp->state = IB_QPS_ERR; 5180 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5181 5182 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5183 return; 5184 5185 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5186 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5187 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5188 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5189 } 5190 5191 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5192 const struct ib_qp_attr *attr, 5193 int attr_mask, enum ib_qp_state cur_state, 5194 enum ib_qp_state new_state, struct ib_udata *udata) 5195 { 5196 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5197 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5198 struct hns_roce_v2_qp_context ctx[2]; 5199 struct hns_roce_v2_qp_context *context = ctx; 5200 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5201 struct ib_device *ibdev = &hr_dev->ib_dev; 5202 int ret; 5203 5204 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5205 return -EOPNOTSUPP; 5206 5207 /* 5208 * In v2 engine, software pass context and context mask to hardware 5209 * when modifying qp. If software need modify some fields in context, 5210 * we should set all bits of the relevant fields in context mask to 5211 * 0 at the same time, else set them to 0x1. 5212 */ 5213 memset(context, 0, hr_dev->caps.qpc_sz); 5214 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5215 5216 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5217 new_state, context, qpc_mask, udata); 5218 if (ret) 5219 goto out; 5220 5221 /* When QP state is err, SQ and RQ WQE should be flushed */ 5222 if (new_state == IB_QPS_ERR) 5223 v2_set_flushed_fields(ibqp, context, qpc_mask); 5224 5225 /* Configure the optional fields */ 5226 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5227 qpc_mask); 5228 if (ret) 5229 goto out; 5230 5231 hr_reg_write_bool(context, QPC_INV_CREDIT, 5232 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5233 ibqp->srq); 5234 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5235 5236 /* Every status migrate must change state */ 5237 hr_reg_write(context, QPC_QP_ST, new_state); 5238 hr_reg_clear(qpc_mask, QPC_QP_ST); 5239 5240 /* SW pass context to HW */ 5241 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5242 if (ret) { 5243 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5244 goto out; 5245 } 5246 5247 hr_qp->state = new_state; 5248 5249 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5250 5251 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5252 clear_qp(hr_qp); 5253 5254 out: 5255 return ret; 5256 } 5257 5258 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5259 { 5260 static const enum ib_qp_state map[] = { 5261 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5262 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5263 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5264 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5265 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5266 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5267 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5268 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5269 }; 5270 5271 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5272 } 5273 5274 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5275 void *buffer) 5276 { 5277 struct hns_roce_cmd_mailbox *mailbox; 5278 int ret; 5279 5280 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5281 if (IS_ERR(mailbox)) 5282 return PTR_ERR(mailbox); 5283 5284 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5285 qpn); 5286 if (ret) 5287 goto out; 5288 5289 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5290 5291 out: 5292 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5293 return ret; 5294 } 5295 5296 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5297 void *buffer) 5298 { 5299 struct hns_roce_srq_context *context; 5300 struct hns_roce_cmd_mailbox *mailbox; 5301 int ret; 5302 5303 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5304 if (IS_ERR(mailbox)) 5305 return PTR_ERR(mailbox); 5306 5307 context = mailbox->buf; 5308 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5309 srqn); 5310 if (ret) 5311 goto out; 5312 5313 memcpy(buffer, context, sizeof(*context)); 5314 5315 out: 5316 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5317 return ret; 5318 } 5319 5320 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 qpn, 5321 void *buffer) 5322 { 5323 struct hns_roce_v2_scc_context *context; 5324 struct hns_roce_cmd_mailbox *mailbox; 5325 int ret; 5326 5327 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5328 if (IS_ERR(mailbox)) 5329 return PTR_ERR(mailbox); 5330 5331 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5332 qpn); 5333 if (ret) 5334 goto out; 5335 5336 context = mailbox->buf; 5337 memcpy(buffer, context, sizeof(*context)); 5338 5339 out: 5340 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5341 return ret; 5342 } 5343 5344 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5345 struct hns_roce_v2_qp_context *context) 5346 { 5347 u8 timeout; 5348 5349 timeout = (u8)hr_reg_read(context, QPC_AT); 5350 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5351 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5352 5353 return timeout; 5354 } 5355 5356 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5357 int qp_attr_mask, 5358 struct ib_qp_init_attr *qp_init_attr) 5359 { 5360 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5361 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5362 struct hns_roce_v2_qp_context context = {}; 5363 struct ib_device *ibdev = &hr_dev->ib_dev; 5364 int tmp_qp_state; 5365 int state; 5366 int ret; 5367 5368 memset(qp_attr, 0, sizeof(*qp_attr)); 5369 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5370 5371 mutex_lock(&hr_qp->mutex); 5372 5373 if (hr_qp->state == IB_QPS_RESET) { 5374 qp_attr->qp_state = IB_QPS_RESET; 5375 ret = 0; 5376 goto done; 5377 } 5378 5379 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5380 if (ret) { 5381 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5382 ret = -EINVAL; 5383 goto out; 5384 } 5385 5386 state = hr_reg_read(&context, QPC_QP_ST); 5387 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5388 if (tmp_qp_state == -1) { 5389 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5390 ret = -EINVAL; 5391 goto out; 5392 } 5393 hr_qp->state = (u8)tmp_qp_state; 5394 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5395 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5396 qp_attr->path_mig_state = IB_MIG_ARMED; 5397 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5398 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5399 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5400 5401 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5402 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5403 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5404 qp_attr->qp_access_flags = 5405 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5406 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5407 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5408 5409 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5410 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5411 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5412 struct ib_global_route *grh = 5413 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5414 5415 rdma_ah_set_sl(&qp_attr->ah_attr, 5416 hr_reg_read(&context, QPC_SL)); 5417 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5418 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5419 grh->flow_label = hr_reg_read(&context, QPC_FL); 5420 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5421 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5422 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5423 5424 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5425 } 5426 5427 qp_attr->port_num = hr_qp->port + 1; 5428 qp_attr->sq_draining = 0; 5429 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5430 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5431 5432 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5433 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5434 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5435 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5436 5437 done: 5438 qp_attr->cur_qp_state = qp_attr->qp_state; 5439 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5440 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5441 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5442 5443 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5444 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5445 5446 qp_init_attr->qp_context = ibqp->qp_context; 5447 qp_init_attr->qp_type = ibqp->qp_type; 5448 qp_init_attr->recv_cq = ibqp->recv_cq; 5449 qp_init_attr->send_cq = ibqp->send_cq; 5450 qp_init_attr->srq = ibqp->srq; 5451 qp_init_attr->cap = qp_attr->cap; 5452 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5453 5454 out: 5455 mutex_unlock(&hr_qp->mutex); 5456 return ret; 5457 } 5458 5459 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5460 { 5461 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5462 hr_qp->ibqp.qp_type == IB_QPT_UD || 5463 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5464 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5465 hr_qp->state != IB_QPS_RESET); 5466 } 5467 5468 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5469 struct hns_roce_qp *hr_qp, 5470 struct ib_udata *udata) 5471 { 5472 struct ib_device *ibdev = &hr_dev->ib_dev; 5473 struct hns_roce_cq *send_cq, *recv_cq; 5474 unsigned long flags; 5475 int ret = 0; 5476 5477 if (modify_qp_is_ok(hr_qp)) { 5478 /* Modify qp to reset before destroying qp */ 5479 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5480 hr_qp->state, IB_QPS_RESET, udata); 5481 if (ret) 5482 ibdev_err(ibdev, 5483 "failed to modify QP to RST, ret = %d.\n", 5484 ret); 5485 } 5486 5487 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5488 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5489 5490 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5491 hns_roce_lock_cqs(send_cq, recv_cq); 5492 5493 if (!udata) { 5494 if (recv_cq) 5495 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5496 (hr_qp->ibqp.srq ? 5497 to_hr_srq(hr_qp->ibqp.srq) : 5498 NULL)); 5499 5500 if (send_cq && send_cq != recv_cq) 5501 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5502 } 5503 5504 hns_roce_qp_remove(hr_dev, hr_qp); 5505 5506 hns_roce_unlock_cqs(send_cq, recv_cq); 5507 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5508 5509 return ret; 5510 } 5511 5512 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5513 { 5514 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5515 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5516 int ret; 5517 5518 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5519 if (ret) 5520 ibdev_err(&hr_dev->ib_dev, 5521 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5522 hr_qp->qpn, ret); 5523 5524 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5525 5526 return 0; 5527 } 5528 5529 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5530 struct hns_roce_qp *hr_qp) 5531 { 5532 struct ib_device *ibdev = &hr_dev->ib_dev; 5533 struct hns_roce_sccc_clr_done *resp; 5534 struct hns_roce_sccc_clr *clr; 5535 struct hns_roce_cmq_desc desc; 5536 int ret, i; 5537 5538 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5539 return 0; 5540 5541 mutex_lock(&hr_dev->qp_table.scc_mutex); 5542 5543 /* set scc ctx clear done flag */ 5544 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5545 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5546 if (ret) { 5547 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5548 goto out; 5549 } 5550 5551 /* clear scc context */ 5552 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5553 clr = (struct hns_roce_sccc_clr *)desc.data; 5554 clr->qpn = cpu_to_le32(hr_qp->qpn); 5555 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5556 if (ret) { 5557 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5558 goto out; 5559 } 5560 5561 /* query scc context clear is done or not */ 5562 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5563 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5564 hns_roce_cmq_setup_basic_desc(&desc, 5565 HNS_ROCE_OPC_QUERY_SCCC, true); 5566 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5567 if (ret) { 5568 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5569 ret); 5570 goto out; 5571 } 5572 5573 if (resp->clr_done) 5574 goto out; 5575 5576 msleep(20); 5577 } 5578 5579 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5580 ret = -ETIMEDOUT; 5581 5582 out: 5583 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5584 return ret; 5585 } 5586 5587 #define DMA_IDX_SHIFT 3 5588 #define DMA_WQE_SHIFT 3 5589 5590 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5591 struct hns_roce_srq_context *ctx) 5592 { 5593 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5594 struct ib_device *ibdev = srq->ibsrq.device; 5595 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5596 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5597 dma_addr_t dma_handle_idx; 5598 int ret; 5599 5600 /* Get physical address of idx que buf */ 5601 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5602 ARRAY_SIZE(mtts_idx)); 5603 if (ret) { 5604 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5605 ret); 5606 return ret; 5607 } 5608 5609 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 5610 5611 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5612 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5613 5614 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5615 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5616 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5617 5618 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5619 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5620 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5621 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5622 5623 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5624 to_hr_hw_page_addr(mtts_idx[0])); 5625 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5626 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5627 5628 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5629 to_hr_hw_page_addr(mtts_idx[1])); 5630 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5631 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5632 5633 return 0; 5634 } 5635 5636 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5637 { 5638 struct ib_device *ibdev = srq->ibsrq.device; 5639 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5640 struct hns_roce_srq_context *ctx = mb_buf; 5641 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5642 dma_addr_t dma_handle_wqe; 5643 int ret; 5644 5645 memset(ctx, 0, sizeof(*ctx)); 5646 5647 /* Get the physical address of srq buf */ 5648 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5649 ARRAY_SIZE(mtts_wqe)); 5650 if (ret) { 5651 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5652 ret); 5653 return ret; 5654 } 5655 5656 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 5657 5658 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5659 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5660 srq->ibsrq.srq_type == IB_SRQT_XRC); 5661 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5662 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5663 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5664 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5665 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5666 hr_reg_write(ctx, SRQC_RQWS, 5667 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5668 5669 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5670 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5671 srq->wqe_cnt)); 5672 5673 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5674 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5675 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5676 5677 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5678 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5679 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5680 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5681 5682 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5683 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5684 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5685 lower_32_bits(srq->rdb.dma) >> 1); 5686 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5687 upper_32_bits(srq->rdb.dma)); 5688 } 5689 5690 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5691 } 5692 5693 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5694 struct ib_srq_attr *srq_attr, 5695 enum ib_srq_attr_mask srq_attr_mask, 5696 struct ib_udata *udata) 5697 { 5698 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5699 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5700 struct hns_roce_srq_context *srq_context; 5701 struct hns_roce_srq_context *srqc_mask; 5702 struct hns_roce_cmd_mailbox *mailbox; 5703 int ret = 0; 5704 5705 /* Resizing SRQs is not supported yet */ 5706 if (srq_attr_mask & IB_SRQ_MAX_WR) { 5707 ret = -EOPNOTSUPP; 5708 goto out; 5709 } 5710 5711 if (srq_attr_mask & IB_SRQ_LIMIT) { 5712 if (srq_attr->srq_limit > srq->wqe_cnt) { 5713 ret = -EINVAL; 5714 goto out; 5715 } 5716 5717 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5718 if (IS_ERR(mailbox)) { 5719 ret = PTR_ERR(mailbox); 5720 goto out; 5721 } 5722 5723 srq_context = mailbox->buf; 5724 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5725 5726 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5727 5728 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5729 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5730 5731 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5732 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5733 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5734 if (ret) 5735 ibdev_err(&hr_dev->ib_dev, 5736 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5737 ret); 5738 } 5739 5740 out: 5741 if (ret) 5742 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 5743 5744 return ret; 5745 } 5746 5747 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5748 { 5749 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5750 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5751 struct hns_roce_srq_context *srq_context; 5752 struct hns_roce_cmd_mailbox *mailbox; 5753 int ret; 5754 5755 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5756 if (IS_ERR(mailbox)) 5757 return PTR_ERR(mailbox); 5758 5759 srq_context = mailbox->buf; 5760 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5761 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5762 if (ret) { 5763 ibdev_err(&hr_dev->ib_dev, 5764 "failed to process cmd of querying SRQ, ret = %d.\n", 5765 ret); 5766 goto out; 5767 } 5768 5769 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5770 attr->max_wr = srq->wqe_cnt; 5771 attr->max_sge = srq->max_gs - srq->rsv_sge; 5772 5773 out: 5774 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5775 return ret; 5776 } 5777 5778 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5779 { 5780 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5781 struct hns_roce_v2_cq_context *cq_context; 5782 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5783 struct hns_roce_v2_cq_context *cqc_mask; 5784 struct hns_roce_cmd_mailbox *mailbox; 5785 int ret; 5786 5787 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5788 ret = PTR_ERR_OR_ZERO(mailbox); 5789 if (ret) 5790 goto err_out; 5791 5792 cq_context = mailbox->buf; 5793 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5794 5795 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5796 5797 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5798 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5799 5800 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5801 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5802 dev_info(hr_dev->dev, 5803 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5804 cq_period); 5805 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5806 } 5807 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5808 } 5809 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5810 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5811 5812 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5813 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5814 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5815 if (ret) 5816 ibdev_err(&hr_dev->ib_dev, 5817 "failed to process cmd when modifying CQ, ret = %d.\n", 5818 ret); 5819 5820 err_out: 5821 if (ret) 5822 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 5823 5824 return ret; 5825 } 5826 5827 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5828 void *buffer) 5829 { 5830 struct hns_roce_v2_cq_context *context; 5831 struct hns_roce_cmd_mailbox *mailbox; 5832 int ret; 5833 5834 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5835 if (IS_ERR(mailbox)) 5836 return PTR_ERR(mailbox); 5837 5838 context = mailbox->buf; 5839 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5840 HNS_ROCE_CMD_QUERY_CQC, cqn); 5841 if (ret) { 5842 ibdev_err(&hr_dev->ib_dev, 5843 "failed to process cmd when querying CQ, ret = %d.\n", 5844 ret); 5845 goto err_mailbox; 5846 } 5847 5848 memcpy(buffer, context, sizeof(*context)); 5849 5850 err_mailbox: 5851 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5852 5853 return ret; 5854 } 5855 5856 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5857 void *buffer) 5858 { 5859 struct hns_roce_v2_mpt_entry *context; 5860 struct hns_roce_cmd_mailbox *mailbox; 5861 int ret; 5862 5863 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5864 if (IS_ERR(mailbox)) 5865 return PTR_ERR(mailbox); 5866 5867 context = mailbox->buf; 5868 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5869 key_to_hw_index(key)); 5870 if (ret) { 5871 ibdev_err(&hr_dev->ib_dev, 5872 "failed to process cmd when querying MPT, ret = %d.\n", 5873 ret); 5874 goto err_mailbox; 5875 } 5876 5877 memcpy(buffer, context, sizeof(*context)); 5878 5879 err_mailbox: 5880 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5881 5882 return ret; 5883 } 5884 5885 static void hns_roce_irq_work_handle(struct work_struct *work) 5886 { 5887 struct hns_roce_work *irq_work = 5888 container_of(work, struct hns_roce_work, work); 5889 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5890 5891 switch (irq_work->event_type) { 5892 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5893 ibdev_info(ibdev, "path migrated succeeded.\n"); 5894 break; 5895 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5896 ibdev_warn(ibdev, "path migration failed.\n"); 5897 break; 5898 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5899 break; 5900 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5901 ibdev_dbg(ibdev, "send queue drained.\n"); 5902 break; 5903 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5904 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5905 irq_work->queue_num, irq_work->sub_type); 5906 break; 5907 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5908 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5909 irq_work->queue_num); 5910 break; 5911 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5912 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5913 irq_work->queue_num, irq_work->sub_type); 5914 break; 5915 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5916 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 5917 break; 5918 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5919 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 5920 break; 5921 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5922 ibdev_err(ibdev, "SRQ catas error.\n"); 5923 break; 5924 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5925 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5926 break; 5927 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5928 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5929 break; 5930 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5931 ibdev_warn(ibdev, "DB overflow.\n"); 5932 break; 5933 case HNS_ROCE_EVENT_TYPE_FLR: 5934 ibdev_warn(ibdev, "function level reset.\n"); 5935 break; 5936 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5937 ibdev_err(ibdev, "xrc domain violation error.\n"); 5938 break; 5939 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5940 ibdev_err(ibdev, "invalid xrceth error.\n"); 5941 break; 5942 default: 5943 break; 5944 } 5945 5946 kfree(irq_work); 5947 } 5948 5949 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5950 struct hns_roce_eq *eq, u32 queue_num) 5951 { 5952 struct hns_roce_work *irq_work; 5953 5954 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5955 if (!irq_work) 5956 return; 5957 5958 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5959 irq_work->hr_dev = hr_dev; 5960 irq_work->event_type = eq->event_type; 5961 irq_work->sub_type = eq->sub_type; 5962 irq_work->queue_num = queue_num; 5963 queue_work(hr_dev->irq_workq, &irq_work->work); 5964 } 5965 5966 static void update_eq_db(struct hns_roce_eq *eq) 5967 { 5968 struct hns_roce_dev *hr_dev = eq->hr_dev; 5969 struct hns_roce_v2_db eq_db = {}; 5970 5971 if (eq->type_flag == HNS_ROCE_AEQ) { 5972 hr_reg_write(&eq_db, EQ_DB_CMD, 5973 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5974 HNS_ROCE_EQ_DB_CMD_AEQ : 5975 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5976 } else { 5977 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5978 5979 hr_reg_write(&eq_db, EQ_DB_CMD, 5980 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5981 HNS_ROCE_EQ_DB_CMD_CEQ : 5982 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5983 } 5984 5985 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5986 5987 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5988 } 5989 5990 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5991 { 5992 struct hns_roce_aeqe *aeqe; 5993 5994 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5995 (eq->cons_index & (eq->entries - 1)) * 5996 eq->eqe_size); 5997 5998 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5999 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6000 } 6001 6002 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6003 struct hns_roce_eq *eq) 6004 { 6005 struct device *dev = hr_dev->dev; 6006 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6007 irqreturn_t aeqe_found = IRQ_NONE; 6008 int event_type; 6009 u32 queue_num; 6010 int sub_type; 6011 6012 while (aeqe) { 6013 /* Make sure we read AEQ entry after we have checked the 6014 * ownership bit 6015 */ 6016 dma_rmb(); 6017 6018 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6019 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6020 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6021 6022 switch (event_type) { 6023 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6024 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6025 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6026 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6027 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6028 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6029 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6030 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6031 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6032 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6033 hns_roce_qp_event(hr_dev, queue_num, event_type); 6034 break; 6035 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6036 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6037 hns_roce_srq_event(hr_dev, queue_num, event_type); 6038 break; 6039 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6040 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6041 hns_roce_cq_event(hr_dev, queue_num, event_type); 6042 break; 6043 case HNS_ROCE_EVENT_TYPE_MB: 6044 hns_roce_cmd_event(hr_dev, 6045 le16_to_cpu(aeqe->event.cmd.token), 6046 aeqe->event.cmd.status, 6047 le64_to_cpu(aeqe->event.cmd.out_param)); 6048 break; 6049 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6050 case HNS_ROCE_EVENT_TYPE_FLR: 6051 break; 6052 default: 6053 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 6054 event_type, eq->eqn, eq->cons_index); 6055 break; 6056 } 6057 6058 eq->event_type = event_type; 6059 eq->sub_type = sub_type; 6060 ++eq->cons_index; 6061 aeqe_found = IRQ_HANDLED; 6062 6063 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6064 6065 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6066 6067 aeqe = next_aeqe_sw_v2(eq); 6068 } 6069 6070 update_eq_db(eq); 6071 6072 return IRQ_RETVAL(aeqe_found); 6073 } 6074 6075 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6076 { 6077 struct hns_roce_ceqe *ceqe; 6078 6079 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6080 (eq->cons_index & (eq->entries - 1)) * 6081 eq->eqe_size); 6082 6083 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6084 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6085 } 6086 6087 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6088 struct hns_roce_eq *eq) 6089 { 6090 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6091 irqreturn_t ceqe_found = IRQ_NONE; 6092 u32 cqn; 6093 6094 while (ceqe) { 6095 /* Make sure we read CEQ entry after we have checked the 6096 * ownership bit 6097 */ 6098 dma_rmb(); 6099 6100 cqn = hr_reg_read(ceqe, CEQE_CQN); 6101 6102 hns_roce_cq_completion(hr_dev, cqn); 6103 6104 ++eq->cons_index; 6105 ceqe_found = IRQ_HANDLED; 6106 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6107 6108 ceqe = next_ceqe_sw_v2(eq); 6109 } 6110 6111 update_eq_db(eq); 6112 6113 return IRQ_RETVAL(ceqe_found); 6114 } 6115 6116 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6117 { 6118 struct hns_roce_eq *eq = eq_ptr; 6119 struct hns_roce_dev *hr_dev = eq->hr_dev; 6120 irqreturn_t int_work; 6121 6122 if (eq->type_flag == HNS_ROCE_CEQ) 6123 /* Completion event interrupt */ 6124 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6125 else 6126 /* Asynchronous event interrupt */ 6127 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6128 6129 return IRQ_RETVAL(int_work); 6130 } 6131 6132 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6133 u32 int_st) 6134 { 6135 struct pci_dev *pdev = hr_dev->pci_dev; 6136 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6137 const struct hnae3_ae_ops *ops = ae_dev->ops; 6138 irqreturn_t int_work = IRQ_NONE; 6139 u32 int_en; 6140 6141 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6142 6143 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6144 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6145 6146 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6147 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6148 6149 /* Set reset level for reset_event() */ 6150 if (ops->set_default_reset_request) 6151 ops->set_default_reset_request(ae_dev, 6152 HNAE3_FUNC_RESET); 6153 if (ops->reset_event) 6154 ops->reset_event(pdev, NULL); 6155 6156 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6157 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6158 6159 int_work = IRQ_HANDLED; 6160 } else { 6161 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6162 } 6163 6164 return IRQ_RETVAL(int_work); 6165 } 6166 6167 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6168 struct fmea_ram_ecc *ecc_info) 6169 { 6170 struct hns_roce_cmq_desc desc; 6171 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6172 int ret; 6173 6174 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6175 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6176 if (ret) 6177 return ret; 6178 6179 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6180 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6181 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6182 6183 return 0; 6184 } 6185 6186 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6187 { 6188 struct hns_roce_cmq_desc desc; 6189 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6190 u32 addr_upper; 6191 u32 addr_low; 6192 int ret; 6193 6194 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6195 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6196 6197 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6198 if (ret) { 6199 dev_err(hr_dev->dev, 6200 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6201 return ret; 6202 } 6203 6204 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6205 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6206 6207 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6208 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6209 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6210 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6211 6212 return hns_roce_cmq_send(hr_dev, &desc, 1); 6213 } 6214 6215 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6216 { 6217 if (res_type == ECC_RESOURCE_QPC_TIMER || 6218 res_type == ECC_RESOURCE_CQC_TIMER || 6219 res_type == ECC_RESOURCE_SCCC) 6220 return le64_to_cpu(*data); 6221 6222 return le64_to_cpu(*data) << PAGE_SHIFT; 6223 } 6224 6225 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6226 u32 index) 6227 { 6228 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6229 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6230 struct hns_roce_cmd_mailbox *mailbox; 6231 u64 addr; 6232 int ret; 6233 6234 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6235 if (IS_ERR(mailbox)) 6236 return PTR_ERR(mailbox); 6237 6238 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6239 if (ret) { 6240 dev_err(hr_dev->dev, 6241 "failed to execute cmd to read fmea ram, ret = %d.\n", 6242 ret); 6243 goto out; 6244 } 6245 6246 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6247 6248 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6249 if (ret) 6250 dev_err(hr_dev->dev, 6251 "failed to execute cmd to write fmea ram, ret = %d.\n", 6252 ret); 6253 6254 out: 6255 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6256 return ret; 6257 } 6258 6259 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6260 struct fmea_ram_ecc *ecc_info) 6261 { 6262 u32 res_type = ecc_info->res_type; 6263 u32 index = ecc_info->index; 6264 int ret; 6265 6266 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6267 6268 if (res_type >= ECC_RESOURCE_COUNT) { 6269 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6270 res_type); 6271 return; 6272 } 6273 6274 if (res_type == ECC_RESOURCE_GMV) 6275 ret = fmea_recover_gmv(hr_dev, index); 6276 else 6277 ret = fmea_recover_others(hr_dev, res_type, index); 6278 if (ret) 6279 dev_err(hr_dev->dev, 6280 "failed to recover %s, index = %u, ret = %d.\n", 6281 fmea_ram_res[res_type].name, index, ret); 6282 } 6283 6284 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6285 { 6286 struct hns_roce_dev *hr_dev = 6287 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6288 struct fmea_ram_ecc ecc_info = {}; 6289 6290 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6291 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6292 return; 6293 } 6294 6295 if (!ecc_info.is_ecc_err) { 6296 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6297 return; 6298 } 6299 6300 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6301 } 6302 6303 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6304 { 6305 struct hns_roce_dev *hr_dev = dev_id; 6306 irqreturn_t int_work = IRQ_NONE; 6307 u32 int_st; 6308 6309 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6310 6311 if (int_st) { 6312 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6313 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6314 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6315 int_work = IRQ_HANDLED; 6316 } else { 6317 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6318 } 6319 6320 return IRQ_RETVAL(int_work); 6321 } 6322 6323 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6324 int eq_num, u32 enable_flag) 6325 { 6326 int i; 6327 6328 for (i = 0; i < eq_num; i++) 6329 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6330 i * EQ_REG_OFFSET, enable_flag); 6331 6332 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6333 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6334 } 6335 6336 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6337 { 6338 struct device *dev = hr_dev->dev; 6339 int ret; 6340 u8 cmd; 6341 6342 if (eqn < hr_dev->caps.num_comp_vectors) 6343 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6344 else 6345 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6346 6347 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6348 if (ret) 6349 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6350 } 6351 6352 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6353 { 6354 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6355 } 6356 6357 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6358 { 6359 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6360 eq->cons_index = 0; 6361 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6362 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6363 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6364 eq->shift = ilog2((unsigned int)eq->entries); 6365 } 6366 6367 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6368 void *mb_buf) 6369 { 6370 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6371 struct hns_roce_eq_context *eqc; 6372 u64 bt_ba = 0; 6373 int ret; 6374 6375 eqc = mb_buf; 6376 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6377 6378 init_eq_config(hr_dev, eq); 6379 6380 /* if not multi-hop, eqe buffer only use one trunk */ 6381 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6382 ARRAY_SIZE(eqe_ba)); 6383 if (ret) { 6384 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6385 return ret; 6386 } 6387 6388 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6389 6390 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6391 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6392 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6393 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6394 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6395 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6396 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6397 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6398 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6399 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6400 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6401 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6402 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6403 6404 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6405 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6406 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6407 eq->eq_period); 6408 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6409 } 6410 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6411 } 6412 6413 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6414 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6415 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6416 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6417 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6418 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6419 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6420 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6421 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6422 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6423 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6424 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6425 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6426 6427 return 0; 6428 } 6429 6430 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6431 { 6432 struct hns_roce_buf_attr buf_attr = {}; 6433 int err; 6434 6435 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6436 eq->hop_num = 0; 6437 else 6438 eq->hop_num = hr_dev->caps.eqe_hop_num; 6439 6440 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6441 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6442 buf_attr.region[0].hopnum = eq->hop_num; 6443 buf_attr.region_count = 1; 6444 6445 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6446 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6447 0); 6448 if (err) 6449 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6450 6451 return err; 6452 } 6453 6454 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6455 struct hns_roce_eq *eq, u8 eq_cmd) 6456 { 6457 struct hns_roce_cmd_mailbox *mailbox; 6458 int ret; 6459 6460 /* Allocate mailbox memory */ 6461 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6462 if (IS_ERR(mailbox)) 6463 return PTR_ERR(mailbox); 6464 6465 ret = alloc_eq_buf(hr_dev, eq); 6466 if (ret) 6467 goto free_cmd_mbox; 6468 6469 ret = config_eqc(hr_dev, eq, mailbox->buf); 6470 if (ret) 6471 goto err_cmd_mbox; 6472 6473 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6474 if (ret) { 6475 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6476 goto err_cmd_mbox; 6477 } 6478 6479 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6480 6481 return 0; 6482 6483 err_cmd_mbox: 6484 free_eq_buf(hr_dev, eq); 6485 6486 free_cmd_mbox: 6487 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6488 6489 return ret; 6490 } 6491 6492 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6493 int comp_num, int aeq_num, int other_num) 6494 { 6495 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6496 int i, j; 6497 int ret; 6498 6499 for (i = 0; i < irq_num; i++) { 6500 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6501 GFP_KERNEL); 6502 if (!hr_dev->irq_names[i]) { 6503 ret = -ENOMEM; 6504 goto err_kzalloc_failed; 6505 } 6506 } 6507 6508 /* irq contains: abnormal + AEQ + CEQ */ 6509 for (j = 0; j < other_num; j++) 6510 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6511 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 6512 6513 for (j = other_num; j < (other_num + aeq_num); j++) 6514 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6515 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 6516 6517 for (j = (other_num + aeq_num); j < irq_num; j++) 6518 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6519 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 6520 j - other_num - aeq_num); 6521 6522 for (j = 0; j < irq_num; j++) { 6523 if (j < other_num) 6524 ret = request_irq(hr_dev->irq[j], 6525 hns_roce_v2_msix_interrupt_abn, 6526 0, hr_dev->irq_names[j], hr_dev); 6527 6528 else if (j < (other_num + comp_num)) 6529 ret = request_irq(eq_table->eq[j - other_num].irq, 6530 hns_roce_v2_msix_interrupt_eq, 6531 0, hr_dev->irq_names[j + aeq_num], 6532 &eq_table->eq[j - other_num]); 6533 else 6534 ret = request_irq(eq_table->eq[j - other_num].irq, 6535 hns_roce_v2_msix_interrupt_eq, 6536 0, hr_dev->irq_names[j - comp_num], 6537 &eq_table->eq[j - other_num]); 6538 if (ret) { 6539 dev_err(hr_dev->dev, "request irq error!\n"); 6540 goto err_request_failed; 6541 } 6542 } 6543 6544 return 0; 6545 6546 err_request_failed: 6547 for (j -= 1; j >= 0; j--) 6548 if (j < other_num) 6549 free_irq(hr_dev->irq[j], hr_dev); 6550 else 6551 free_irq(eq_table->eq[j - other_num].irq, 6552 &eq_table->eq[j - other_num]); 6553 6554 err_kzalloc_failed: 6555 for (i -= 1; i >= 0; i--) 6556 kfree(hr_dev->irq_names[i]); 6557 6558 return ret; 6559 } 6560 6561 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6562 { 6563 int irq_num; 6564 int eq_num; 6565 int i; 6566 6567 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6568 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6569 6570 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6571 free_irq(hr_dev->irq[i], hr_dev); 6572 6573 for (i = 0; i < eq_num; i++) 6574 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6575 6576 for (i = 0; i < irq_num; i++) 6577 kfree(hr_dev->irq_names[i]); 6578 } 6579 6580 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6581 { 6582 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6583 struct device *dev = hr_dev->dev; 6584 struct hns_roce_eq *eq; 6585 int other_num; 6586 int comp_num; 6587 int aeq_num; 6588 int irq_num; 6589 int eq_num; 6590 u8 eq_cmd; 6591 int ret; 6592 int i; 6593 6594 other_num = hr_dev->caps.num_other_vectors; 6595 comp_num = hr_dev->caps.num_comp_vectors; 6596 aeq_num = hr_dev->caps.num_aeq_vectors; 6597 6598 eq_num = comp_num + aeq_num; 6599 irq_num = eq_num + other_num; 6600 6601 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6602 if (!eq_table->eq) 6603 return -ENOMEM; 6604 6605 /* create eq */ 6606 for (i = 0; i < eq_num; i++) { 6607 eq = &eq_table->eq[i]; 6608 eq->hr_dev = hr_dev; 6609 eq->eqn = i; 6610 if (i < comp_num) { 6611 /* CEQ */ 6612 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6613 eq->type_flag = HNS_ROCE_CEQ; 6614 eq->entries = hr_dev->caps.ceqe_depth; 6615 eq->eqe_size = hr_dev->caps.ceqe_size; 6616 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6617 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6618 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6619 } else { 6620 /* AEQ */ 6621 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6622 eq->type_flag = HNS_ROCE_AEQ; 6623 eq->entries = hr_dev->caps.aeqe_depth; 6624 eq->eqe_size = hr_dev->caps.aeqe_size; 6625 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6626 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6627 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6628 } 6629 6630 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6631 if (ret) { 6632 dev_err(dev, "failed to create eq.\n"); 6633 goto err_create_eq_fail; 6634 } 6635 } 6636 6637 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6638 6639 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6640 if (!hr_dev->irq_workq) { 6641 dev_err(dev, "failed to create irq workqueue.\n"); 6642 ret = -ENOMEM; 6643 goto err_create_eq_fail; 6644 } 6645 6646 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6647 other_num); 6648 if (ret) { 6649 dev_err(dev, "failed to request irq.\n"); 6650 goto err_request_irq_fail; 6651 } 6652 6653 /* enable irq */ 6654 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6655 6656 return 0; 6657 6658 err_request_irq_fail: 6659 destroy_workqueue(hr_dev->irq_workq); 6660 6661 err_create_eq_fail: 6662 for (i -= 1; i >= 0; i--) 6663 free_eq_buf(hr_dev, &eq_table->eq[i]); 6664 kfree(eq_table->eq); 6665 6666 return ret; 6667 } 6668 6669 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6670 { 6671 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6672 int eq_num; 6673 int i; 6674 6675 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6676 6677 /* Disable irq */ 6678 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6679 6680 __hns_roce_free_irq(hr_dev); 6681 destroy_workqueue(hr_dev->irq_workq); 6682 6683 for (i = 0; i < eq_num; i++) { 6684 hns_roce_v2_destroy_eqc(hr_dev, i); 6685 6686 free_eq_buf(hr_dev, &eq_table->eq[i]); 6687 } 6688 6689 kfree(eq_table->eq); 6690 } 6691 6692 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6693 .destroy_qp = hns_roce_v2_destroy_qp, 6694 .modify_cq = hns_roce_v2_modify_cq, 6695 .poll_cq = hns_roce_v2_poll_cq, 6696 .post_recv = hns_roce_v2_post_recv, 6697 .post_send = hns_roce_v2_post_send, 6698 .query_qp = hns_roce_v2_query_qp, 6699 .req_notify_cq = hns_roce_v2_req_notify_cq, 6700 }; 6701 6702 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6703 .modify_srq = hns_roce_v2_modify_srq, 6704 .post_srq_recv = hns_roce_v2_post_srq_recv, 6705 .query_srq = hns_roce_v2_query_srq, 6706 }; 6707 6708 static const struct hns_roce_hw hns_roce_hw_v2 = { 6709 .cmq_init = hns_roce_v2_cmq_init, 6710 .cmq_exit = hns_roce_v2_cmq_exit, 6711 .hw_profile = hns_roce_v2_profile, 6712 .hw_init = hns_roce_v2_init, 6713 .hw_exit = hns_roce_v2_exit, 6714 .post_mbox = v2_post_mbox, 6715 .poll_mbox_done = v2_poll_mbox_done, 6716 .chk_mbox_avail = v2_chk_mbox_is_avail, 6717 .set_gid = hns_roce_v2_set_gid, 6718 .set_mac = hns_roce_v2_set_mac, 6719 .write_mtpt = hns_roce_v2_write_mtpt, 6720 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6721 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6722 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6723 .write_cqc = hns_roce_v2_write_cqc, 6724 .set_hem = hns_roce_v2_set_hem, 6725 .clear_hem = hns_roce_v2_clear_hem, 6726 .modify_qp = hns_roce_v2_modify_qp, 6727 .dereg_mr = hns_roce_v2_dereg_mr, 6728 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6729 .init_eq = hns_roce_v2_init_eq_table, 6730 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6731 .write_srqc = hns_roce_v2_write_srqc, 6732 .query_cqc = hns_roce_v2_query_cqc, 6733 .query_qpc = hns_roce_v2_query_qpc, 6734 .query_mpt = hns_roce_v2_query_mpt, 6735 .query_srqc = hns_roce_v2_query_srqc, 6736 .query_sccc = hns_roce_v2_query_sccc, 6737 .query_hw_counter = hns_roce_hw_v2_query_counter, 6738 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6739 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6740 }; 6741 6742 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6743 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6744 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6745 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6746 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6747 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6748 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6749 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6750 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6751 /* required last entry */ 6752 {0, } 6753 }; 6754 6755 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6756 6757 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6758 struct hnae3_handle *handle) 6759 { 6760 struct hns_roce_v2_priv *priv = hr_dev->priv; 6761 const struct pci_device_id *id; 6762 int i; 6763 6764 hr_dev->pci_dev = handle->pdev; 6765 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6766 hr_dev->is_vf = id->driver_data; 6767 hr_dev->dev = &handle->pdev->dev; 6768 hr_dev->hw = &hns_roce_hw_v2; 6769 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6770 hr_dev->odb_offset = hr_dev->sdb_offset; 6771 6772 /* Get info from NIC driver. */ 6773 hr_dev->reg_base = handle->rinfo.roce_io_base; 6774 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6775 hr_dev->caps.num_ports = 1; 6776 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6777 hr_dev->iboe.phy_port[0] = 0; 6778 6779 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6780 hr_dev->iboe.netdevs[0]->dev_addr); 6781 6782 for (i = 0; i < handle->rinfo.num_vectors; i++) 6783 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6784 i + handle->rinfo.base_vector); 6785 6786 /* cmd issue mode: 0 is poll, 1 is event */ 6787 hr_dev->cmd_mod = 1; 6788 hr_dev->loop_idc = 0; 6789 6790 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6791 priv->handle = handle; 6792 } 6793 6794 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6795 { 6796 struct hns_roce_dev *hr_dev; 6797 int ret; 6798 6799 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6800 if (!hr_dev) 6801 return -ENOMEM; 6802 6803 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6804 if (!hr_dev->priv) { 6805 ret = -ENOMEM; 6806 goto error_failed_kzalloc; 6807 } 6808 6809 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6810 6811 ret = hns_roce_init(hr_dev); 6812 if (ret) { 6813 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6814 goto error_failed_roce_init; 6815 } 6816 6817 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6818 ret = free_mr_init(hr_dev); 6819 if (ret) { 6820 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6821 goto error_failed_free_mr_init; 6822 } 6823 } 6824 6825 handle->priv = hr_dev; 6826 6827 return 0; 6828 6829 error_failed_free_mr_init: 6830 hns_roce_exit(hr_dev); 6831 6832 error_failed_roce_init: 6833 kfree(hr_dev->priv); 6834 6835 error_failed_kzalloc: 6836 ib_dealloc_device(&hr_dev->ib_dev); 6837 6838 return ret; 6839 } 6840 6841 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6842 bool reset) 6843 { 6844 struct hns_roce_dev *hr_dev = handle->priv; 6845 6846 if (!hr_dev) 6847 return; 6848 6849 handle->priv = NULL; 6850 6851 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6852 hns_roce_handle_device_err(hr_dev); 6853 6854 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6855 free_mr_exit(hr_dev); 6856 6857 hns_roce_exit(hr_dev); 6858 kfree(hr_dev->priv); 6859 ib_dealloc_device(&hr_dev->ib_dev); 6860 } 6861 6862 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6863 { 6864 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6865 const struct pci_device_id *id; 6866 struct device *dev = &handle->pdev->dev; 6867 int ret; 6868 6869 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6870 6871 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6872 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6873 goto reset_chk_err; 6874 } 6875 6876 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6877 if (!id) 6878 return 0; 6879 6880 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6881 return 0; 6882 6883 ret = __hns_roce_hw_v2_init_instance(handle); 6884 if (ret) { 6885 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6886 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6887 if (ops->ae_dev_resetting(handle) || 6888 ops->get_hw_reset_stat(handle)) 6889 goto reset_chk_err; 6890 else 6891 return ret; 6892 } 6893 6894 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6895 6896 return 0; 6897 6898 reset_chk_err: 6899 dev_err(dev, "Device is busy in resetting state.\n" 6900 "please retry later.\n"); 6901 6902 return -EBUSY; 6903 } 6904 6905 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6906 bool reset) 6907 { 6908 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6909 return; 6910 6911 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6912 6913 __hns_roce_hw_v2_uninit_instance(handle, reset); 6914 6915 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6916 } 6917 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6918 { 6919 struct hns_roce_dev *hr_dev; 6920 6921 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6922 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6923 return 0; 6924 } 6925 6926 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6927 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6928 6929 hr_dev = handle->priv; 6930 if (!hr_dev) 6931 return 0; 6932 6933 hr_dev->active = false; 6934 hr_dev->dis_db = true; 6935 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6936 6937 return 0; 6938 } 6939 6940 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6941 { 6942 struct device *dev = &handle->pdev->dev; 6943 int ret; 6944 6945 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6946 &handle->rinfo.state)) { 6947 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6948 return 0; 6949 } 6950 6951 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6952 6953 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6954 ret = __hns_roce_hw_v2_init_instance(handle); 6955 if (ret) { 6956 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6957 * callback function, RoCE Engine reinitialize. If RoCE reinit 6958 * failed, we should inform NIC driver. 6959 */ 6960 handle->priv = NULL; 6961 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6962 } else { 6963 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6964 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6965 } 6966 6967 return ret; 6968 } 6969 6970 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6971 { 6972 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6973 return 0; 6974 6975 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6976 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6977 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6978 __hns_roce_hw_v2_uninit_instance(handle, false); 6979 6980 return 0; 6981 } 6982 6983 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6984 enum hnae3_reset_notify_type type) 6985 { 6986 int ret = 0; 6987 6988 switch (type) { 6989 case HNAE3_DOWN_CLIENT: 6990 ret = hns_roce_hw_v2_reset_notify_down(handle); 6991 break; 6992 case HNAE3_INIT_CLIENT: 6993 ret = hns_roce_hw_v2_reset_notify_init(handle); 6994 break; 6995 case HNAE3_UNINIT_CLIENT: 6996 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6997 break; 6998 default: 6999 break; 7000 } 7001 7002 return ret; 7003 } 7004 7005 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7006 .init_instance = hns_roce_hw_v2_init_instance, 7007 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7008 .reset_notify = hns_roce_hw_v2_reset_notify, 7009 }; 7010 7011 static struct hnae3_client hns_roce_hw_v2_client = { 7012 .name = "hns_roce_hw_v2", 7013 .type = HNAE3_CLIENT_ROCE, 7014 .ops = &hns_roce_hw_v2_ops, 7015 }; 7016 7017 static int __init hns_roce_hw_v2_init(void) 7018 { 7019 hns_roce_init_debugfs(); 7020 return hnae3_register_client(&hns_roce_hw_v2_client); 7021 } 7022 7023 static void __exit hns_roce_hw_v2_exit(void) 7024 { 7025 hnae3_unregister_client(&hns_roce_hw_v2_client); 7026 hns_roce_cleanup_debugfs(); 7027 } 7028 7029 module_init(hns_roce_hw_v2_init); 7030 module_exit(hns_roce_hw_v2_exit); 7031 7032 MODULE_LICENSE("Dual BSD/GPL"); 7033 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7034 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7035 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7036 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7037