1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <linux/workqueue.h> 40 #include <net/addrconf.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <rdma/ib_umem.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include "hnae3.h" 47 #include "hns_roce_common.h" 48 #include "hns_roce_device.h" 49 #include "hns_roce_cmd.h" 50 #include "hns_roce_hem.h" 51 #include "hns_roce_hw_v2.h" 52 53 enum { 54 CMD_RST_PRC_OTHERS, 55 CMD_RST_PRC_SUCCESS, 56 CMD_RST_PRC_EBUSY, 57 }; 58 59 enum ecc_resource_type { 60 ECC_RESOURCE_QPC, 61 ECC_RESOURCE_CQC, 62 ECC_RESOURCE_MPT, 63 ECC_RESOURCE_SRQC, 64 ECC_RESOURCE_GMV, 65 ECC_RESOURCE_QPC_TIMER, 66 ECC_RESOURCE_CQC_TIMER, 67 ECC_RESOURCE_SCCC, 68 ECC_RESOURCE_COUNT, 69 }; 70 71 static const struct { 72 const char *name; 73 u8 read_bt0_op; 74 u8 write_bt0_op; 75 } fmea_ram_res[] = { 76 { "ECC_RESOURCE_QPC", 77 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 78 { "ECC_RESOURCE_CQC", 79 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 80 { "ECC_RESOURCE_MPT", 81 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 82 { "ECC_RESOURCE_SRQC", 83 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 84 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 85 { "ECC_RESOURCE_GMV", 86 0, 0 }, 87 { "ECC_RESOURCE_QPC_TIMER", 88 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 89 { "ECC_RESOURCE_CQC_TIMER", 90 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 91 { "ECC_RESOURCE_SCCC", 92 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 93 }; 94 95 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 96 struct ib_sge *sg) 97 { 98 dseg->lkey = cpu_to_le32(sg->lkey); 99 dseg->addr = cpu_to_le64(sg->addr); 100 dseg->len = cpu_to_le32(sg->length); 101 } 102 103 /* 104 * mapped-value = 1 + real-value 105 * The hns wr opcode real value is start from 0, In order to distinguish between 106 * initialized and uninitialized map values, we plus 1 to the actual value when 107 * defining the mapping, so that the validity can be identified by checking the 108 * mapped value is greater than 0. 109 */ 110 #define HR_OPC_MAP(ib_key, hr_key) \ 111 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 112 113 static const u32 hns_roce_op_code[] = { 114 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 115 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 116 HR_OPC_MAP(SEND, SEND), 117 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 118 HR_OPC_MAP(RDMA_READ, RDMA_READ), 119 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 120 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 121 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 122 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 123 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 124 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 125 }; 126 127 static u32 to_hr_opcode(u32 ib_opcode) 128 { 129 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 130 return HNS_ROCE_V2_WQE_OP_MASK; 131 132 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 133 HNS_ROCE_V2_WQE_OP_MASK; 134 } 135 136 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 137 const struct ib_reg_wr *wr) 138 { 139 struct hns_roce_wqe_frmr_seg *fseg = 140 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 141 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 142 u64 pbl_ba; 143 144 /* use ib_access_flags */ 145 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 146 hr_reg_write_bool(fseg, FRMR_ATOMIC, 147 wr->access & IB_ACCESS_REMOTE_ATOMIC); 148 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 149 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 150 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 151 152 /* Data structure reuse may lead to confusion */ 153 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 154 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 155 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 156 157 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 158 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 159 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 160 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 161 162 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 163 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 164 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 165 hr_reg_clear(fseg, FRMR_BLK_MODE); 166 } 167 168 static void set_atomic_seg(const struct ib_send_wr *wr, 169 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 170 unsigned int valid_num_sge) 171 { 172 struct hns_roce_v2_wqe_data_seg *dseg = 173 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 174 struct hns_roce_wqe_atomic_seg *aseg = 175 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 176 177 set_data_seg_v2(dseg, wr->sg_list); 178 179 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 180 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 181 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 182 } else { 183 aseg->fetchadd_swap_data = 184 cpu_to_le64(atomic_wr(wr)->compare_add); 185 aseg->cmp_data = 0; 186 } 187 188 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 189 } 190 191 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 192 const struct ib_send_wr *wr, 193 unsigned int *sge_idx, u32 msg_len) 194 { 195 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 196 unsigned int left_len_in_pg; 197 unsigned int idx = *sge_idx; 198 unsigned int i = 0; 199 unsigned int len; 200 void *addr; 201 void *dseg; 202 203 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 204 ibdev_err(ibdev, 205 "no enough extended sge space for inline data.\n"); 206 return -EINVAL; 207 } 208 209 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 210 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 211 len = wr->sg_list[0].length; 212 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 213 214 /* When copying data to extended sge space, the left length in page may 215 * not long enough for current user's sge. So the data should be 216 * splited into several parts, one in the first page, and the others in 217 * the subsequent pages. 218 */ 219 while (1) { 220 if (len <= left_len_in_pg) { 221 memcpy(dseg, addr, len); 222 223 idx += len / HNS_ROCE_SGE_SIZE; 224 225 i++; 226 if (i >= wr->num_sge) 227 break; 228 229 left_len_in_pg -= len; 230 len = wr->sg_list[i].length; 231 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 232 dseg += len; 233 } else { 234 memcpy(dseg, addr, left_len_in_pg); 235 236 len -= left_len_in_pg; 237 addr += left_len_in_pg; 238 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 239 dseg = hns_roce_get_extend_sge(qp, 240 idx & (qp->sge.sge_cnt - 1)); 241 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 242 } 243 } 244 245 *sge_idx = idx; 246 247 return 0; 248 } 249 250 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 251 unsigned int *sge_ind, unsigned int cnt) 252 { 253 struct hns_roce_v2_wqe_data_seg *dseg; 254 unsigned int idx = *sge_ind; 255 256 while (cnt > 0) { 257 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 258 if (likely(sge->length)) { 259 set_data_seg_v2(dseg, sge); 260 idx++; 261 cnt--; 262 } 263 sge++; 264 } 265 266 *sge_ind = idx; 267 } 268 269 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 270 { 271 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 272 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 273 274 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 275 ibdev_err(&hr_dev->ib_dev, 276 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 277 len, qp->max_inline_data, mtu); 278 return false; 279 } 280 281 return true; 282 } 283 284 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 285 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 286 unsigned int *sge_idx) 287 { 288 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 289 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 290 struct ib_device *ibdev = &hr_dev->ib_dev; 291 unsigned int curr_idx = *sge_idx; 292 void *dseg = rc_sq_wqe; 293 unsigned int i; 294 int ret; 295 296 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 297 ibdev_err(ibdev, "invalid inline parameters!\n"); 298 return -EINVAL; 299 } 300 301 if (!check_inl_data_len(qp, msg_len)) 302 return -EINVAL; 303 304 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 305 306 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 307 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 308 309 for (i = 0; i < wr->num_sge; i++) { 310 memcpy(dseg, ((void *)wr->sg_list[i].addr), 311 wr->sg_list[i].length); 312 dseg += wr->sg_list[i].length; 313 } 314 } else { 315 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 316 317 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 318 if (ret) 319 return ret; 320 321 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 322 } 323 324 *sge_idx = curr_idx; 325 326 return 0; 327 } 328 329 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 330 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 331 unsigned int *sge_ind, 332 unsigned int valid_num_sge) 333 { 334 struct hns_roce_v2_wqe_data_seg *dseg = 335 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 336 struct hns_roce_qp *qp = to_hr_qp(ibqp); 337 int j = 0; 338 int i; 339 340 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 341 (*sge_ind) & (qp->sge.sge_cnt - 1)); 342 343 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 344 !!(wr->send_flags & IB_SEND_INLINE)); 345 if (wr->send_flags & IB_SEND_INLINE) 346 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 347 348 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 349 for (i = 0; i < wr->num_sge; i++) { 350 if (likely(wr->sg_list[i].length)) { 351 set_data_seg_v2(dseg, wr->sg_list + i); 352 dseg++; 353 } 354 } 355 } else { 356 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 357 if (likely(wr->sg_list[i].length)) { 358 set_data_seg_v2(dseg, wr->sg_list + i); 359 dseg++; 360 j++; 361 } 362 } 363 364 set_extend_sge(qp, wr->sg_list + i, sge_ind, 365 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 366 } 367 368 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 369 370 return 0; 371 } 372 373 static int check_send_valid(struct hns_roce_dev *hr_dev, 374 struct hns_roce_qp *hr_qp) 375 { 376 if (unlikely(hr_qp->state == IB_QPS_RESET || 377 hr_qp->state == IB_QPS_INIT || 378 hr_qp->state == IB_QPS_RTR)) 379 return -EINVAL; 380 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 381 return -EIO; 382 383 return 0; 384 } 385 386 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 387 unsigned int *sge_len) 388 { 389 unsigned int valid_num = 0; 390 unsigned int len = 0; 391 int i; 392 393 for (i = 0; i < wr->num_sge; i++) { 394 if (likely(wr->sg_list[i].length)) { 395 len += wr->sg_list[i].length; 396 valid_num++; 397 } 398 } 399 400 *sge_len = len; 401 return valid_num; 402 } 403 404 static __le32 get_immtdata(const struct ib_send_wr *wr) 405 { 406 switch (wr->opcode) { 407 case IB_WR_SEND_WITH_IMM: 408 case IB_WR_RDMA_WRITE_WITH_IMM: 409 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 410 default: 411 return 0; 412 } 413 } 414 415 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 416 const struct ib_send_wr *wr) 417 { 418 u32 ib_op = wr->opcode; 419 420 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 421 return -EINVAL; 422 423 ud_sq_wqe->immtdata = get_immtdata(wr); 424 425 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 426 427 return 0; 428 } 429 430 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 431 struct hns_roce_ah *ah) 432 { 433 struct ib_device *ib_dev = ah->ibah.device; 434 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 435 436 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 437 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 441 442 ud_sq_wqe->sgid_index = ah->av.gid_index; 443 444 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 445 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 446 447 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 448 return 0; 449 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 451 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 452 453 return 0; 454 } 455 456 static inline int set_ud_wqe(struct hns_roce_qp *qp, 457 const struct ib_send_wr *wr, 458 void *wqe, unsigned int *sge_idx, 459 unsigned int owner_bit) 460 { 461 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 462 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 463 unsigned int curr_idx = *sge_idx; 464 unsigned int valid_num_sge; 465 u32 msg_len = 0; 466 int ret; 467 468 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 469 470 ret = set_ud_opcode(ud_sq_wqe, wr); 471 if (WARN_ON_ONCE(ret)) 472 return ret; 473 474 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 475 476 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 477 !!(wr->send_flags & IB_SEND_SIGNALED)); 478 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 479 !!(wr->send_flags & IB_SEND_SOLICITED)); 480 481 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 482 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 483 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 484 curr_idx & (qp->sge.sge_cnt - 1)); 485 486 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 487 qp->qkey : ud_wr(wr)->remote_qkey); 488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 489 490 ret = fill_ud_av(ud_sq_wqe, ah); 491 if (ret) 492 return ret; 493 494 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 495 496 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 497 498 /* 499 * The pipeline can sequentially post all valid WQEs into WQ buffer, 500 * including new WQEs waiting for the doorbell to update the PI again. 501 * Therefore, the owner bit of WQE MUST be updated after all fields 502 * and extSGEs have been written into DDR instead of cache. 503 */ 504 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 505 dma_wmb(); 506 507 *sge_idx = curr_idx; 508 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 509 510 return 0; 511 } 512 513 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 514 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 515 const struct ib_send_wr *wr) 516 { 517 u32 ib_op = wr->opcode; 518 int ret = 0; 519 520 rc_sq_wqe->immtdata = get_immtdata(wr); 521 522 switch (ib_op) { 523 case IB_WR_RDMA_READ: 524 case IB_WR_RDMA_WRITE: 525 case IB_WR_RDMA_WRITE_WITH_IMM: 526 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 527 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 528 break; 529 case IB_WR_SEND: 530 case IB_WR_SEND_WITH_IMM: 531 break; 532 case IB_WR_ATOMIC_CMP_AND_SWP: 533 case IB_WR_ATOMIC_FETCH_AND_ADD: 534 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 535 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 536 break; 537 case IB_WR_REG_MR: 538 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 539 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 540 else 541 ret = -EOPNOTSUPP; 542 break; 543 case IB_WR_SEND_WITH_INV: 544 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 545 break; 546 default: 547 ret = -EINVAL; 548 } 549 550 if (unlikely(ret)) 551 return ret; 552 553 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 554 555 return ret; 556 } 557 558 static inline int set_rc_wqe(struct hns_roce_qp *qp, 559 const struct ib_send_wr *wr, 560 void *wqe, unsigned int *sge_idx, 561 unsigned int owner_bit) 562 { 563 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 564 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 565 unsigned int curr_idx = *sge_idx; 566 unsigned int valid_num_sge; 567 u32 msg_len = 0; 568 int ret; 569 570 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 571 572 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 573 574 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 575 if (WARN_ON_ONCE(ret)) 576 return ret; 577 578 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO, 579 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 580 581 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 582 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 583 584 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 585 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 586 587 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 588 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 589 if (msg_len != ATOMIC_WR_LEN) 590 return -EINVAL; 591 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 592 } else if (wr->opcode != IB_WR_REG_MR) { 593 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 594 &curr_idx, valid_num_sge); 595 if (ret) 596 return ret; 597 } 598 599 /* 600 * The pipeline can sequentially post all valid WQEs into WQ buffer, 601 * including new WQEs waiting for the doorbell to update the PI again. 602 * Therefore, the owner bit of WQE MUST be updated after all fields 603 * and extSGEs have been written into DDR instead of cache. 604 */ 605 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 606 dma_wmb(); 607 608 *sge_idx = curr_idx; 609 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 610 611 return ret; 612 } 613 614 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 615 struct hns_roce_qp *qp) 616 { 617 if (unlikely(qp->state == IB_QPS_ERR)) { 618 flush_cqe(hr_dev, qp); 619 } else { 620 struct hns_roce_v2_db sq_db = {}; 621 622 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 623 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 624 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 625 hr_reg_write(&sq_db, DB_SL, qp->sl); 626 627 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 628 } 629 } 630 631 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 632 struct hns_roce_qp *qp) 633 { 634 if (unlikely(qp->state == IB_QPS_ERR)) { 635 flush_cqe(hr_dev, qp); 636 } else { 637 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 638 *qp->rdb.db_record = 639 qp->rq.head & V2_DB_PRODUCER_IDX_M; 640 } else { 641 struct hns_roce_v2_db rq_db = {}; 642 643 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 644 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 645 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 646 647 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 648 qp->rq.db_reg); 649 } 650 } 651 } 652 653 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 654 u64 __iomem *dest) 655 { 656 #define HNS_ROCE_WRITE_TIMES 8 657 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 658 struct hnae3_handle *handle = priv->handle; 659 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 660 int i; 661 662 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 663 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 664 writeq_relaxed(*(val + i), dest + i); 665 } 666 667 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 668 void *wqe) 669 { 670 #define HNS_ROCE_SL_SHIFT 2 671 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 672 673 if (unlikely(qp->state == IB_QPS_ERR)) { 674 flush_cqe(hr_dev, qp); 675 return; 676 } 677 /* All kinds of DirectWQE have the same header field layout */ 678 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 679 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 680 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 681 qp->sl >> HNS_ROCE_SL_SHIFT); 682 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 683 684 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 685 } 686 687 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 688 const struct ib_send_wr *wr, 689 const struct ib_send_wr **bad_wr) 690 { 691 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 692 struct ib_device *ibdev = &hr_dev->ib_dev; 693 struct hns_roce_qp *qp = to_hr_qp(ibqp); 694 unsigned long flags = 0; 695 unsigned int owner_bit; 696 unsigned int sge_idx; 697 unsigned int wqe_idx; 698 void *wqe = NULL; 699 u32 nreq; 700 int ret; 701 702 spin_lock_irqsave(&qp->sq.lock, flags); 703 704 ret = check_send_valid(hr_dev, qp); 705 if (unlikely(ret)) { 706 *bad_wr = wr; 707 nreq = 0; 708 goto out; 709 } 710 711 sge_idx = qp->next_sge; 712 713 for (nreq = 0; wr; ++nreq, wr = wr->next) { 714 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 715 ret = -ENOMEM; 716 *bad_wr = wr; 717 goto out; 718 } 719 720 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 721 722 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 723 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 724 wr->num_sge, qp->sq.max_gs); 725 ret = -EINVAL; 726 *bad_wr = wr; 727 goto out; 728 } 729 730 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 731 qp->sq.wrid[wqe_idx] = wr->wr_id; 732 owner_bit = 733 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 734 735 /* Corresponding to the QP type, wqe process separately */ 736 if (ibqp->qp_type == IB_QPT_RC) 737 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 738 else 739 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 740 741 if (unlikely(ret)) { 742 *bad_wr = wr; 743 goto out; 744 } 745 } 746 747 out: 748 if (likely(nreq)) { 749 qp->sq.head += nreq; 750 qp->next_sge = sge_idx; 751 752 if (nreq == 1 && !ret && 753 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 754 write_dwqe(hr_dev, qp, wqe); 755 else 756 update_sq_db(hr_dev, qp); 757 } 758 759 spin_unlock_irqrestore(&qp->sq.lock, flags); 760 761 return ret; 762 } 763 764 static int check_recv_valid(struct hns_roce_dev *hr_dev, 765 struct hns_roce_qp *hr_qp) 766 { 767 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 768 return -EIO; 769 770 if (hr_qp->state == IB_QPS_RESET) 771 return -EINVAL; 772 773 return 0; 774 } 775 776 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 777 u32 max_sge, bool rsv) 778 { 779 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 780 u32 i, cnt; 781 782 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 783 /* Skip zero-length sge */ 784 if (!wr->sg_list[i].length) 785 continue; 786 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 787 cnt++; 788 } 789 790 /* Fill a reserved sge to make hw stop reading remaining segments */ 791 if (rsv) { 792 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 793 dseg[cnt].addr = 0; 794 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 795 } else { 796 /* Clear remaining segments to make ROCEE ignore sges */ 797 if (cnt < max_sge) 798 memset(dseg + cnt, 0, 799 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 800 } 801 } 802 803 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 804 u32 wqe_idx, u32 max_sge) 805 { 806 void *wqe = NULL; 807 808 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 809 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 810 } 811 812 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 813 const struct ib_recv_wr *wr, 814 const struct ib_recv_wr **bad_wr) 815 { 816 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 817 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 818 struct ib_device *ibdev = &hr_dev->ib_dev; 819 u32 wqe_idx, nreq, max_sge; 820 unsigned long flags; 821 int ret; 822 823 spin_lock_irqsave(&hr_qp->rq.lock, flags); 824 825 ret = check_recv_valid(hr_dev, hr_qp); 826 if (unlikely(ret)) { 827 *bad_wr = wr; 828 nreq = 0; 829 goto out; 830 } 831 832 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 833 for (nreq = 0; wr; ++nreq, wr = wr->next) { 834 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 835 hr_qp->ibqp.recv_cq))) { 836 ret = -ENOMEM; 837 *bad_wr = wr; 838 goto out; 839 } 840 841 if (unlikely(wr->num_sge > max_sge)) { 842 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 843 wr->num_sge, max_sge); 844 ret = -EINVAL; 845 *bad_wr = wr; 846 goto out; 847 } 848 849 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 850 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 851 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 852 } 853 854 out: 855 if (likely(nreq)) { 856 hr_qp->rq.head += nreq; 857 858 update_rq_db(hr_dev, hr_qp); 859 } 860 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 861 862 return ret; 863 } 864 865 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 866 { 867 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 868 } 869 870 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 871 { 872 return hns_roce_buf_offset(idx_que->mtr.kmem, 873 n << idx_que->entry_shift); 874 } 875 876 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 877 { 878 /* always called with interrupts disabled. */ 879 spin_lock(&srq->lock); 880 881 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 882 srq->idx_que.tail++; 883 884 spin_unlock(&srq->lock); 885 } 886 887 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 888 { 889 struct hns_roce_idx_que *idx_que = &srq->idx_que; 890 891 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 892 } 893 894 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 895 const struct ib_recv_wr *wr) 896 { 897 struct ib_device *ib_dev = srq->ibsrq.device; 898 899 if (unlikely(wr->num_sge > max_sge)) { 900 ibdev_err(ib_dev, 901 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 902 wr->num_sge, max_sge); 903 return -EINVAL; 904 } 905 906 if (unlikely(hns_roce_srqwq_overflow(srq))) { 907 ibdev_err(ib_dev, 908 "failed to check srqwq status, srqwq is full.\n"); 909 return -ENOMEM; 910 } 911 912 return 0; 913 } 914 915 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 916 { 917 struct hns_roce_idx_que *idx_que = &srq->idx_que; 918 u32 pos; 919 920 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 921 if (unlikely(pos == srq->wqe_cnt)) 922 return -ENOSPC; 923 924 bitmap_set(idx_que->bitmap, pos, 1); 925 *wqe_idx = pos; 926 return 0; 927 } 928 929 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 930 { 931 struct hns_roce_idx_que *idx_que = &srq->idx_que; 932 unsigned int head; 933 __le32 *buf; 934 935 head = idx_que->head & (srq->wqe_cnt - 1); 936 937 buf = get_idx_buf(idx_que, head); 938 *buf = cpu_to_le32(wqe_idx); 939 940 idx_que->head++; 941 } 942 943 static void update_srq_db(struct hns_roce_srq *srq) 944 { 945 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 946 struct hns_roce_v2_db db; 947 948 hr_reg_write(&db, DB_TAG, srq->srqn); 949 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 950 hr_reg_write(&db, DB_PI, srq->idx_que.head); 951 952 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 953 } 954 955 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 956 const struct ib_recv_wr *wr, 957 const struct ib_recv_wr **bad_wr) 958 { 959 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 960 unsigned long flags; 961 int ret = 0; 962 u32 max_sge; 963 u32 wqe_idx; 964 void *wqe; 965 u32 nreq; 966 967 spin_lock_irqsave(&srq->lock, flags); 968 969 max_sge = srq->max_gs - srq->rsv_sge; 970 for (nreq = 0; wr; ++nreq, wr = wr->next) { 971 ret = check_post_srq_valid(srq, max_sge, wr); 972 if (ret) { 973 *bad_wr = wr; 974 break; 975 } 976 977 ret = get_srq_wqe_idx(srq, &wqe_idx); 978 if (unlikely(ret)) { 979 *bad_wr = wr; 980 break; 981 } 982 983 wqe = get_srq_wqe_buf(srq, wqe_idx); 984 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 985 fill_wqe_idx(srq, wqe_idx); 986 srq->wrid[wqe_idx] = wr->wr_id; 987 } 988 989 if (likely(nreq)) { 990 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 991 *srq->rdb.db_record = srq->idx_que.head & 992 V2_DB_PRODUCER_IDX_M; 993 else 994 update_srq_db(srq); 995 } 996 997 spin_unlock_irqrestore(&srq->lock, flags); 998 999 return ret; 1000 } 1001 1002 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1003 unsigned long instance_stage, 1004 unsigned long reset_stage) 1005 { 1006 /* When hardware reset has been completed once or more, we should stop 1007 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1008 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1009 * stage of soft reset process, we should exit with error, and then 1010 * HNAE3_INIT_CLIENT related process can rollback the operation like 1011 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1012 * process will exit with error to notify NIC driver to reschedule soft 1013 * reset process once again. 1014 */ 1015 hr_dev->is_reset = true; 1016 hr_dev->dis_db = true; 1017 1018 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1019 instance_stage == HNS_ROCE_STATE_INIT) 1020 return CMD_RST_PRC_EBUSY; 1021 1022 return CMD_RST_PRC_SUCCESS; 1023 } 1024 1025 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1026 unsigned long instance_stage, 1027 unsigned long reset_stage) 1028 { 1029 #define HW_RESET_TIMEOUT_US 1000000 1030 #define HW_RESET_SLEEP_US 1000 1031 1032 struct hns_roce_v2_priv *priv = hr_dev->priv; 1033 struct hnae3_handle *handle = priv->handle; 1034 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1035 unsigned long val; 1036 int ret; 1037 1038 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1039 * doorbell to hardware. If now in .init_instance() function, we should 1040 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1041 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1042 * related process can rollback the operation like notifing hardware to 1043 * free resources, HNAE3_INIT_CLIENT related process will exit with 1044 * error to notify NIC driver to reschedule soft reset process once 1045 * again. 1046 */ 1047 hr_dev->dis_db = true; 1048 1049 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1050 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1051 HW_RESET_TIMEOUT_US, false, handle); 1052 if (!ret) 1053 hr_dev->is_reset = true; 1054 1055 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1056 instance_stage == HNS_ROCE_STATE_INIT) 1057 return CMD_RST_PRC_EBUSY; 1058 1059 return CMD_RST_PRC_SUCCESS; 1060 } 1061 1062 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1063 { 1064 struct hns_roce_v2_priv *priv = hr_dev->priv; 1065 struct hnae3_handle *handle = priv->handle; 1066 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1067 1068 /* When software reset is detected at .init_instance() function, we 1069 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1070 * with error. 1071 */ 1072 hr_dev->dis_db = true; 1073 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1074 hr_dev->is_reset = true; 1075 1076 return CMD_RST_PRC_EBUSY; 1077 } 1078 1079 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1080 struct hnae3_handle *handle) 1081 { 1082 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1083 unsigned long instance_stage; /* the current instance stage */ 1084 unsigned long reset_stage; /* the current reset stage */ 1085 unsigned long reset_cnt; 1086 bool sw_resetting; 1087 bool hw_resetting; 1088 1089 /* Get information about reset from NIC driver or RoCE driver itself, 1090 * the meaning of the following variables from NIC driver are described 1091 * as below: 1092 * reset_cnt -- The count value of completed hardware reset. 1093 * hw_resetting -- Whether hardware device is resetting now. 1094 * sw_resetting -- Whether NIC's software reset process is running now. 1095 */ 1096 instance_stage = handle->rinfo.instance_state; 1097 reset_stage = handle->rinfo.reset_state; 1098 reset_cnt = ops->ae_dev_reset_cnt(handle); 1099 if (reset_cnt != hr_dev->reset_cnt) 1100 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1101 reset_stage); 1102 1103 hw_resetting = ops->get_cmdq_stat(handle); 1104 if (hw_resetting) 1105 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1106 reset_stage); 1107 1108 sw_resetting = ops->ae_dev_resetting(handle); 1109 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1110 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1111 1112 return CMD_RST_PRC_OTHERS; 1113 } 1114 1115 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1116 { 1117 struct hns_roce_v2_priv *priv = hr_dev->priv; 1118 struct hnae3_handle *handle = priv->handle; 1119 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1120 1121 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1122 return true; 1123 1124 if (ops->get_hw_reset_stat(handle)) 1125 return true; 1126 1127 if (ops->ae_dev_resetting(handle)) 1128 return true; 1129 1130 return false; 1131 } 1132 1133 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1134 { 1135 struct hns_roce_v2_priv *priv = hr_dev->priv; 1136 u32 status; 1137 1138 if (hr_dev->is_reset) 1139 status = CMD_RST_PRC_SUCCESS; 1140 else 1141 status = check_aedev_reset_status(hr_dev, priv->handle); 1142 1143 *busy = (status == CMD_RST_PRC_EBUSY); 1144 1145 return status == CMD_RST_PRC_OTHERS; 1146 } 1147 1148 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1149 struct hns_roce_v2_cmq_ring *ring) 1150 { 1151 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1152 1153 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1154 &ring->desc_dma_addr, GFP_KERNEL); 1155 if (!ring->desc) 1156 return -ENOMEM; 1157 1158 return 0; 1159 } 1160 1161 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1162 struct hns_roce_v2_cmq_ring *ring) 1163 { 1164 dma_free_coherent(hr_dev->dev, 1165 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1166 ring->desc, ring->desc_dma_addr); 1167 1168 ring->desc_dma_addr = 0; 1169 } 1170 1171 static int init_csq(struct hns_roce_dev *hr_dev, 1172 struct hns_roce_v2_cmq_ring *csq) 1173 { 1174 dma_addr_t dma; 1175 int ret; 1176 1177 csq->desc_num = CMD_CSQ_DESC_NUM; 1178 spin_lock_init(&csq->lock); 1179 csq->flag = TYPE_CSQ; 1180 csq->head = 0; 1181 1182 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1183 if (ret) 1184 return ret; 1185 1186 dma = csq->desc_dma_addr; 1187 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1188 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1189 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1190 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1191 1192 /* Make sure to write CI first and then PI */ 1193 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1194 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1195 1196 return 0; 1197 } 1198 1199 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1200 { 1201 struct hns_roce_v2_priv *priv = hr_dev->priv; 1202 int ret; 1203 1204 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1205 1206 ret = init_csq(hr_dev, &priv->cmq.csq); 1207 if (ret) 1208 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1209 1210 return ret; 1211 } 1212 1213 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1214 { 1215 struct hns_roce_v2_priv *priv = hr_dev->priv; 1216 1217 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1218 } 1219 1220 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1221 enum hns_roce_opcode_type opcode, 1222 bool is_read) 1223 { 1224 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1225 desc->opcode = cpu_to_le16(opcode); 1226 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1227 if (is_read) 1228 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1229 else 1230 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1231 } 1232 1233 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1234 { 1235 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1236 struct hns_roce_v2_priv *priv = hr_dev->priv; 1237 1238 return tail == priv->cmq.csq.head; 1239 } 1240 1241 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1242 { 1243 struct hns_roce_v2_priv *priv = hr_dev->priv; 1244 struct hnae3_handle *handle = priv->handle; 1245 1246 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1247 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1248 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1249 } 1250 1251 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1252 { 1253 struct hns_roce_cmd_errcode errcode_table[] = { 1254 {CMD_EXEC_SUCCESS, 0}, 1255 {CMD_NO_AUTH, -EPERM}, 1256 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1257 {CMD_CRQ_FULL, -EXFULL}, 1258 {CMD_NEXT_ERR, -ENOSR}, 1259 {CMD_NOT_EXEC, -ENOTBLK}, 1260 {CMD_PARA_ERR, -EINVAL}, 1261 {CMD_RESULT_ERR, -ERANGE}, 1262 {CMD_TIMEOUT, -ETIME}, 1263 {CMD_HILINK_ERR, -ENOLINK}, 1264 {CMD_INFO_ILLEGAL, -ENXIO}, 1265 {CMD_INVALID, -EBADR}, 1266 }; 1267 u16 i; 1268 1269 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1270 if (desc_ret == errcode_table[i].return_status) 1271 return errcode_table[i].errno; 1272 return -EIO; 1273 } 1274 1275 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 1276 { 1277 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = { 1278 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT}, 1279 }; 1280 int i; 1281 1282 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++) 1283 if (cmdq_tx_timeout[i].opcode == opcode) 1284 return cmdq_tx_timeout[i].tx_timeout; 1285 1286 return tx_timeout; 1287 } 1288 1289 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout) 1290 { 1291 u32 timeout = 0; 1292 1293 do { 1294 if (hns_roce_cmq_csq_done(hr_dev)) 1295 break; 1296 udelay(1); 1297 } while (++timeout < tx_timeout); 1298 } 1299 1300 static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev, 1301 struct hns_roce_cmq_desc *desc, 1302 int num, u32 tx_timeout) 1303 { 1304 struct hns_roce_v2_priv *priv = hr_dev->priv; 1305 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1306 u16 desc_ret; 1307 u32 tail; 1308 int ret; 1309 int i; 1310 1311 tail = csq->head; 1312 1313 for (i = 0; i < num; i++) { 1314 csq->desc[csq->head++] = desc[i]; 1315 if (csq->head == csq->desc_num) 1316 csq->head = 0; 1317 } 1318 1319 /* Write to hardware */ 1320 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1321 1322 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1323 1324 hns_roce_wait_csq_done(hr_dev, tx_timeout); 1325 if (hns_roce_cmq_csq_done(hr_dev)) { 1326 ret = 0; 1327 for (i = 0; i < num; i++) { 1328 /* check the result of hardware write back */ 1329 desc_ret = le16_to_cpu(csq->desc[tail++].retval); 1330 if (tail == csq->desc_num) 1331 tail = 0; 1332 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1333 continue; 1334 1335 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1336 } 1337 } else { 1338 /* FW/HW reset or incorrect number of desc */ 1339 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1340 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1341 csq->head, tail); 1342 csq->head = tail; 1343 1344 update_cmdq_status(hr_dev); 1345 1346 ret = -EAGAIN; 1347 } 1348 1349 if (ret) 1350 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1351 1352 return ret; 1353 } 1354 1355 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1356 struct hns_roce_cmq_desc *desc, int num) 1357 { 1358 struct hns_roce_v2_priv *priv = hr_dev->priv; 1359 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1360 u16 opcode = le16_to_cpu(desc->opcode); 1361 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout); 1362 u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT; 1363 u32 rsv_tail; 1364 int ret; 1365 int i; 1366 1367 while (try_cnt) { 1368 try_cnt--; 1369 1370 spin_lock_bh(&csq->lock); 1371 rsv_tail = csq->head; 1372 ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout); 1373 if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME && 1374 try_cnt) { 1375 spin_unlock_bh(&csq->lock); 1376 mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC); 1377 continue; 1378 } 1379 1380 for (i = 0; i < num; i++) { 1381 desc[i] = csq->desc[rsv_tail++]; 1382 if (rsv_tail == csq->desc_num) 1383 rsv_tail = 0; 1384 } 1385 spin_unlock_bh(&csq->lock); 1386 break; 1387 } 1388 1389 if (ret) 1390 dev_err_ratelimited(hr_dev->dev, 1391 "Cmdq IO error, opcode = 0x%x, return = %d.\n", 1392 opcode, ret); 1393 1394 return ret; 1395 } 1396 1397 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1398 struct hns_roce_cmq_desc *desc, int num) 1399 { 1400 bool busy; 1401 int ret; 1402 1403 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1404 return -EIO; 1405 1406 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1407 return busy ? -EBUSY : 0; 1408 1409 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1410 if (ret) { 1411 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1412 return busy ? -EBUSY : 0; 1413 } 1414 1415 return ret; 1416 } 1417 1418 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1419 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1420 { 1421 struct hns_roce_cmd_mailbox *mbox; 1422 int ret; 1423 1424 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1425 if (IS_ERR(mbox)) 1426 return PTR_ERR(mbox); 1427 1428 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1429 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1430 return ret; 1431 } 1432 1433 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1434 { 1435 struct hns_roce_query_version *resp; 1436 struct hns_roce_cmq_desc desc; 1437 int ret; 1438 1439 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1440 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1441 if (ret) 1442 return ret; 1443 1444 resp = (struct hns_roce_query_version *)desc.data; 1445 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1446 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1447 1448 return 0; 1449 } 1450 1451 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1452 struct hnae3_handle *handle) 1453 { 1454 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1455 unsigned long end; 1456 1457 hr_dev->dis_db = true; 1458 1459 dev_warn(hr_dev->dev, 1460 "func clear is pending, device in resetting state.\n"); 1461 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1462 while (end) { 1463 if (!ops->get_hw_reset_stat(handle)) { 1464 hr_dev->is_reset = true; 1465 dev_info(hr_dev->dev, 1466 "func clear success after reset.\n"); 1467 return; 1468 } 1469 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1470 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1471 } 1472 1473 dev_warn(hr_dev->dev, "func clear failed.\n"); 1474 } 1475 1476 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1477 struct hnae3_handle *handle) 1478 { 1479 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1480 unsigned long end; 1481 1482 hr_dev->dis_db = true; 1483 1484 dev_warn(hr_dev->dev, 1485 "func clear is pending, device in resetting state.\n"); 1486 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1487 while (end) { 1488 if (ops->ae_dev_reset_cnt(handle) != 1489 hr_dev->reset_cnt) { 1490 hr_dev->is_reset = true; 1491 dev_info(hr_dev->dev, 1492 "func clear success after sw reset\n"); 1493 return; 1494 } 1495 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1496 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1497 } 1498 1499 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1500 } 1501 1502 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1503 int flag) 1504 { 1505 struct hns_roce_v2_priv *priv = hr_dev->priv; 1506 struct hnae3_handle *handle = priv->handle; 1507 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1508 1509 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1510 hr_dev->dis_db = true; 1511 hr_dev->is_reset = true; 1512 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1513 return; 1514 } 1515 1516 if (ops->get_hw_reset_stat(handle)) { 1517 func_clr_hw_resetting_state(hr_dev, handle); 1518 return; 1519 } 1520 1521 if (ops->ae_dev_resetting(handle) && 1522 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1523 func_clr_sw_resetting_state(hr_dev, handle); 1524 return; 1525 } 1526 1527 if (retval && !flag) 1528 dev_warn(hr_dev->dev, 1529 "func clear read failed, ret = %d.\n", retval); 1530 1531 dev_warn(hr_dev->dev, "func clear failed.\n"); 1532 } 1533 1534 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1535 { 1536 bool fclr_write_fail_flag = false; 1537 struct hns_roce_func_clear *resp; 1538 struct hns_roce_cmq_desc desc; 1539 unsigned long end; 1540 int ret = 0; 1541 1542 if (check_device_is_in_reset(hr_dev)) 1543 goto out; 1544 1545 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1546 resp = (struct hns_roce_func_clear *)desc.data; 1547 resp->rst_funcid_en = cpu_to_le32(vf_id); 1548 1549 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1550 if (ret) { 1551 fclr_write_fail_flag = true; 1552 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1553 ret); 1554 goto out; 1555 } 1556 1557 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1558 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1559 while (end) { 1560 if (check_device_is_in_reset(hr_dev)) 1561 goto out; 1562 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1563 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1564 1565 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1566 true); 1567 1568 resp->rst_funcid_en = cpu_to_le32(vf_id); 1569 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1570 if (ret) 1571 continue; 1572 1573 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1574 if (vf_id == 0) 1575 hr_dev->is_reset = true; 1576 return; 1577 } 1578 } 1579 1580 out: 1581 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1582 } 1583 1584 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1585 { 1586 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1587 struct hns_roce_cmq_desc desc[2]; 1588 struct hns_roce_cmq_req *req_a; 1589 1590 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1591 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1592 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1593 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1594 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1595 1596 return hns_roce_cmq_send(hr_dev, desc, 2); 1597 } 1598 1599 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1600 { 1601 int ret; 1602 int i; 1603 1604 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1605 return; 1606 1607 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1608 __hns_roce_function_clear(hr_dev, i); 1609 1610 if (i == 0) 1611 continue; 1612 1613 ret = hns_roce_free_vf_resource(hr_dev, i); 1614 if (ret) 1615 ibdev_err(&hr_dev->ib_dev, 1616 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1617 i, ret); 1618 } 1619 } 1620 1621 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1622 { 1623 struct hns_roce_cmq_desc desc; 1624 int ret; 1625 1626 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1627 false); 1628 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1629 if (ret) 1630 ibdev_err(&hr_dev->ib_dev, 1631 "failed to clear extended doorbell info, ret = %d.\n", 1632 ret); 1633 1634 return ret; 1635 } 1636 1637 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1638 { 1639 struct hns_roce_query_fw_info *resp; 1640 struct hns_roce_cmq_desc desc; 1641 int ret; 1642 1643 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1644 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1645 if (ret) 1646 return ret; 1647 1648 resp = (struct hns_roce_query_fw_info *)desc.data; 1649 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1650 1651 return 0; 1652 } 1653 1654 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1655 { 1656 struct hns_roce_cmq_desc desc; 1657 int ret; 1658 1659 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1660 hr_dev->func_num = 1; 1661 return 0; 1662 } 1663 1664 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1665 true); 1666 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1667 if (ret) { 1668 hr_dev->func_num = 1; 1669 return ret; 1670 } 1671 1672 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1673 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1674 1675 return 0; 1676 } 1677 1678 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1679 u64 *stats, u32 port, int *num_counters) 1680 { 1681 #define CNT_PER_DESC 3 1682 struct hns_roce_cmq_desc *desc; 1683 int bd_idx, cnt_idx; 1684 __le64 *cnt_data; 1685 int desc_num; 1686 int ret; 1687 int i; 1688 1689 if (port > hr_dev->caps.num_ports) 1690 return -EINVAL; 1691 1692 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1693 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1694 if (!desc) 1695 return -ENOMEM; 1696 1697 for (i = 0; i < desc_num; i++) { 1698 hns_roce_cmq_setup_basic_desc(&desc[i], 1699 HNS_ROCE_OPC_QUERY_COUNTER, true); 1700 if (i != desc_num - 1) 1701 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1702 } 1703 1704 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1705 if (ret) { 1706 ibdev_err(&hr_dev->ib_dev, 1707 "failed to get counter, ret = %d.\n", ret); 1708 goto err_out; 1709 } 1710 1711 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1712 bd_idx = i / CNT_PER_DESC; 1713 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC && 1714 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT))) 1715 break; 1716 1717 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1718 cnt_idx = i % CNT_PER_DESC; 1719 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1720 } 1721 *num_counters = i; 1722 1723 err_out: 1724 kfree(desc); 1725 return ret; 1726 } 1727 1728 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1729 { 1730 struct hns_roce_cmq_desc desc; 1731 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1732 u32 clock_cycles_of_1us; 1733 1734 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1735 false); 1736 1737 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1738 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1739 else 1740 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1741 1742 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1743 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1744 1745 return hns_roce_cmq_send(hr_dev, &desc, 1); 1746 } 1747 1748 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1749 { 1750 struct hns_roce_cmq_desc desc[2]; 1751 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1752 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1753 struct hns_roce_caps *caps = &hr_dev->caps; 1754 enum hns_roce_opcode_type opcode; 1755 u32 func_num; 1756 int ret; 1757 1758 if (is_vf) { 1759 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1760 func_num = 1; 1761 } else { 1762 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1763 func_num = hr_dev->func_num; 1764 } 1765 1766 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1767 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1768 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1769 1770 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1771 if (ret) 1772 return ret; 1773 1774 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1775 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1776 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1777 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1778 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1779 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1780 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1781 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1782 1783 if (is_vf) { 1784 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1785 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1786 func_num; 1787 } else { 1788 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1789 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1790 func_num; 1791 } 1792 1793 return 0; 1794 } 1795 1796 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1797 { 1798 struct hns_roce_cmq_desc desc; 1799 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1800 struct hns_roce_caps *caps = &hr_dev->caps; 1801 int ret; 1802 1803 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1804 true); 1805 1806 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1807 if (ret) 1808 return ret; 1809 1810 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1811 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1812 1813 return 0; 1814 } 1815 1816 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1817 { 1818 struct device *dev = hr_dev->dev; 1819 int ret; 1820 1821 ret = load_func_res_caps(hr_dev, false); 1822 if (ret) { 1823 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1824 return ret; 1825 } 1826 1827 ret = load_pf_timer_res_caps(hr_dev); 1828 if (ret) 1829 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1830 ret); 1831 1832 return ret; 1833 } 1834 1835 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1836 { 1837 struct device *dev = hr_dev->dev; 1838 int ret; 1839 1840 ret = load_func_res_caps(hr_dev, true); 1841 if (ret) 1842 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1843 1844 return ret; 1845 } 1846 1847 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1848 u32 vf_id) 1849 { 1850 struct hns_roce_vf_switch *swt; 1851 struct hns_roce_cmq_desc desc; 1852 int ret; 1853 1854 swt = (struct hns_roce_vf_switch *)desc.data; 1855 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1856 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1857 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1858 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1859 if (ret) 1860 return ret; 1861 1862 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1863 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1864 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1865 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1866 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1867 1868 return hns_roce_cmq_send(hr_dev, &desc, 1); 1869 } 1870 1871 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1872 { 1873 u32 vf_id; 1874 int ret; 1875 1876 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1877 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1878 if (ret) 1879 return ret; 1880 } 1881 return 0; 1882 } 1883 1884 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1885 { 1886 struct hns_roce_cmq_desc desc[2]; 1887 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1888 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1889 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1890 struct hns_roce_caps *caps = &hr_dev->caps; 1891 1892 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1893 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1894 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1895 1896 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1897 1898 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1899 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1900 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1901 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1902 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1903 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1904 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1905 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1906 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1907 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1908 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1909 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1910 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1911 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1912 1913 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1914 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1915 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1916 vf_id * caps->gmv_bt_num); 1917 } else { 1918 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1919 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1920 vf_id * caps->sgid_bt_num); 1921 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1922 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1923 vf_id * caps->smac_bt_num); 1924 } 1925 1926 return hns_roce_cmq_send(hr_dev, desc, 2); 1927 } 1928 1929 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1930 { 1931 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1932 u32 vf_id; 1933 int ret; 1934 1935 for (vf_id = 0; vf_id < func_num; vf_id++) { 1936 ret = config_vf_hem_resource(hr_dev, vf_id); 1937 if (ret) { 1938 dev_err(hr_dev->dev, 1939 "failed to config vf-%u hem res, ret = %d.\n", 1940 vf_id, ret); 1941 return ret; 1942 } 1943 } 1944 1945 return 0; 1946 } 1947 1948 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1949 { 1950 struct hns_roce_cmq_desc desc; 1951 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1952 struct hns_roce_caps *caps = &hr_dev->caps; 1953 1954 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1955 1956 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1957 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1958 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1959 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1960 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1961 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1962 1963 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1964 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1965 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1966 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1967 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1968 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1969 1970 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1971 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1972 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1973 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1974 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1975 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1976 1977 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1978 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1979 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1980 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1981 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1982 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1983 1984 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1985 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1986 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1987 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1988 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1989 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1990 1991 return hns_roce_cmq_send(hr_dev, &desc, 1); 1992 } 1993 1994 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1995 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1996 { 1997 u64 obj_per_chunk; 1998 u64 bt_chunk_size = PAGE_SIZE; 1999 u64 buf_chunk_size = PAGE_SIZE; 2000 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2001 2002 *buf_page_size = 0; 2003 *bt_page_size = 0; 2004 2005 switch (hop_num) { 2006 case 3: 2007 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2008 (bt_chunk_size / BA_BYTE_LEN) * 2009 (bt_chunk_size / BA_BYTE_LEN) * 2010 obj_per_chunk_default; 2011 break; 2012 case 2: 2013 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2014 (bt_chunk_size / BA_BYTE_LEN) * 2015 obj_per_chunk_default; 2016 break; 2017 case 1: 2018 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2019 obj_per_chunk_default; 2020 break; 2021 case HNS_ROCE_HOP_NUM_0: 2022 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2023 break; 2024 default: 2025 pr_err("table %u not support hop_num = %u!\n", hem_type, 2026 hop_num); 2027 return; 2028 } 2029 2030 if (hem_type >= HEM_TYPE_MTT) 2031 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2032 else 2033 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2034 } 2035 2036 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2037 { 2038 struct hns_roce_caps *caps = &hr_dev->caps; 2039 2040 /* EQ */ 2041 caps->eqe_ba_pg_sz = 0; 2042 caps->eqe_buf_pg_sz = 0; 2043 2044 /* Link Table */ 2045 caps->llm_buf_pg_sz = 0; 2046 2047 /* MR */ 2048 caps->mpt_ba_pg_sz = 0; 2049 caps->mpt_buf_pg_sz = 0; 2050 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2051 caps->pbl_buf_pg_sz = 0; 2052 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2053 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2054 HEM_TYPE_MTPT); 2055 2056 /* QP */ 2057 caps->qpc_ba_pg_sz = 0; 2058 caps->qpc_buf_pg_sz = 0; 2059 caps->qpc_timer_ba_pg_sz = 0; 2060 caps->qpc_timer_buf_pg_sz = 0; 2061 caps->sccc_ba_pg_sz = 0; 2062 caps->sccc_buf_pg_sz = 0; 2063 caps->mtt_ba_pg_sz = 0; 2064 caps->mtt_buf_pg_sz = 0; 2065 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2066 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2067 HEM_TYPE_QPC); 2068 2069 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2070 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2071 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2072 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2073 2074 /* CQ */ 2075 caps->cqc_ba_pg_sz = 0; 2076 caps->cqc_buf_pg_sz = 0; 2077 caps->cqc_timer_ba_pg_sz = 0; 2078 caps->cqc_timer_buf_pg_sz = 0; 2079 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2080 caps->cqe_buf_pg_sz = 0; 2081 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2082 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2083 HEM_TYPE_CQC); 2084 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2085 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2086 2087 /* SRQ */ 2088 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2089 caps->srqc_ba_pg_sz = 0; 2090 caps->srqc_buf_pg_sz = 0; 2091 caps->srqwqe_ba_pg_sz = 0; 2092 caps->srqwqe_buf_pg_sz = 0; 2093 caps->idx_ba_pg_sz = 0; 2094 caps->idx_buf_pg_sz = 0; 2095 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2096 caps->srqc_hop_num, caps->srqc_bt_num, 2097 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2098 HEM_TYPE_SRQC); 2099 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2100 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2101 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2102 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2103 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2104 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2105 } 2106 2107 /* GMV */ 2108 caps->gmv_ba_pg_sz = 0; 2109 caps->gmv_buf_pg_sz = 0; 2110 } 2111 2112 /* Apply all loaded caps before setting to hardware */ 2113 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2114 { 2115 #define MAX_GID_TBL_LEN 256 2116 struct hns_roce_caps *caps = &hr_dev->caps; 2117 struct hns_roce_v2_priv *priv = hr_dev->priv; 2118 2119 /* The following configurations don't need to be got from firmware. */ 2120 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2121 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2122 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2123 2124 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2125 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2126 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2127 2128 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2129 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2130 2131 if (!caps->num_comp_vectors) 2132 caps->num_comp_vectors = 2133 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2134 (u32)priv->handle->rinfo.num_vectors - 2135 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2136 2137 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2138 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2139 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2140 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2141 2142 /* The following configurations will be overwritten */ 2143 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2144 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2145 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2146 2147 /* The following configurations are not got from firmware */ 2148 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2149 2150 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2151 2152 /* It's meaningless to support excessively large gid_table_len, 2153 * as the type of sgid_index in kernel struct ib_global_route 2154 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2155 */ 2156 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2157 caps->gmv_bt_num * 2158 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2159 2160 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2161 caps->gmv_entry_sz); 2162 } else { 2163 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2164 2165 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2166 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2167 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2168 caps->gid_table_len[0] /= func_num; 2169 } 2170 2171 if (hr_dev->is_vf) { 2172 caps->default_aeq_arm_st = 0x3; 2173 caps->default_ceq_arm_st = 0x3; 2174 caps->default_ceq_max_cnt = 0x1; 2175 caps->default_ceq_period = 0x10; 2176 caps->default_aeq_max_cnt = 0x1; 2177 caps->default_aeq_period = 0x10; 2178 } 2179 2180 set_hem_page_size(hr_dev); 2181 } 2182 2183 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2184 { 2185 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2186 struct hns_roce_caps *caps = &hr_dev->caps; 2187 struct hns_roce_query_pf_caps_a *resp_a; 2188 struct hns_roce_query_pf_caps_b *resp_b; 2189 struct hns_roce_query_pf_caps_c *resp_c; 2190 struct hns_roce_query_pf_caps_d *resp_d; 2191 struct hns_roce_query_pf_caps_e *resp_e; 2192 enum hns_roce_opcode_type cmd; 2193 int ctx_hop_num; 2194 int pbl_hop_num; 2195 int ret; 2196 int i; 2197 2198 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2199 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2200 2201 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2202 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2203 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2204 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2205 else 2206 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2207 } 2208 2209 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2210 if (ret) 2211 return ret; 2212 2213 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2214 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2215 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2216 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2217 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2218 2219 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2220 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2221 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2222 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2223 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2224 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2225 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2226 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2227 caps->num_other_vectors = resp_a->num_other_vectors; 2228 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2229 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2230 2231 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2232 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2233 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2234 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2235 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2236 caps->idx_entry_sz = resp_b->idx_entry_sz; 2237 caps->sccc_sz = resp_b->sccc_sz; 2238 caps->max_mtu = resp_b->max_mtu; 2239 caps->min_cqes = resp_b->min_cqes; 2240 caps->min_wqes = resp_b->min_wqes; 2241 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2242 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2243 caps->phy_num_uars = resp_b->phy_num_uars; 2244 ctx_hop_num = resp_b->ctx_hop_num; 2245 pbl_hop_num = resp_b->pbl_hop_num; 2246 2247 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2248 2249 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2250 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2251 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2252 2253 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2254 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2255 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2256 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2257 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2258 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2259 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2260 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2261 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2262 2263 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2264 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2265 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2266 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2267 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2268 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2269 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2270 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2271 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2272 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2273 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2274 2275 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2276 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2277 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2278 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2279 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2280 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2281 2282 caps->qpc_hop_num = ctx_hop_num; 2283 caps->sccc_hop_num = ctx_hop_num; 2284 caps->srqc_hop_num = ctx_hop_num; 2285 caps->cqc_hop_num = ctx_hop_num; 2286 caps->mpt_hop_num = ctx_hop_num; 2287 caps->mtt_hop_num = pbl_hop_num; 2288 caps->cqe_hop_num = pbl_hop_num; 2289 caps->srqwqe_hop_num = pbl_hop_num; 2290 caps->idx_hop_num = pbl_hop_num; 2291 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2292 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2293 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2294 2295 if (!(caps->page_size_cap & PAGE_SIZE)) 2296 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2297 2298 if (!hr_dev->is_vf) { 2299 caps->cqe_sz = resp_a->cqe_sz; 2300 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2301 caps->default_aeq_arm_st = 2302 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2303 caps->default_ceq_arm_st = 2304 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2305 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2306 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2307 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2308 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2309 } 2310 2311 return 0; 2312 } 2313 2314 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2315 { 2316 struct hns_roce_cmq_desc desc; 2317 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2318 2319 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2320 false); 2321 2322 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2323 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2324 2325 return hns_roce_cmq_send(hr_dev, &desc, 1); 2326 } 2327 2328 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2329 { 2330 struct hns_roce_caps *caps = &hr_dev->caps; 2331 int ret; 2332 2333 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2334 return 0; 2335 2336 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2337 caps->qpc_sz); 2338 if (ret) { 2339 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2340 return ret; 2341 } 2342 2343 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2344 caps->sccc_sz); 2345 if (ret) 2346 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2347 2348 return ret; 2349 } 2350 2351 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2352 { 2353 struct device *dev = hr_dev->dev; 2354 int ret; 2355 2356 hr_dev->func_num = 1; 2357 2358 ret = hns_roce_query_caps(hr_dev); 2359 if (ret) { 2360 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2361 return ret; 2362 } 2363 2364 ret = hns_roce_query_vf_resource(hr_dev); 2365 if (ret) { 2366 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2367 return ret; 2368 } 2369 2370 apply_func_caps(hr_dev); 2371 2372 ret = hns_roce_v2_set_bt(hr_dev); 2373 if (ret) 2374 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2375 2376 return ret; 2377 } 2378 2379 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2380 { 2381 struct device *dev = hr_dev->dev; 2382 int ret; 2383 2384 ret = hns_roce_query_func_info(hr_dev); 2385 if (ret) { 2386 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2387 return ret; 2388 } 2389 2390 ret = hns_roce_config_global_param(hr_dev); 2391 if (ret) { 2392 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2393 return ret; 2394 } 2395 2396 ret = hns_roce_set_vf_switch_param(hr_dev); 2397 if (ret) { 2398 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2399 return ret; 2400 } 2401 2402 ret = hns_roce_query_caps(hr_dev); 2403 if (ret) { 2404 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2405 return ret; 2406 } 2407 2408 ret = hns_roce_query_pf_resource(hr_dev); 2409 if (ret) { 2410 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2411 return ret; 2412 } 2413 2414 apply_func_caps(hr_dev); 2415 2416 ret = hns_roce_alloc_vf_resource(hr_dev); 2417 if (ret) { 2418 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2419 return ret; 2420 } 2421 2422 ret = hns_roce_v2_set_bt(hr_dev); 2423 if (ret) { 2424 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2425 return ret; 2426 } 2427 2428 /* Configure the size of QPC, SCCC, etc. */ 2429 return hns_roce_config_entry_size(hr_dev); 2430 } 2431 2432 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2433 { 2434 struct device *dev = hr_dev->dev; 2435 int ret; 2436 2437 ret = hns_roce_cmq_query_hw_info(hr_dev); 2438 if (ret) { 2439 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2440 return ret; 2441 } 2442 2443 ret = hns_roce_query_fw_ver(hr_dev); 2444 if (ret) { 2445 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2446 return ret; 2447 } 2448 2449 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2450 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2451 2452 if (hr_dev->is_vf) 2453 return hns_roce_v2_vf_profile(hr_dev); 2454 else 2455 return hns_roce_v2_pf_profile(hr_dev); 2456 } 2457 2458 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2459 { 2460 u32 i, next_ptr, page_num; 2461 __le64 *entry = cfg_buf; 2462 dma_addr_t addr; 2463 u64 val; 2464 2465 page_num = data_buf->npages; 2466 for (i = 0; i < page_num; i++) { 2467 addr = hns_roce_buf_page(data_buf, i); 2468 if (i == (page_num - 1)) 2469 next_ptr = 0; 2470 else 2471 next_ptr = i + 1; 2472 2473 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2474 entry[i] = cpu_to_le64(val); 2475 } 2476 } 2477 2478 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2479 struct hns_roce_link_table *table) 2480 { 2481 struct hns_roce_cmq_desc desc[2]; 2482 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2483 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2484 struct hns_roce_buf *buf = table->buf; 2485 enum hns_roce_opcode_type opcode; 2486 dma_addr_t addr; 2487 2488 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2489 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2490 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2491 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2492 2493 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2494 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2495 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2496 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2497 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2498 2499 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2500 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2501 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2502 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2503 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2504 2505 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2506 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2507 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2508 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2509 2510 return hns_roce_cmq_send(hr_dev, desc, 2); 2511 } 2512 2513 static struct hns_roce_link_table * 2514 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2515 { 2516 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2517 struct hns_roce_v2_priv *priv = hr_dev->priv; 2518 struct hns_roce_link_table *link_tbl; 2519 u32 pg_shift, size, min_size; 2520 2521 link_tbl = &priv->ext_llm; 2522 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2523 size = hr_dev->caps.num_qps * hr_dev->func_num * 2524 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2525 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2526 2527 /* Alloc data table */ 2528 size = max(size, min_size); 2529 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2530 if (IS_ERR(link_tbl->buf)) 2531 return ERR_PTR(-ENOMEM); 2532 2533 /* Alloc config table */ 2534 size = link_tbl->buf->npages * sizeof(u64); 2535 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2536 &link_tbl->table.map, 2537 GFP_KERNEL); 2538 if (!link_tbl->table.buf) { 2539 hns_roce_buf_free(hr_dev, link_tbl->buf); 2540 return ERR_PTR(-ENOMEM); 2541 } 2542 2543 return link_tbl; 2544 } 2545 2546 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2547 struct hns_roce_link_table *tbl) 2548 { 2549 if (tbl->buf) { 2550 u32 size = tbl->buf->npages * sizeof(u64); 2551 2552 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2553 tbl->table.map); 2554 } 2555 2556 hns_roce_buf_free(hr_dev, tbl->buf); 2557 } 2558 2559 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2560 { 2561 struct hns_roce_link_table *link_tbl; 2562 int ret; 2563 2564 link_tbl = alloc_link_table_buf(hr_dev); 2565 if (IS_ERR(link_tbl)) 2566 return -ENOMEM; 2567 2568 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2569 ret = -EINVAL; 2570 goto err_alloc; 2571 } 2572 2573 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2574 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2575 if (ret) 2576 goto err_alloc; 2577 2578 return 0; 2579 2580 err_alloc: 2581 free_link_table_buf(hr_dev, link_tbl); 2582 return ret; 2583 } 2584 2585 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2586 { 2587 struct hns_roce_v2_priv *priv = hr_dev->priv; 2588 2589 free_link_table_buf(hr_dev, &priv->ext_llm); 2590 } 2591 2592 static void free_dip_entry(struct hns_roce_dev *hr_dev) 2593 { 2594 struct hns_roce_dip *hr_dip; 2595 unsigned long idx; 2596 2597 xa_lock(&hr_dev->qp_table.dip_xa); 2598 2599 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) { 2600 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx); 2601 kfree(hr_dip); 2602 } 2603 2604 xa_unlock(&hr_dev->qp_table.dip_xa); 2605 } 2606 2607 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2608 { 2609 struct hns_roce_v2_priv *priv = hr_dev->priv; 2610 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2611 struct ib_device *ibdev = &hr_dev->ib_dev; 2612 struct hns_roce_pd *hr_pd; 2613 struct ib_pd *pd; 2614 2615 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2616 if (ZERO_OR_NULL_PTR(hr_pd)) 2617 return NULL; 2618 pd = &hr_pd->ibpd; 2619 pd->device = ibdev; 2620 2621 if (hns_roce_alloc_pd(pd, NULL)) { 2622 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2623 kfree(hr_pd); 2624 return NULL; 2625 } 2626 free_mr->rsv_pd = to_hr_pd(pd); 2627 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2628 free_mr->rsv_pd->ibpd.uobject = NULL; 2629 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2630 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2631 2632 return pd; 2633 } 2634 2635 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2636 { 2637 struct hns_roce_v2_priv *priv = hr_dev->priv; 2638 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2639 struct ib_device *ibdev = &hr_dev->ib_dev; 2640 struct ib_cq_init_attr cq_init_attr = {}; 2641 struct hns_roce_cq *hr_cq; 2642 struct ib_cq *cq; 2643 2644 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2645 2646 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2647 if (ZERO_OR_NULL_PTR(hr_cq)) 2648 return NULL; 2649 2650 cq = &hr_cq->ib_cq; 2651 cq->device = ibdev; 2652 2653 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2654 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2655 kfree(hr_cq); 2656 return NULL; 2657 } 2658 free_mr->rsv_cq = to_hr_cq(cq); 2659 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2660 free_mr->rsv_cq->ib_cq.uobject = NULL; 2661 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2662 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2663 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2664 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2665 2666 return cq; 2667 } 2668 2669 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2670 struct ib_qp_init_attr *init_attr, int i) 2671 { 2672 struct hns_roce_v2_priv *priv = hr_dev->priv; 2673 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2674 struct ib_device *ibdev = &hr_dev->ib_dev; 2675 struct hns_roce_qp *hr_qp; 2676 struct ib_qp *qp; 2677 int ret; 2678 2679 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2680 if (ZERO_OR_NULL_PTR(hr_qp)) 2681 return -ENOMEM; 2682 2683 qp = &hr_qp->ibqp; 2684 qp->device = ibdev; 2685 2686 ret = hns_roce_create_qp(qp, init_attr, NULL); 2687 if (ret) { 2688 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2689 kfree(hr_qp); 2690 return ret; 2691 } 2692 2693 free_mr->rsv_qp[i] = hr_qp; 2694 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2695 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2696 2697 return 0; 2698 } 2699 2700 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2701 { 2702 struct hns_roce_v2_priv *priv = hr_dev->priv; 2703 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2704 struct ib_qp *qp; 2705 int i; 2706 2707 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2708 if (free_mr->rsv_qp[i]) { 2709 qp = &free_mr->rsv_qp[i]->ibqp; 2710 hns_roce_v2_destroy_qp(qp, NULL); 2711 kfree(free_mr->rsv_qp[i]); 2712 free_mr->rsv_qp[i] = NULL; 2713 } 2714 } 2715 2716 if (free_mr->rsv_cq) { 2717 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2718 kfree(free_mr->rsv_cq); 2719 free_mr->rsv_cq = NULL; 2720 } 2721 2722 if (free_mr->rsv_pd) { 2723 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2724 kfree(free_mr->rsv_pd); 2725 free_mr->rsv_pd = NULL; 2726 } 2727 2728 mutex_destroy(&free_mr->mutex); 2729 } 2730 2731 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2732 { 2733 struct hns_roce_v2_priv *priv = hr_dev->priv; 2734 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2735 struct ib_qp_init_attr qp_init_attr = {}; 2736 struct ib_pd *pd; 2737 struct ib_cq *cq; 2738 int ret; 2739 int i; 2740 2741 pd = free_mr_init_pd(hr_dev); 2742 if (!pd) 2743 return -ENOMEM; 2744 2745 cq = free_mr_init_cq(hr_dev); 2746 if (!cq) { 2747 ret = -ENOMEM; 2748 goto create_failed_cq; 2749 } 2750 2751 qp_init_attr.qp_type = IB_QPT_RC; 2752 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2753 qp_init_attr.send_cq = cq; 2754 qp_init_attr.recv_cq = cq; 2755 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2756 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2757 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2758 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2759 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2760 2761 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2762 if (ret) 2763 goto create_failed_qp; 2764 } 2765 2766 return 0; 2767 2768 create_failed_qp: 2769 for (i--; i >= 0; i--) { 2770 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 2771 kfree(free_mr->rsv_qp[i]); 2772 } 2773 hns_roce_destroy_cq(cq, NULL); 2774 kfree(cq); 2775 2776 create_failed_cq: 2777 hns_roce_dealloc_pd(pd, NULL); 2778 kfree(pd); 2779 2780 return ret; 2781 } 2782 2783 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2784 struct ib_qp_attr *attr, int sl_num) 2785 { 2786 struct hns_roce_v2_priv *priv = hr_dev->priv; 2787 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2788 struct ib_device *ibdev = &hr_dev->ib_dev; 2789 struct hns_roce_qp *hr_qp; 2790 int loopback; 2791 int mask; 2792 int ret; 2793 2794 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2795 hr_qp->free_mr_en = 1; 2796 hr_qp->ibqp.device = ibdev; 2797 hr_qp->ibqp.qp_type = IB_QPT_RC; 2798 2799 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2800 attr->qp_state = IB_QPS_INIT; 2801 attr->port_num = 1; 2802 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2803 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2804 IB_QPS_INIT, NULL); 2805 if (ret) { 2806 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n", 2807 ret); 2808 return ret; 2809 } 2810 2811 loopback = hr_dev->loop_idc; 2812 /* Set qpc lbi = 1 incidate loopback IO */ 2813 hr_dev->loop_idc = 1; 2814 2815 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2816 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2817 attr->qp_state = IB_QPS_RTR; 2818 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2819 attr->path_mtu = IB_MTU_256; 2820 attr->dest_qp_num = hr_qp->qpn; 2821 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2822 2823 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2824 2825 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2826 IB_QPS_RTR, NULL); 2827 hr_dev->loop_idc = loopback; 2828 if (ret) { 2829 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2830 ret); 2831 return ret; 2832 } 2833 2834 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2835 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2836 attr->qp_state = IB_QPS_RTS; 2837 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2838 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2839 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2840 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2841 IB_QPS_RTS, NULL); 2842 if (ret) 2843 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2844 ret); 2845 2846 return ret; 2847 } 2848 2849 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2850 { 2851 struct hns_roce_v2_priv *priv = hr_dev->priv; 2852 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2853 struct ib_qp_attr attr = {}; 2854 int ret; 2855 int i; 2856 2857 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2858 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2859 rdma_ah_set_port_num(&attr.ah_attr, 1); 2860 2861 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2862 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2863 if (ret) 2864 return ret; 2865 } 2866 2867 return 0; 2868 } 2869 2870 static int free_mr_init(struct hns_roce_dev *hr_dev) 2871 { 2872 struct hns_roce_v2_priv *priv = hr_dev->priv; 2873 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2874 int ret; 2875 2876 mutex_init(&free_mr->mutex); 2877 2878 ret = free_mr_alloc_res(hr_dev); 2879 if (ret) { 2880 mutex_destroy(&free_mr->mutex); 2881 return ret; 2882 } 2883 2884 ret = free_mr_modify_qp(hr_dev); 2885 if (ret) 2886 goto err_modify_qp; 2887 2888 return 0; 2889 2890 err_modify_qp: 2891 free_mr_exit(hr_dev); 2892 2893 return ret; 2894 } 2895 2896 static int get_hem_table(struct hns_roce_dev *hr_dev) 2897 { 2898 unsigned int qpc_count; 2899 unsigned int cqc_count; 2900 unsigned int gmv_count; 2901 int ret; 2902 int i; 2903 2904 /* Alloc memory for source address table buffer space chunk */ 2905 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2906 gmv_count++) { 2907 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2908 if (ret) 2909 goto err_gmv_failed; 2910 } 2911 2912 if (hr_dev->is_vf) 2913 return 0; 2914 2915 /* Alloc memory for QPC Timer buffer space chunk */ 2916 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2917 qpc_count++) { 2918 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2919 qpc_count); 2920 if (ret) { 2921 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2922 goto err_qpc_timer_failed; 2923 } 2924 } 2925 2926 /* Alloc memory for CQC Timer buffer space chunk */ 2927 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2928 cqc_count++) { 2929 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2930 cqc_count); 2931 if (ret) { 2932 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2933 goto err_cqc_timer_failed; 2934 } 2935 } 2936 2937 return 0; 2938 2939 err_cqc_timer_failed: 2940 for (i = 0; i < cqc_count; i++) 2941 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2942 2943 err_qpc_timer_failed: 2944 for (i = 0; i < qpc_count; i++) 2945 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2946 2947 err_gmv_failed: 2948 for (i = 0; i < gmv_count; i++) 2949 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2950 2951 return ret; 2952 } 2953 2954 static void put_hem_table(struct hns_roce_dev *hr_dev) 2955 { 2956 int i; 2957 2958 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2959 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2960 2961 if (hr_dev->is_vf) 2962 return; 2963 2964 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2965 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2966 2967 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2968 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2969 } 2970 2971 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2972 { 2973 int ret; 2974 2975 /* The hns ROCEE requires the extdb info to be cleared before using */ 2976 ret = hns_roce_clear_extdb_list_info(hr_dev); 2977 if (ret) 2978 return ret; 2979 2980 ret = get_hem_table(hr_dev); 2981 if (ret) 2982 return ret; 2983 2984 if (hr_dev->is_vf) 2985 return 0; 2986 2987 ret = hns_roce_init_link_table(hr_dev); 2988 if (ret) { 2989 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2990 goto err_llm_init_failed; 2991 } 2992 2993 return 0; 2994 2995 err_llm_init_failed: 2996 put_hem_table(hr_dev); 2997 2998 return ret; 2999 } 3000 3001 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 3002 { 3003 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3004 free_mr_exit(hr_dev); 3005 3006 hns_roce_function_clear(hr_dev); 3007 3008 if (!hr_dev->is_vf) 3009 hns_roce_free_link_table(hr_dev); 3010 3011 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 3012 free_dip_entry(hr_dev); 3013 } 3014 3015 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 3016 struct hns_roce_mbox_msg *mbox_msg) 3017 { 3018 struct hns_roce_cmq_desc desc; 3019 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 3020 3021 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 3022 3023 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 3024 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 3025 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 3026 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 3027 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 3028 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 3029 mbox_msg->token); 3030 3031 return hns_roce_cmq_send(hr_dev, &desc, 1); 3032 } 3033 3034 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 3035 u8 *complete_status) 3036 { 3037 struct hns_roce_mbox_status *mb_st; 3038 struct hns_roce_cmq_desc desc; 3039 unsigned long end; 3040 int ret = -EBUSY; 3041 u32 status; 3042 bool busy; 3043 3044 mb_st = (struct hns_roce_mbox_status *)desc.data; 3045 end = msecs_to_jiffies(timeout) + jiffies; 3046 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3047 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3048 return -EIO; 3049 3050 status = 0; 3051 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3052 true); 3053 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3054 if (!ret) { 3055 status = le32_to_cpu(mb_st->mb_status_hw_run); 3056 /* No pending message exists in ROCEE mbox. */ 3057 if (!(status & MB_ST_HW_RUN_M)) 3058 break; 3059 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3060 break; 3061 } 3062 3063 if (time_after(jiffies, end)) { 3064 dev_err_ratelimited(hr_dev->dev, 3065 "failed to wait mbox status 0x%x\n", 3066 status); 3067 return -ETIMEDOUT; 3068 } 3069 3070 cond_resched(); 3071 ret = -EBUSY; 3072 } 3073 3074 if (!ret) { 3075 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3076 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3077 /* Ignore all errors if the mbox is unavailable. */ 3078 ret = 0; 3079 *complete_status = MB_ST_COMPLETE_M; 3080 } 3081 3082 return ret; 3083 } 3084 3085 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3086 struct hns_roce_mbox_msg *mbox_msg) 3087 { 3088 u8 status = 0; 3089 int ret; 3090 3091 /* Waiting for the mbox to be idle */ 3092 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3093 &status); 3094 if (unlikely(ret)) { 3095 dev_err_ratelimited(hr_dev->dev, 3096 "failed to check post mbox status = 0x%x, ret = %d.\n", 3097 status, ret); 3098 return ret; 3099 } 3100 3101 /* Post new message to mbox */ 3102 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3103 if (ret) 3104 dev_err_ratelimited(hr_dev->dev, 3105 "failed to post mailbox, ret = %d.\n", ret); 3106 3107 return ret; 3108 } 3109 3110 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3111 { 3112 u8 status = 0; 3113 int ret; 3114 3115 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3116 &status); 3117 if (!ret) { 3118 if (status != MB_ST_COMPLETE_SUCC) 3119 return -EBUSY; 3120 } else { 3121 dev_err_ratelimited(hr_dev->dev, 3122 "failed to check mbox status = 0x%x, ret = %d.\n", 3123 status, ret); 3124 } 3125 3126 return ret; 3127 } 3128 3129 static void copy_gid(void *dest, const union ib_gid *gid) 3130 { 3131 #define GID_SIZE 4 3132 const union ib_gid *src = gid; 3133 __le32 (*p)[GID_SIZE] = dest; 3134 int i; 3135 3136 if (!gid) 3137 src = &zgid; 3138 3139 for (i = 0; i < GID_SIZE; i++) 3140 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3141 } 3142 3143 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3144 int gid_index, const union ib_gid *gid, 3145 enum hns_roce_sgid_type sgid_type) 3146 { 3147 struct hns_roce_cmq_desc desc; 3148 struct hns_roce_cfg_sgid_tb *sgid_tb = 3149 (struct hns_roce_cfg_sgid_tb *)desc.data; 3150 3151 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3152 3153 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3154 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3155 3156 copy_gid(&sgid_tb->vf_sgid_l, gid); 3157 3158 return hns_roce_cmq_send(hr_dev, &desc, 1); 3159 } 3160 3161 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3162 int gid_index, const union ib_gid *gid, 3163 enum hns_roce_sgid_type sgid_type, 3164 const struct ib_gid_attr *attr) 3165 { 3166 struct hns_roce_cmq_desc desc[2]; 3167 struct hns_roce_cfg_gmv_tb_a *tb_a = 3168 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3169 struct hns_roce_cfg_gmv_tb_b *tb_b = 3170 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3171 3172 u16 vlan_id = VLAN_CFI_MASK; 3173 u8 mac[ETH_ALEN] = {}; 3174 int ret; 3175 3176 if (gid) { 3177 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3178 if (ret) 3179 return ret; 3180 } 3181 3182 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3183 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3184 3185 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3186 3187 copy_gid(&tb_a->vf_sgid_l, gid); 3188 3189 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3190 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3191 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3192 3193 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3194 3195 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3196 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3197 3198 return hns_roce_cmq_send(hr_dev, desc, 2); 3199 } 3200 3201 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3202 const union ib_gid *gid, 3203 const struct ib_gid_attr *attr) 3204 { 3205 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3206 int ret; 3207 3208 if (gid) { 3209 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3210 if (ipv6_addr_v4mapped((void *)gid)) 3211 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3212 else 3213 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3214 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3215 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3216 } 3217 } 3218 3219 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3220 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3221 else 3222 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3223 3224 if (ret) 3225 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3226 ret); 3227 3228 return ret; 3229 } 3230 3231 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3232 const u8 *addr) 3233 { 3234 struct hns_roce_cmq_desc desc; 3235 struct hns_roce_cfg_smac_tb *smac_tb = 3236 (struct hns_roce_cfg_smac_tb *)desc.data; 3237 u16 reg_smac_h; 3238 u32 reg_smac_l; 3239 3240 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3241 3242 reg_smac_l = *(u32 *)(&addr[0]); 3243 reg_smac_h = *(u16 *)(&addr[4]); 3244 3245 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3246 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3247 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3248 3249 return hns_roce_cmq_send(hr_dev, &desc, 1); 3250 } 3251 3252 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3253 struct hns_roce_v2_mpt_entry *mpt_entry, 3254 struct hns_roce_mr *mr) 3255 { 3256 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3257 struct ib_device *ibdev = &hr_dev->ib_dev; 3258 dma_addr_t pbl_ba; 3259 int ret; 3260 int i; 3261 3262 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3263 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3264 if (ret) { 3265 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3266 return ret; 3267 } 3268 3269 /* Aligned to the hardware address access unit */ 3270 for (i = 0; i < ARRAY_SIZE(pages); i++) 3271 pages[i] >>= MPT_PBL_BUF_ADDR_S; 3272 3273 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3274 3275 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3276 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S); 3277 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3278 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3279 3280 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3281 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3282 3283 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3284 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3285 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3286 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3287 3288 return 0; 3289 } 3290 3291 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3292 void *mb_buf, struct hns_roce_mr *mr) 3293 { 3294 struct hns_roce_v2_mpt_entry *mpt_entry; 3295 3296 mpt_entry = mb_buf; 3297 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3298 3299 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3300 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3301 3302 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3303 mr->access & IB_ACCESS_MW_BIND); 3304 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3305 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3306 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3307 mr->access & IB_ACCESS_REMOTE_READ); 3308 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3309 mr->access & IB_ACCESS_REMOTE_WRITE); 3310 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3311 mr->access & IB_ACCESS_LOCAL_WRITE); 3312 3313 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3314 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3315 mpt_entry->lkey = cpu_to_le32(mr->key); 3316 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3317 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3318 3319 if (mr->type != MR_TYPE_MR) 3320 hr_reg_enable(mpt_entry, MPT_PA); 3321 3322 if (mr->type == MR_TYPE_DMA) 3323 return 0; 3324 3325 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3326 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3327 3328 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3329 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3330 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3331 3332 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3333 } 3334 3335 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3336 struct hns_roce_mr *mr, int flags, 3337 void *mb_buf) 3338 { 3339 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3340 u32 mr_access_flags = mr->access; 3341 int ret = 0; 3342 3343 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3344 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3345 3346 if (flags & IB_MR_REREG_ACCESS) { 3347 hr_reg_write(mpt_entry, MPT_BIND_EN, 3348 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3349 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3350 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3351 hr_reg_write(mpt_entry, MPT_RR_EN, 3352 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3353 hr_reg_write(mpt_entry, MPT_RW_EN, 3354 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3355 hr_reg_write(mpt_entry, MPT_LW_EN, 3356 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3357 } 3358 3359 if (flags & IB_MR_REREG_TRANS) { 3360 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3361 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3362 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3363 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3364 3365 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3366 } 3367 3368 return ret; 3369 } 3370 3371 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 3372 { 3373 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3374 struct hns_roce_v2_mpt_entry *mpt_entry; 3375 3376 mpt_entry = mb_buf; 3377 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3378 3379 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3380 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3381 3382 hr_reg_enable(mpt_entry, MPT_RA_EN); 3383 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3384 3385 hr_reg_enable(mpt_entry, MPT_FRE); 3386 hr_reg_clear(mpt_entry, MPT_MR_MW); 3387 hr_reg_enable(mpt_entry, MPT_BPD); 3388 hr_reg_clear(mpt_entry, MPT_PA); 3389 3390 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3391 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3392 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3393 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3394 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3395 3396 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3397 3398 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3399 MPT_PBL_BA_ADDR_S)); 3400 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3401 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3402 3403 return 0; 3404 } 3405 3406 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3407 { 3408 struct hns_roce_v2_mpt_entry *mpt_entry; 3409 3410 mpt_entry = mb_buf; 3411 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3412 3413 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3414 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3415 3416 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3417 hr_reg_enable(mpt_entry, MPT_LW_EN); 3418 3419 hr_reg_enable(mpt_entry, MPT_MR_MW); 3420 hr_reg_enable(mpt_entry, MPT_BPD); 3421 hr_reg_clear(mpt_entry, MPT_PA); 3422 hr_reg_write(mpt_entry, MPT_BQP, 3423 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3424 3425 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3426 3427 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3428 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3429 mw->pbl_hop_num); 3430 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3431 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3432 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3433 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3434 3435 return 0; 3436 } 3437 3438 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3439 { 3440 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3441 struct ib_device *ibdev = &hr_dev->ib_dev; 3442 const struct ib_send_wr *bad_wr; 3443 struct ib_rdma_wr rdma_wr = {}; 3444 struct ib_send_wr *send_wr; 3445 int ret; 3446 3447 send_wr = &rdma_wr.wr; 3448 send_wr->opcode = IB_WR_RDMA_WRITE; 3449 3450 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3451 if (ret) { 3452 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3453 ret); 3454 return ret; 3455 } 3456 3457 return 0; 3458 } 3459 3460 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3461 struct ib_wc *wc); 3462 3463 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3464 { 3465 struct hns_roce_v2_priv *priv = hr_dev->priv; 3466 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3467 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3468 struct ib_device *ibdev = &hr_dev->ib_dev; 3469 struct hns_roce_qp *hr_qp; 3470 unsigned long end; 3471 int cqe_cnt = 0; 3472 int npolled; 3473 int ret; 3474 int i; 3475 3476 /* 3477 * If the device initialization is not complete or in the uninstall 3478 * process, then there is no need to execute free mr. 3479 */ 3480 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3481 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3482 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3483 return; 3484 3485 mutex_lock(&free_mr->mutex); 3486 3487 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3488 hr_qp = free_mr->rsv_qp[i]; 3489 3490 ret = free_mr_post_send_lp_wqe(hr_qp); 3491 if (ret) { 3492 ibdev_err_ratelimited(ibdev, 3493 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3494 hr_qp->qpn, ret); 3495 break; 3496 } 3497 3498 cqe_cnt++; 3499 } 3500 3501 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3502 while (cqe_cnt) { 3503 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3504 if (npolled < 0) { 3505 ibdev_err_ratelimited(ibdev, 3506 "failed to poll cqe for free mr, remain %d cqe.\n", 3507 cqe_cnt); 3508 goto out; 3509 } 3510 3511 if (time_after(jiffies, end)) { 3512 ibdev_err_ratelimited(ibdev, 3513 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3514 cqe_cnt); 3515 goto out; 3516 } 3517 cqe_cnt -= npolled; 3518 } 3519 3520 out: 3521 mutex_unlock(&free_mr->mutex); 3522 } 3523 3524 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3525 { 3526 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3527 free_mr_send_cmd_to_hw(hr_dev); 3528 } 3529 3530 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3531 { 3532 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3533 } 3534 3535 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3536 { 3537 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3538 3539 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3540 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3541 NULL; 3542 } 3543 3544 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3545 struct hns_roce_cq *hr_cq) 3546 { 3547 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3548 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3549 } else { 3550 struct hns_roce_v2_db cq_db = {}; 3551 3552 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3553 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3554 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3555 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3556 3557 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3558 } 3559 } 3560 3561 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3562 struct hns_roce_srq *srq) 3563 { 3564 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3565 struct hns_roce_v2_cqe *cqe, *dest; 3566 u32 prod_index; 3567 int nfreed = 0; 3568 int wqe_index; 3569 u8 owner_bit; 3570 3571 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3572 ++prod_index) { 3573 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3574 break; 3575 } 3576 3577 /* 3578 * Now backwards through the CQ, removing CQ entries 3579 * that match our QP by overwriting them with next entries. 3580 */ 3581 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3582 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3583 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3584 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3585 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3586 hns_roce_free_srq_wqe(srq, wqe_index); 3587 } 3588 ++nfreed; 3589 } else if (nfreed) { 3590 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3591 hr_cq->ib_cq.cqe); 3592 owner_bit = hr_reg_read(dest, CQE_OWNER); 3593 memcpy(dest, cqe, hr_cq->cqe_size); 3594 hr_reg_write(dest, CQE_OWNER, owner_bit); 3595 } 3596 } 3597 3598 if (nfreed) { 3599 hr_cq->cons_index += nfreed; 3600 update_cq_db(hr_dev, hr_cq); 3601 } 3602 } 3603 3604 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3605 struct hns_roce_srq *srq) 3606 { 3607 spin_lock_irq(&hr_cq->lock); 3608 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3609 spin_unlock_irq(&hr_cq->lock); 3610 } 3611 3612 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3613 struct hns_roce_cq *hr_cq, void *mb_buf, 3614 u64 *mtts, dma_addr_t dma_handle) 3615 { 3616 struct hns_roce_v2_cq_context *cq_context; 3617 3618 cq_context = mb_buf; 3619 memset(cq_context, 0, sizeof(*cq_context)); 3620 3621 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3622 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3623 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3624 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3625 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3626 3627 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3628 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3629 3630 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3631 hr_reg_enable(cq_context, CQC_STASH); 3632 3633 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3634 to_hr_hw_page_addr(mtts[0])); 3635 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3636 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3637 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3638 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3639 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3640 to_hr_hw_page_addr(mtts[1])); 3641 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3642 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3643 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3644 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3645 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3646 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3647 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S); 3648 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S); 3649 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3650 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3651 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3652 ((u32)hr_cq->db.dma) >> 1); 3653 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3654 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S); 3655 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3656 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3657 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3658 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3659 } 3660 3661 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3662 enum ib_cq_notify_flags flags) 3663 { 3664 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3665 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3666 struct hns_roce_v2_db cq_db = {}; 3667 u32 notify_flag; 3668 3669 /* 3670 * flags = 0, then notify_flag : next 3671 * flags = 1, then notify flag : solocited 3672 */ 3673 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3674 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3675 3676 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3677 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3678 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3679 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3680 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3681 3682 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3683 3684 return 0; 3685 } 3686 3687 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3688 int num_entries, struct ib_wc *wc) 3689 { 3690 unsigned int left; 3691 int npolled = 0; 3692 3693 left = wq->head - wq->tail; 3694 if (left == 0) 3695 return 0; 3696 3697 left = min_t(unsigned int, (unsigned int)num_entries, left); 3698 while (npolled < left) { 3699 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3700 wc->status = IB_WC_WR_FLUSH_ERR; 3701 wc->vendor_err = 0; 3702 wc->qp = &hr_qp->ibqp; 3703 3704 wq->tail++; 3705 wc++; 3706 npolled++; 3707 } 3708 3709 return npolled; 3710 } 3711 3712 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3713 struct ib_wc *wc) 3714 { 3715 struct hns_roce_qp *hr_qp; 3716 int npolled = 0; 3717 3718 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3719 npolled += sw_comp(hr_qp, &hr_qp->sq, 3720 num_entries - npolled, wc + npolled); 3721 if (npolled >= num_entries) 3722 goto out; 3723 } 3724 3725 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3726 npolled += sw_comp(hr_qp, &hr_qp->rq, 3727 num_entries - npolled, wc + npolled); 3728 if (npolled >= num_entries) 3729 goto out; 3730 } 3731 3732 out: 3733 return npolled; 3734 } 3735 3736 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3737 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3738 struct ib_wc *wc) 3739 { 3740 static const struct { 3741 u32 cqe_status; 3742 enum ib_wc_status wc_status; 3743 } map[] = { 3744 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3745 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3746 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3747 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3748 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3749 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3750 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3751 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3752 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3753 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3754 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3755 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3756 IB_WC_RETRY_EXC_ERR }, 3757 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3758 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3759 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3760 }; 3761 3762 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3763 int i; 3764 3765 wc->status = IB_WC_GENERAL_ERR; 3766 for (i = 0; i < ARRAY_SIZE(map); i++) 3767 if (cqe_status == map[i].cqe_status) { 3768 wc->status = map[i].wc_status; 3769 break; 3770 } 3771 3772 if (likely(wc->status == IB_WC_SUCCESS || 3773 wc->status == IB_WC_WR_FLUSH_ERR)) 3774 return; 3775 3776 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 3777 cqe_status); 3778 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3779 cq->cqe_size, false); 3780 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3781 3782 /* 3783 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3784 * the standard protocol, the driver must ignore it and needn't to set 3785 * the QP to an error state. 3786 */ 3787 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3788 return; 3789 3790 flush_cqe(hr_dev, qp); 3791 } 3792 3793 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3794 struct hns_roce_qp **cur_qp) 3795 { 3796 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3797 struct hns_roce_qp *hr_qp = *cur_qp; 3798 u32 qpn; 3799 3800 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3801 3802 if (!hr_qp || qpn != hr_qp->qpn) { 3803 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3804 if (unlikely(!hr_qp)) { 3805 ibdev_err(&hr_dev->ib_dev, 3806 "CQ %06lx with entry for unknown QPN %06x\n", 3807 hr_cq->cqn, qpn); 3808 return -EINVAL; 3809 } 3810 *cur_qp = hr_qp; 3811 } 3812 3813 return 0; 3814 } 3815 3816 /* 3817 * mapped-value = 1 + real-value 3818 * The ib wc opcode's real value is start from 0, In order to distinguish 3819 * between initialized and uninitialized map values, we plus 1 to the actual 3820 * value when defining the mapping, so that the validity can be identified by 3821 * checking whether the mapped value is greater than 0. 3822 */ 3823 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3824 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3825 3826 static const u32 wc_send_op_map[] = { 3827 HR_WC_OP_MAP(SEND, SEND), 3828 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3829 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3830 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3831 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3832 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3833 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3834 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3835 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3836 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3837 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3838 HR_WC_OP_MAP(BIND_MW, REG_MR), 3839 }; 3840 3841 static int to_ib_wc_send_op(u32 hr_opcode) 3842 { 3843 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3844 return -EINVAL; 3845 3846 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3847 -EINVAL; 3848 } 3849 3850 static const u32 wc_recv_op_map[] = { 3851 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3852 HR_WC_OP_MAP(SEND, RECV), 3853 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3854 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3855 }; 3856 3857 static int to_ib_wc_recv_op(u32 hr_opcode) 3858 { 3859 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3860 return -EINVAL; 3861 3862 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3863 -EINVAL; 3864 } 3865 3866 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3867 { 3868 u32 hr_opcode; 3869 int ib_opcode; 3870 3871 wc->wc_flags = 0; 3872 3873 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3874 switch (hr_opcode) { 3875 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3876 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3877 break; 3878 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3879 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3880 wc->wc_flags |= IB_WC_WITH_IMM; 3881 break; 3882 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3883 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3884 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3885 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3886 wc->byte_len = 8; 3887 break; 3888 default: 3889 break; 3890 } 3891 3892 ib_opcode = to_ib_wc_send_op(hr_opcode); 3893 if (ib_opcode < 0) 3894 wc->status = IB_WC_GENERAL_ERR; 3895 else 3896 wc->opcode = ib_opcode; 3897 } 3898 3899 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3900 { 3901 u32 hr_opcode; 3902 int ib_opcode; 3903 3904 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3905 3906 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3907 switch (hr_opcode) { 3908 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3909 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3910 wc->wc_flags = IB_WC_WITH_IMM; 3911 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3912 break; 3913 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3914 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3915 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3916 break; 3917 default: 3918 wc->wc_flags = 0; 3919 } 3920 3921 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3922 if (ib_opcode < 0) 3923 wc->status = IB_WC_GENERAL_ERR; 3924 else 3925 wc->opcode = ib_opcode; 3926 3927 wc->sl = hr_reg_read(cqe, CQE_SL); 3928 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3929 wc->slid = 0; 3930 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3931 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3932 wc->pkey_index = 0; 3933 3934 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3935 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3936 wc->wc_flags |= IB_WC_WITH_VLAN; 3937 } else { 3938 wc->vlan_id = 0xffff; 3939 } 3940 3941 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3942 3943 return 0; 3944 } 3945 3946 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3947 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3948 { 3949 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3950 struct hns_roce_qp *qp = *cur_qp; 3951 struct hns_roce_srq *srq = NULL; 3952 struct hns_roce_v2_cqe *cqe; 3953 struct hns_roce_wq *wq; 3954 int is_send; 3955 u16 wqe_idx; 3956 int ret; 3957 3958 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3959 if (!cqe) 3960 return -EAGAIN; 3961 3962 ++hr_cq->cons_index; 3963 /* Memory barrier */ 3964 rmb(); 3965 3966 ret = get_cur_qp(hr_cq, cqe, &qp); 3967 if (ret) 3968 return ret; 3969 3970 wc->qp = &qp->ibqp; 3971 wc->vendor_err = 0; 3972 3973 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3974 3975 is_send = !hr_reg_read(cqe, CQE_S_R); 3976 if (is_send) { 3977 wq = &qp->sq; 3978 3979 /* If sg_signal_bit is set, tail pointer will be updated to 3980 * the WQE corresponding to the current CQE. 3981 */ 3982 if (qp->sq_signal_bits) 3983 wq->tail += (wqe_idx - (u16)wq->tail) & 3984 (wq->wqe_cnt - 1); 3985 3986 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3987 ++wq->tail; 3988 3989 fill_send_wc(wc, cqe); 3990 } else { 3991 if (qp->ibqp.srq) { 3992 srq = to_hr_srq(qp->ibqp.srq); 3993 wc->wr_id = srq->wrid[wqe_idx]; 3994 hns_roce_free_srq_wqe(srq, wqe_idx); 3995 } else { 3996 wq = &qp->rq; 3997 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3998 ++wq->tail; 3999 } 4000 4001 ret = fill_recv_wc(wc, cqe); 4002 } 4003 4004 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 4005 if (unlikely(wc->status != IB_WC_SUCCESS)) 4006 return 0; 4007 4008 return ret; 4009 } 4010 4011 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 4012 struct ib_wc *wc) 4013 { 4014 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 4015 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 4016 struct hns_roce_qp *cur_qp = NULL; 4017 unsigned long flags; 4018 int npolled; 4019 4020 spin_lock_irqsave(&hr_cq->lock, flags); 4021 4022 /* 4023 * When the device starts to reset, the state is RST_DOWN. At this time, 4024 * there may still be some valid CQEs in the hardware that are not 4025 * polled. Therefore, it is not allowed to switch to the software mode 4026 * immediately. When the state changes to UNINIT, CQE no longer exists 4027 * in the hardware, and then switch to software mode. 4028 */ 4029 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 4030 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4031 goto out; 4032 } 4033 4034 for (npolled = 0; npolled < num_entries; ++npolled) { 4035 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4036 break; 4037 } 4038 4039 if (npolled) 4040 update_cq_db(hr_dev, hr_cq); 4041 4042 out: 4043 spin_unlock_irqrestore(&hr_cq->lock, flags); 4044 4045 return npolled; 4046 } 4047 4048 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4049 u32 step_idx, u8 *mbox_cmd) 4050 { 4051 u8 cmd; 4052 4053 switch (type) { 4054 case HEM_TYPE_QPC: 4055 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4056 break; 4057 case HEM_TYPE_MTPT: 4058 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4059 break; 4060 case HEM_TYPE_CQC: 4061 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4062 break; 4063 case HEM_TYPE_SRQC: 4064 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4065 break; 4066 case HEM_TYPE_SCCC: 4067 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4068 break; 4069 case HEM_TYPE_QPC_TIMER: 4070 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4071 break; 4072 case HEM_TYPE_CQC_TIMER: 4073 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4074 break; 4075 default: 4076 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4077 return -EINVAL; 4078 } 4079 4080 *mbox_cmd = cmd + step_idx; 4081 4082 return 0; 4083 } 4084 4085 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4086 dma_addr_t base_addr) 4087 { 4088 struct hns_roce_cmq_desc desc; 4089 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4090 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4091 u64 addr = to_hr_hw_page_addr(base_addr); 4092 4093 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4094 4095 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4096 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4097 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4098 4099 return hns_roce_cmq_send(hr_dev, &desc, 1); 4100 } 4101 4102 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4103 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4104 { 4105 int ret; 4106 u8 cmd; 4107 4108 if (unlikely(hem_type == HEM_TYPE_GMV)) 4109 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4110 4111 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4112 return 0; 4113 4114 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4115 if (ret < 0) 4116 return ret; 4117 4118 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4119 } 4120 4121 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4122 struct hns_roce_hem_table *table, int obj, 4123 u32 step_idx) 4124 { 4125 struct hns_roce_hem_mhop mhop; 4126 struct hns_roce_hem *hem; 4127 unsigned long mhop_obj = obj; 4128 int i, j, k; 4129 int ret = 0; 4130 u64 hem_idx = 0; 4131 u64 l1_idx = 0; 4132 u64 bt_ba = 0; 4133 u32 chunk_ba_num; 4134 u32 hop_num; 4135 4136 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4137 return 0; 4138 4139 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4140 i = mhop.l0_idx; 4141 j = mhop.l1_idx; 4142 k = mhop.l2_idx; 4143 hop_num = mhop.hop_num; 4144 chunk_ba_num = mhop.bt_chunk_size / 8; 4145 4146 if (hop_num == 2) { 4147 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4148 k; 4149 l1_idx = i * chunk_ba_num + j; 4150 } else if (hop_num == 1) { 4151 hem_idx = i * chunk_ba_num + j; 4152 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4153 hem_idx = i; 4154 } 4155 4156 if (table->type == HEM_TYPE_SCCC) 4157 obj = mhop.l0_idx; 4158 4159 if (check_whether_last_step(hop_num, step_idx)) { 4160 hem = table->hem[hem_idx]; 4161 4162 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4163 } else { 4164 if (step_idx == 0) 4165 bt_ba = table->bt_l0_dma_addr[i]; 4166 else if (step_idx == 1 && hop_num == 2) 4167 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4168 4169 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4170 } 4171 4172 return ret; 4173 } 4174 4175 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4176 struct hns_roce_hem_table *table, 4177 int tag, u32 step_idx) 4178 { 4179 struct hns_roce_cmd_mailbox *mailbox; 4180 struct device *dev = hr_dev->dev; 4181 u8 cmd = 0xff; 4182 int ret; 4183 4184 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4185 return 0; 4186 4187 switch (table->type) { 4188 case HEM_TYPE_QPC: 4189 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4190 break; 4191 case HEM_TYPE_MTPT: 4192 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4193 break; 4194 case HEM_TYPE_CQC: 4195 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4196 break; 4197 case HEM_TYPE_SRQC: 4198 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4199 break; 4200 case HEM_TYPE_SCCC: 4201 case HEM_TYPE_QPC_TIMER: 4202 case HEM_TYPE_CQC_TIMER: 4203 case HEM_TYPE_GMV: 4204 return 0; 4205 default: 4206 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4207 table->type); 4208 return 0; 4209 } 4210 4211 cmd += step_idx; 4212 4213 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4214 if (IS_ERR(mailbox)) 4215 return PTR_ERR(mailbox); 4216 4217 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4218 4219 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4220 return ret; 4221 } 4222 4223 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4224 struct hns_roce_v2_qp_context *context, 4225 struct hns_roce_v2_qp_context *qpc_mask, 4226 struct hns_roce_qp *hr_qp) 4227 { 4228 struct hns_roce_cmd_mailbox *mailbox; 4229 int qpc_size; 4230 int ret; 4231 4232 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4233 if (IS_ERR(mailbox)) 4234 return PTR_ERR(mailbox); 4235 4236 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4237 qpc_size = hr_dev->caps.qpc_sz; 4238 memcpy(mailbox->buf, context, qpc_size); 4239 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4240 4241 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4242 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4243 4244 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4245 4246 return ret; 4247 } 4248 4249 static void set_access_flags(struct hns_roce_qp *hr_qp, 4250 struct hns_roce_v2_qp_context *context, 4251 struct hns_roce_v2_qp_context *qpc_mask, 4252 const struct ib_qp_attr *attr, int attr_mask) 4253 { 4254 u8 dest_rd_atomic; 4255 u32 access_flags; 4256 4257 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4258 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4259 4260 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4261 attr->qp_access_flags : hr_qp->atomic_rd_en; 4262 4263 if (!dest_rd_atomic) 4264 access_flags &= IB_ACCESS_REMOTE_WRITE; 4265 4266 hr_reg_write_bool(context, QPC_RRE, 4267 access_flags & IB_ACCESS_REMOTE_READ); 4268 hr_reg_clear(qpc_mask, QPC_RRE); 4269 4270 hr_reg_write_bool(context, QPC_RWE, 4271 access_flags & IB_ACCESS_REMOTE_WRITE); 4272 hr_reg_clear(qpc_mask, QPC_RWE); 4273 4274 hr_reg_write_bool(context, QPC_ATE, 4275 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4276 hr_reg_clear(qpc_mask, QPC_ATE); 4277 hr_reg_write_bool(context, QPC_EXT_ATE, 4278 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4279 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4280 } 4281 4282 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4283 struct hns_roce_v2_qp_context *context) 4284 { 4285 hr_reg_write(context, QPC_SGE_SHIFT, 4286 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4287 hr_qp->sge.sge_shift)); 4288 4289 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4290 4291 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4292 } 4293 4294 static inline int get_cqn(struct ib_cq *ib_cq) 4295 { 4296 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4297 } 4298 4299 static inline int get_pdn(struct ib_pd *ib_pd) 4300 { 4301 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4302 } 4303 4304 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4305 struct hns_roce_v2_qp_context *context, 4306 struct hns_roce_v2_qp_context *qpc_mask) 4307 { 4308 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4309 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4310 4311 /* 4312 * In v2 engine, software pass context and context mask to hardware 4313 * when modifying qp. If software need modify some fields in context, 4314 * we should set all bits of the relevant fields in context mask to 4315 * 0 at the same time, else set them to 0x1. 4316 */ 4317 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4318 4319 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4320 4321 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4322 4323 set_qpc_wqe_cnt(hr_qp, context); 4324 4325 /* No VLAN need to set 0xFFF */ 4326 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4327 4328 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4329 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4330 4331 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4332 } 4333 4334 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4335 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4336 4337 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4338 hr_reg_enable(context, QPC_OWNER_MODE); 4339 4340 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4341 lower_32_bits(hr_qp->rdb.dma) >> 1); 4342 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4343 upper_32_bits(hr_qp->rdb.dma)); 4344 4345 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4346 4347 if (ibqp->srq) { 4348 hr_reg_enable(context, QPC_SRQ_EN); 4349 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4350 } 4351 4352 hr_reg_enable(context, QPC_FRE); 4353 4354 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4355 4356 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4357 return; 4358 4359 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4360 hr_reg_enable(&context->ext, QPCEX_STASH); 4361 } 4362 4363 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4364 struct hns_roce_v2_qp_context *context, 4365 struct hns_roce_v2_qp_context *qpc_mask) 4366 { 4367 /* 4368 * In v2 engine, software pass context and context mask to hardware 4369 * when modifying qp. If software need modify some fields in context, 4370 * we should set all bits of the relevant fields in context mask to 4371 * 0 at the same time, else set them to 0x1. 4372 */ 4373 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4374 hr_reg_clear(qpc_mask, QPC_TST); 4375 4376 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4377 hr_reg_clear(qpc_mask, QPC_PD); 4378 4379 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4380 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4381 4382 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4383 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4384 4385 if (ibqp->srq) { 4386 hr_reg_enable(context, QPC_SRQ_EN); 4387 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4388 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4389 hr_reg_clear(qpc_mask, QPC_SRQN); 4390 } 4391 } 4392 4393 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4394 struct hns_roce_qp *hr_qp, 4395 struct hns_roce_v2_qp_context *context, 4396 struct hns_roce_v2_qp_context *qpc_mask) 4397 { 4398 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4399 u64 wqe_sge_ba; 4400 int ret; 4401 4402 /* Search qp buf's mtts */ 4403 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4404 MTT_MIN_COUNT); 4405 if (hr_qp->rq.wqe_cnt && ret) { 4406 ibdev_err(&hr_dev->ib_dev, 4407 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4408 hr_qp->qpn, ret); 4409 return ret; 4410 } 4411 4412 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4413 4414 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4415 qpc_mask->wqe_sge_ba = 0; 4416 4417 /* 4418 * In v2 engine, software pass context and context mask to hardware 4419 * when modifying qp. If software need modify some fields in context, 4420 * we should set all bits of the relevant fields in context mask to 4421 * 0 at the same time, else set them to 0x1. 4422 */ 4423 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4424 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4425 4426 hr_reg_write(context, QPC_SQ_HOP_NUM, 4427 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4428 hr_qp->sq.wqe_cnt)); 4429 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4430 4431 hr_reg_write(context, QPC_SGE_HOP_NUM, 4432 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4433 hr_qp->sge.sge_cnt)); 4434 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4435 4436 hr_reg_write(context, QPC_RQ_HOP_NUM, 4437 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4438 hr_qp->rq.wqe_cnt)); 4439 4440 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4441 4442 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4443 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4444 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4445 4446 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4447 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4448 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4449 4450 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4451 qpc_mask->rq_cur_blk_addr = 0; 4452 4453 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4454 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4455 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4456 4457 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4458 context->rq_nxt_blk_addr = 4459 cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4460 qpc_mask->rq_nxt_blk_addr = 0; 4461 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4462 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4463 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4464 } 4465 4466 return 0; 4467 } 4468 4469 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4470 struct hns_roce_qp *hr_qp, 4471 struct hns_roce_v2_qp_context *context, 4472 struct hns_roce_v2_qp_context *qpc_mask) 4473 { 4474 struct ib_device *ibdev = &hr_dev->ib_dev; 4475 u64 sge_cur_blk = 0; 4476 u64 sq_cur_blk = 0; 4477 int ret; 4478 4479 /* search qp buf's mtts */ 4480 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4481 &sq_cur_blk, 1); 4482 if (ret) { 4483 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4484 hr_qp->qpn, ret); 4485 return ret; 4486 } 4487 if (hr_qp->sge.sge_cnt > 0) { 4488 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4489 hr_qp->sge.offset, &sge_cur_blk, 1); 4490 if (ret) { 4491 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4492 hr_qp->qpn, ret); 4493 return ret; 4494 } 4495 } 4496 4497 /* 4498 * In v2 engine, software pass context and context mask to hardware 4499 * when modifying qp. If software need modify some fields in context, 4500 * we should set all bits of the relevant fields in context mask to 4501 * 0 at the same time, else set them to 0x1. 4502 */ 4503 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4504 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4505 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4506 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4507 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4508 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4509 4510 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4511 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4512 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4513 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4514 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4515 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4516 4517 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4518 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4519 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4520 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4521 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4522 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4523 4524 return 0; 4525 } 4526 4527 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4528 const struct ib_qp_attr *attr) 4529 { 4530 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4531 return IB_MTU_4096; 4532 4533 return attr->path_mtu; 4534 } 4535 4536 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4537 const struct ib_qp_attr *attr, int attr_mask, 4538 struct hns_roce_v2_qp_context *context, 4539 struct hns_roce_v2_qp_context *qpc_mask, 4540 struct ib_udata *udata) 4541 { 4542 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4543 struct hns_roce_ucontext, ibucontext); 4544 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4545 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4546 struct ib_device *ibdev = &hr_dev->ib_dev; 4547 dma_addr_t trrl_ba; 4548 dma_addr_t irrl_ba; 4549 enum ib_mtu ib_mtu; 4550 const u8 *smac; 4551 u8 lp_pktn_ini; 4552 u64 *mtts; 4553 u8 *dmac; 4554 u32 port; 4555 int mtu; 4556 int ret; 4557 4558 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4559 if (ret) { 4560 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4561 return ret; 4562 } 4563 4564 /* Search IRRL's mtts */ 4565 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4566 hr_qp->qpn, &irrl_ba); 4567 if (!mtts) { 4568 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4569 return -EINVAL; 4570 } 4571 4572 /* Search TRRL's mtts */ 4573 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4574 hr_qp->qpn, &trrl_ba); 4575 if (!mtts) { 4576 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4577 return -EINVAL; 4578 } 4579 4580 if (attr_mask & IB_QP_ALT_PATH) { 4581 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4582 attr_mask); 4583 return -EINVAL; 4584 } 4585 4586 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S); 4587 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4588 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S); 4589 qpc_mask->trrl_ba = 0; 4590 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S); 4591 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4592 4593 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S); 4594 qpc_mask->irrl_ba = 0; 4595 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S); 4596 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4597 4598 hr_reg_enable(context, QPC_RMT_E2E); 4599 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4600 4601 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4602 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4603 4604 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4605 4606 smac = (const u8 *)hr_dev->dev_addr[port]; 4607 dmac = (u8 *)attr->ah_attr.roce.dmac; 4608 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4609 if (ether_addr_equal_unaligned(dmac, smac) || 4610 hr_dev->loop_idc == 0x1) { 4611 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4612 hr_reg_clear(qpc_mask, QPC_LBI); 4613 } 4614 4615 if (attr_mask & IB_QP_DEST_QPN) { 4616 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4617 hr_reg_clear(qpc_mask, QPC_DQPN); 4618 } 4619 4620 memcpy(&context->dmac, dmac, sizeof(u32)); 4621 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4622 qpc_mask->dmac = 0; 4623 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4624 4625 ib_mtu = get_mtu(ibqp, attr); 4626 hr_qp->path_mtu = ib_mtu; 4627 4628 mtu = ib_mtu_enum_to_int(ib_mtu); 4629 if (WARN_ON(mtu <= 0)) 4630 return -EINVAL; 4631 #define MIN_LP_MSG_LEN 1024 4632 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4633 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4634 4635 if (attr_mask & IB_QP_PATH_MTU) { 4636 hr_reg_write(context, QPC_MTU, ib_mtu); 4637 hr_reg_clear(qpc_mask, QPC_MTU); 4638 } 4639 4640 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4641 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4642 4643 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4644 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4645 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4646 4647 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4648 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4649 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4650 4651 context->rq_rnr_timer = 0; 4652 qpc_mask->rq_rnr_timer = 0; 4653 4654 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4655 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4656 4657 #define MAX_LP_SGEN 3 4658 /* rocee send 2^lp_sgen_ini segs every time */ 4659 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN); 4660 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4661 4662 if (udata && ibqp->qp_type == IB_QPT_RC && 4663 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4664 hr_reg_write_bool(context, QPC_RQIE, 4665 hr_dev->caps.flags & 4666 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4667 hr_reg_clear(qpc_mask, QPC_RQIE); 4668 } 4669 4670 if (udata && 4671 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4672 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4673 hr_reg_write_bool(context, QPC_CQEIE, 4674 hr_dev->caps.flags & 4675 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4676 hr_reg_clear(qpc_mask, QPC_CQEIE); 4677 4678 hr_reg_write(context, QPC_CQEIS, 0); 4679 hr_reg_clear(qpc_mask, QPC_CQEIS); 4680 } 4681 4682 return 0; 4683 } 4684 4685 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, 4686 struct hns_roce_v2_qp_context *context, 4687 struct hns_roce_v2_qp_context *qpc_mask) 4688 { 4689 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4690 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4691 struct ib_device *ibdev = &hr_dev->ib_dev; 4692 int ret; 4693 4694 /* Not support alternate path and path migration */ 4695 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4696 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4697 return -EINVAL; 4698 } 4699 4700 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4701 if (ret) { 4702 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4703 return ret; 4704 } 4705 4706 /* 4707 * Set some fields in context to zero, Because the default values 4708 * of all fields in context are zero, we need not set them to 0 again. 4709 * but we should set the relevant fields of context mask to 0. 4710 */ 4711 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4712 4713 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4714 4715 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4716 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4717 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4718 4719 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4720 4721 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4722 4723 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4724 4725 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4726 4727 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4728 4729 return 0; 4730 } 4731 4732 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn) 4733 { 4734 struct hns_roce_dip *hr_dip; 4735 int ret; 4736 4737 hr_dip = xa_load(dip_xa, qpn); 4738 if (hr_dip) 4739 return 0; 4740 4741 hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL); 4742 if (!hr_dip) 4743 return -ENOMEM; 4744 4745 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL)); 4746 if (ret) 4747 kfree(hr_dip); 4748 4749 return ret; 4750 } 4751 4752 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4753 u32 *dip_idx) 4754 { 4755 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4756 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4757 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa; 4758 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4759 struct hns_roce_dip *hr_dip; 4760 unsigned long idx; 4761 int ret = 0; 4762 4763 ret = alloc_dip_entry(dip_xa, ibqp->qp_num); 4764 if (ret) 4765 return ret; 4766 4767 xa_lock(dip_xa); 4768 4769 xa_for_each(dip_xa, idx, hr_dip) { 4770 if (hr_dip->qp_cnt && 4771 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) { 4772 *dip_idx = hr_dip->dip_idx; 4773 hr_dip->qp_cnt++; 4774 hr_qp->dip = hr_dip; 4775 goto out; 4776 } 4777 } 4778 4779 /* If no dgid is found, a new dip and a mapping between dgid and 4780 * dip_idx will be created. 4781 */ 4782 xa_for_each(dip_xa, idx, hr_dip) { 4783 if (hr_dip->qp_cnt) 4784 continue; 4785 4786 *dip_idx = idx; 4787 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4788 hr_dip->dip_idx = idx; 4789 hr_dip->qp_cnt++; 4790 hr_qp->dip = hr_dip; 4791 break; 4792 } 4793 4794 /* This should never happen. */ 4795 if (WARN_ON_ONCE(!hr_qp->dip)) 4796 ret = -ENOSPC; 4797 4798 out: 4799 xa_unlock(dip_xa); 4800 return ret; 4801 } 4802 4803 enum { 4804 CONG_DCQCN, 4805 CONG_WINDOW, 4806 }; 4807 4808 enum { 4809 UNSUPPORT_CONG_LEVEL, 4810 SUPPORT_CONG_LEVEL, 4811 }; 4812 4813 enum { 4814 CONG_LDCP, 4815 CONG_HC3, 4816 }; 4817 4818 enum { 4819 DIP_INVALID, 4820 DIP_VALID, 4821 }; 4822 4823 enum { 4824 WND_LIMIT, 4825 WND_UNLIMIT, 4826 }; 4827 4828 static int check_cong_type(struct ib_qp *ibqp, 4829 struct hns_roce_congestion_algorithm *cong_alg) 4830 { 4831 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4832 4833 /* different congestion types match different configurations */ 4834 switch (hr_qp->cong_type) { 4835 case CONG_TYPE_DCQCN: 4836 cong_alg->alg_sel = CONG_DCQCN; 4837 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4838 cong_alg->dip_vld = DIP_INVALID; 4839 cong_alg->wnd_mode_sel = WND_LIMIT; 4840 break; 4841 case CONG_TYPE_LDCP: 4842 cong_alg->alg_sel = CONG_WINDOW; 4843 cong_alg->alg_sub_sel = CONG_LDCP; 4844 cong_alg->dip_vld = DIP_INVALID; 4845 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4846 break; 4847 case CONG_TYPE_HC3: 4848 cong_alg->alg_sel = CONG_WINDOW; 4849 cong_alg->alg_sub_sel = CONG_HC3; 4850 cong_alg->dip_vld = DIP_INVALID; 4851 cong_alg->wnd_mode_sel = WND_LIMIT; 4852 break; 4853 case CONG_TYPE_DIP: 4854 cong_alg->alg_sel = CONG_DCQCN; 4855 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4856 cong_alg->dip_vld = DIP_VALID; 4857 cong_alg->wnd_mode_sel = WND_LIMIT; 4858 break; 4859 default: 4860 hr_qp->cong_type = CONG_TYPE_DCQCN; 4861 cong_alg->alg_sel = CONG_DCQCN; 4862 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4863 cong_alg->dip_vld = DIP_INVALID; 4864 cong_alg->wnd_mode_sel = WND_LIMIT; 4865 break; 4866 } 4867 4868 return 0; 4869 } 4870 4871 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4872 struct hns_roce_v2_qp_context *context, 4873 struct hns_roce_v2_qp_context *qpc_mask) 4874 { 4875 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4876 struct hns_roce_congestion_algorithm cong_field; 4877 struct ib_device *ibdev = ibqp->device; 4878 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4879 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4880 u32 dip_idx = 0; 4881 int ret; 4882 4883 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4884 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4885 return 0; 4886 4887 ret = check_cong_type(ibqp, &cong_field); 4888 if (ret) 4889 return ret; 4890 4891 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4892 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 4893 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4894 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4895 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4896 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4897 cong_field.alg_sub_sel); 4898 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4899 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4900 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4901 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4902 cong_field.wnd_mode_sel); 4903 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4904 4905 /* if dip is disabled, there is no need to set dip idx */ 4906 if (cong_field.dip_vld == 0) 4907 return 0; 4908 4909 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4910 if (ret) { 4911 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4912 return ret; 4913 } 4914 4915 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4916 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4917 4918 return 0; 4919 } 4920 4921 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, 4922 u8 *tc_mode, u8 *priority) 4923 { 4924 struct hns_roce_v2_priv *priv = hr_dev->priv; 4925 struct hnae3_handle *handle = priv->handle; 4926 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 4927 4928 if (!ops->get_dscp_prio) 4929 return -EOPNOTSUPP; 4930 4931 return ops->get_dscp_prio(handle, dscp, tc_mode, priority); 4932 } 4933 4934 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) 4935 { 4936 u32 max_sl; 4937 4938 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4939 if (unlikely(sl > max_sl)) { 4940 ibdev_err_ratelimited(&hr_dev->ib_dev, 4941 "failed to set SL(%u). Shouldn't be larger than %u.\n", 4942 sl, max_sl); 4943 return false; 4944 } 4945 4946 return true; 4947 } 4948 4949 static int hns_roce_set_sl(struct ib_qp *ibqp, 4950 const struct ib_qp_attr *attr, 4951 struct hns_roce_v2_qp_context *context, 4952 struct hns_roce_v2_qp_context *qpc_mask) 4953 { 4954 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4955 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4956 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4957 struct ib_device *ibdev = &hr_dev->ib_dev; 4958 int ret; 4959 4960 ret = hns_roce_hw_v2_get_dscp(hr_dev, get_tclass(&attr->ah_attr.grh), 4961 &hr_qp->tc_mode, &hr_qp->priority); 4962 if (ret && ret != -EOPNOTSUPP && 4963 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 4964 ibdev_err_ratelimited(ibdev, 4965 "failed to get dscp, ret = %d.\n", ret); 4966 return ret; 4967 } 4968 4969 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP && 4970 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 4971 hr_qp->sl = hr_qp->priority; 4972 else 4973 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4974 4975 if (!check_sl_valid(hr_dev, hr_qp->sl)) 4976 return -EINVAL; 4977 4978 hr_reg_write(context, QPC_SL, hr_qp->sl); 4979 hr_reg_clear(qpc_mask, QPC_SL); 4980 4981 return 0; 4982 } 4983 4984 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4985 const struct ib_qp_attr *attr, 4986 int attr_mask, 4987 struct hns_roce_v2_qp_context *context, 4988 struct hns_roce_v2_qp_context *qpc_mask) 4989 { 4990 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4991 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4992 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4993 struct ib_device *ibdev = &hr_dev->ib_dev; 4994 const struct ib_gid_attr *gid_attr = NULL; 4995 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4996 int is_roce_protocol; 4997 u16 vlan_id = 0xffff; 4998 bool is_udp = false; 4999 u8 ib_port; 5000 u8 hr_port; 5001 int ret; 5002 5003 /* 5004 * If free_mr_en of qp is set, it means that this qp comes from 5005 * free mr. This qp will perform the loopback operation. 5006 * In the loopback scenario, only sl needs to be set. 5007 */ 5008 if (hr_qp->free_mr_en) { 5009 if (!check_sl_valid(hr_dev, sl)) 5010 return -EINVAL; 5011 hr_reg_write(context, QPC_SL, sl); 5012 hr_reg_clear(qpc_mask, QPC_SL); 5013 hr_qp->sl = sl; 5014 return 0; 5015 } 5016 5017 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 5018 hr_port = ib_port - 1; 5019 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 5020 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 5021 5022 if (is_roce_protocol) { 5023 gid_attr = attr->ah_attr.grh.sgid_attr; 5024 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 5025 if (ret) 5026 return ret; 5027 5028 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 5029 } 5030 5031 /* Only HIP08 needs to set the vlan_en bits in QPC */ 5032 if (vlan_id < VLAN_N_VID && 5033 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5034 hr_reg_enable(context, QPC_RQ_VLAN_EN); 5035 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 5036 hr_reg_enable(context, QPC_SQ_VLAN_EN); 5037 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 5038 } 5039 5040 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 5041 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 5042 5043 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 5044 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 5045 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 5046 return -EINVAL; 5047 } 5048 5049 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 5050 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 5051 return -EINVAL; 5052 } 5053 5054 hr_reg_write(context, QPC_UDPSPN, 5055 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 5056 attr->dest_qp_num) : 5057 0); 5058 5059 hr_reg_clear(qpc_mask, QPC_UDPSPN); 5060 5061 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5062 5063 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5064 5065 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5066 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5067 5068 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5069 if (ret) 5070 return ret; 5071 5072 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5073 hr_reg_clear(qpc_mask, QPC_TC); 5074 5075 hr_reg_write(context, QPC_FL, grh->flow_label); 5076 hr_reg_clear(qpc_mask, QPC_FL); 5077 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5078 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5079 5080 return hns_roce_set_sl(ibqp, attr, context, qpc_mask); 5081 } 5082 5083 static bool check_qp_state(enum ib_qp_state cur_state, 5084 enum ib_qp_state new_state) 5085 { 5086 static const bool sm[][IB_QPS_ERR + 1] = { 5087 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5088 [IB_QPS_INIT] = true }, 5089 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5090 [IB_QPS_INIT] = true, 5091 [IB_QPS_RTR] = true, 5092 [IB_QPS_ERR] = true }, 5093 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5094 [IB_QPS_RTS] = true, 5095 [IB_QPS_ERR] = true }, 5096 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5097 [IB_QPS_RTS] = true, 5098 [IB_QPS_ERR] = true }, 5099 [IB_QPS_SQD] = {}, 5100 [IB_QPS_SQE] = {}, 5101 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5102 [IB_QPS_ERR] = true } 5103 }; 5104 5105 return sm[cur_state][new_state]; 5106 } 5107 5108 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5109 const struct ib_qp_attr *attr, 5110 int attr_mask, 5111 enum ib_qp_state cur_state, 5112 enum ib_qp_state new_state, 5113 struct hns_roce_v2_qp_context *context, 5114 struct hns_roce_v2_qp_context *qpc_mask, 5115 struct ib_udata *udata) 5116 { 5117 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5118 int ret = 0; 5119 5120 if (!check_qp_state(cur_state, new_state)) 5121 return -EINVAL; 5122 5123 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5124 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5125 modify_qp_reset_to_init(ibqp, context, qpc_mask); 5126 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5127 modify_qp_init_to_init(ibqp, context, qpc_mask); 5128 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5129 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5130 qpc_mask, udata); 5131 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5132 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask); 5133 } 5134 5135 return ret; 5136 } 5137 5138 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5139 { 5140 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5141 #define QP_ACK_TIMEOUT_MAX 31 5142 5143 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5144 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5145 ibdev_warn(&hr_dev->ib_dev, 5146 "local ACK timeout shall be 0 to 20.\n"); 5147 return false; 5148 } 5149 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5150 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5151 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5152 ibdev_warn(&hr_dev->ib_dev, 5153 "local ACK timeout shall be 0 to 31.\n"); 5154 return false; 5155 } 5156 } 5157 5158 return true; 5159 } 5160 5161 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5162 const struct ib_qp_attr *attr, 5163 int attr_mask, 5164 struct hns_roce_v2_qp_context *context, 5165 struct hns_roce_v2_qp_context *qpc_mask) 5166 { 5167 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5168 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5169 int ret = 0; 5170 u8 timeout; 5171 5172 if (attr_mask & IB_QP_AV) { 5173 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5174 qpc_mask); 5175 if (ret) 5176 return ret; 5177 } 5178 5179 if (attr_mask & IB_QP_TIMEOUT) { 5180 timeout = attr->timeout; 5181 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5182 hr_reg_write(context, QPC_AT, timeout); 5183 hr_reg_clear(qpc_mask, QPC_AT); 5184 } 5185 } 5186 5187 if (attr_mask & IB_QP_RETRY_CNT) { 5188 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5189 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5190 5191 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5192 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5193 } 5194 5195 if (attr_mask & IB_QP_RNR_RETRY) { 5196 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5197 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5198 5199 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5200 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5201 } 5202 5203 if (attr_mask & IB_QP_SQ_PSN) { 5204 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5205 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5206 5207 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5208 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5209 5210 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5211 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5212 5213 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5214 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5215 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5216 5217 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5218 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5219 5220 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5221 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5222 } 5223 5224 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5225 attr->max_dest_rd_atomic) { 5226 hr_reg_write(context, QPC_RR_MAX, 5227 fls(attr->max_dest_rd_atomic - 1)); 5228 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5229 } 5230 5231 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5232 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5233 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5234 } 5235 5236 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5237 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5238 5239 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5240 hr_reg_write(context, QPC_MIN_RNR_TIME, 5241 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5242 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5243 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5244 } 5245 5246 if (attr_mask & IB_QP_RQ_PSN) { 5247 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5248 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5249 5250 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5251 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5252 } 5253 5254 if (attr_mask & IB_QP_QKEY) { 5255 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5256 qpc_mask->qkey_xrcd = 0; 5257 hr_qp->qkey = attr->qkey; 5258 } 5259 5260 return ret; 5261 } 5262 5263 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5264 const struct ib_qp_attr *attr, 5265 int attr_mask) 5266 { 5267 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5268 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5269 5270 if (attr_mask & IB_QP_ACCESS_FLAGS) 5271 hr_qp->atomic_rd_en = attr->qp_access_flags; 5272 5273 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5274 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5275 if (attr_mask & IB_QP_PORT) { 5276 hr_qp->port = attr->port_num - 1; 5277 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5278 } 5279 } 5280 5281 static void clear_qp(struct hns_roce_qp *hr_qp) 5282 { 5283 struct ib_qp *ibqp = &hr_qp->ibqp; 5284 5285 if (ibqp->send_cq) 5286 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5287 hr_qp->qpn, NULL); 5288 5289 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5290 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5291 hr_qp->qpn, ibqp->srq ? 5292 to_hr_srq(ibqp->srq) : NULL); 5293 5294 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5295 *hr_qp->rdb.db_record = 0; 5296 5297 hr_qp->rq.head = 0; 5298 hr_qp->rq.tail = 0; 5299 hr_qp->sq.head = 0; 5300 hr_qp->sq.tail = 0; 5301 hr_qp->next_sge = 0; 5302 } 5303 5304 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5305 struct hns_roce_v2_qp_context *context, 5306 struct hns_roce_v2_qp_context *qpc_mask) 5307 { 5308 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5309 unsigned long sq_flag = 0; 5310 unsigned long rq_flag = 0; 5311 5312 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5313 return; 5314 5315 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5316 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5317 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5318 hr_qp->state = IB_QPS_ERR; 5319 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5320 5321 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5322 return; 5323 5324 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5325 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5326 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5327 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5328 } 5329 5330 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5331 const struct ib_qp_attr *attr, 5332 int attr_mask, enum ib_qp_state cur_state, 5333 enum ib_qp_state new_state, struct ib_udata *udata) 5334 { 5335 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5336 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5337 struct hns_roce_v2_qp_context ctx[2]; 5338 struct hns_roce_v2_qp_context *context = ctx; 5339 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5340 struct ib_device *ibdev = &hr_dev->ib_dev; 5341 int ret; 5342 5343 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5344 return -EOPNOTSUPP; 5345 5346 /* 5347 * In v2 engine, software pass context and context mask to hardware 5348 * when modifying qp. If software need modify some fields in context, 5349 * we should set all bits of the relevant fields in context mask to 5350 * 0 at the same time, else set them to 0x1. 5351 */ 5352 memset(context, 0, hr_dev->caps.qpc_sz); 5353 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5354 5355 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5356 new_state, context, qpc_mask, udata); 5357 if (ret) 5358 goto out; 5359 5360 /* When QP state is err, SQ and RQ WQE should be flushed */ 5361 if (new_state == IB_QPS_ERR) 5362 v2_set_flushed_fields(ibqp, context, qpc_mask); 5363 5364 /* Configure the optional fields */ 5365 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5366 qpc_mask); 5367 if (ret) 5368 goto out; 5369 5370 hr_reg_write_bool(context, QPC_INV_CREDIT, 5371 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5372 ibqp->srq); 5373 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5374 5375 /* Every status migrate must change state */ 5376 hr_reg_write(context, QPC_QP_ST, new_state); 5377 hr_reg_clear(qpc_mask, QPC_QP_ST); 5378 5379 /* SW pass context to HW */ 5380 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5381 if (ret) { 5382 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret); 5383 goto out; 5384 } 5385 5386 hr_qp->state = new_state; 5387 5388 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5389 5390 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5391 clear_qp(hr_qp); 5392 5393 out: 5394 return ret; 5395 } 5396 5397 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5398 { 5399 static const enum ib_qp_state map[] = { 5400 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5401 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5402 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5403 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5404 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5405 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5406 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5407 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5408 }; 5409 5410 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5411 } 5412 5413 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5414 void *buffer) 5415 { 5416 struct hns_roce_cmd_mailbox *mailbox; 5417 int ret; 5418 5419 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5420 if (IS_ERR(mailbox)) 5421 return PTR_ERR(mailbox); 5422 5423 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5424 qpn); 5425 if (ret) 5426 goto out; 5427 5428 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5429 5430 out: 5431 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5432 return ret; 5433 } 5434 5435 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5436 void *buffer) 5437 { 5438 struct hns_roce_srq_context *context; 5439 struct hns_roce_cmd_mailbox *mailbox; 5440 int ret; 5441 5442 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5443 if (IS_ERR(mailbox)) 5444 return PTR_ERR(mailbox); 5445 5446 context = mailbox->buf; 5447 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5448 srqn); 5449 if (ret) 5450 goto out; 5451 5452 memcpy(buffer, context, sizeof(*context)); 5453 5454 out: 5455 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5456 return ret; 5457 } 5458 5459 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 qpn, 5460 void *buffer) 5461 { 5462 struct hns_roce_v2_scc_context *context; 5463 struct hns_roce_cmd_mailbox *mailbox; 5464 int ret; 5465 5466 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5467 if (IS_ERR(mailbox)) 5468 return PTR_ERR(mailbox); 5469 5470 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5471 qpn); 5472 if (ret) 5473 goto out; 5474 5475 context = mailbox->buf; 5476 memcpy(buffer, context, sizeof(*context)); 5477 5478 out: 5479 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5480 return ret; 5481 } 5482 5483 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5484 struct hns_roce_v2_qp_context *context) 5485 { 5486 u8 timeout; 5487 5488 timeout = (u8)hr_reg_read(context, QPC_AT); 5489 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5490 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5491 5492 return timeout; 5493 } 5494 5495 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5496 int qp_attr_mask, 5497 struct ib_qp_init_attr *qp_init_attr) 5498 { 5499 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5500 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5501 struct hns_roce_v2_qp_context context = {}; 5502 struct ib_device *ibdev = &hr_dev->ib_dev; 5503 int tmp_qp_state; 5504 int state; 5505 int ret; 5506 5507 memset(qp_attr, 0, sizeof(*qp_attr)); 5508 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5509 5510 mutex_lock(&hr_qp->mutex); 5511 5512 if (hr_qp->state == IB_QPS_RESET) { 5513 qp_attr->qp_state = IB_QPS_RESET; 5514 ret = 0; 5515 goto done; 5516 } 5517 5518 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5519 if (ret) { 5520 ibdev_err_ratelimited(ibdev, 5521 "failed to query QPC, ret = %d.\n", 5522 ret); 5523 ret = -EINVAL; 5524 goto out; 5525 } 5526 5527 state = hr_reg_read(&context, QPC_QP_ST); 5528 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5529 if (tmp_qp_state == -1) { 5530 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n"); 5531 ret = -EINVAL; 5532 goto out; 5533 } 5534 hr_qp->state = (u8)tmp_qp_state; 5535 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5536 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5537 qp_attr->path_mig_state = IB_MIG_ARMED; 5538 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5539 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5540 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5541 5542 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5543 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5544 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5545 qp_attr->qp_access_flags = 5546 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5547 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5548 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5549 5550 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5551 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5552 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5553 struct ib_global_route *grh = 5554 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5555 5556 rdma_ah_set_sl(&qp_attr->ah_attr, 5557 hr_reg_read(&context, QPC_SL)); 5558 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5559 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5560 grh->flow_label = hr_reg_read(&context, QPC_FL); 5561 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5562 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5563 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5564 5565 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5566 } 5567 5568 qp_attr->port_num = hr_qp->port + 1; 5569 qp_attr->sq_draining = 0; 5570 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5571 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5572 5573 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5574 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5575 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5576 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5577 5578 done: 5579 qp_attr->cur_qp_state = qp_attr->qp_state; 5580 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5581 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5582 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5583 5584 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5585 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5586 5587 qp_init_attr->qp_context = ibqp->qp_context; 5588 qp_init_attr->qp_type = ibqp->qp_type; 5589 qp_init_attr->recv_cq = ibqp->recv_cq; 5590 qp_init_attr->send_cq = ibqp->send_cq; 5591 qp_init_attr->srq = ibqp->srq; 5592 qp_init_attr->cap = qp_attr->cap; 5593 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5594 5595 out: 5596 mutex_unlock(&hr_qp->mutex); 5597 return ret; 5598 } 5599 5600 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5601 { 5602 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5603 hr_qp->ibqp.qp_type == IB_QPT_UD || 5604 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5605 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5606 hr_qp->state != IB_QPS_RESET); 5607 } 5608 5609 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5610 struct hns_roce_qp *hr_qp, 5611 struct ib_udata *udata) 5612 { 5613 struct ib_device *ibdev = &hr_dev->ib_dev; 5614 struct hns_roce_cq *send_cq, *recv_cq; 5615 unsigned long flags; 5616 int ret = 0; 5617 5618 if (modify_qp_is_ok(hr_qp)) { 5619 /* Modify qp to reset before destroying qp */ 5620 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5621 hr_qp->state, IB_QPS_RESET, udata); 5622 if (ret) 5623 ibdev_err_ratelimited(ibdev, 5624 "failed to modify QP to RST, ret = %d.\n", 5625 ret); 5626 } 5627 5628 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5629 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5630 5631 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5632 hns_roce_lock_cqs(send_cq, recv_cq); 5633 5634 if (!udata) { 5635 if (recv_cq) 5636 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5637 (hr_qp->ibqp.srq ? 5638 to_hr_srq(hr_qp->ibqp.srq) : 5639 NULL)); 5640 5641 if (send_cq && send_cq != recv_cq) 5642 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5643 } 5644 5645 hns_roce_qp_remove(hr_dev, hr_qp); 5646 5647 hns_roce_unlock_cqs(send_cq, recv_cq); 5648 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5649 5650 return ret; 5651 } 5652 5653 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev, 5654 struct hns_roce_qp *hr_qp) 5655 { 5656 struct hns_roce_dip *hr_dip = hr_qp->dip; 5657 5658 if (!hr_dip) 5659 return; 5660 5661 xa_lock(&hr_dev->qp_table.dip_xa); 5662 5663 hr_dip->qp_cnt--; 5664 if (!hr_dip->qp_cnt) 5665 memset(hr_dip->dgid, 0, GID_LEN_V2); 5666 5667 xa_unlock(&hr_dev->qp_table.dip_xa); 5668 } 5669 5670 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5671 { 5672 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5673 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5674 unsigned long flags; 5675 int ret; 5676 5677 /* Make sure flush_cqe() is completed */ 5678 spin_lock_irqsave(&hr_qp->flush_lock, flags); 5679 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag); 5680 spin_unlock_irqrestore(&hr_qp->flush_lock, flags); 5681 flush_work(&hr_qp->flush_work.work); 5682 5683 if (hr_qp->cong_type == CONG_TYPE_DIP) 5684 put_dip_ctx_idx(hr_dev, hr_qp); 5685 5686 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5687 if (ret) 5688 ibdev_err_ratelimited(&hr_dev->ib_dev, 5689 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5690 hr_qp->qpn, ret); 5691 5692 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5693 5694 return 0; 5695 } 5696 5697 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5698 struct hns_roce_qp *hr_qp) 5699 { 5700 struct ib_device *ibdev = &hr_dev->ib_dev; 5701 struct hns_roce_sccc_clr_done *resp; 5702 struct hns_roce_sccc_clr *clr; 5703 struct hns_roce_cmq_desc desc; 5704 int ret, i; 5705 5706 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5707 return 0; 5708 5709 mutex_lock(&hr_dev->qp_table.scc_mutex); 5710 5711 /* set scc ctx clear done flag */ 5712 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5713 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5714 if (ret) { 5715 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5716 goto out; 5717 } 5718 5719 /* clear scc context */ 5720 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5721 clr = (struct hns_roce_sccc_clr *)desc.data; 5722 clr->qpn = cpu_to_le32(hr_qp->qpn); 5723 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5724 if (ret) { 5725 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5726 goto out; 5727 } 5728 5729 /* query scc context clear is done or not */ 5730 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5731 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5732 hns_roce_cmq_setup_basic_desc(&desc, 5733 HNS_ROCE_OPC_QUERY_SCCC, true); 5734 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5735 if (ret) { 5736 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5737 ret); 5738 goto out; 5739 } 5740 5741 if (resp->clr_done) 5742 goto out; 5743 5744 msleep(20); 5745 } 5746 5747 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5748 ret = -ETIMEDOUT; 5749 5750 out: 5751 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5752 return ret; 5753 } 5754 5755 #define DMA_IDX_SHIFT 3 5756 #define DMA_WQE_SHIFT 3 5757 5758 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5759 struct hns_roce_srq_context *ctx) 5760 { 5761 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5762 struct ib_device *ibdev = srq->ibsrq.device; 5763 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5764 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5765 dma_addr_t dma_handle_idx; 5766 int ret; 5767 5768 /* Get physical address of idx que buf */ 5769 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5770 ARRAY_SIZE(mtts_idx)); 5771 if (ret) { 5772 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5773 ret); 5774 return ret; 5775 } 5776 5777 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 5778 5779 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5780 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5781 5782 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5783 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5784 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5785 5786 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5787 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5788 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5789 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5790 5791 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5792 to_hr_hw_page_addr(mtts_idx[0])); 5793 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5794 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5795 5796 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5797 to_hr_hw_page_addr(mtts_idx[1])); 5798 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5799 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5800 5801 return 0; 5802 } 5803 5804 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5805 { 5806 struct ib_device *ibdev = srq->ibsrq.device; 5807 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5808 struct hns_roce_srq_context *ctx = mb_buf; 5809 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5810 dma_addr_t dma_handle_wqe; 5811 int ret; 5812 5813 memset(ctx, 0, sizeof(*ctx)); 5814 5815 /* Get the physical address of srq buf */ 5816 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5817 ARRAY_SIZE(mtts_wqe)); 5818 if (ret) { 5819 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5820 ret); 5821 return ret; 5822 } 5823 5824 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 5825 5826 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5827 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5828 srq->ibsrq.srq_type == IB_SRQT_XRC); 5829 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5830 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5831 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5832 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5833 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5834 hr_reg_write(ctx, SRQC_RQWS, 5835 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5836 5837 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5838 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5839 srq->wqe_cnt)); 5840 5841 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5842 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5843 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5844 5845 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5846 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5847 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5848 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5849 5850 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5851 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5852 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5853 lower_32_bits(srq->rdb.dma) >> 1); 5854 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5855 upper_32_bits(srq->rdb.dma)); 5856 } 5857 5858 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5859 } 5860 5861 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5862 struct ib_srq_attr *srq_attr, 5863 enum ib_srq_attr_mask srq_attr_mask, 5864 struct ib_udata *udata) 5865 { 5866 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5867 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5868 struct hns_roce_srq_context *srq_context; 5869 struct hns_roce_srq_context *srqc_mask; 5870 struct hns_roce_cmd_mailbox *mailbox; 5871 int ret = 0; 5872 5873 /* Resizing SRQs is not supported yet */ 5874 if (srq_attr_mask & IB_SRQ_MAX_WR) { 5875 ret = -EOPNOTSUPP; 5876 goto out; 5877 } 5878 5879 if (srq_attr_mask & IB_SRQ_LIMIT) { 5880 if (srq_attr->srq_limit > srq->wqe_cnt) { 5881 ret = -EINVAL; 5882 goto out; 5883 } 5884 5885 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5886 if (IS_ERR(mailbox)) { 5887 ret = PTR_ERR(mailbox); 5888 goto out; 5889 } 5890 5891 srq_context = mailbox->buf; 5892 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5893 5894 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5895 5896 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5897 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5898 5899 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5900 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5901 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5902 if (ret) 5903 ibdev_err(&hr_dev->ib_dev, 5904 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5905 ret); 5906 } 5907 5908 out: 5909 if (ret) 5910 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 5911 5912 return ret; 5913 } 5914 5915 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5916 { 5917 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5918 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5919 struct hns_roce_srq_context *srq_context; 5920 struct hns_roce_cmd_mailbox *mailbox; 5921 int ret; 5922 5923 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5924 if (IS_ERR(mailbox)) 5925 return PTR_ERR(mailbox); 5926 5927 srq_context = mailbox->buf; 5928 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5929 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5930 if (ret) { 5931 ibdev_err(&hr_dev->ib_dev, 5932 "failed to process cmd of querying SRQ, ret = %d.\n", 5933 ret); 5934 goto out; 5935 } 5936 5937 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5938 attr->max_wr = srq->wqe_cnt; 5939 attr->max_sge = srq->max_gs - srq->rsv_sge; 5940 5941 out: 5942 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5943 return ret; 5944 } 5945 5946 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5947 { 5948 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5949 struct hns_roce_v2_cq_context *cq_context; 5950 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5951 struct hns_roce_v2_cq_context *cqc_mask; 5952 struct hns_roce_cmd_mailbox *mailbox; 5953 int ret; 5954 5955 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5956 ret = PTR_ERR_OR_ZERO(mailbox); 5957 if (ret) 5958 goto err_out; 5959 5960 cq_context = mailbox->buf; 5961 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5962 5963 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5964 5965 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5966 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5967 5968 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5969 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5970 dev_info(hr_dev->dev, 5971 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5972 cq_period); 5973 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 5974 } 5975 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5976 } 5977 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5978 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5979 5980 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5981 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5982 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5983 if (ret) 5984 ibdev_err_ratelimited(&hr_dev->ib_dev, 5985 "failed to process cmd when modifying CQ, ret = %d.\n", 5986 ret); 5987 5988 err_out: 5989 if (ret) 5990 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 5991 5992 return ret; 5993 } 5994 5995 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5996 void *buffer) 5997 { 5998 struct hns_roce_v2_cq_context *context; 5999 struct hns_roce_cmd_mailbox *mailbox; 6000 int ret; 6001 6002 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6003 if (IS_ERR(mailbox)) 6004 return PTR_ERR(mailbox); 6005 6006 context = mailbox->buf; 6007 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 6008 HNS_ROCE_CMD_QUERY_CQC, cqn); 6009 if (ret) { 6010 ibdev_err_ratelimited(&hr_dev->ib_dev, 6011 "failed to process cmd when querying CQ, ret = %d.\n", 6012 ret); 6013 goto err_mailbox; 6014 } 6015 6016 memcpy(buffer, context, sizeof(*context)); 6017 6018 err_mailbox: 6019 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6020 6021 return ret; 6022 } 6023 6024 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 6025 void *buffer) 6026 { 6027 struct hns_roce_v2_mpt_entry *context; 6028 struct hns_roce_cmd_mailbox *mailbox; 6029 int ret; 6030 6031 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6032 if (IS_ERR(mailbox)) 6033 return PTR_ERR(mailbox); 6034 6035 context = mailbox->buf; 6036 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 6037 key_to_hw_index(key)); 6038 if (ret) { 6039 ibdev_err(&hr_dev->ib_dev, 6040 "failed to process cmd when querying MPT, ret = %d.\n", 6041 ret); 6042 goto err_mailbox; 6043 } 6044 6045 memcpy(buffer, context, sizeof(*context)); 6046 6047 err_mailbox: 6048 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6049 6050 return ret; 6051 } 6052 6053 static void dump_aeqe_log(struct hns_roce_work *irq_work) 6054 { 6055 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6056 struct ib_device *ibdev = &hr_dev->ib_dev; 6057 6058 switch (irq_work->event_type) { 6059 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6060 ibdev_info(ibdev, "path migrated succeeded.\n"); 6061 break; 6062 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6063 ibdev_warn(ibdev, "path migration failed.\n"); 6064 break; 6065 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6066 break; 6067 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6068 ibdev_dbg(ibdev, "send queue drained.\n"); 6069 break; 6070 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6071 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 6072 irq_work->queue_num, irq_work->sub_type); 6073 break; 6074 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6075 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 6076 irq_work->queue_num); 6077 break; 6078 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6079 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 6080 irq_work->queue_num, irq_work->sub_type); 6081 break; 6082 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6083 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 6084 break; 6085 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6086 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 6087 break; 6088 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6089 ibdev_err(ibdev, "SRQ catas error.\n"); 6090 break; 6091 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6092 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 6093 break; 6094 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6095 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 6096 break; 6097 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6098 ibdev_warn(ibdev, "DB overflow.\n"); 6099 break; 6100 case HNS_ROCE_EVENT_TYPE_MB: 6101 break; 6102 case HNS_ROCE_EVENT_TYPE_FLR: 6103 ibdev_warn(ibdev, "function level reset.\n"); 6104 break; 6105 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6106 ibdev_err(ibdev, "xrc domain violation error.\n"); 6107 break; 6108 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6109 ibdev_err(ibdev, "invalid xrceth error.\n"); 6110 break; 6111 default: 6112 ibdev_info(ibdev, "Undefined event %d.\n", 6113 irq_work->event_type); 6114 break; 6115 } 6116 } 6117 6118 static void hns_roce_irq_work_handle(struct work_struct *work) 6119 { 6120 struct hns_roce_work *irq_work = 6121 container_of(work, struct hns_roce_work, work); 6122 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6123 int event_type = irq_work->event_type; 6124 u32 queue_num = irq_work->queue_num; 6125 6126 switch (event_type) { 6127 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6128 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6129 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6130 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6131 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6132 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6133 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6134 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6135 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6136 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6137 hns_roce_qp_event(hr_dev, queue_num, event_type); 6138 break; 6139 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6140 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6141 hns_roce_srq_event(hr_dev, queue_num, event_type); 6142 break; 6143 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6144 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6145 hns_roce_cq_event(hr_dev, queue_num, event_type); 6146 break; 6147 default: 6148 break; 6149 } 6150 6151 dump_aeqe_log(irq_work); 6152 6153 kfree(irq_work); 6154 } 6155 6156 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 6157 struct hns_roce_eq *eq, u32 queue_num) 6158 { 6159 struct hns_roce_work *irq_work; 6160 6161 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 6162 if (!irq_work) 6163 return; 6164 6165 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 6166 irq_work->hr_dev = hr_dev; 6167 irq_work->event_type = eq->event_type; 6168 irq_work->sub_type = eq->sub_type; 6169 irq_work->queue_num = queue_num; 6170 queue_work(hr_dev->irq_workq, &irq_work->work); 6171 } 6172 6173 static void update_eq_db(struct hns_roce_eq *eq) 6174 { 6175 struct hns_roce_dev *hr_dev = eq->hr_dev; 6176 struct hns_roce_v2_db eq_db = {}; 6177 6178 if (eq->type_flag == HNS_ROCE_AEQ) { 6179 hr_reg_write(&eq_db, EQ_DB_CMD, 6180 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6181 HNS_ROCE_EQ_DB_CMD_AEQ : 6182 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 6183 } else { 6184 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 6185 6186 hr_reg_write(&eq_db, EQ_DB_CMD, 6187 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6188 HNS_ROCE_EQ_DB_CMD_CEQ : 6189 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 6190 } 6191 6192 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 6193 6194 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 6195 } 6196 6197 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6198 { 6199 struct hns_roce_aeqe *aeqe; 6200 6201 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6202 (eq->cons_index & (eq->entries - 1)) * 6203 eq->eqe_size); 6204 6205 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6206 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6207 } 6208 6209 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6210 struct hns_roce_eq *eq) 6211 { 6212 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6213 irqreturn_t aeqe_found = IRQ_NONE; 6214 int num_aeqes = 0; 6215 int event_type; 6216 u32 queue_num; 6217 int sub_type; 6218 6219 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) { 6220 /* Make sure we read AEQ entry after we have checked the 6221 * ownership bit 6222 */ 6223 dma_rmb(); 6224 6225 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6226 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6227 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6228 6229 switch (event_type) { 6230 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6231 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6232 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6233 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6234 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6235 hns_roce_flush_cqe(hr_dev, queue_num); 6236 break; 6237 case HNS_ROCE_EVENT_TYPE_MB: 6238 hns_roce_cmd_event(hr_dev, 6239 le16_to_cpu(aeqe->event.cmd.token), 6240 aeqe->event.cmd.status, 6241 le64_to_cpu(aeqe->event.cmd.out_param)); 6242 break; 6243 default: 6244 break; 6245 } 6246 6247 eq->event_type = event_type; 6248 eq->sub_type = sub_type; 6249 ++eq->cons_index; 6250 aeqe_found = IRQ_HANDLED; 6251 6252 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6253 6254 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6255 6256 aeqe = next_aeqe_sw_v2(eq); 6257 ++num_aeqes; 6258 } 6259 6260 update_eq_db(eq); 6261 6262 return IRQ_RETVAL(aeqe_found); 6263 } 6264 6265 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6266 { 6267 struct hns_roce_ceqe *ceqe; 6268 6269 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6270 (eq->cons_index & (eq->entries - 1)) * 6271 eq->eqe_size); 6272 6273 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6274 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6275 } 6276 6277 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) 6278 { 6279 queue_work(system_bh_wq, &eq->work); 6280 6281 return IRQ_HANDLED; 6282 } 6283 6284 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6285 { 6286 struct hns_roce_eq *eq = eq_ptr; 6287 struct hns_roce_dev *hr_dev = eq->hr_dev; 6288 irqreturn_t int_work; 6289 6290 if (eq->type_flag == HNS_ROCE_CEQ) 6291 /* Completion event interrupt */ 6292 int_work = hns_roce_v2_ceq_int(eq); 6293 else 6294 /* Asynchronous event interrupt */ 6295 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6296 6297 return IRQ_RETVAL(int_work); 6298 } 6299 6300 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6301 u32 int_st) 6302 { 6303 struct pci_dev *pdev = hr_dev->pci_dev; 6304 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6305 const struct hnae3_ae_ops *ops = ae_dev->ops; 6306 enum hnae3_reset_type reset_type; 6307 irqreturn_t int_work = IRQ_NONE; 6308 u32 int_en; 6309 6310 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6311 6312 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6313 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6314 6315 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6316 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6317 6318 reset_type = hr_dev->is_vf ? 6319 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET; 6320 6321 /* Set reset level for reset_event() */ 6322 if (ops->set_default_reset_request) 6323 ops->set_default_reset_request(ae_dev, reset_type); 6324 if (ops->reset_event) 6325 ops->reset_event(pdev, NULL); 6326 6327 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6328 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6329 6330 int_work = IRQ_HANDLED; 6331 } else { 6332 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6333 } 6334 6335 return IRQ_RETVAL(int_work); 6336 } 6337 6338 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6339 struct fmea_ram_ecc *ecc_info) 6340 { 6341 struct hns_roce_cmq_desc desc; 6342 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6343 int ret; 6344 6345 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6346 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6347 if (ret) 6348 return ret; 6349 6350 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6351 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6352 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6353 6354 return 0; 6355 } 6356 6357 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6358 { 6359 struct hns_roce_cmq_desc desc; 6360 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6361 u32 addr_upper; 6362 u32 addr_low; 6363 int ret; 6364 6365 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6366 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6367 6368 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6369 if (ret) { 6370 dev_err(hr_dev->dev, 6371 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6372 return ret; 6373 } 6374 6375 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6376 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6377 6378 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6379 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6380 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6381 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6382 6383 return hns_roce_cmq_send(hr_dev, &desc, 1); 6384 } 6385 6386 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6387 { 6388 if (res_type == ECC_RESOURCE_QPC_TIMER || 6389 res_type == ECC_RESOURCE_CQC_TIMER || 6390 res_type == ECC_RESOURCE_SCCC) 6391 return le64_to_cpu(*data); 6392 6393 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT; 6394 } 6395 6396 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6397 u32 index) 6398 { 6399 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6400 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6401 struct hns_roce_cmd_mailbox *mailbox; 6402 u64 addr; 6403 int ret; 6404 6405 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6406 if (IS_ERR(mailbox)) 6407 return PTR_ERR(mailbox); 6408 6409 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6410 if (ret) { 6411 dev_err(hr_dev->dev, 6412 "failed to execute cmd to read fmea ram, ret = %d.\n", 6413 ret); 6414 goto out; 6415 } 6416 6417 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6418 6419 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6420 if (ret) 6421 dev_err(hr_dev->dev, 6422 "failed to execute cmd to write fmea ram, ret = %d.\n", 6423 ret); 6424 6425 out: 6426 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6427 return ret; 6428 } 6429 6430 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6431 struct fmea_ram_ecc *ecc_info) 6432 { 6433 u32 res_type = ecc_info->res_type; 6434 u32 index = ecc_info->index; 6435 int ret; 6436 6437 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6438 6439 if (res_type >= ECC_RESOURCE_COUNT) { 6440 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6441 res_type); 6442 return; 6443 } 6444 6445 if (res_type == ECC_RESOURCE_GMV) 6446 ret = fmea_recover_gmv(hr_dev, index); 6447 else 6448 ret = fmea_recover_others(hr_dev, res_type, index); 6449 if (ret) 6450 dev_err(hr_dev->dev, 6451 "failed to recover %s, index = %u, ret = %d.\n", 6452 fmea_ram_res[res_type].name, index, ret); 6453 } 6454 6455 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6456 { 6457 struct hns_roce_dev *hr_dev = 6458 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6459 struct fmea_ram_ecc ecc_info = {}; 6460 6461 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6462 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6463 return; 6464 } 6465 6466 if (!ecc_info.is_ecc_err) { 6467 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6468 return; 6469 } 6470 6471 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6472 } 6473 6474 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6475 { 6476 struct hns_roce_dev *hr_dev = dev_id; 6477 irqreturn_t int_work = IRQ_NONE; 6478 u32 int_st; 6479 6480 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6481 6482 if (int_st) { 6483 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6484 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6485 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6486 int_work = IRQ_HANDLED; 6487 } else { 6488 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6489 } 6490 6491 return IRQ_RETVAL(int_work); 6492 } 6493 6494 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6495 int eq_num, u32 enable_flag) 6496 { 6497 int i; 6498 6499 for (i = 0; i < eq_num; i++) 6500 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6501 i * EQ_REG_OFFSET, enable_flag); 6502 6503 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6504 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6505 } 6506 6507 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6508 { 6509 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6510 } 6511 6512 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6513 struct hns_roce_eq *eq) 6514 { 6515 struct device *dev = hr_dev->dev; 6516 int eqn = eq->eqn; 6517 int ret; 6518 u8 cmd; 6519 6520 if (eqn < hr_dev->caps.num_comp_vectors) 6521 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6522 else 6523 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6524 6525 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6526 if (ret) 6527 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6528 6529 free_eq_buf(hr_dev, eq); 6530 } 6531 6532 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6533 { 6534 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6535 eq->cons_index = 0; 6536 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6537 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6538 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6539 eq->shift = ilog2((unsigned int)eq->entries); 6540 } 6541 6542 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6543 void *mb_buf) 6544 { 6545 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6546 struct hns_roce_eq_context *eqc; 6547 u64 bt_ba = 0; 6548 int ret; 6549 6550 eqc = mb_buf; 6551 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6552 6553 init_eq_config(hr_dev, eq); 6554 6555 /* if not multi-hop, eqe buffer only use one trunk */ 6556 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6557 ARRAY_SIZE(eqe_ba)); 6558 if (ret) { 6559 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6560 return ret; 6561 } 6562 6563 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6564 6565 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6566 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6567 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6568 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6569 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6570 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6571 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6572 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6573 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6574 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6575 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6576 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6577 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6578 6579 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6580 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6581 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6582 eq->eq_period); 6583 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6584 } 6585 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6586 } 6587 6588 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6589 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6590 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6591 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6592 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6593 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6594 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6595 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6596 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6597 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6598 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6599 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6600 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6601 6602 return 0; 6603 } 6604 6605 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6606 { 6607 struct hns_roce_buf_attr buf_attr = {}; 6608 int err; 6609 6610 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6611 eq->hop_num = 0; 6612 else 6613 eq->hop_num = hr_dev->caps.eqe_hop_num; 6614 6615 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6616 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6617 buf_attr.region[0].hopnum = eq->hop_num; 6618 buf_attr.region_count = 1; 6619 6620 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6621 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6622 0); 6623 if (err) 6624 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6625 6626 return err; 6627 } 6628 6629 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6630 struct hns_roce_eq *eq, u8 eq_cmd) 6631 { 6632 struct hns_roce_cmd_mailbox *mailbox; 6633 int ret; 6634 6635 /* Allocate mailbox memory */ 6636 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6637 if (IS_ERR(mailbox)) 6638 return PTR_ERR(mailbox); 6639 6640 ret = alloc_eq_buf(hr_dev, eq); 6641 if (ret) 6642 goto free_cmd_mbox; 6643 6644 ret = config_eqc(hr_dev, eq, mailbox->buf); 6645 if (ret) 6646 goto err_cmd_mbox; 6647 6648 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6649 if (ret) { 6650 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6651 goto err_cmd_mbox; 6652 } 6653 6654 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6655 6656 return 0; 6657 6658 err_cmd_mbox: 6659 free_eq_buf(hr_dev, eq); 6660 6661 free_cmd_mbox: 6662 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6663 6664 return ret; 6665 } 6666 6667 static void hns_roce_ceq_work(struct work_struct *work) 6668 { 6669 struct hns_roce_eq *eq = from_work(eq, work, work); 6670 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6671 struct hns_roce_dev *hr_dev = eq->hr_dev; 6672 int ceqe_num = 0; 6673 u32 cqn; 6674 6675 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) { 6676 /* Make sure we read CEQ entry after we have checked the 6677 * ownership bit 6678 */ 6679 dma_rmb(); 6680 6681 cqn = hr_reg_read(ceqe, CEQE_CQN); 6682 6683 hns_roce_cq_completion(hr_dev, cqn); 6684 6685 ++eq->cons_index; 6686 ++ceqe_num; 6687 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6688 6689 ceqe = next_ceqe_sw_v2(eq); 6690 } 6691 6692 update_eq_db(eq); 6693 } 6694 6695 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6696 int comp_num, int aeq_num, int other_num) 6697 { 6698 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6699 int i, j; 6700 int ret; 6701 6702 for (i = 0; i < irq_num; i++) { 6703 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6704 GFP_KERNEL); 6705 if (!hr_dev->irq_names[i]) { 6706 ret = -ENOMEM; 6707 goto err_kzalloc_failed; 6708 } 6709 } 6710 6711 /* irq contains: abnormal + AEQ + CEQ */ 6712 for (j = 0; j < other_num; j++) 6713 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6714 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 6715 6716 for (j = other_num; j < (other_num + aeq_num); j++) 6717 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6718 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 6719 6720 for (j = (other_num + aeq_num); j < irq_num; j++) 6721 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6722 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 6723 j - other_num - aeq_num); 6724 6725 for (j = 0; j < irq_num; j++) { 6726 if (j < other_num) { 6727 ret = request_irq(hr_dev->irq[j], 6728 hns_roce_v2_msix_interrupt_abn, 6729 0, hr_dev->irq_names[j], hr_dev); 6730 } else if (j < (other_num + comp_num)) { 6731 INIT_WORK(&eq_table->eq[j - other_num].work, 6732 hns_roce_ceq_work); 6733 ret = request_irq(eq_table->eq[j - other_num].irq, 6734 hns_roce_v2_msix_interrupt_eq, 6735 0, hr_dev->irq_names[j + aeq_num], 6736 &eq_table->eq[j - other_num]); 6737 } else { 6738 ret = request_irq(eq_table->eq[j - other_num].irq, 6739 hns_roce_v2_msix_interrupt_eq, 6740 0, hr_dev->irq_names[j - comp_num], 6741 &eq_table->eq[j - other_num]); 6742 } 6743 6744 if (ret) { 6745 dev_err(hr_dev->dev, "request irq error!\n"); 6746 goto err_request_failed; 6747 } 6748 } 6749 6750 return 0; 6751 6752 err_request_failed: 6753 for (j -= 1; j >= 0; j--) { 6754 if (j < other_num) { 6755 free_irq(hr_dev->irq[j], hr_dev); 6756 continue; 6757 } 6758 free_irq(eq_table->eq[j - other_num].irq, 6759 &eq_table->eq[j - other_num]); 6760 if (j < other_num + comp_num) 6761 cancel_work_sync(&eq_table->eq[j - other_num].work); 6762 } 6763 6764 err_kzalloc_failed: 6765 for (i -= 1; i >= 0; i--) 6766 kfree(hr_dev->irq_names[i]); 6767 6768 return ret; 6769 } 6770 6771 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6772 { 6773 int irq_num; 6774 int eq_num; 6775 int i; 6776 6777 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6778 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6779 6780 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6781 free_irq(hr_dev->irq[i], hr_dev); 6782 6783 for (i = 0; i < eq_num; i++) { 6784 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6785 if (i < hr_dev->caps.num_comp_vectors) 6786 cancel_work_sync(&hr_dev->eq_table.eq[i].work); 6787 } 6788 6789 for (i = 0; i < irq_num; i++) 6790 kfree(hr_dev->irq_names[i]); 6791 } 6792 6793 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6794 { 6795 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6796 struct device *dev = hr_dev->dev; 6797 struct hns_roce_eq *eq; 6798 int other_num; 6799 int comp_num; 6800 int aeq_num; 6801 int irq_num; 6802 int eq_num; 6803 u8 eq_cmd; 6804 int ret; 6805 int i; 6806 6807 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET) 6808 return -EINVAL; 6809 6810 other_num = hr_dev->caps.num_other_vectors; 6811 comp_num = hr_dev->caps.num_comp_vectors; 6812 aeq_num = hr_dev->caps.num_aeq_vectors; 6813 6814 eq_num = comp_num + aeq_num; 6815 irq_num = eq_num + other_num; 6816 6817 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6818 if (!eq_table->eq) 6819 return -ENOMEM; 6820 6821 /* create eq */ 6822 for (i = 0; i < eq_num; i++) { 6823 eq = &eq_table->eq[i]; 6824 eq->hr_dev = hr_dev; 6825 eq->eqn = i; 6826 if (i < comp_num) { 6827 /* CEQ */ 6828 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6829 eq->type_flag = HNS_ROCE_CEQ; 6830 eq->entries = hr_dev->caps.ceqe_depth; 6831 eq->eqe_size = hr_dev->caps.ceqe_size; 6832 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6833 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6834 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6835 } else { 6836 /* AEQ */ 6837 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6838 eq->type_flag = HNS_ROCE_AEQ; 6839 eq->entries = hr_dev->caps.aeqe_depth; 6840 eq->eqe_size = hr_dev->caps.aeqe_size; 6841 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6842 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6843 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6844 } 6845 6846 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6847 if (ret) { 6848 dev_err(dev, "failed to create eq.\n"); 6849 goto err_create_eq_fail; 6850 } 6851 } 6852 6853 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6854 6855 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6856 if (!hr_dev->irq_workq) { 6857 dev_err(dev, "failed to create irq workqueue.\n"); 6858 ret = -ENOMEM; 6859 goto err_create_eq_fail; 6860 } 6861 6862 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6863 other_num); 6864 if (ret) { 6865 dev_err(dev, "failed to request irq.\n"); 6866 goto err_request_irq_fail; 6867 } 6868 6869 /* enable irq */ 6870 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6871 6872 return 0; 6873 6874 err_request_irq_fail: 6875 destroy_workqueue(hr_dev->irq_workq); 6876 6877 err_create_eq_fail: 6878 for (i -= 1; i >= 0; i--) 6879 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6880 kfree(eq_table->eq); 6881 6882 return ret; 6883 } 6884 6885 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6886 { 6887 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6888 int eq_num; 6889 int i; 6890 6891 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6892 6893 /* Disable irq */ 6894 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6895 6896 __hns_roce_free_irq(hr_dev); 6897 destroy_workqueue(hr_dev->irq_workq); 6898 6899 for (i = 0; i < eq_num; i++) 6900 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6901 6902 kfree(eq_table->eq); 6903 } 6904 6905 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6906 .destroy_qp = hns_roce_v2_destroy_qp, 6907 .modify_cq = hns_roce_v2_modify_cq, 6908 .poll_cq = hns_roce_v2_poll_cq, 6909 .post_recv = hns_roce_v2_post_recv, 6910 .post_send = hns_roce_v2_post_send, 6911 .query_qp = hns_roce_v2_query_qp, 6912 .req_notify_cq = hns_roce_v2_req_notify_cq, 6913 }; 6914 6915 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6916 .modify_srq = hns_roce_v2_modify_srq, 6917 .post_srq_recv = hns_roce_v2_post_srq_recv, 6918 .query_srq = hns_roce_v2_query_srq, 6919 }; 6920 6921 static const struct hns_roce_hw hns_roce_hw_v2 = { 6922 .cmq_init = hns_roce_v2_cmq_init, 6923 .cmq_exit = hns_roce_v2_cmq_exit, 6924 .hw_profile = hns_roce_v2_profile, 6925 .hw_init = hns_roce_v2_init, 6926 .hw_exit = hns_roce_v2_exit, 6927 .post_mbox = v2_post_mbox, 6928 .poll_mbox_done = v2_poll_mbox_done, 6929 .chk_mbox_avail = v2_chk_mbox_is_avail, 6930 .set_gid = hns_roce_v2_set_gid, 6931 .set_mac = hns_roce_v2_set_mac, 6932 .write_mtpt = hns_roce_v2_write_mtpt, 6933 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6934 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6935 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6936 .write_cqc = hns_roce_v2_write_cqc, 6937 .set_hem = hns_roce_v2_set_hem, 6938 .clear_hem = hns_roce_v2_clear_hem, 6939 .modify_qp = hns_roce_v2_modify_qp, 6940 .dereg_mr = hns_roce_v2_dereg_mr, 6941 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6942 .init_eq = hns_roce_v2_init_eq_table, 6943 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6944 .write_srqc = hns_roce_v2_write_srqc, 6945 .query_cqc = hns_roce_v2_query_cqc, 6946 .query_qpc = hns_roce_v2_query_qpc, 6947 .query_mpt = hns_roce_v2_query_mpt, 6948 .query_srqc = hns_roce_v2_query_srqc, 6949 .query_sccc = hns_roce_v2_query_sccc, 6950 .query_hw_counter = hns_roce_hw_v2_query_counter, 6951 .get_dscp = hns_roce_hw_v2_get_dscp, 6952 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6953 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6954 }; 6955 6956 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6957 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6958 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6959 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6960 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6961 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6962 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6963 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6964 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6965 /* required last entry */ 6966 {0, } 6967 }; 6968 6969 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6970 6971 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6972 struct hnae3_handle *handle) 6973 { 6974 struct hns_roce_v2_priv *priv = hr_dev->priv; 6975 const struct pci_device_id *id; 6976 int i; 6977 6978 hr_dev->pci_dev = handle->pdev; 6979 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6980 hr_dev->is_vf = id->driver_data; 6981 hr_dev->dev = &handle->pdev->dev; 6982 hr_dev->hw = &hns_roce_hw_v2; 6983 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6984 hr_dev->odb_offset = hr_dev->sdb_offset; 6985 6986 /* Get info from NIC driver. */ 6987 hr_dev->reg_base = handle->rinfo.roce_io_base; 6988 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6989 hr_dev->caps.num_ports = 1; 6990 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6991 hr_dev->iboe.phy_port[0] = 0; 6992 6993 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6994 hr_dev->iboe.netdevs[0]->dev_addr); 6995 6996 for (i = 0; i < handle->rinfo.num_vectors; i++) 6997 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6998 i + handle->rinfo.base_vector); 6999 7000 /* cmd issue mode: 0 is poll, 1 is event */ 7001 hr_dev->cmd_mod = 1; 7002 hr_dev->loop_idc = 0; 7003 7004 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 7005 priv->handle = handle; 7006 } 7007 7008 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7009 { 7010 struct hns_roce_dev *hr_dev; 7011 int ret; 7012 7013 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 7014 if (!hr_dev) 7015 return -ENOMEM; 7016 7017 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 7018 if (!hr_dev->priv) { 7019 ret = -ENOMEM; 7020 goto error_failed_kzalloc; 7021 } 7022 7023 hns_roce_hw_v2_get_cfg(hr_dev, handle); 7024 7025 ret = hns_roce_init(hr_dev); 7026 if (ret) { 7027 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 7028 goto error_failed_roce_init; 7029 } 7030 7031 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 7032 ret = free_mr_init(hr_dev); 7033 if (ret) { 7034 dev_err(hr_dev->dev, "failed to init free mr!\n"); 7035 goto error_failed_free_mr_init; 7036 } 7037 } 7038 7039 handle->priv = hr_dev; 7040 7041 return 0; 7042 7043 error_failed_free_mr_init: 7044 hns_roce_exit(hr_dev); 7045 7046 error_failed_roce_init: 7047 kfree(hr_dev->priv); 7048 7049 error_failed_kzalloc: 7050 ib_dealloc_device(&hr_dev->ib_dev); 7051 7052 return ret; 7053 } 7054 7055 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7056 bool reset) 7057 { 7058 struct hns_roce_dev *hr_dev = handle->priv; 7059 7060 if (!hr_dev) 7061 return; 7062 7063 handle->priv = NULL; 7064 7065 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 7066 hns_roce_handle_device_err(hr_dev); 7067 7068 hns_roce_exit(hr_dev); 7069 kfree(hr_dev->priv); 7070 ib_dealloc_device(&hr_dev->ib_dev); 7071 } 7072 7073 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7074 { 7075 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 7076 const struct pci_device_id *id; 7077 struct device *dev = &handle->pdev->dev; 7078 int ret; 7079 7080 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 7081 7082 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 7083 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7084 goto reset_chk_err; 7085 } 7086 7087 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 7088 if (!id) 7089 return 0; 7090 7091 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 7092 return 0; 7093 7094 ret = __hns_roce_hw_v2_init_instance(handle); 7095 if (ret) { 7096 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7097 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 7098 if (ops->ae_dev_resetting(handle) || 7099 ops->get_hw_reset_stat(handle)) 7100 goto reset_chk_err; 7101 else 7102 return ret; 7103 } 7104 7105 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 7106 7107 return 0; 7108 7109 reset_chk_err: 7110 dev_err(dev, "Device is busy in resetting state.\n" 7111 "please retry later.\n"); 7112 7113 return -EBUSY; 7114 } 7115 7116 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7117 bool reset) 7118 { 7119 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7120 return; 7121 7122 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 7123 7124 __hns_roce_hw_v2_uninit_instance(handle, reset); 7125 7126 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7127 } 7128 7129 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 7130 { 7131 struct hns_roce_dev *hr_dev; 7132 7133 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 7134 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7135 return 0; 7136 } 7137 7138 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 7139 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7140 7141 hr_dev = handle->priv; 7142 if (!hr_dev) 7143 return 0; 7144 7145 hr_dev->active = false; 7146 hr_dev->dis_db = true; 7147 7148 rdma_user_mmap_disassociate(&hr_dev->ib_dev); 7149 7150 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 7151 7152 return 0; 7153 } 7154 7155 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 7156 { 7157 struct device *dev = &handle->pdev->dev; 7158 int ret; 7159 7160 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 7161 &handle->rinfo.state)) { 7162 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7163 return 0; 7164 } 7165 7166 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 7167 7168 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 7169 ret = __hns_roce_hw_v2_init_instance(handle); 7170 if (ret) { 7171 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 7172 * callback function, RoCE Engine reinitialize. If RoCE reinit 7173 * failed, we should inform NIC driver. 7174 */ 7175 handle->priv = NULL; 7176 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 7177 } else { 7178 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7179 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 7180 } 7181 7182 return ret; 7183 } 7184 7185 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 7186 { 7187 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 7188 return 0; 7189 7190 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 7191 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 7192 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 7193 __hns_roce_hw_v2_uninit_instance(handle, false); 7194 7195 return 0; 7196 } 7197 7198 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 7199 enum hnae3_reset_notify_type type) 7200 { 7201 int ret = 0; 7202 7203 switch (type) { 7204 case HNAE3_DOWN_CLIENT: 7205 ret = hns_roce_hw_v2_reset_notify_down(handle); 7206 break; 7207 case HNAE3_INIT_CLIENT: 7208 ret = hns_roce_hw_v2_reset_notify_init(handle); 7209 break; 7210 case HNAE3_UNINIT_CLIENT: 7211 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 7212 break; 7213 default: 7214 break; 7215 } 7216 7217 return ret; 7218 } 7219 7220 static void hns_roce_hw_v2_link_status_change(struct hnae3_handle *handle, 7221 bool linkup) 7222 { 7223 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 7224 struct net_device *netdev = handle->rinfo.netdev; 7225 7226 if (linkup || !hr_dev) 7227 return; 7228 7229 ib_dispatch_port_state_event(&hr_dev->ib_dev, netdev); 7230 } 7231 7232 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7233 .init_instance = hns_roce_hw_v2_init_instance, 7234 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7235 .link_status_change = hns_roce_hw_v2_link_status_change, 7236 .reset_notify = hns_roce_hw_v2_reset_notify, 7237 }; 7238 7239 static struct hnae3_client hns_roce_hw_v2_client = { 7240 .name = "hns_roce_hw_v2", 7241 .type = HNAE3_CLIENT_ROCE, 7242 .ops = &hns_roce_hw_v2_ops, 7243 }; 7244 7245 static int __init hns_roce_hw_v2_init(void) 7246 { 7247 hns_roce_init_debugfs(); 7248 return hnae3_register_client(&hns_roce_hw_v2_client); 7249 } 7250 7251 static void __exit hns_roce_hw_v2_exit(void) 7252 { 7253 hnae3_unregister_client(&hns_roce_hw_v2_client); 7254 hns_roce_cleanup_debugfs(); 7255 } 7256 7257 module_init(hns_roce_hw_v2_init); 7258 module_exit(hns_roce_hw_v2_exit); 7259 7260 MODULE_LICENSE("Dual BSD/GPL"); 7261 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7262 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7263 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7264 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7265