1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 #include "hns_roce_debugfs.h" 39 40 #define PCI_REVISION_ID_HIP08 0x21 41 #define PCI_REVISION_ID_HIP09 0x30 42 43 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 44 45 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 46 47 #define BA_BYTE_LEN 8 48 49 #define HNS_ROCE_MIN_CQE_NUM 0x40 50 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 51 52 #define HNS_ROCE_MAX_IRQ_NUM 128 53 54 #define HNS_ROCE_SGE_IN_WQE 2 55 #define HNS_ROCE_SGE_SHIFT 4 56 57 #define EQ_ENABLE 1 58 #define EQ_DISABLE 0 59 60 #define HNS_ROCE_CEQ 0 61 #define HNS_ROCE_AEQ 1 62 63 #define HNS_ROCE_CEQE_SIZE 0x4 64 #define HNS_ROCE_AEQE_SIZE 0x10 65 66 #define HNS_ROCE_V3_EQE_SIZE 0x40 67 68 #define HNS_ROCE_V2_CQE_SIZE 32 69 #define HNS_ROCE_V3_CQE_SIZE 64 70 71 #define HNS_ROCE_V2_QPC_SZ 256 72 #define HNS_ROCE_V3_QPC_SZ 512 73 74 #define HNS_ROCE_MAX_PORTS 6 75 #define HNS_ROCE_GID_SIZE 16 76 #define HNS_ROCE_SGE_SIZE 16 77 #define HNS_ROCE_DWQE_SIZE 65536 78 79 #define HNS_ROCE_HOP_NUM_0 0xff 80 81 #define MR_TYPE_MR 0x00 82 #define MR_TYPE_FRMR 0x01 83 #define MR_TYPE_DMA 0x03 84 85 #define HNS_ROCE_FRMR_MAX_PA 512 86 #define HNS_ROCE_FRMR_ALIGN_SIZE 128 87 88 #define PKEY_ID 0xffff 89 #define NODE_DESC_SIZE 64 90 #define DB_REG_OFFSET 0x1000 91 92 /* Configure to HW for PAGE_SIZE larger than 4KB */ 93 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 94 95 #define ATOMIC_WR_LEN 8 96 97 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 98 #define SRQ_DB_REG 0x230 99 100 #define HNS_ROCE_QP_BANK_NUM 8 101 #define HNS_ROCE_CQ_BANK_NUM 4 102 103 #define CQ_BANKID_SHIFT 2 104 #define CQ_BANKID_MASK GENMASK(1, 0) 105 106 #define HNS_ROCE_MAX_CQ_COUNT 0xFFFF 107 #define HNS_ROCE_MAX_CQ_PERIOD 0xFFFF 108 109 enum { 110 SERV_TYPE_RC, 111 SERV_TYPE_UC, 112 SERV_TYPE_RD, 113 SERV_TYPE_UD, 114 SERV_TYPE_XRC = 5, 115 }; 116 117 enum hns_roce_event { 118 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 119 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 120 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 121 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 122 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 123 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 124 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 125 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 126 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 127 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 128 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 129 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 130 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 131 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 132 /* 0x10 and 0x11 is unused in currently application case */ 133 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 134 HNS_ROCE_EVENT_TYPE_MB = 0x13, 135 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 136 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 137 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 138 }; 139 140 enum { 141 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 142 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 143 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 144 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 145 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 146 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 147 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 148 HNS_ROCE_CAP_FLAG_MW = BIT(7), 149 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 150 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 151 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 152 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), 153 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 154 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 155 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 156 HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB = BIT(22), 157 }; 158 159 #define HNS_ROCE_DB_TYPE_COUNT 2 160 #define HNS_ROCE_DB_UNIT_SIZE 4 161 162 enum { 163 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 164 }; 165 166 enum hns_roce_reset_stage { 167 HNS_ROCE_STATE_NON_RST, 168 HNS_ROCE_STATE_RST_BEF_DOWN, 169 HNS_ROCE_STATE_RST_DOWN, 170 HNS_ROCE_STATE_RST_UNINIT, 171 HNS_ROCE_STATE_RST_INIT, 172 HNS_ROCE_STATE_RST_INITED, 173 }; 174 175 enum hns_roce_instance_state { 176 HNS_ROCE_STATE_NON_INIT, 177 HNS_ROCE_STATE_INIT, 178 HNS_ROCE_STATE_INITED, 179 HNS_ROCE_STATE_UNINIT, 180 }; 181 182 enum { 183 HNS_ROCE_RST_DIRECT_RETURN = 0, 184 }; 185 186 #define HNS_ROCE_CMD_SUCCESS 1 187 188 #define HNS_ROCE_MAX_HOP_NUM 3 189 /* The minimum page size is 4K for hardware */ 190 #define HNS_HW_PAGE_SHIFT 12 191 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 192 193 #define HNS_HW_MAX_PAGE_SHIFT 27 194 #define HNS_HW_MAX_PAGE_SIZE (1 << HNS_HW_MAX_PAGE_SHIFT) 195 196 struct hns_roce_uar { 197 u64 pfn; 198 unsigned long index; 199 unsigned long logic_idx; 200 }; 201 202 enum hns_roce_mmap_type { 203 HNS_ROCE_MMAP_TYPE_DB = 1, 204 HNS_ROCE_MMAP_TYPE_DWQE, 205 }; 206 207 struct hns_user_mmap_entry { 208 struct rdma_user_mmap_entry rdma_entry; 209 enum hns_roce_mmap_type mmap_type; 210 u64 address; 211 }; 212 213 struct hns_roce_ucontext { 214 struct ib_ucontext ibucontext; 215 struct hns_roce_uar uar; 216 struct list_head page_list; 217 struct mutex page_mutex; 218 struct hns_user_mmap_entry *db_mmap_entry; 219 u32 config; 220 }; 221 222 struct hns_roce_pd { 223 struct ib_pd ibpd; 224 unsigned long pdn; 225 }; 226 227 struct hns_roce_xrcd { 228 struct ib_xrcd ibxrcd; 229 u32 xrcdn; 230 }; 231 232 struct hns_roce_bitmap { 233 /* Bitmap Traversal last a bit which is 1 */ 234 unsigned long last; 235 unsigned long top; 236 unsigned long max; 237 unsigned long reserved_top; 238 unsigned long mask; 239 spinlock_t lock; 240 unsigned long *table; 241 }; 242 243 struct hns_roce_ida { 244 struct ida ida; 245 u32 min; /* Lowest ID to allocate. */ 246 u32 max; /* Highest ID to allocate. */ 247 }; 248 249 /* For Hardware Entry Memory */ 250 struct hns_roce_hem_table { 251 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 252 u32 type; 253 /* HEM array elment num */ 254 unsigned long num_hem; 255 /* Single obj size */ 256 unsigned long obj_size; 257 unsigned long table_chunk_size; 258 struct mutex mutex; 259 struct hns_roce_hem **hem; 260 u64 **bt_l1; 261 dma_addr_t *bt_l1_dma_addr; 262 u64 **bt_l0; 263 dma_addr_t *bt_l0_dma_addr; 264 }; 265 266 struct hns_roce_buf_region { 267 u32 offset; /* page offset */ 268 u32 count; /* page count */ 269 int hopnum; /* addressing hop num */ 270 }; 271 272 #define HNS_ROCE_MAX_BT_REGION 3 273 #define HNS_ROCE_MAX_BT_LEVEL 3 274 struct hns_roce_hem_list { 275 struct list_head root_bt; 276 /* link all bt dma mem by hop config */ 277 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 278 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 279 dma_addr_t root_ba; /* pointer to the root ba table */ 280 }; 281 282 enum mtr_type { 283 MTR_DEFAULT = 0, 284 MTR_PBL, 285 }; 286 287 struct hns_roce_buf_attr { 288 struct { 289 size_t size; /* region size */ 290 int hopnum; /* multi-hop addressing hop num */ 291 } region[HNS_ROCE_MAX_BT_REGION]; 292 unsigned int region_count; /* valid region count */ 293 unsigned int page_shift; /* buffer page shift */ 294 unsigned int user_access; /* umem access flag */ 295 u64 iova; 296 enum mtr_type type; 297 bool mtt_only; /* only alloc buffer-required MTT memory */ 298 bool adaptive; /* adaptive for page_shift and hopnum */ 299 }; 300 301 struct hns_roce_hem_cfg { 302 dma_addr_t root_ba; /* root BA table's address */ 303 bool is_direct; /* addressing without BA table */ 304 unsigned int ba_pg_shift; /* BA table page shift */ 305 unsigned int buf_pg_shift; /* buffer page shift */ 306 unsigned int buf_pg_count; /* buffer page count */ 307 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 308 unsigned int region_count; 309 }; 310 311 /* memory translate region */ 312 struct hns_roce_mtr { 313 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 314 struct ib_umem *umem; /* user space buffer */ 315 struct hns_roce_buf *kmem; /* kernel space buffer */ 316 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 317 }; 318 319 struct hns_roce_mr { 320 struct ib_mr ibmr; 321 u64 iova; /* MR's virtual original addr */ 322 u64 size; /* Address range of MR */ 323 u32 key; /* Key of MR */ 324 u32 pd; /* PD num of MR */ 325 u32 access; /* Access permission of MR */ 326 int enabled; /* MR's active status */ 327 int type; /* MR's register type */ 328 u32 pbl_hop_num; /* multi-hop number */ 329 struct hns_roce_mtr pbl_mtr; 330 u32 npages; 331 dma_addr_t *page_list; 332 }; 333 334 struct hns_roce_mr_table { 335 struct hns_roce_ida mtpt_ida; 336 struct hns_roce_hem_table mtpt_table; 337 }; 338 339 struct hns_roce_wq { 340 u64 *wrid; /* Work request ID */ 341 spinlock_t lock; 342 u32 wqe_cnt; /* WQE num */ 343 u32 max_gs; 344 u32 rsv_sge; 345 u32 offset; 346 u32 wqe_shift; /* WQE size */ 347 u32 head; 348 u32 tail; 349 void __iomem *db_reg; 350 u32 ext_sge_cnt; 351 }; 352 353 struct hns_roce_sge { 354 unsigned int sge_cnt; /* SGE num */ 355 u32 offset; 356 u32 sge_shift; /* SGE size */ 357 }; 358 359 struct hns_roce_buf_list { 360 void *buf; 361 dma_addr_t map; 362 }; 363 364 /* 365 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 366 * dma address range. 367 * 368 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 369 * 370 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 371 * the allocated size is smaller than the required size. 372 */ 373 enum { 374 HNS_ROCE_BUF_DIRECT = BIT(0), 375 HNS_ROCE_BUF_NOSLEEP = BIT(1), 376 HNS_ROCE_BUF_NOFAIL = BIT(2), 377 }; 378 379 struct hns_roce_buf { 380 struct hns_roce_buf_list *trunk_list; 381 u32 ntrunks; 382 u32 npages; 383 unsigned int trunk_shift; 384 unsigned int page_shift; 385 }; 386 387 struct hns_roce_db_pgdir { 388 struct list_head list; 389 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 390 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 391 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 392 u32 *page; 393 dma_addr_t db_dma; 394 }; 395 396 struct hns_roce_user_db_page { 397 struct list_head list; 398 struct ib_umem *umem; 399 unsigned long user_virt; 400 refcount_t refcount; 401 }; 402 403 struct hns_roce_db { 404 u32 *db_record; 405 union { 406 struct hns_roce_db_pgdir *pgdir; 407 struct hns_roce_user_db_page *user_page; 408 } u; 409 dma_addr_t dma; 410 void *virt_addr; 411 unsigned long index; 412 unsigned long order; 413 }; 414 415 struct hns_roce_cq { 416 struct ib_cq ib_cq; 417 struct hns_roce_mtr mtr; 418 struct hns_roce_db db; 419 u32 flags; 420 spinlock_t lock; 421 u32 cq_depth; 422 u32 cons_index; 423 u32 *set_ci_db; 424 void __iomem *db_reg; 425 int arm_sn; 426 int cqe_size; 427 unsigned long cqn; 428 u32 vector; 429 refcount_t refcount; 430 struct completion free; 431 struct list_head sq_list; /* all qps on this send cq */ 432 struct list_head rq_list; /* all qps on this recv cq */ 433 int is_armed; /* cq is armed */ 434 struct list_head node; /* all armed cqs are on a list */ 435 }; 436 437 struct hns_roce_idx_que { 438 struct hns_roce_mtr mtr; 439 u32 entry_shift; 440 unsigned long *bitmap; 441 u32 head; 442 u32 tail; 443 }; 444 445 struct hns_roce_srq { 446 struct ib_srq ibsrq; 447 unsigned long srqn; 448 u32 wqe_cnt; 449 int max_gs; 450 u32 rsv_sge; 451 u32 wqe_shift; 452 u32 cqn; 453 u32 xrcdn; 454 void __iomem *db_reg; 455 456 refcount_t refcount; 457 struct completion free; 458 459 struct hns_roce_mtr buf_mtr; 460 461 u64 *wrid; 462 struct hns_roce_idx_que idx_que; 463 spinlock_t lock; 464 struct mutex mutex; 465 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 466 struct hns_roce_db rdb; 467 u32 cap_flags; 468 }; 469 470 struct hns_roce_uar_table { 471 struct hns_roce_bitmap bitmap; 472 }; 473 474 struct hns_roce_bank { 475 struct ida ida; 476 u32 inuse; /* Number of IDs allocated */ 477 u32 min; /* Lowest ID to allocate. */ 478 u32 max; /* Highest ID to allocate. */ 479 u32 next; /* Next ID to allocate. */ 480 }; 481 482 struct hns_roce_qp_table { 483 struct hns_roce_hem_table qp_table; 484 struct hns_roce_hem_table irrl_table; 485 struct hns_roce_hem_table trrl_table; 486 struct hns_roce_hem_table sccc_table; 487 struct mutex scc_mutex; 488 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 489 struct mutex bank_mutex; 490 struct xarray dip_xa; 491 }; 492 493 struct hns_roce_cq_table { 494 struct xarray array; 495 struct hns_roce_hem_table table; 496 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 497 struct mutex bank_mutex; 498 }; 499 500 struct hns_roce_srq_table { 501 struct hns_roce_ida srq_ida; 502 struct xarray xa; 503 struct hns_roce_hem_table table; 504 }; 505 506 struct hns_roce_av { 507 u8 port; 508 u8 gid_index; 509 u8 stat_rate; 510 u8 hop_limit; 511 u32 flowlabel; 512 u16 udp_sport; 513 u8 sl; 514 u8 tclass; 515 u8 dgid[HNS_ROCE_GID_SIZE]; 516 u8 mac[ETH_ALEN]; 517 u16 vlan_id; 518 u8 vlan_en; 519 }; 520 521 struct hns_roce_ah { 522 struct ib_ah ibah; 523 struct hns_roce_av av; 524 }; 525 526 struct hns_roce_cmd_context { 527 struct completion done; 528 int result; 529 int next; 530 u64 out_param; 531 u16 token; 532 u16 busy; 533 }; 534 535 enum hns_roce_cmdq_state { 536 HNS_ROCE_CMDQ_STATE_NORMAL, 537 HNS_ROCE_CMDQ_STATE_FATAL_ERR, 538 }; 539 540 struct hns_roce_cmdq { 541 struct dma_pool *pool; 542 struct semaphore poll_sem; 543 /* 544 * Event mode: cmd register mutex protection, 545 * ensure to not exceed max_cmds and user use limit region 546 */ 547 struct semaphore event_sem; 548 int max_cmds; 549 spinlock_t context_lock; 550 int free_head; 551 struct hns_roce_cmd_context *context; 552 /* 553 * Process whether use event mode, init default non-zero 554 * After the event queue of cmd event ready, 555 * can switch into event mode 556 * close device, switch into poll mode(non event mode) 557 */ 558 u8 use_events; 559 enum hns_roce_cmdq_state state; 560 }; 561 562 struct hns_roce_cmd_mailbox { 563 void *buf; 564 dma_addr_t dma; 565 }; 566 567 struct hns_roce_mbox_msg { 568 u64 in_param; 569 u64 out_param; 570 u8 cmd; 571 u32 tag; 572 u16 token; 573 u8 event_en; 574 }; 575 576 struct hns_roce_dev; 577 578 enum { 579 HNS_ROCE_FLUSH_FLAG = 0, 580 HNS_ROCE_STOP_FLUSH_FLAG = 1, 581 }; 582 583 struct hns_roce_work { 584 struct hns_roce_dev *hr_dev; 585 struct work_struct work; 586 int event_type; 587 int sub_type; 588 u32 queue_num; 589 }; 590 591 enum hns_roce_cong_type { 592 CONG_TYPE_DCQCN, 593 CONG_TYPE_LDCP, 594 CONG_TYPE_HC3, 595 CONG_TYPE_DIP, 596 }; 597 598 struct hns_roce_qp { 599 struct ib_qp ibqp; 600 struct hns_roce_wq rq; 601 struct hns_roce_db rdb; 602 struct hns_roce_db sdb; 603 unsigned long en_flags; 604 enum ib_sig_type sq_signal_bits; 605 struct hns_roce_wq sq; 606 607 struct hns_roce_mtr mtr; 608 609 u32 buff_size; 610 struct mutex mutex; 611 u8 port; 612 u8 phy_port; 613 u8 sl; 614 u8 resp_depth; 615 u8 state; 616 u32 atomic_rd_en; 617 u32 qkey; 618 void (*event)(struct hns_roce_qp *qp, 619 enum hns_roce_event event_type); 620 unsigned long qpn; 621 622 u32 xrcdn; 623 624 refcount_t refcount; 625 struct completion free; 626 627 struct hns_roce_sge sge; 628 u32 next_sge; 629 enum ib_mtu path_mtu; 630 u32 max_inline_data; 631 u8 free_mr_en; 632 633 /* 0: flush needed, 1: unneeded */ 634 unsigned long flush_flag; 635 struct hns_roce_work flush_work; 636 struct list_head node; /* all qps are on a list */ 637 struct list_head rq_node; /* all recv qps are on a list */ 638 struct list_head sq_node; /* all send qps are on a list */ 639 struct hns_user_mmap_entry *dwqe_mmap_entry; 640 u32 config; 641 enum hns_roce_cong_type cong_type; 642 u8 tc_mode; 643 u8 priority; 644 spinlock_t flush_lock; 645 struct hns_roce_dip *dip; 646 }; 647 648 struct hns_roce_ib_iboe { 649 spinlock_t lock; 650 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 651 struct notifier_block nb; 652 u8 phy_port[HNS_ROCE_MAX_PORTS]; 653 }; 654 655 struct hns_roce_ceqe { 656 __le32 comp; 657 __le32 rsv[15]; 658 }; 659 660 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l) 661 662 #define CEQE_CQN CEQE_FIELD_LOC(23, 0) 663 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31) 664 665 struct hns_roce_aeqe { 666 __le32 asyn; 667 union { 668 struct { 669 __le32 num; 670 u32 rsv0; 671 u32 rsv1; 672 } queue_event; 673 674 struct { 675 __le64 out_param; 676 __le16 token; 677 u8 status; 678 u8 rsv0; 679 } __packed cmd; 680 } event; 681 __le32 rsv[12]; 682 }; 683 684 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l) 685 686 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0) 687 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8) 688 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31) 689 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32) 690 691 struct hns_roce_eq { 692 struct hns_roce_dev *hr_dev; 693 void __iomem *db_reg; 694 695 int type_flag; /* Aeq:1 ceq:0 */ 696 int eqn; 697 u32 entries; 698 int eqe_size; 699 int irq; 700 u32 cons_index; 701 int over_ignore; 702 int coalesce; 703 int arm_st; 704 int hop_num; 705 struct hns_roce_mtr mtr; 706 u16 eq_max_cnt; 707 u32 eq_period; 708 int shift; 709 int event_type; 710 int sub_type; 711 struct work_struct work; 712 }; 713 714 struct hns_roce_eq_table { 715 struct hns_roce_eq *eq; 716 }; 717 718 struct hns_roce_caps { 719 u64 fw_ver; 720 u8 num_ports; 721 int gid_table_len[HNS_ROCE_MAX_PORTS]; 722 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 723 int local_ca_ack_delay; 724 int num_uars; 725 u32 phy_num_uars; 726 u32 max_sq_sg; 727 u32 max_sq_inline; 728 u32 max_rq_sg; 729 u32 rsv0; 730 u32 num_qps; 731 u32 reserved_qps; 732 u32 num_srqs; 733 u32 max_wqes; 734 u32 max_srq_wrs; 735 u32 max_srq_sges; 736 u32 max_sq_desc_sz; 737 u32 max_rq_desc_sz; 738 u32 rsv2; 739 int max_qp_init_rdma; 740 int max_qp_dest_rdma; 741 u32 num_cqs; 742 u32 max_cqes; 743 u32 min_cqes; 744 u32 min_wqes; 745 u32 reserved_cqs; 746 u32 reserved_srqs; 747 int num_aeq_vectors; 748 int num_comp_vectors; 749 int num_other_vectors; 750 u32 num_mtpts; 751 u32 rsv1; 752 u32 num_srqwqe_segs; 753 u32 num_idx_segs; 754 int reserved_mrws; 755 int reserved_uars; 756 int num_pds; 757 int reserved_pds; 758 u32 num_xrcds; 759 u32 reserved_xrcds; 760 u32 mtt_entry_sz; 761 u32 cqe_sz; 762 u32 page_size_cap; 763 u32 reserved_lkey; 764 int mtpt_entry_sz; 765 int qpc_sz; 766 int irrl_entry_sz; 767 int trrl_entry_sz; 768 int cqc_entry_sz; 769 int sccc_sz; 770 int qpc_timer_entry_sz; 771 int cqc_timer_entry_sz; 772 int srqc_entry_sz; 773 int idx_entry_sz; 774 u32 pbl_ba_pg_sz; 775 u32 pbl_buf_pg_sz; 776 u32 pbl_hop_num; 777 int aeqe_depth; 778 int ceqe_depth; 779 u32 aeqe_size; 780 u32 ceqe_size; 781 enum ib_mtu max_mtu; 782 u32 qpc_bt_num; 783 u32 qpc_timer_bt_num; 784 u32 srqc_bt_num; 785 u32 cqc_bt_num; 786 u32 cqc_timer_bt_num; 787 u32 mpt_bt_num; 788 u32 eqc_bt_num; 789 u32 smac_bt_num; 790 u32 sgid_bt_num; 791 u32 sccc_bt_num; 792 u32 gmv_bt_num; 793 u32 qpc_ba_pg_sz; 794 u32 qpc_buf_pg_sz; 795 u32 qpc_hop_num; 796 u32 srqc_ba_pg_sz; 797 u32 srqc_buf_pg_sz; 798 u32 srqc_hop_num; 799 u32 cqc_ba_pg_sz; 800 u32 cqc_buf_pg_sz; 801 u32 cqc_hop_num; 802 u32 mpt_ba_pg_sz; 803 u32 mpt_buf_pg_sz; 804 u32 mpt_hop_num; 805 u32 mtt_ba_pg_sz; 806 u32 mtt_buf_pg_sz; 807 u32 mtt_hop_num; 808 u32 wqe_sq_hop_num; 809 u32 wqe_sge_hop_num; 810 u32 wqe_rq_hop_num; 811 u32 sccc_ba_pg_sz; 812 u32 sccc_buf_pg_sz; 813 u32 sccc_hop_num; 814 u32 qpc_timer_ba_pg_sz; 815 u32 qpc_timer_buf_pg_sz; 816 u32 qpc_timer_hop_num; 817 u32 cqc_timer_ba_pg_sz; 818 u32 cqc_timer_buf_pg_sz; 819 u32 cqc_timer_hop_num; 820 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 821 u32 cqe_buf_pg_sz; 822 u32 cqe_hop_num; 823 u32 srqwqe_ba_pg_sz; 824 u32 srqwqe_buf_pg_sz; 825 u32 srqwqe_hop_num; 826 u32 idx_ba_pg_sz; 827 u32 idx_buf_pg_sz; 828 u32 idx_hop_num; 829 u32 eqe_ba_pg_sz; 830 u32 eqe_buf_pg_sz; 831 u32 eqe_hop_num; 832 u32 gmv_entry_num; 833 u32 gmv_entry_sz; 834 u32 gmv_ba_pg_sz; 835 u32 gmv_buf_pg_sz; 836 u32 gmv_hop_num; 837 u32 sl_num; 838 u32 llm_buf_pg_sz; 839 u32 chunk_sz; /* chunk size in non multihop mode */ 840 u64 flags; 841 u16 default_ceq_max_cnt; 842 u16 default_ceq_period; 843 u16 default_aeq_max_cnt; 844 u16 default_aeq_period; 845 u16 default_aeq_arm_st; 846 u16 default_ceq_arm_st; 847 u8 cong_cap; 848 enum hns_roce_cong_type default_cong_type; 849 u32 max_ack_req_msg_len; 850 }; 851 852 enum hns_roce_device_state { 853 HNS_ROCE_DEVICE_STATE_INITED, 854 HNS_ROCE_DEVICE_STATE_RST_DOWN, 855 HNS_ROCE_DEVICE_STATE_UNINIT, 856 }; 857 858 enum hns_roce_hw_pkt_stat_index { 859 HNS_ROCE_HW_RX_RC_PKT_CNT, 860 HNS_ROCE_HW_RX_UC_PKT_CNT, 861 HNS_ROCE_HW_RX_UD_PKT_CNT, 862 HNS_ROCE_HW_RX_XRC_PKT_CNT, 863 HNS_ROCE_HW_RX_PKT_CNT, 864 HNS_ROCE_HW_RX_ERR_PKT_CNT, 865 HNS_ROCE_HW_RX_CNP_PKT_CNT, 866 HNS_ROCE_HW_TX_RC_PKT_CNT, 867 HNS_ROCE_HW_TX_UC_PKT_CNT, 868 HNS_ROCE_HW_TX_UD_PKT_CNT, 869 HNS_ROCE_HW_TX_XRC_PKT_CNT, 870 HNS_ROCE_HW_TX_PKT_CNT, 871 HNS_ROCE_HW_TX_ERR_PKT_CNT, 872 HNS_ROCE_HW_TX_CNP_PKT_CNT, 873 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT, 874 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT, 875 HNS_ROCE_HW_ECN_DB_CNT, 876 HNS_ROCE_HW_RX_BUF_CNT, 877 HNS_ROCE_HW_TRP_RX_SOF_CNT, 878 HNS_ROCE_HW_CQ_CQE_CNT, 879 HNS_ROCE_HW_CQ_POE_CNT, 880 HNS_ROCE_HW_CQ_NOTIFY_CNT, 881 HNS_ROCE_HW_CNT_TOTAL 882 }; 883 884 enum hns_roce_sw_dfx_stat_index { 885 HNS_ROCE_DFX_AEQE_CNT, 886 HNS_ROCE_DFX_CEQE_CNT, 887 HNS_ROCE_DFX_CMDS_CNT, 888 HNS_ROCE_DFX_CMDS_ERR_CNT, 889 HNS_ROCE_DFX_MBX_POSTED_CNT, 890 HNS_ROCE_DFX_MBX_POLLED_CNT, 891 HNS_ROCE_DFX_MBX_EVENT_CNT, 892 HNS_ROCE_DFX_QP_CREATE_ERR_CNT, 893 HNS_ROCE_DFX_QP_MODIFY_ERR_CNT, 894 HNS_ROCE_DFX_CQ_CREATE_ERR_CNT, 895 HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT, 896 HNS_ROCE_DFX_SRQ_CREATE_ERR_CNT, 897 HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT, 898 HNS_ROCE_DFX_XRCD_ALLOC_ERR_CNT, 899 HNS_ROCE_DFX_MR_REG_ERR_CNT, 900 HNS_ROCE_DFX_MR_REREG_ERR_CNT, 901 HNS_ROCE_DFX_AH_CREATE_ERR_CNT, 902 HNS_ROCE_DFX_MMAP_ERR_CNT, 903 HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT, 904 HNS_ROCE_DFX_CNT_TOTAL 905 }; 906 907 struct hns_roce_hw { 908 int (*cmq_init)(struct hns_roce_dev *hr_dev); 909 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 910 int (*hw_profile)(struct hns_roce_dev *hr_dev); 911 int (*hw_init)(struct hns_roce_dev *hr_dev); 912 void (*hw_exit)(struct hns_roce_dev *hr_dev); 913 int (*post_mbox)(struct hns_roce_dev *hr_dev, 914 struct hns_roce_mbox_msg *mbox_msg); 915 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); 916 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 917 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, 918 const union ib_gid *gid, const struct ib_gid_attr *attr); 919 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, 920 const u8 *addr); 921 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 922 struct hns_roce_mr *mr); 923 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 924 struct hns_roce_mr *mr, int flags, 925 void *mb_buf); 926 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); 927 void (*write_cqc)(struct hns_roce_dev *hr_dev, 928 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 929 dma_addr_t dma_handle); 930 int (*set_hem)(struct hns_roce_dev *hr_dev, 931 struct hns_roce_hem_table *table, int obj, u32 step_idx); 932 int (*clear_hem)(struct hns_roce_dev *hr_dev, 933 struct hns_roce_hem_table *table, int obj, 934 u32 step_idx); 935 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 936 int attr_mask, enum ib_qp_state cur_state, 937 enum ib_qp_state new_state, struct ib_udata *udata); 938 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 939 struct hns_roce_qp *hr_qp); 940 void (*dereg_mr)(struct hns_roce_dev *hr_dev); 941 int (*init_eq)(struct hns_roce_dev *hr_dev); 942 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 943 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 944 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 945 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 946 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 947 int (*query_srqc)(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer); 948 int (*query_sccc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 949 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 950 u64 *stats, u32 port, int *hw_counters); 951 int (*get_dscp)(struct hns_roce_dev *hr_dev, u8 dscp, 952 u8 *tc_mode, u8 *priority); 953 const struct ib_device_ops *hns_roce_dev_ops; 954 const struct ib_device_ops *hns_roce_dev_srq_ops; 955 }; 956 957 struct hns_roce_dev { 958 struct ib_device ib_dev; 959 struct pci_dev *pci_dev; 960 struct device *dev; 961 struct hns_roce_uar priv_uar; 962 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 963 spinlock_t sm_lock; 964 bool active; 965 bool is_reset; 966 bool dis_db; 967 unsigned long reset_cnt; 968 struct hns_roce_ib_iboe iboe; 969 enum hns_roce_device_state state; 970 struct list_head qp_list; /* list of all qps on this dev */ 971 spinlock_t qp_list_lock; /* protect qp_list */ 972 973 struct list_head pgdir_list; 974 struct mutex pgdir_mutex; 975 int irq[HNS_ROCE_MAX_IRQ_NUM]; 976 u8 __iomem *reg_base; 977 void __iomem *mem_base; 978 struct hns_roce_caps caps; 979 struct xarray qp_table_xa; 980 981 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 982 u64 sys_image_guid; 983 u32 vendor_id; 984 u32 vendor_part_id; 985 u32 hw_rev; 986 void __iomem *priv_addr; 987 988 struct hns_roce_cmdq cmd; 989 struct hns_roce_ida pd_ida; 990 struct hns_roce_ida xrcd_ida; 991 struct hns_roce_ida uar_ida; 992 struct hns_roce_mr_table mr_table; 993 struct hns_roce_cq_table cq_table; 994 struct hns_roce_srq_table srq_table; 995 struct hns_roce_qp_table qp_table; 996 struct hns_roce_eq_table eq_table; 997 struct hns_roce_hem_table qpc_timer_table; 998 struct hns_roce_hem_table cqc_timer_table; 999 /* GMV is the memory area that the driver allocates for the hardware 1000 * to store SGID, SMAC and VLAN information. 1001 */ 1002 struct hns_roce_hem_table gmv_table; 1003 1004 int cmd_mod; 1005 int loop_idc; 1006 u32 sdb_offset; 1007 u32 odb_offset; 1008 const struct hns_roce_hw *hw; 1009 void *priv; 1010 struct workqueue_struct *irq_workq; 1011 struct work_struct ecc_work; 1012 u32 func_num; 1013 u32 is_vf; 1014 u32 cong_algo_tmpl_id; 1015 u64 dwqe_page; 1016 struct hns_roce_dev_debugfs dbgfs; 1017 atomic64_t *dfx_cnt; 1018 }; 1019 1020 enum hns_roce_trace_type { 1021 TRACE_SQ, 1022 TRACE_RQ, 1023 TRACE_SRQ, 1024 }; 1025 1026 static inline const char *trace_type_to_str(enum hns_roce_trace_type type) 1027 { 1028 switch (type) { 1029 case TRACE_SQ: 1030 return "SQ"; 1031 case TRACE_RQ: 1032 return "RQ"; 1033 case TRACE_SRQ: 1034 return "SRQ"; 1035 default: 1036 return "UNKNOWN"; 1037 } 1038 } 1039 1040 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1041 { 1042 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1043 } 1044 1045 static inline struct hns_roce_ucontext 1046 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1047 { 1048 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1049 } 1050 1051 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1052 { 1053 return container_of(ibpd, struct hns_roce_pd, ibpd); 1054 } 1055 1056 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 1057 { 1058 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1059 } 1060 1061 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1062 { 1063 return container_of(ibah, struct hns_roce_ah, ibah); 1064 } 1065 1066 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1067 { 1068 return container_of(ibmr, struct hns_roce_mr, ibmr); 1069 } 1070 1071 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1072 { 1073 return container_of(ibqp, struct hns_roce_qp, ibqp); 1074 } 1075 1076 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1077 { 1078 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1079 } 1080 1081 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1082 { 1083 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1084 } 1085 1086 static inline struct hns_user_mmap_entry * 1087 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) 1088 { 1089 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); 1090 } 1091 1092 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1093 { 1094 writeq(*(u64 *)val, dest); 1095 } 1096 1097 static inline struct hns_roce_qp 1098 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1099 { 1100 return xa_load(&hr_dev->qp_table_xa, qpn); 1101 } 1102 1103 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1104 unsigned int offset) 1105 { 1106 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1107 (offset & ((1 << buf->trunk_shift) - 1)); 1108 } 1109 1110 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1111 unsigned int offset) 1112 { 1113 return buf->trunk_list[offset >> buf->trunk_shift].map + 1114 (offset & ((1 << buf->trunk_shift) - 1)); 1115 } 1116 1117 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1118 { 1119 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1120 } 1121 1122 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1123 1124 static inline u64 to_hr_hw_page_addr(u64 addr) 1125 { 1126 return addr >> HNS_HW_PAGE_SHIFT; 1127 } 1128 1129 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1130 { 1131 return page_shift - HNS_HW_PAGE_SHIFT; 1132 } 1133 1134 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1135 { 1136 if (count > 0) 1137 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1138 1139 return 0; 1140 } 1141 1142 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1143 { 1144 return hr_hw_page_align(count << buf_shift); 1145 } 1146 1147 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1148 { 1149 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1150 } 1151 1152 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1153 { 1154 if (!count) 1155 return 0; 1156 1157 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1158 } 1159 1160 #define DSCP_SHIFT 2 1161 1162 static inline u8 get_tclass(const struct ib_global_route *grh) 1163 { 1164 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1165 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1166 } 1167 1168 void hns_roce_init_uar_table(struct hns_roce_dev *dev); 1169 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1170 1171 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1172 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1173 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1174 u64 out_param); 1175 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1176 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1177 1178 /* hns roce hw need current block and next block addr from mtt */ 1179 #define MTT_MIN_COUNT 2 1180 static inline dma_addr_t hns_roce_get_mtr_ba(struct hns_roce_mtr *mtr) 1181 { 1182 return mtr->hem_cfg.root_ba; 1183 } 1184 1185 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1186 u32 offset, u64 *mtt_buf, int mtt_max); 1187 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1188 struct hns_roce_buf_attr *buf_attr, 1189 unsigned int page_shift, struct ib_udata *udata, 1190 unsigned long user_addr); 1191 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1192 struct hns_roce_mtr *mtr); 1193 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1194 dma_addr_t *pages, unsigned int page_cnt); 1195 1196 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1197 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1198 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1199 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1200 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1201 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1202 1203 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1204 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1205 1206 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1207 1208 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1209 struct ib_udata *udata); 1210 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1211 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1212 { 1213 return 0; 1214 } 1215 1216 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1217 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1218 1219 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1220 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1221 u64 virt_addr, int access_flags, 1222 struct ib_dmah *dmah, 1223 struct ib_udata *udata); 1224 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1225 u64 length, u64 virt_addr, 1226 int mr_access_flags, struct ib_pd *pd, 1227 struct ib_udata *udata); 1228 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1229 u32 max_num_sg); 1230 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1231 unsigned int *sg_offset); 1232 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1233 unsigned long key_to_hw_index(u32 key); 1234 1235 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1236 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1237 u32 page_shift, u32 flags); 1238 1239 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1240 int buf_cnt, struct hns_roce_buf *buf, 1241 unsigned int page_shift); 1242 int hns_roce_get_umem_bufs(dma_addr_t *bufs, 1243 int buf_cnt, struct ib_umem *umem, 1244 unsigned int page_shift); 1245 1246 int hns_roce_create_srq(struct ib_srq *srq, 1247 struct ib_srq_init_attr *srq_init_attr, 1248 struct ib_udata *udata); 1249 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1250 1251 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1252 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1253 1254 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, 1255 struct ib_udata *udata); 1256 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1257 int attr_mask, struct ib_udata *udata); 1258 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1259 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1260 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1261 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1262 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1263 struct ib_cq *ib_cq); 1264 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1265 struct hns_roce_cq *recv_cq); 1266 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1267 struct hns_roce_cq *recv_cq); 1268 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1269 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1270 struct ib_udata *udata); 1271 __be32 send_ieth(const struct ib_send_wr *wr); 1272 int to_hr_qp_type(int qp_type); 1273 1274 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1275 struct uverbs_attr_bundle *attrs); 1276 1277 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1278 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1279 struct hns_roce_db *db); 1280 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1281 struct hns_roce_db *db); 1282 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1283 int order); 1284 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1285 1286 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1287 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1288 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1289 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1290 void hns_roce_flush_cqe(struct hns_roce_dev *hr_dev, u32 qpn); 1291 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1292 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1293 int hns_roce_init(struct hns_roce_dev *hr_dev); 1294 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1295 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq); 1296 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq); 1297 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp); 1298 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1299 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1300 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1301 int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq); 1302 int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq); 1303 struct hns_user_mmap_entry * 1304 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1305 size_t length, 1306 enum hns_roce_mmap_type mmap_type); 1307 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl); 1308 1309 #endif /* _HNS_ROCE_DEVICE_H */ 1310