1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 39 #define PCI_REVISION_ID_HIP08 0x21 40 #define PCI_REVISION_ID_HIP09 0x30 41 42 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 43 44 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 45 46 #define BA_BYTE_LEN 8 47 48 #define HNS_ROCE_MIN_CQE_NUM 0x40 49 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 50 51 #define HNS_ROCE_MAX_IRQ_NUM 128 52 53 #define HNS_ROCE_SGE_IN_WQE 2 54 #define HNS_ROCE_SGE_SHIFT 4 55 56 #define EQ_ENABLE 1 57 #define EQ_DISABLE 0 58 59 #define HNS_ROCE_CEQ 0 60 #define HNS_ROCE_AEQ 1 61 62 #define HNS_ROCE_CEQE_SIZE 0x4 63 #define HNS_ROCE_AEQE_SIZE 0x10 64 65 #define HNS_ROCE_V3_EQE_SIZE 0x40 66 67 #define HNS_ROCE_V2_CQE_SIZE 32 68 #define HNS_ROCE_V3_CQE_SIZE 64 69 70 #define HNS_ROCE_V2_QPC_SZ 256 71 #define HNS_ROCE_V3_QPC_SZ 512 72 73 #define HNS_ROCE_MAX_PORTS 6 74 #define HNS_ROCE_GID_SIZE 16 75 #define HNS_ROCE_SGE_SIZE 16 76 #define HNS_ROCE_DWQE_SIZE 65536 77 78 #define HNS_ROCE_HOP_NUM_0 0xff 79 80 #define MR_TYPE_MR 0x00 81 #define MR_TYPE_FRMR 0x01 82 #define MR_TYPE_DMA 0x03 83 84 #define HNS_ROCE_FRMR_MAX_PA 512 85 86 #define PKEY_ID 0xffff 87 #define NODE_DESC_SIZE 64 88 #define DB_REG_OFFSET 0x1000 89 90 /* Configure to HW for PAGE_SIZE larger than 4KB */ 91 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 92 93 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 94 #define SRQ_DB_REG 0x230 95 96 #define HNS_ROCE_QP_BANK_NUM 8 97 #define HNS_ROCE_CQ_BANK_NUM 4 98 99 #define CQ_BANKID_SHIFT 2 100 #define CQ_BANKID_MASK GENMASK(1, 0) 101 102 enum { 103 SERV_TYPE_RC, 104 SERV_TYPE_UC, 105 SERV_TYPE_RD, 106 SERV_TYPE_UD, 107 SERV_TYPE_XRC = 5, 108 }; 109 110 enum hns_roce_event { 111 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 112 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 113 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 114 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 115 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 116 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 117 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 118 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 119 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 120 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 121 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 122 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 123 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 124 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 125 /* 0x10 and 0x11 is unused in currently application case */ 126 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 127 HNS_ROCE_EVENT_TYPE_MB = 0x13, 128 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 129 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 130 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 131 }; 132 133 enum { 134 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 135 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 136 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 137 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 138 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 139 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 140 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 141 HNS_ROCE_CAP_FLAG_MW = BIT(7), 142 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 143 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 144 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 145 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), 146 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 147 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 148 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 149 HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB = BIT(22), 150 }; 151 152 #define HNS_ROCE_DB_TYPE_COUNT 2 153 #define HNS_ROCE_DB_UNIT_SIZE 4 154 155 enum { 156 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 157 }; 158 159 enum hns_roce_reset_stage { 160 HNS_ROCE_STATE_NON_RST, 161 HNS_ROCE_STATE_RST_BEF_DOWN, 162 HNS_ROCE_STATE_RST_DOWN, 163 HNS_ROCE_STATE_RST_UNINIT, 164 HNS_ROCE_STATE_RST_INIT, 165 HNS_ROCE_STATE_RST_INITED, 166 }; 167 168 enum hns_roce_instance_state { 169 HNS_ROCE_STATE_NON_INIT, 170 HNS_ROCE_STATE_INIT, 171 HNS_ROCE_STATE_INITED, 172 HNS_ROCE_STATE_UNINIT, 173 }; 174 175 enum { 176 HNS_ROCE_RST_DIRECT_RETURN = 0, 177 }; 178 179 #define HNS_ROCE_CMD_SUCCESS 1 180 181 /* The minimum page size is 4K for hardware */ 182 #define HNS_HW_PAGE_SHIFT 12 183 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 184 185 struct hns_roce_uar { 186 u64 pfn; 187 unsigned long index; 188 unsigned long logic_idx; 189 }; 190 191 enum hns_roce_mmap_type { 192 HNS_ROCE_MMAP_TYPE_DB = 1, 193 HNS_ROCE_MMAP_TYPE_DWQE, 194 }; 195 196 struct hns_user_mmap_entry { 197 struct rdma_user_mmap_entry rdma_entry; 198 enum hns_roce_mmap_type mmap_type; 199 u64 address; 200 }; 201 202 struct hns_roce_ucontext { 203 struct ib_ucontext ibucontext; 204 struct hns_roce_uar uar; 205 struct list_head page_list; 206 struct mutex page_mutex; 207 struct hns_user_mmap_entry *db_mmap_entry; 208 u32 config; 209 }; 210 211 struct hns_roce_pd { 212 struct ib_pd ibpd; 213 unsigned long pdn; 214 }; 215 216 struct hns_roce_xrcd { 217 struct ib_xrcd ibxrcd; 218 u32 xrcdn; 219 }; 220 221 struct hns_roce_bitmap { 222 /* Bitmap Traversal last a bit which is 1 */ 223 unsigned long last; 224 unsigned long top; 225 unsigned long max; 226 unsigned long reserved_top; 227 unsigned long mask; 228 spinlock_t lock; 229 unsigned long *table; 230 }; 231 232 struct hns_roce_ida { 233 struct ida ida; 234 u32 min; /* Lowest ID to allocate. */ 235 u32 max; /* Highest ID to allocate. */ 236 }; 237 238 /* For Hardware Entry Memory */ 239 struct hns_roce_hem_table { 240 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 241 u32 type; 242 /* HEM array elment num */ 243 unsigned long num_hem; 244 /* Single obj size */ 245 unsigned long obj_size; 246 unsigned long table_chunk_size; 247 struct mutex mutex; 248 struct hns_roce_hem **hem; 249 u64 **bt_l1; 250 dma_addr_t *bt_l1_dma_addr; 251 u64 **bt_l0; 252 dma_addr_t *bt_l0_dma_addr; 253 }; 254 255 struct hns_roce_buf_region { 256 u32 offset; /* page offset */ 257 u32 count; /* page count */ 258 int hopnum; /* addressing hop num */ 259 }; 260 261 #define HNS_ROCE_MAX_BT_REGION 3 262 #define HNS_ROCE_MAX_BT_LEVEL 3 263 struct hns_roce_hem_list { 264 struct list_head root_bt; 265 /* link all bt dma mem by hop config */ 266 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 267 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 268 dma_addr_t root_ba; /* pointer to the root ba table */ 269 }; 270 271 struct hns_roce_buf_attr { 272 struct { 273 size_t size; /* region size */ 274 int hopnum; /* multi-hop addressing hop num */ 275 } region[HNS_ROCE_MAX_BT_REGION]; 276 unsigned int region_count; /* valid region count */ 277 unsigned int page_shift; /* buffer page shift */ 278 unsigned int user_access; /* umem access flag */ 279 bool mtt_only; /* only alloc buffer-required MTT memory */ 280 }; 281 282 struct hns_roce_hem_cfg { 283 dma_addr_t root_ba; /* root BA table's address */ 284 bool is_direct; /* addressing without BA table */ 285 unsigned int ba_pg_shift; /* BA table page shift */ 286 unsigned int buf_pg_shift; /* buffer page shift */ 287 unsigned int buf_pg_count; /* buffer page count */ 288 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 289 unsigned int region_count; 290 }; 291 292 /* memory translate region */ 293 struct hns_roce_mtr { 294 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 295 struct ib_umem *umem; /* user space buffer */ 296 struct hns_roce_buf *kmem; /* kernel space buffer */ 297 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 298 }; 299 300 struct hns_roce_mw { 301 struct ib_mw ibmw; 302 u32 pdn; 303 u32 rkey; 304 int enabled; /* MW's active status */ 305 u32 pbl_hop_num; 306 u32 pbl_ba_pg_sz; 307 u32 pbl_buf_pg_sz; 308 }; 309 310 struct hns_roce_mr { 311 struct ib_mr ibmr; 312 u64 iova; /* MR's virtual original addr */ 313 u64 size; /* Address range of MR */ 314 u32 key; /* Key of MR */ 315 u32 pd; /* PD num of MR */ 316 u32 access; /* Access permission of MR */ 317 int enabled; /* MR's active status */ 318 int type; /* MR's register type */ 319 u32 pbl_hop_num; /* multi-hop number */ 320 struct hns_roce_mtr pbl_mtr; 321 u32 npages; 322 dma_addr_t *page_list; 323 }; 324 325 struct hns_roce_mr_table { 326 struct hns_roce_ida mtpt_ida; 327 struct hns_roce_hem_table mtpt_table; 328 }; 329 330 struct hns_roce_wq { 331 u64 *wrid; /* Work request ID */ 332 spinlock_t lock; 333 u32 wqe_cnt; /* WQE num */ 334 u32 max_gs; 335 u32 rsv_sge; 336 u32 offset; 337 u32 wqe_shift; /* WQE size */ 338 u32 head; 339 u32 tail; 340 void __iomem *db_reg; 341 u32 ext_sge_cnt; 342 }; 343 344 struct hns_roce_sge { 345 unsigned int sge_cnt; /* SGE num */ 346 u32 offset; 347 u32 sge_shift; /* SGE size */ 348 }; 349 350 struct hns_roce_buf_list { 351 void *buf; 352 dma_addr_t map; 353 }; 354 355 /* 356 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 357 * dma address range. 358 * 359 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 360 * 361 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 362 * the allocated size is smaller than the required size. 363 */ 364 enum { 365 HNS_ROCE_BUF_DIRECT = BIT(0), 366 HNS_ROCE_BUF_NOSLEEP = BIT(1), 367 HNS_ROCE_BUF_NOFAIL = BIT(2), 368 }; 369 370 struct hns_roce_buf { 371 struct hns_roce_buf_list *trunk_list; 372 u32 ntrunks; 373 u32 npages; 374 unsigned int trunk_shift; 375 unsigned int page_shift; 376 }; 377 378 struct hns_roce_db_pgdir { 379 struct list_head list; 380 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 381 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 382 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 383 u32 *page; 384 dma_addr_t db_dma; 385 }; 386 387 struct hns_roce_user_db_page { 388 struct list_head list; 389 struct ib_umem *umem; 390 unsigned long user_virt; 391 refcount_t refcount; 392 }; 393 394 struct hns_roce_db { 395 u32 *db_record; 396 union { 397 struct hns_roce_db_pgdir *pgdir; 398 struct hns_roce_user_db_page *user_page; 399 } u; 400 dma_addr_t dma; 401 void *virt_addr; 402 unsigned long index; 403 unsigned long order; 404 }; 405 406 struct hns_roce_cq { 407 struct ib_cq ib_cq; 408 struct hns_roce_mtr mtr; 409 struct hns_roce_db db; 410 u32 flags; 411 spinlock_t lock; 412 u32 cq_depth; 413 u32 cons_index; 414 u32 *set_ci_db; 415 void __iomem *db_reg; 416 int arm_sn; 417 int cqe_size; 418 unsigned long cqn; 419 u32 vector; 420 refcount_t refcount; 421 struct completion free; 422 struct list_head sq_list; /* all qps on this send cq */ 423 struct list_head rq_list; /* all qps on this recv cq */ 424 int is_armed; /* cq is armed */ 425 struct list_head node; /* all armed cqs are on a list */ 426 }; 427 428 struct hns_roce_idx_que { 429 struct hns_roce_mtr mtr; 430 u32 entry_shift; 431 unsigned long *bitmap; 432 u32 head; 433 u32 tail; 434 }; 435 436 struct hns_roce_srq { 437 struct ib_srq ibsrq; 438 unsigned long srqn; 439 u32 wqe_cnt; 440 int max_gs; 441 u32 rsv_sge; 442 u32 wqe_shift; 443 u32 cqn; 444 u32 xrcdn; 445 void __iomem *db_reg; 446 447 refcount_t refcount; 448 struct completion free; 449 450 struct hns_roce_mtr buf_mtr; 451 452 u64 *wrid; 453 struct hns_roce_idx_que idx_que; 454 spinlock_t lock; 455 struct mutex mutex; 456 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 457 struct hns_roce_db rdb; 458 u32 cap_flags; 459 }; 460 461 struct hns_roce_uar_table { 462 struct hns_roce_bitmap bitmap; 463 }; 464 465 struct hns_roce_bank { 466 struct ida ida; 467 u32 inuse; /* Number of IDs allocated */ 468 u32 min; /* Lowest ID to allocate. */ 469 u32 max; /* Highest ID to allocate. */ 470 u32 next; /* Next ID to allocate. */ 471 }; 472 473 struct hns_roce_idx_table { 474 u32 *spare_idx; 475 u32 head; 476 u32 tail; 477 }; 478 479 struct hns_roce_qp_table { 480 struct hns_roce_hem_table qp_table; 481 struct hns_roce_hem_table irrl_table; 482 struct hns_roce_hem_table trrl_table; 483 struct hns_roce_hem_table sccc_table; 484 struct mutex scc_mutex; 485 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 486 struct mutex bank_mutex; 487 struct hns_roce_idx_table idx_table; 488 }; 489 490 struct hns_roce_cq_table { 491 struct xarray array; 492 struct hns_roce_hem_table table; 493 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 494 struct mutex bank_mutex; 495 }; 496 497 struct hns_roce_srq_table { 498 struct hns_roce_ida srq_ida; 499 struct xarray xa; 500 struct hns_roce_hem_table table; 501 }; 502 503 struct hns_roce_av { 504 u8 port; 505 u8 gid_index; 506 u8 stat_rate; 507 u8 hop_limit; 508 u32 flowlabel; 509 u16 udp_sport; 510 u8 sl; 511 u8 tclass; 512 u8 dgid[HNS_ROCE_GID_SIZE]; 513 u8 mac[ETH_ALEN]; 514 u16 vlan_id; 515 u8 vlan_en; 516 }; 517 518 struct hns_roce_ah { 519 struct ib_ah ibah; 520 struct hns_roce_av av; 521 }; 522 523 struct hns_roce_cmd_context { 524 struct completion done; 525 int result; 526 int next; 527 u64 out_param; 528 u16 token; 529 u16 busy; 530 }; 531 532 enum hns_roce_cmdq_state { 533 HNS_ROCE_CMDQ_STATE_NORMAL, 534 HNS_ROCE_CMDQ_STATE_FATAL_ERR, 535 }; 536 537 struct hns_roce_cmdq { 538 struct dma_pool *pool; 539 struct semaphore poll_sem; 540 /* 541 * Event mode: cmd register mutex protection, 542 * ensure to not exceed max_cmds and user use limit region 543 */ 544 struct semaphore event_sem; 545 int max_cmds; 546 spinlock_t context_lock; 547 int free_head; 548 struct hns_roce_cmd_context *context; 549 /* 550 * Process whether use event mode, init default non-zero 551 * After the event queue of cmd event ready, 552 * can switch into event mode 553 * close device, switch into poll mode(non event mode) 554 */ 555 u8 use_events; 556 enum hns_roce_cmdq_state state; 557 }; 558 559 struct hns_roce_cmd_mailbox { 560 void *buf; 561 dma_addr_t dma; 562 }; 563 564 struct hns_roce_mbox_msg { 565 u64 in_param; 566 u64 out_param; 567 u8 cmd; 568 u32 tag; 569 u16 token; 570 u8 event_en; 571 }; 572 573 struct hns_roce_dev; 574 575 enum { 576 HNS_ROCE_FLUSH_FLAG = 0, 577 }; 578 579 struct hns_roce_work { 580 struct hns_roce_dev *hr_dev; 581 struct work_struct work; 582 int event_type; 583 int sub_type; 584 u32 queue_num; 585 }; 586 587 struct hns_roce_qp { 588 struct ib_qp ibqp; 589 struct hns_roce_wq rq; 590 struct hns_roce_db rdb; 591 struct hns_roce_db sdb; 592 unsigned long en_flags; 593 enum ib_sig_type sq_signal_bits; 594 struct hns_roce_wq sq; 595 596 struct hns_roce_mtr mtr; 597 598 u32 buff_size; 599 struct mutex mutex; 600 u8 port; 601 u8 phy_port; 602 u8 sl; 603 u8 resp_depth; 604 u8 state; 605 u32 atomic_rd_en; 606 u32 qkey; 607 void (*event)(struct hns_roce_qp *qp, 608 enum hns_roce_event event_type); 609 unsigned long qpn; 610 611 u32 xrcdn; 612 613 refcount_t refcount; 614 struct completion free; 615 616 struct hns_roce_sge sge; 617 u32 next_sge; 618 enum ib_mtu path_mtu; 619 u32 max_inline_data; 620 u8 free_mr_en; 621 622 /* 0: flush needed, 1: unneeded */ 623 unsigned long flush_flag; 624 struct hns_roce_work flush_work; 625 struct list_head node; /* all qps are on a list */ 626 struct list_head rq_node; /* all recv qps are on a list */ 627 struct list_head sq_node; /* all send qps are on a list */ 628 struct hns_user_mmap_entry *dwqe_mmap_entry; 629 u32 config; 630 }; 631 632 struct hns_roce_ib_iboe { 633 spinlock_t lock; 634 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 635 struct notifier_block nb; 636 u8 phy_port[HNS_ROCE_MAX_PORTS]; 637 }; 638 639 struct hns_roce_ceqe { 640 __le32 comp; 641 __le32 rsv[15]; 642 }; 643 644 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l) 645 646 #define CEQE_CQN CEQE_FIELD_LOC(23, 0) 647 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31) 648 649 struct hns_roce_aeqe { 650 __le32 asyn; 651 union { 652 struct { 653 __le32 num; 654 u32 rsv0; 655 u32 rsv1; 656 } queue_event; 657 658 struct { 659 __le64 out_param; 660 __le16 token; 661 u8 status; 662 u8 rsv0; 663 } __packed cmd; 664 } event; 665 __le32 rsv[12]; 666 }; 667 668 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l) 669 670 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0) 671 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8) 672 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31) 673 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32) 674 675 struct hns_roce_eq { 676 struct hns_roce_dev *hr_dev; 677 void __iomem *db_reg; 678 679 int type_flag; /* Aeq:1 ceq:0 */ 680 int eqn; 681 u32 entries; 682 int eqe_size; 683 int irq; 684 u32 cons_index; 685 int over_ignore; 686 int coalesce; 687 int arm_st; 688 int hop_num; 689 struct hns_roce_mtr mtr; 690 u16 eq_max_cnt; 691 u32 eq_period; 692 int shift; 693 int event_type; 694 int sub_type; 695 }; 696 697 struct hns_roce_eq_table { 698 struct hns_roce_eq *eq; 699 }; 700 701 enum cong_type { 702 CONG_TYPE_DCQCN, 703 CONG_TYPE_LDCP, 704 CONG_TYPE_HC3, 705 CONG_TYPE_DIP, 706 }; 707 708 struct hns_roce_caps { 709 u64 fw_ver; 710 u8 num_ports; 711 int gid_table_len[HNS_ROCE_MAX_PORTS]; 712 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 713 int local_ca_ack_delay; 714 int num_uars; 715 u32 phy_num_uars; 716 u32 max_sq_sg; 717 u32 max_sq_inline; 718 u32 max_rq_sg; 719 u32 rsv0; 720 u32 num_qps; 721 u32 reserved_qps; 722 u32 num_srqs; 723 u32 max_wqes; 724 u32 max_srq_wrs; 725 u32 max_srq_sges; 726 u32 max_sq_desc_sz; 727 u32 max_rq_desc_sz; 728 u32 rsv2; 729 int max_qp_init_rdma; 730 int max_qp_dest_rdma; 731 u32 num_cqs; 732 u32 max_cqes; 733 u32 min_cqes; 734 u32 min_wqes; 735 u32 reserved_cqs; 736 u32 reserved_srqs; 737 int num_aeq_vectors; 738 int num_comp_vectors; 739 int num_other_vectors; 740 u32 num_mtpts; 741 u32 rsv1; 742 u32 num_srqwqe_segs; 743 u32 num_idx_segs; 744 int reserved_mrws; 745 int reserved_uars; 746 int num_pds; 747 int reserved_pds; 748 u32 num_xrcds; 749 u32 reserved_xrcds; 750 u32 mtt_entry_sz; 751 u32 cqe_sz; 752 u32 page_size_cap; 753 u32 reserved_lkey; 754 int mtpt_entry_sz; 755 int qpc_sz; 756 int irrl_entry_sz; 757 int trrl_entry_sz; 758 int cqc_entry_sz; 759 int sccc_sz; 760 int qpc_timer_entry_sz; 761 int cqc_timer_entry_sz; 762 int srqc_entry_sz; 763 int idx_entry_sz; 764 u32 pbl_ba_pg_sz; 765 u32 pbl_buf_pg_sz; 766 u32 pbl_hop_num; 767 int aeqe_depth; 768 int ceqe_depth; 769 u32 aeqe_size; 770 u32 ceqe_size; 771 enum ib_mtu max_mtu; 772 u32 qpc_bt_num; 773 u32 qpc_timer_bt_num; 774 u32 srqc_bt_num; 775 u32 cqc_bt_num; 776 u32 cqc_timer_bt_num; 777 u32 mpt_bt_num; 778 u32 eqc_bt_num; 779 u32 smac_bt_num; 780 u32 sgid_bt_num; 781 u32 sccc_bt_num; 782 u32 gmv_bt_num; 783 u32 qpc_ba_pg_sz; 784 u32 qpc_buf_pg_sz; 785 u32 qpc_hop_num; 786 u32 srqc_ba_pg_sz; 787 u32 srqc_buf_pg_sz; 788 u32 srqc_hop_num; 789 u32 cqc_ba_pg_sz; 790 u32 cqc_buf_pg_sz; 791 u32 cqc_hop_num; 792 u32 mpt_ba_pg_sz; 793 u32 mpt_buf_pg_sz; 794 u32 mpt_hop_num; 795 u32 mtt_ba_pg_sz; 796 u32 mtt_buf_pg_sz; 797 u32 mtt_hop_num; 798 u32 wqe_sq_hop_num; 799 u32 wqe_sge_hop_num; 800 u32 wqe_rq_hop_num; 801 u32 sccc_ba_pg_sz; 802 u32 sccc_buf_pg_sz; 803 u32 sccc_hop_num; 804 u32 qpc_timer_ba_pg_sz; 805 u32 qpc_timer_buf_pg_sz; 806 u32 qpc_timer_hop_num; 807 u32 cqc_timer_ba_pg_sz; 808 u32 cqc_timer_buf_pg_sz; 809 u32 cqc_timer_hop_num; 810 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 811 u32 cqe_buf_pg_sz; 812 u32 cqe_hop_num; 813 u32 srqwqe_ba_pg_sz; 814 u32 srqwqe_buf_pg_sz; 815 u32 srqwqe_hop_num; 816 u32 idx_ba_pg_sz; 817 u32 idx_buf_pg_sz; 818 u32 idx_hop_num; 819 u32 eqe_ba_pg_sz; 820 u32 eqe_buf_pg_sz; 821 u32 eqe_hop_num; 822 u32 gmv_entry_num; 823 u32 gmv_entry_sz; 824 u32 gmv_ba_pg_sz; 825 u32 gmv_buf_pg_sz; 826 u32 gmv_hop_num; 827 u32 sl_num; 828 u32 llm_buf_pg_sz; 829 u32 chunk_sz; /* chunk size in non multihop mode */ 830 u64 flags; 831 u16 default_ceq_max_cnt; 832 u16 default_ceq_period; 833 u16 default_aeq_max_cnt; 834 u16 default_aeq_period; 835 u16 default_aeq_arm_st; 836 u16 default_ceq_arm_st; 837 enum cong_type cong_type; 838 }; 839 840 enum hns_roce_device_state { 841 HNS_ROCE_DEVICE_STATE_INITED, 842 HNS_ROCE_DEVICE_STATE_RST_DOWN, 843 HNS_ROCE_DEVICE_STATE_UNINIT, 844 }; 845 846 enum hns_roce_hw_pkt_stat_index { 847 HNS_ROCE_HW_RX_RC_PKT_CNT, 848 HNS_ROCE_HW_RX_UC_PKT_CNT, 849 HNS_ROCE_HW_RX_UD_PKT_CNT, 850 HNS_ROCE_HW_RX_XRC_PKT_CNT, 851 HNS_ROCE_HW_RX_PKT_CNT, 852 HNS_ROCE_HW_RX_ERR_PKT_CNT, 853 HNS_ROCE_HW_RX_CNP_PKT_CNT, 854 HNS_ROCE_HW_TX_RC_PKT_CNT, 855 HNS_ROCE_HW_TX_UC_PKT_CNT, 856 HNS_ROCE_HW_TX_UD_PKT_CNT, 857 HNS_ROCE_HW_TX_XRC_PKT_CNT, 858 HNS_ROCE_HW_TX_PKT_CNT, 859 HNS_ROCE_HW_TX_ERR_PKT_CNT, 860 HNS_ROCE_HW_TX_CNP_PKT_CNT, 861 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT, 862 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT, 863 HNS_ROCE_HW_ECN_DB_CNT, 864 HNS_ROCE_HW_RX_BUF_CNT, 865 HNS_ROCE_HW_TRP_RX_SOF_CNT, 866 HNS_ROCE_HW_CQ_CQE_CNT, 867 HNS_ROCE_HW_CQ_POE_CNT, 868 HNS_ROCE_HW_CQ_NOTIFY_CNT, 869 HNS_ROCE_HW_CNT_TOTAL 870 }; 871 872 struct hns_roce_hw { 873 int (*cmq_init)(struct hns_roce_dev *hr_dev); 874 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 875 int (*hw_profile)(struct hns_roce_dev *hr_dev); 876 int (*hw_init)(struct hns_roce_dev *hr_dev); 877 void (*hw_exit)(struct hns_roce_dev *hr_dev); 878 int (*post_mbox)(struct hns_roce_dev *hr_dev, 879 struct hns_roce_mbox_msg *mbox_msg); 880 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); 881 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 882 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, 883 const union ib_gid *gid, const struct ib_gid_attr *attr); 884 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, 885 const u8 *addr); 886 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 887 struct hns_roce_mr *mr); 888 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 889 struct hns_roce_mr *mr, int flags, 890 void *mb_buf); 891 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 892 struct hns_roce_mr *mr); 893 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 894 void (*write_cqc)(struct hns_roce_dev *hr_dev, 895 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 896 dma_addr_t dma_handle); 897 int (*set_hem)(struct hns_roce_dev *hr_dev, 898 struct hns_roce_hem_table *table, int obj, u32 step_idx); 899 int (*clear_hem)(struct hns_roce_dev *hr_dev, 900 struct hns_roce_hem_table *table, int obj, 901 u32 step_idx); 902 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 903 int attr_mask, enum ib_qp_state cur_state, 904 enum ib_qp_state new_state, struct ib_udata *udata); 905 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 906 struct hns_roce_qp *hr_qp); 907 void (*dereg_mr)(struct hns_roce_dev *hr_dev); 908 int (*init_eq)(struct hns_roce_dev *hr_dev); 909 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 910 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 911 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 912 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 913 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 914 int (*query_srqc)(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer); 915 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 916 u64 *stats, u32 port, int *hw_counters); 917 const struct ib_device_ops *hns_roce_dev_ops; 918 const struct ib_device_ops *hns_roce_dev_srq_ops; 919 }; 920 921 struct hns_roce_dev { 922 struct ib_device ib_dev; 923 struct pci_dev *pci_dev; 924 struct device *dev; 925 struct hns_roce_uar priv_uar; 926 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 927 spinlock_t sm_lock; 928 bool active; 929 bool is_reset; 930 bool dis_db; 931 unsigned long reset_cnt; 932 struct hns_roce_ib_iboe iboe; 933 enum hns_roce_device_state state; 934 struct list_head qp_list; /* list of all qps on this dev */ 935 spinlock_t qp_list_lock; /* protect qp_list */ 936 struct list_head dip_list; /* list of all dest ips on this dev */ 937 spinlock_t dip_list_lock; /* protect dip_list */ 938 939 struct list_head pgdir_list; 940 struct mutex pgdir_mutex; 941 int irq[HNS_ROCE_MAX_IRQ_NUM]; 942 u8 __iomem *reg_base; 943 void __iomem *mem_base; 944 struct hns_roce_caps caps; 945 struct xarray qp_table_xa; 946 947 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 948 u64 sys_image_guid; 949 u32 vendor_id; 950 u32 vendor_part_id; 951 u32 hw_rev; 952 void __iomem *priv_addr; 953 954 struct hns_roce_cmdq cmd; 955 struct hns_roce_ida pd_ida; 956 struct hns_roce_ida xrcd_ida; 957 struct hns_roce_ida uar_ida; 958 struct hns_roce_mr_table mr_table; 959 struct hns_roce_cq_table cq_table; 960 struct hns_roce_srq_table srq_table; 961 struct hns_roce_qp_table qp_table; 962 struct hns_roce_eq_table eq_table; 963 struct hns_roce_hem_table qpc_timer_table; 964 struct hns_roce_hem_table cqc_timer_table; 965 /* GMV is the memory area that the driver allocates for the hardware 966 * to store SGID, SMAC and VLAN information. 967 */ 968 struct hns_roce_hem_table gmv_table; 969 970 int cmd_mod; 971 int loop_idc; 972 u32 sdb_offset; 973 u32 odb_offset; 974 const struct hns_roce_hw *hw; 975 void *priv; 976 struct workqueue_struct *irq_workq; 977 struct work_struct ecc_work; 978 u32 func_num; 979 u32 is_vf; 980 u32 cong_algo_tmpl_id; 981 u64 dwqe_page; 982 }; 983 984 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 985 { 986 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 987 } 988 989 static inline struct hns_roce_ucontext 990 *to_hr_ucontext(struct ib_ucontext *ibucontext) 991 { 992 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 993 } 994 995 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 996 { 997 return container_of(ibpd, struct hns_roce_pd, ibpd); 998 } 999 1000 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 1001 { 1002 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1003 } 1004 1005 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1006 { 1007 return container_of(ibah, struct hns_roce_ah, ibah); 1008 } 1009 1010 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1011 { 1012 return container_of(ibmr, struct hns_roce_mr, ibmr); 1013 } 1014 1015 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1016 { 1017 return container_of(ibmw, struct hns_roce_mw, ibmw); 1018 } 1019 1020 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1021 { 1022 return container_of(ibqp, struct hns_roce_qp, ibqp); 1023 } 1024 1025 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1026 { 1027 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1028 } 1029 1030 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1031 { 1032 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1033 } 1034 1035 static inline struct hns_user_mmap_entry * 1036 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) 1037 { 1038 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); 1039 } 1040 1041 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1042 { 1043 writeq(*(u64 *)val, dest); 1044 } 1045 1046 static inline struct hns_roce_qp 1047 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1048 { 1049 return xa_load(&hr_dev->qp_table_xa, qpn); 1050 } 1051 1052 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1053 unsigned int offset) 1054 { 1055 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1056 (offset & ((1 << buf->trunk_shift) - 1)); 1057 } 1058 1059 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1060 unsigned int offset) 1061 { 1062 return buf->trunk_list[offset >> buf->trunk_shift].map + 1063 (offset & ((1 << buf->trunk_shift) - 1)); 1064 } 1065 1066 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1067 { 1068 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1069 } 1070 1071 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1072 1073 static inline u64 to_hr_hw_page_addr(u64 addr) 1074 { 1075 return addr >> HNS_HW_PAGE_SHIFT; 1076 } 1077 1078 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1079 { 1080 return page_shift - HNS_HW_PAGE_SHIFT; 1081 } 1082 1083 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1084 { 1085 if (count > 0) 1086 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1087 1088 return 0; 1089 } 1090 1091 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1092 { 1093 return hr_hw_page_align(count << buf_shift); 1094 } 1095 1096 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1097 { 1098 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1099 } 1100 1101 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1102 { 1103 if (!count) 1104 return 0; 1105 1106 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1107 } 1108 1109 #define DSCP_SHIFT 2 1110 1111 static inline u8 get_tclass(const struct ib_global_route *grh) 1112 { 1113 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1114 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1115 } 1116 1117 void hns_roce_init_uar_table(struct hns_roce_dev *dev); 1118 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1119 1120 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1121 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1122 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1123 u64 out_param); 1124 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1125 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1126 1127 /* hns roce hw need current block and next block addr from mtt */ 1128 #define MTT_MIN_COUNT 2 1129 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1130 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1131 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1132 struct hns_roce_buf_attr *buf_attr, 1133 unsigned int page_shift, struct ib_udata *udata, 1134 unsigned long user_addr); 1135 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1136 struct hns_roce_mtr *mtr); 1137 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1138 dma_addr_t *pages, unsigned int page_cnt); 1139 1140 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1141 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1142 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1143 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1144 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1145 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1146 1147 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1148 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1149 1150 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1151 1152 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1153 struct ib_udata *udata); 1154 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1155 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1156 { 1157 return 0; 1158 } 1159 1160 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1161 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1162 1163 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1164 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1165 u64 virt_addr, int access_flags, 1166 struct ib_udata *udata); 1167 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1168 u64 length, u64 virt_addr, 1169 int mr_access_flags, struct ib_pd *pd, 1170 struct ib_udata *udata); 1171 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1172 u32 max_num_sg); 1173 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1174 unsigned int *sg_offset); 1175 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1176 unsigned long key_to_hw_index(u32 key); 1177 1178 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1179 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1180 1181 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1182 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1183 u32 page_shift, u32 flags); 1184 1185 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1186 int buf_cnt, struct hns_roce_buf *buf, 1187 unsigned int page_shift); 1188 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1189 int buf_cnt, struct ib_umem *umem, 1190 unsigned int page_shift); 1191 1192 int hns_roce_create_srq(struct ib_srq *srq, 1193 struct ib_srq_init_attr *srq_init_attr, 1194 struct ib_udata *udata); 1195 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1196 1197 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1198 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1199 1200 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, 1201 struct ib_udata *udata); 1202 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1203 int attr_mask, struct ib_udata *udata); 1204 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1205 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1206 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1207 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1208 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1209 struct ib_cq *ib_cq); 1210 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1211 struct hns_roce_cq *recv_cq); 1212 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1213 struct hns_roce_cq *recv_cq); 1214 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1215 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1216 struct ib_udata *udata); 1217 __be32 send_ieth(const struct ib_send_wr *wr); 1218 int to_hr_qp_type(int qp_type); 1219 1220 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1221 struct ib_udata *udata); 1222 1223 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1224 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1225 struct hns_roce_db *db); 1226 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1227 struct hns_roce_db *db); 1228 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1229 int order); 1230 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1231 1232 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1233 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1234 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1235 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1236 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1237 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1238 int hns_roce_init(struct hns_roce_dev *hr_dev); 1239 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1240 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq); 1241 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq); 1242 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp); 1243 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1244 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1245 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1246 int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq); 1247 int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq); 1248 struct hns_user_mmap_entry * 1249 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1250 size_t length, 1251 enum hns_roce_mmap_type mmap_type); 1252 #endif /* _HNS_ROCE_DEVICE_H */ 1253