1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 38 #define DRV_NAME "hns_roce" 39 40 #define MAC_ADDR_OCTET_NUM 6 41 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 42 43 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b)) 44 45 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 46 47 #define HNS_ROCE_BA_SIZE (32 * 4096) 48 49 /* Hardware specification only for v1 engine */ 50 #define HNS_ROCE_MIN_CQE_NUM 0x40 51 #define HNS_ROCE_MIN_WQE_NUM 0x20 52 53 /* Hardware specification only for v1 engine */ 54 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 55 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 56 57 #define HNS_ROCE_MAX_IRQ_NUM 34 58 59 #define HNS_ROCE_COMP_VEC_NUM 32 60 61 #define HNS_ROCE_AEQE_VEC_NUM 1 62 #define HNS_ROCE_AEQE_OF_VEC_NUM 1 63 64 /* 4G/4K = 1M */ 65 #define HNS_ROCE_SL_SHIFT 28 66 #define HNS_ROCE_TCLASS_SHIFT 20 67 #define HNS_ROCE_FLOW_LABLE_MASK 0xfffff 68 69 #define HNS_ROCE_MAX_PORTS 6 70 #define HNS_ROCE_MAX_GID_NUM 16 71 #define HNS_ROCE_GID_SIZE 16 72 73 #define MR_TYPE_MR 0x00 74 #define MR_TYPE_DMA 0x03 75 76 #define PKEY_ID 0xffff 77 #define GUID_LEN 8 78 #define NODE_DESC_SIZE 64 79 #define DB_REG_OFFSET 0x1000 80 81 #define SERV_TYPE_RC 0 82 #define SERV_TYPE_RD 1 83 #define SERV_TYPE_UC 2 84 #define SERV_TYPE_UD 3 85 86 #define PAGES_SHIFT_8 8 87 #define PAGES_SHIFT_16 16 88 #define PAGES_SHIFT_24 24 89 #define PAGES_SHIFT_32 32 90 91 enum hns_roce_qp_state { 92 HNS_ROCE_QP_STATE_RST, 93 HNS_ROCE_QP_STATE_INIT, 94 HNS_ROCE_QP_STATE_RTR, 95 HNS_ROCE_QP_STATE_RTS, 96 HNS_ROCE_QP_STATE_SQD, 97 HNS_ROCE_QP_STATE_ERR, 98 HNS_ROCE_QP_NUM_STATE, 99 }; 100 101 enum hns_roce_event { 102 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 103 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 104 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 105 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 106 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 107 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 108 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 109 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 110 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 111 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 112 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 113 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 114 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 115 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 116 /* 0x10 and 0x11 is unused in currently application case */ 117 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 118 HNS_ROCE_EVENT_TYPE_MB = 0x13, 119 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, 120 }; 121 122 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 123 enum { 124 HNS_ROCE_LWQCE_QPC_ERROR = 1, 125 HNS_ROCE_LWQCE_MTU_ERROR = 2, 126 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 127 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 128 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 129 HNS_ROCE_LWQCE_SL_ERROR = 6, 130 HNS_ROCE_LWQCE_PORT_ERROR = 7, 131 }; 132 133 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 134 enum { 135 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 136 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 137 HNS_ROCE_LAVWQE_VA_ERROR = 3, 138 HNS_ROCE_LAVWQE_PD_ERROR = 4, 139 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 140 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 141 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 142 }; 143 144 /* DOORBELL overflow subtype */ 145 enum { 146 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 147 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 148 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 149 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 150 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 151 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 152 }; 153 154 enum { 155 /* RQ&SRQ related operations */ 156 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 157 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 158 }; 159 160 #define HNS_ROCE_CMD_SUCCESS 1 161 162 #define HNS_ROCE_PORT_DOWN 0 163 #define HNS_ROCE_PORT_UP 1 164 165 #define HNS_ROCE_MTT_ENTRY_PER_SEG 8 166 167 #define PAGE_ADDR_SHIFT 12 168 169 struct hns_roce_uar { 170 u64 pfn; 171 unsigned long index; 172 }; 173 174 struct hns_roce_ucontext { 175 struct ib_ucontext ibucontext; 176 struct hns_roce_uar uar; 177 }; 178 179 struct hns_roce_pd { 180 struct ib_pd ibpd; 181 unsigned long pdn; 182 }; 183 184 struct hns_roce_bitmap { 185 /* Bitmap Traversal last a bit which is 1 */ 186 unsigned long last; 187 unsigned long top; 188 unsigned long max; 189 unsigned long reserved_top; 190 unsigned long mask; 191 spinlock_t lock; 192 unsigned long *table; 193 }; 194 195 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */ 196 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */ 197 /* Every bit repesent to a partner free/used status in bitmap */ 198 /* 199 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1 200 * Bit = 1 represent to idle and available; bit = 0: not available 201 */ 202 struct hns_roce_buddy { 203 /* Members point to every order level bitmap */ 204 unsigned long **bits; 205 /* Represent to avail bits of the order level bitmap */ 206 u32 *num_free; 207 int max_order; 208 spinlock_t lock; 209 }; 210 211 /* For Hardware Entry Memory */ 212 struct hns_roce_hem_table { 213 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 214 u32 type; 215 /* HEM array elment num */ 216 unsigned long num_hem; 217 /* HEM entry record obj total num */ 218 unsigned long num_obj; 219 /*Single obj size */ 220 unsigned long obj_size; 221 int lowmem; 222 struct mutex mutex; 223 struct hns_roce_hem **hem; 224 }; 225 226 struct hns_roce_mtt { 227 unsigned long first_seg; 228 int order; 229 int page_shift; 230 }; 231 232 /* Only support 4K page size for mr register */ 233 #define MR_SIZE_4K 0 234 235 struct hns_roce_mr { 236 struct ib_mr ibmr; 237 struct ib_umem *umem; 238 u64 iova; /* MR's virtual orignal addr */ 239 u64 size; /* Address range of MR */ 240 u32 key; /* Key of MR */ 241 u32 pd; /* PD num of MR */ 242 u32 access;/* Access permission of MR */ 243 int enabled; /* MR's active status */ 244 int type; /* MR's register type */ 245 u64 *pbl_buf;/* MR's PBL space */ 246 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */ 247 }; 248 249 struct hns_roce_mr_table { 250 struct hns_roce_bitmap mtpt_bitmap; 251 struct hns_roce_buddy mtt_buddy; 252 struct hns_roce_hem_table mtt_table; 253 struct hns_roce_hem_table mtpt_table; 254 }; 255 256 struct hns_roce_wq { 257 u64 *wrid; /* Work request ID */ 258 spinlock_t lock; 259 int wqe_cnt; /* WQE num */ 260 u32 max_post; 261 int max_gs; 262 int offset; 263 int wqe_shift;/* WQE size */ 264 u32 head; 265 u32 tail; 266 void __iomem *db_reg_l; 267 }; 268 269 struct hns_roce_buf_list { 270 void *buf; 271 dma_addr_t map; 272 }; 273 274 struct hns_roce_buf { 275 struct hns_roce_buf_list direct; 276 struct hns_roce_buf_list *page_list; 277 int nbufs; 278 u32 npages; 279 int page_shift; 280 }; 281 282 struct hns_roce_cq_buf { 283 struct hns_roce_buf hr_buf; 284 struct hns_roce_mtt hr_mtt; 285 }; 286 287 struct hns_roce_cq { 288 struct ib_cq ib_cq; 289 struct hns_roce_cq_buf hr_buf; 290 spinlock_t lock; 291 struct ib_umem *umem; 292 void (*comp)(struct hns_roce_cq *); 293 void (*event)(struct hns_roce_cq *, enum hns_roce_event); 294 295 struct hns_roce_uar *uar; 296 u32 cq_depth; 297 u32 cons_index; 298 void __iomem *cq_db_l; 299 void __iomem *tptr_addr; 300 unsigned long cqn; 301 u32 vector; 302 atomic_t refcount; 303 struct completion free; 304 }; 305 306 struct hns_roce_srq { 307 struct ib_srq ibsrq; 308 int srqn; 309 }; 310 311 struct hns_roce_uar_table { 312 struct hns_roce_bitmap bitmap; 313 }; 314 315 struct hns_roce_qp_table { 316 struct hns_roce_bitmap bitmap; 317 spinlock_t lock; 318 struct hns_roce_hem_table qp_table; 319 struct hns_roce_hem_table irrl_table; 320 }; 321 322 struct hns_roce_cq_table { 323 struct hns_roce_bitmap bitmap; 324 spinlock_t lock; 325 struct radix_tree_root tree; 326 struct hns_roce_hem_table table; 327 }; 328 329 struct hns_roce_raq_table { 330 struct hns_roce_buf_list *e_raq_buf; 331 }; 332 333 struct hns_roce_av { 334 __le32 port_pd; 335 u8 gid_index; 336 u8 stat_rate; 337 u8 hop_limit; 338 __le32 sl_tclass_flowlabel; 339 u8 dgid[HNS_ROCE_GID_SIZE]; 340 u8 mac[6]; 341 __le16 vlan; 342 }; 343 344 struct hns_roce_ah { 345 struct ib_ah ibah; 346 struct hns_roce_av av; 347 }; 348 349 struct hns_roce_cmd_context { 350 struct completion done; 351 int result; 352 int next; 353 u64 out_param; 354 u16 token; 355 }; 356 357 struct hns_roce_cmdq { 358 struct dma_pool *pool; 359 u8 __iomem *hcr; 360 struct mutex hcr_mutex; 361 struct semaphore poll_sem; 362 /* 363 * Event mode: cmd register mutex protection, 364 * ensure to not exceed max_cmds and user use limit region 365 */ 366 struct semaphore event_sem; 367 int max_cmds; 368 spinlock_t context_lock; 369 int free_head; 370 struct hns_roce_cmd_context *context; 371 /* 372 * Result of get integer part 373 * which max_comds compute according a power of 2 374 */ 375 u16 token_mask; 376 /* 377 * Process whether use event mode, init default non-zero 378 * After the event queue of cmd event ready, 379 * can switch into event mode 380 * close device, switch into poll mode(non event mode) 381 */ 382 u8 use_events; 383 u8 toggle; 384 }; 385 386 struct hns_roce_dev; 387 388 struct hns_roce_qp { 389 struct ib_qp ibqp; 390 struct hns_roce_buf hr_buf; 391 struct hns_roce_wq rq; 392 __le64 doorbell_qpn; 393 __le32 sq_signal_bits; 394 u32 sq_next_wqe; 395 int sq_max_wqes_per_wr; 396 int sq_spare_wqes; 397 struct hns_roce_wq sq; 398 399 struct ib_umem *umem; 400 struct hns_roce_mtt mtt; 401 u32 buff_size; 402 struct mutex mutex; 403 u8 port; 404 u8 phy_port; 405 u8 sl; 406 u8 resp_depth; 407 u8 state; 408 u32 access_flags; 409 u32 pkey_index; 410 void (*event)(struct hns_roce_qp *, 411 enum hns_roce_event); 412 unsigned long qpn; 413 414 atomic_t refcount; 415 struct completion free; 416 }; 417 418 struct hns_roce_sqp { 419 struct hns_roce_qp hr_qp; 420 }; 421 422 struct hns_roce_ib_iboe { 423 spinlock_t lock; 424 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 425 struct notifier_block nb; 426 struct notifier_block nb_inet; 427 /* 16 GID is shared by 6 port in v1 engine. */ 428 union ib_gid gid_table[HNS_ROCE_MAX_GID_NUM]; 429 u8 phy_port[HNS_ROCE_MAX_PORTS]; 430 }; 431 432 struct hns_roce_eq { 433 struct hns_roce_dev *hr_dev; 434 void __iomem *doorbell; 435 436 int type_flag;/* Aeq:1 ceq:0 */ 437 int eqn; 438 u32 entries; 439 int log_entries; 440 int eqe_size; 441 int irq; 442 int log_page_size; 443 int cons_index; 444 struct hns_roce_buf_list *buf_list; 445 }; 446 447 struct hns_roce_eq_table { 448 struct hns_roce_eq *eq; 449 void __iomem **eqc_base; 450 }; 451 452 struct hns_roce_caps { 453 u8 num_ports; 454 int gid_table_len[HNS_ROCE_MAX_PORTS]; 455 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 456 int local_ca_ack_delay; 457 int num_uars; 458 u32 phy_num_uars; 459 u32 max_sq_sg; /* 2 */ 460 u32 max_sq_inline; /* 32 */ 461 u32 max_rq_sg; /* 2 */ 462 int num_qps; /* 256k */ 463 u32 max_wqes; /* 16k */ 464 u32 max_sq_desc_sz; /* 64 */ 465 u32 max_rq_desc_sz; /* 64 */ 466 int max_qp_init_rdma; 467 int max_qp_dest_rdma; 468 int num_cqs; 469 int max_cqes; 470 int reserved_cqs; 471 int num_aeq_vectors; /* 1 */ 472 int num_comp_vectors; /* 32 ceq */ 473 int num_other_vectors; 474 int num_mtpts; 475 u32 num_mtt_segs; 476 int reserved_mrws; 477 int reserved_uars; 478 int num_pds; 479 int reserved_pds; 480 u32 mtt_entry_sz; 481 u32 cq_entry_sz; 482 u32 page_size_cap; 483 u32 reserved_lkey; 484 int mtpt_entry_sz; 485 int qpc_entry_sz; 486 int irrl_entry_sz; 487 int cqc_entry_sz; 488 int aeqe_depth; 489 int ceqe_depth[HNS_ROCE_COMP_VEC_NUM]; 490 enum ib_mtu max_mtu; 491 }; 492 493 struct hns_roce_hw { 494 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 495 void (*hw_profile)(struct hns_roce_dev *hr_dev); 496 int (*hw_init)(struct hns_roce_dev *hr_dev); 497 void (*hw_exit)(struct hns_roce_dev *hr_dev); 498 void (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 499 union ib_gid *gid); 500 void (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 501 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 502 enum ib_mtu mtu); 503 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr, 504 unsigned long mtpt_idx); 505 void (*write_cqc)(struct hns_roce_dev *hr_dev, 506 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 507 dma_addr_t dma_handle, int nent, u32 vector); 508 int (*clear_hem)(struct hns_roce_dev *hr_dev, 509 struct hns_roce_hem_table *table, int obj); 510 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 511 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 512 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 513 int attr_mask, enum ib_qp_state cur_state, 514 enum ib_qp_state new_state); 515 int (*destroy_qp)(struct ib_qp *ibqp); 516 int (*post_send)(struct ib_qp *ibqp, struct ib_send_wr *wr, 517 struct ib_send_wr **bad_wr); 518 int (*post_recv)(struct ib_qp *qp, struct ib_recv_wr *recv_wr, 519 struct ib_recv_wr **bad_recv_wr); 520 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 521 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 522 void *priv; 523 }; 524 525 struct hns_roce_dev { 526 struct ib_device ib_dev; 527 struct platform_device *pdev; 528 struct hns_roce_uar priv_uar; 529 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 530 spinlock_t sm_lock; 531 spinlock_t bt_cmd_lock; 532 struct hns_roce_ib_iboe iboe; 533 534 int irq[HNS_ROCE_MAX_IRQ_NUM]; 535 u8 __iomem *reg_base; 536 struct hns_roce_caps caps; 537 struct radix_tree_root qp_table_tree; 538 539 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM]; 540 u64 sys_image_guid; 541 u32 vendor_id; 542 u32 vendor_part_id; 543 u32 hw_rev; 544 void __iomem *priv_addr; 545 546 struct hns_roce_cmdq cmd; 547 struct hns_roce_bitmap pd_bitmap; 548 struct hns_roce_uar_table uar_table; 549 struct hns_roce_mr_table mr_table; 550 struct hns_roce_cq_table cq_table; 551 struct hns_roce_qp_table qp_table; 552 struct hns_roce_eq_table eq_table; 553 554 int cmd_mod; 555 int loop_idc; 556 struct hns_roce_hw *hw; 557 }; 558 559 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 560 { 561 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 562 } 563 564 static inline struct hns_roce_ucontext 565 *to_hr_ucontext(struct ib_ucontext *ibucontext) 566 { 567 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 568 } 569 570 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 571 { 572 return container_of(ibpd, struct hns_roce_pd, ibpd); 573 } 574 575 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 576 { 577 return container_of(ibah, struct hns_roce_ah, ibah); 578 } 579 580 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 581 { 582 return container_of(ibmr, struct hns_roce_mr, ibmr); 583 } 584 585 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 586 { 587 return container_of(ibqp, struct hns_roce_qp, ibqp); 588 } 589 590 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 591 { 592 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 593 } 594 595 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 596 { 597 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 598 } 599 600 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp) 601 { 602 return container_of(hr_qp, struct hns_roce_sqp, hr_qp); 603 } 604 605 static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest) 606 { 607 __raw_writeq(*(u64 *) val, dest); 608 } 609 610 static inline struct hns_roce_qp 611 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 612 { 613 return radix_tree_lookup(&hr_dev->qp_table_tree, 614 qpn & (hr_dev->caps.num_qps - 1)); 615 } 616 617 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 618 { 619 u32 bits_per_long_val = BITS_PER_LONG; 620 621 if (bits_per_long_val == 64 || buf->nbufs == 1) 622 return (char *)(buf->direct.buf) + offset; 623 else 624 return (char *)(buf->page_list[offset >> PAGE_SHIFT].buf) + 625 (offset & (PAGE_SIZE - 1)); 626 } 627 628 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 629 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 630 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 631 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 632 633 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 634 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 635 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 636 u64 out_param); 637 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 638 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 639 640 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift, 641 struct hns_roce_mtt *mtt); 642 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, 643 struct hns_roce_mtt *mtt); 644 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev, 645 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf); 646 647 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 648 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 649 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev); 650 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 651 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 652 653 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 654 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 655 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 656 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 657 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 658 659 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 660 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj); 661 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 662 u32 reserved_bot, u32 resetrved_top); 663 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 664 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 665 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 666 int align, unsigned long *obj); 667 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 668 unsigned long obj, int cnt); 669 670 struct ib_ah *hns_roce_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 671 int hns_roce_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 672 int hns_roce_destroy_ah(struct ib_ah *ah); 673 674 struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev, 675 struct ib_ucontext *context, 676 struct ib_udata *udata); 677 int hns_roce_dealloc_pd(struct ib_pd *pd); 678 679 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 680 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 681 u64 virt_addr, int access_flags, 682 struct ib_udata *udata); 683 int hns_roce_dereg_mr(struct ib_mr *ibmr); 684 685 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, 686 struct hns_roce_buf *buf); 687 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 688 struct hns_roce_buf *buf); 689 690 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, 691 struct hns_roce_mtt *mtt, struct ib_umem *umem); 692 693 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 694 struct ib_qp_init_attr *init_attr, 695 struct ib_udata *udata); 696 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 697 int attr_mask, struct ib_udata *udata); 698 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 699 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n); 700 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 701 struct ib_cq *ib_cq); 702 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 703 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 704 struct hns_roce_cq *recv_cq); 705 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 706 struct hns_roce_cq *recv_cq); 707 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 708 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 709 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, 710 int cnt); 711 __be32 send_ieth(struct ib_send_wr *wr); 712 int to_hr_qp_type(int qp_type); 713 714 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev, 715 const struct ib_cq_init_attr *attr, 716 struct ib_ucontext *context, 717 struct ib_udata *udata); 718 719 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq); 720 721 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 722 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 723 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 724 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 725 726 extern struct hns_roce_hw hns_roce_hw_v1; 727 728 #endif /* _HNS_ROCE_DEVICE_H */ 729