1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 #include "hns_roce_debugfs.h" 39 40 #define PCI_REVISION_ID_HIP08 0x21 41 #define PCI_REVISION_ID_HIP09 0x30 42 43 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 44 45 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 46 47 #define BA_BYTE_LEN 8 48 49 #define HNS_ROCE_MIN_CQE_NUM 0x40 50 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 51 52 #define HNS_ROCE_MAX_IRQ_NUM 128 53 54 #define HNS_ROCE_SGE_IN_WQE 2 55 #define HNS_ROCE_SGE_SHIFT 4 56 57 #define EQ_ENABLE 1 58 #define EQ_DISABLE 0 59 60 #define HNS_ROCE_CEQ 0 61 #define HNS_ROCE_AEQ 1 62 63 #define HNS_ROCE_CEQE_SIZE 0x4 64 #define HNS_ROCE_AEQE_SIZE 0x10 65 66 #define HNS_ROCE_V3_EQE_SIZE 0x40 67 68 #define HNS_ROCE_V2_CQE_SIZE 32 69 #define HNS_ROCE_V3_CQE_SIZE 64 70 71 #define HNS_ROCE_V2_QPC_SZ 256 72 #define HNS_ROCE_V3_QPC_SZ 512 73 74 #define HNS_ROCE_MAX_PORTS 6 75 #define HNS_ROCE_GID_SIZE 16 76 #define HNS_ROCE_SGE_SIZE 16 77 #define HNS_ROCE_DWQE_SIZE 65536 78 79 #define HNS_ROCE_HOP_NUM_0 0xff 80 81 #define MR_TYPE_MR 0x00 82 #define MR_TYPE_FRMR 0x01 83 #define MR_TYPE_DMA 0x03 84 85 #define HNS_ROCE_FRMR_MAX_PA 512 86 87 #define PKEY_ID 0xffff 88 #define NODE_DESC_SIZE 64 89 #define DB_REG_OFFSET 0x1000 90 91 /* Configure to HW for PAGE_SIZE larger than 4KB */ 92 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 93 94 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 95 #define SRQ_DB_REG 0x230 96 97 #define HNS_ROCE_QP_BANK_NUM 8 98 #define HNS_ROCE_CQ_BANK_NUM 4 99 100 #define CQ_BANKID_SHIFT 2 101 #define CQ_BANKID_MASK GENMASK(1, 0) 102 103 #define HNS_ROCE_MAX_CQ_COUNT 0xFFFF 104 #define HNS_ROCE_MAX_CQ_PERIOD 0xFFFF 105 106 enum { 107 SERV_TYPE_RC, 108 SERV_TYPE_UC, 109 SERV_TYPE_RD, 110 SERV_TYPE_UD, 111 SERV_TYPE_XRC = 5, 112 }; 113 114 enum hns_roce_event { 115 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 116 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 117 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 118 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 119 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 120 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 121 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 122 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 123 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 124 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 125 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 126 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 127 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 128 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 129 /* 0x10 and 0x11 is unused in currently application case */ 130 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 131 HNS_ROCE_EVENT_TYPE_MB = 0x13, 132 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 133 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 134 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 135 }; 136 137 enum { 138 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 139 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 140 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 141 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 142 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 143 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 144 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 145 HNS_ROCE_CAP_FLAG_MW = BIT(7), 146 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 147 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 148 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 149 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), 150 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 151 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 152 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 153 HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB = BIT(22), 154 }; 155 156 #define HNS_ROCE_DB_TYPE_COUNT 2 157 #define HNS_ROCE_DB_UNIT_SIZE 4 158 159 enum { 160 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 161 }; 162 163 enum hns_roce_reset_stage { 164 HNS_ROCE_STATE_NON_RST, 165 HNS_ROCE_STATE_RST_BEF_DOWN, 166 HNS_ROCE_STATE_RST_DOWN, 167 HNS_ROCE_STATE_RST_UNINIT, 168 HNS_ROCE_STATE_RST_INIT, 169 HNS_ROCE_STATE_RST_INITED, 170 }; 171 172 enum hns_roce_instance_state { 173 HNS_ROCE_STATE_NON_INIT, 174 HNS_ROCE_STATE_INIT, 175 HNS_ROCE_STATE_INITED, 176 HNS_ROCE_STATE_UNINIT, 177 }; 178 179 enum { 180 HNS_ROCE_RST_DIRECT_RETURN = 0, 181 }; 182 183 #define HNS_ROCE_CMD_SUCCESS 1 184 185 #define HNS_ROCE_MAX_HOP_NUM 3 186 /* The minimum page size is 4K for hardware */ 187 #define HNS_HW_PAGE_SHIFT 12 188 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 189 190 struct hns_roce_uar { 191 u64 pfn; 192 unsigned long index; 193 unsigned long logic_idx; 194 }; 195 196 enum hns_roce_mmap_type { 197 HNS_ROCE_MMAP_TYPE_DB = 1, 198 HNS_ROCE_MMAP_TYPE_DWQE, 199 }; 200 201 struct hns_user_mmap_entry { 202 struct rdma_user_mmap_entry rdma_entry; 203 enum hns_roce_mmap_type mmap_type; 204 u64 address; 205 }; 206 207 struct hns_roce_ucontext { 208 struct ib_ucontext ibucontext; 209 struct hns_roce_uar uar; 210 struct list_head page_list; 211 struct mutex page_mutex; 212 struct hns_user_mmap_entry *db_mmap_entry; 213 u32 config; 214 }; 215 216 struct hns_roce_pd { 217 struct ib_pd ibpd; 218 unsigned long pdn; 219 }; 220 221 struct hns_roce_xrcd { 222 struct ib_xrcd ibxrcd; 223 u32 xrcdn; 224 }; 225 226 struct hns_roce_bitmap { 227 /* Bitmap Traversal last a bit which is 1 */ 228 unsigned long last; 229 unsigned long top; 230 unsigned long max; 231 unsigned long reserved_top; 232 unsigned long mask; 233 spinlock_t lock; 234 unsigned long *table; 235 }; 236 237 struct hns_roce_ida { 238 struct ida ida; 239 u32 min; /* Lowest ID to allocate. */ 240 u32 max; /* Highest ID to allocate. */ 241 }; 242 243 /* For Hardware Entry Memory */ 244 struct hns_roce_hem_table { 245 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 246 u32 type; 247 /* HEM array elment num */ 248 unsigned long num_hem; 249 /* Single obj size */ 250 unsigned long obj_size; 251 unsigned long table_chunk_size; 252 struct mutex mutex; 253 struct hns_roce_hem **hem; 254 u64 **bt_l1; 255 dma_addr_t *bt_l1_dma_addr; 256 u64 **bt_l0; 257 dma_addr_t *bt_l0_dma_addr; 258 }; 259 260 struct hns_roce_buf_region { 261 u32 offset; /* page offset */ 262 u32 count; /* page count */ 263 int hopnum; /* addressing hop num */ 264 }; 265 266 #define HNS_ROCE_MAX_BT_REGION 3 267 #define HNS_ROCE_MAX_BT_LEVEL 3 268 struct hns_roce_hem_list { 269 struct list_head root_bt; 270 /* link all bt dma mem by hop config */ 271 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 272 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 273 dma_addr_t root_ba; /* pointer to the root ba table */ 274 }; 275 276 enum mtr_type { 277 MTR_DEFAULT = 0, 278 MTR_PBL, 279 }; 280 281 struct hns_roce_buf_attr { 282 struct { 283 size_t size; /* region size */ 284 int hopnum; /* multi-hop addressing hop num */ 285 } region[HNS_ROCE_MAX_BT_REGION]; 286 unsigned int region_count; /* valid region count */ 287 unsigned int page_shift; /* buffer page shift */ 288 unsigned int user_access; /* umem access flag */ 289 u64 iova; 290 enum mtr_type type; 291 bool mtt_only; /* only alloc buffer-required MTT memory */ 292 bool adaptive; /* adaptive for page_shift and hopnum */ 293 }; 294 295 struct hns_roce_hem_cfg { 296 dma_addr_t root_ba; /* root BA table's address */ 297 bool is_direct; /* addressing without BA table */ 298 unsigned int ba_pg_shift; /* BA table page shift */ 299 unsigned int buf_pg_shift; /* buffer page shift */ 300 unsigned int buf_pg_count; /* buffer page count */ 301 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 302 unsigned int region_count; 303 }; 304 305 /* memory translate region */ 306 struct hns_roce_mtr { 307 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 308 struct ib_umem *umem; /* user space buffer */ 309 struct hns_roce_buf *kmem; /* kernel space buffer */ 310 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 311 }; 312 313 struct hns_roce_mw { 314 struct ib_mw ibmw; 315 u32 pdn; 316 u32 rkey; 317 int enabled; /* MW's active status */ 318 u32 pbl_hop_num; 319 u32 pbl_ba_pg_sz; 320 u32 pbl_buf_pg_sz; 321 }; 322 323 struct hns_roce_mr { 324 struct ib_mr ibmr; 325 u64 iova; /* MR's virtual original addr */ 326 u64 size; /* Address range of MR */ 327 u32 key; /* Key of MR */ 328 u32 pd; /* PD num of MR */ 329 u32 access; /* Access permission of MR */ 330 int enabled; /* MR's active status */ 331 int type; /* MR's register type */ 332 u32 pbl_hop_num; /* multi-hop number */ 333 struct hns_roce_mtr pbl_mtr; 334 u32 npages; 335 dma_addr_t *page_list; 336 }; 337 338 struct hns_roce_mr_table { 339 struct hns_roce_ida mtpt_ida; 340 struct hns_roce_hem_table mtpt_table; 341 }; 342 343 struct hns_roce_wq { 344 u64 *wrid; /* Work request ID */ 345 spinlock_t lock; 346 u32 wqe_cnt; /* WQE num */ 347 u32 max_gs; 348 u32 rsv_sge; 349 u32 offset; 350 u32 wqe_shift; /* WQE size */ 351 u32 head; 352 u32 tail; 353 void __iomem *db_reg; 354 u32 ext_sge_cnt; 355 }; 356 357 struct hns_roce_sge { 358 unsigned int sge_cnt; /* SGE num */ 359 u32 offset; 360 u32 sge_shift; /* SGE size */ 361 }; 362 363 struct hns_roce_buf_list { 364 void *buf; 365 dma_addr_t map; 366 }; 367 368 /* 369 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 370 * dma address range. 371 * 372 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 373 * 374 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 375 * the allocated size is smaller than the required size. 376 */ 377 enum { 378 HNS_ROCE_BUF_DIRECT = BIT(0), 379 HNS_ROCE_BUF_NOSLEEP = BIT(1), 380 HNS_ROCE_BUF_NOFAIL = BIT(2), 381 }; 382 383 struct hns_roce_buf { 384 struct hns_roce_buf_list *trunk_list; 385 u32 ntrunks; 386 u32 npages; 387 unsigned int trunk_shift; 388 unsigned int page_shift; 389 }; 390 391 struct hns_roce_db_pgdir { 392 struct list_head list; 393 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 394 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 395 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 396 u32 *page; 397 dma_addr_t db_dma; 398 }; 399 400 struct hns_roce_user_db_page { 401 struct list_head list; 402 struct ib_umem *umem; 403 unsigned long user_virt; 404 refcount_t refcount; 405 }; 406 407 struct hns_roce_db { 408 u32 *db_record; 409 union { 410 struct hns_roce_db_pgdir *pgdir; 411 struct hns_roce_user_db_page *user_page; 412 } u; 413 dma_addr_t dma; 414 void *virt_addr; 415 unsigned long index; 416 unsigned long order; 417 }; 418 419 struct hns_roce_cq { 420 struct ib_cq ib_cq; 421 struct hns_roce_mtr mtr; 422 struct hns_roce_db db; 423 u32 flags; 424 spinlock_t lock; 425 u32 cq_depth; 426 u32 cons_index; 427 u32 *set_ci_db; 428 void __iomem *db_reg; 429 int arm_sn; 430 int cqe_size; 431 unsigned long cqn; 432 u32 vector; 433 refcount_t refcount; 434 struct completion free; 435 struct list_head sq_list; /* all qps on this send cq */ 436 struct list_head rq_list; /* all qps on this recv cq */ 437 int is_armed; /* cq is armed */ 438 struct list_head node; /* all armed cqs are on a list */ 439 }; 440 441 struct hns_roce_idx_que { 442 struct hns_roce_mtr mtr; 443 u32 entry_shift; 444 unsigned long *bitmap; 445 u32 head; 446 u32 tail; 447 }; 448 449 struct hns_roce_srq { 450 struct ib_srq ibsrq; 451 unsigned long srqn; 452 u32 wqe_cnt; 453 int max_gs; 454 u32 rsv_sge; 455 u32 wqe_shift; 456 u32 cqn; 457 u32 xrcdn; 458 void __iomem *db_reg; 459 460 refcount_t refcount; 461 struct completion free; 462 463 struct hns_roce_mtr buf_mtr; 464 465 u64 *wrid; 466 struct hns_roce_idx_que idx_que; 467 spinlock_t lock; 468 struct mutex mutex; 469 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 470 struct hns_roce_db rdb; 471 u32 cap_flags; 472 }; 473 474 struct hns_roce_uar_table { 475 struct hns_roce_bitmap bitmap; 476 }; 477 478 struct hns_roce_bank { 479 struct ida ida; 480 u32 inuse; /* Number of IDs allocated */ 481 u32 min; /* Lowest ID to allocate. */ 482 u32 max; /* Highest ID to allocate. */ 483 u32 next; /* Next ID to allocate. */ 484 }; 485 486 struct hns_roce_idx_table { 487 u32 *spare_idx; 488 u32 head; 489 u32 tail; 490 }; 491 492 struct hns_roce_qp_table { 493 struct hns_roce_hem_table qp_table; 494 struct hns_roce_hem_table irrl_table; 495 struct hns_roce_hem_table trrl_table; 496 struct hns_roce_hem_table sccc_table; 497 struct mutex scc_mutex; 498 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 499 struct mutex bank_mutex; 500 struct hns_roce_idx_table idx_table; 501 }; 502 503 struct hns_roce_cq_table { 504 struct xarray array; 505 struct hns_roce_hem_table table; 506 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 507 struct mutex bank_mutex; 508 }; 509 510 struct hns_roce_srq_table { 511 struct hns_roce_ida srq_ida; 512 struct xarray xa; 513 struct hns_roce_hem_table table; 514 }; 515 516 struct hns_roce_av { 517 u8 port; 518 u8 gid_index; 519 u8 stat_rate; 520 u8 hop_limit; 521 u32 flowlabel; 522 u16 udp_sport; 523 u8 sl; 524 u8 tclass; 525 u8 dgid[HNS_ROCE_GID_SIZE]; 526 u8 mac[ETH_ALEN]; 527 u16 vlan_id; 528 u8 vlan_en; 529 }; 530 531 struct hns_roce_ah { 532 struct ib_ah ibah; 533 struct hns_roce_av av; 534 }; 535 536 struct hns_roce_cmd_context { 537 struct completion done; 538 int result; 539 int next; 540 u64 out_param; 541 u16 token; 542 u16 busy; 543 }; 544 545 enum hns_roce_cmdq_state { 546 HNS_ROCE_CMDQ_STATE_NORMAL, 547 HNS_ROCE_CMDQ_STATE_FATAL_ERR, 548 }; 549 550 struct hns_roce_cmdq { 551 struct dma_pool *pool; 552 struct semaphore poll_sem; 553 /* 554 * Event mode: cmd register mutex protection, 555 * ensure to not exceed max_cmds and user use limit region 556 */ 557 struct semaphore event_sem; 558 int max_cmds; 559 spinlock_t context_lock; 560 int free_head; 561 struct hns_roce_cmd_context *context; 562 /* 563 * Process whether use event mode, init default non-zero 564 * After the event queue of cmd event ready, 565 * can switch into event mode 566 * close device, switch into poll mode(non event mode) 567 */ 568 u8 use_events; 569 enum hns_roce_cmdq_state state; 570 }; 571 572 struct hns_roce_cmd_mailbox { 573 void *buf; 574 dma_addr_t dma; 575 }; 576 577 struct hns_roce_mbox_msg { 578 u64 in_param; 579 u64 out_param; 580 u8 cmd; 581 u32 tag; 582 u16 token; 583 u8 event_en; 584 }; 585 586 struct hns_roce_dev; 587 588 enum { 589 HNS_ROCE_FLUSH_FLAG = 0, 590 }; 591 592 struct hns_roce_work { 593 struct hns_roce_dev *hr_dev; 594 struct work_struct work; 595 int event_type; 596 int sub_type; 597 u32 queue_num; 598 }; 599 600 enum hns_roce_cong_type { 601 CONG_TYPE_DCQCN, 602 CONG_TYPE_LDCP, 603 CONG_TYPE_HC3, 604 CONG_TYPE_DIP, 605 }; 606 607 struct hns_roce_qp { 608 struct ib_qp ibqp; 609 struct hns_roce_wq rq; 610 struct hns_roce_db rdb; 611 struct hns_roce_db sdb; 612 unsigned long en_flags; 613 enum ib_sig_type sq_signal_bits; 614 struct hns_roce_wq sq; 615 616 struct hns_roce_mtr mtr; 617 618 u32 buff_size; 619 struct mutex mutex; 620 u8 port; 621 u8 phy_port; 622 u8 sl; 623 u8 resp_depth; 624 u8 state; 625 u32 atomic_rd_en; 626 u32 qkey; 627 void (*event)(struct hns_roce_qp *qp, 628 enum hns_roce_event event_type); 629 unsigned long qpn; 630 631 u32 xrcdn; 632 633 refcount_t refcount; 634 struct completion free; 635 636 struct hns_roce_sge sge; 637 u32 next_sge; 638 enum ib_mtu path_mtu; 639 u32 max_inline_data; 640 u8 free_mr_en; 641 642 /* 0: flush needed, 1: unneeded */ 643 unsigned long flush_flag; 644 struct hns_roce_work flush_work; 645 struct list_head node; /* all qps are on a list */ 646 struct list_head rq_node; /* all recv qps are on a list */ 647 struct list_head sq_node; /* all send qps are on a list */ 648 struct hns_user_mmap_entry *dwqe_mmap_entry; 649 u32 config; 650 enum hns_roce_cong_type cong_type; 651 u8 tc_mode; 652 u8 priority; 653 }; 654 655 struct hns_roce_ib_iboe { 656 spinlock_t lock; 657 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 658 struct notifier_block nb; 659 u8 phy_port[HNS_ROCE_MAX_PORTS]; 660 }; 661 662 struct hns_roce_ceqe { 663 __le32 comp; 664 __le32 rsv[15]; 665 }; 666 667 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l) 668 669 #define CEQE_CQN CEQE_FIELD_LOC(23, 0) 670 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31) 671 672 struct hns_roce_aeqe { 673 __le32 asyn; 674 union { 675 struct { 676 __le32 num; 677 u32 rsv0; 678 u32 rsv1; 679 } queue_event; 680 681 struct { 682 __le64 out_param; 683 __le16 token; 684 u8 status; 685 u8 rsv0; 686 } __packed cmd; 687 } event; 688 __le32 rsv[12]; 689 }; 690 691 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l) 692 693 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0) 694 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8) 695 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31) 696 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32) 697 698 struct hns_roce_eq { 699 struct hns_roce_dev *hr_dev; 700 void __iomem *db_reg; 701 702 int type_flag; /* Aeq:1 ceq:0 */ 703 int eqn; 704 u32 entries; 705 int eqe_size; 706 int irq; 707 u32 cons_index; 708 int over_ignore; 709 int coalesce; 710 int arm_st; 711 int hop_num; 712 struct hns_roce_mtr mtr; 713 u16 eq_max_cnt; 714 u32 eq_period; 715 int shift; 716 int event_type; 717 int sub_type; 718 }; 719 720 struct hns_roce_eq_table { 721 struct hns_roce_eq *eq; 722 }; 723 724 struct hns_roce_caps { 725 u64 fw_ver; 726 u8 num_ports; 727 int gid_table_len[HNS_ROCE_MAX_PORTS]; 728 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 729 int local_ca_ack_delay; 730 int num_uars; 731 u32 phy_num_uars; 732 u32 max_sq_sg; 733 u32 max_sq_inline; 734 u32 max_rq_sg; 735 u32 rsv0; 736 u32 num_qps; 737 u32 reserved_qps; 738 u32 num_srqs; 739 u32 max_wqes; 740 u32 max_srq_wrs; 741 u32 max_srq_sges; 742 u32 max_sq_desc_sz; 743 u32 max_rq_desc_sz; 744 u32 rsv2; 745 int max_qp_init_rdma; 746 int max_qp_dest_rdma; 747 u32 num_cqs; 748 u32 max_cqes; 749 u32 min_cqes; 750 u32 min_wqes; 751 u32 reserved_cqs; 752 u32 reserved_srqs; 753 int num_aeq_vectors; 754 int num_comp_vectors; 755 int num_other_vectors; 756 u32 num_mtpts; 757 u32 rsv1; 758 u32 num_srqwqe_segs; 759 u32 num_idx_segs; 760 int reserved_mrws; 761 int reserved_uars; 762 int num_pds; 763 int reserved_pds; 764 u32 num_xrcds; 765 u32 reserved_xrcds; 766 u32 mtt_entry_sz; 767 u32 cqe_sz; 768 u32 page_size_cap; 769 u32 reserved_lkey; 770 int mtpt_entry_sz; 771 int qpc_sz; 772 int irrl_entry_sz; 773 int trrl_entry_sz; 774 int cqc_entry_sz; 775 int sccc_sz; 776 int qpc_timer_entry_sz; 777 int cqc_timer_entry_sz; 778 int srqc_entry_sz; 779 int idx_entry_sz; 780 u32 pbl_ba_pg_sz; 781 u32 pbl_buf_pg_sz; 782 u32 pbl_hop_num; 783 int aeqe_depth; 784 int ceqe_depth; 785 u32 aeqe_size; 786 u32 ceqe_size; 787 enum ib_mtu max_mtu; 788 u32 qpc_bt_num; 789 u32 qpc_timer_bt_num; 790 u32 srqc_bt_num; 791 u32 cqc_bt_num; 792 u32 cqc_timer_bt_num; 793 u32 mpt_bt_num; 794 u32 eqc_bt_num; 795 u32 smac_bt_num; 796 u32 sgid_bt_num; 797 u32 sccc_bt_num; 798 u32 gmv_bt_num; 799 u32 qpc_ba_pg_sz; 800 u32 qpc_buf_pg_sz; 801 u32 qpc_hop_num; 802 u32 srqc_ba_pg_sz; 803 u32 srqc_buf_pg_sz; 804 u32 srqc_hop_num; 805 u32 cqc_ba_pg_sz; 806 u32 cqc_buf_pg_sz; 807 u32 cqc_hop_num; 808 u32 mpt_ba_pg_sz; 809 u32 mpt_buf_pg_sz; 810 u32 mpt_hop_num; 811 u32 mtt_ba_pg_sz; 812 u32 mtt_buf_pg_sz; 813 u32 mtt_hop_num; 814 u32 wqe_sq_hop_num; 815 u32 wqe_sge_hop_num; 816 u32 wqe_rq_hop_num; 817 u32 sccc_ba_pg_sz; 818 u32 sccc_buf_pg_sz; 819 u32 sccc_hop_num; 820 u32 qpc_timer_ba_pg_sz; 821 u32 qpc_timer_buf_pg_sz; 822 u32 qpc_timer_hop_num; 823 u32 cqc_timer_ba_pg_sz; 824 u32 cqc_timer_buf_pg_sz; 825 u32 cqc_timer_hop_num; 826 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 827 u32 cqe_buf_pg_sz; 828 u32 cqe_hop_num; 829 u32 srqwqe_ba_pg_sz; 830 u32 srqwqe_buf_pg_sz; 831 u32 srqwqe_hop_num; 832 u32 idx_ba_pg_sz; 833 u32 idx_buf_pg_sz; 834 u32 idx_hop_num; 835 u32 eqe_ba_pg_sz; 836 u32 eqe_buf_pg_sz; 837 u32 eqe_hop_num; 838 u32 gmv_entry_num; 839 u32 gmv_entry_sz; 840 u32 gmv_ba_pg_sz; 841 u32 gmv_buf_pg_sz; 842 u32 gmv_hop_num; 843 u32 sl_num; 844 u32 llm_buf_pg_sz; 845 u32 chunk_sz; /* chunk size in non multihop mode */ 846 u64 flags; 847 u16 default_ceq_max_cnt; 848 u16 default_ceq_period; 849 u16 default_aeq_max_cnt; 850 u16 default_aeq_period; 851 u16 default_aeq_arm_st; 852 u16 default_ceq_arm_st; 853 u8 cong_cap; 854 enum hns_roce_cong_type default_cong_type; 855 }; 856 857 enum hns_roce_device_state { 858 HNS_ROCE_DEVICE_STATE_INITED, 859 HNS_ROCE_DEVICE_STATE_RST_DOWN, 860 HNS_ROCE_DEVICE_STATE_UNINIT, 861 }; 862 863 enum hns_roce_hw_pkt_stat_index { 864 HNS_ROCE_HW_RX_RC_PKT_CNT, 865 HNS_ROCE_HW_RX_UC_PKT_CNT, 866 HNS_ROCE_HW_RX_UD_PKT_CNT, 867 HNS_ROCE_HW_RX_XRC_PKT_CNT, 868 HNS_ROCE_HW_RX_PKT_CNT, 869 HNS_ROCE_HW_RX_ERR_PKT_CNT, 870 HNS_ROCE_HW_RX_CNP_PKT_CNT, 871 HNS_ROCE_HW_TX_RC_PKT_CNT, 872 HNS_ROCE_HW_TX_UC_PKT_CNT, 873 HNS_ROCE_HW_TX_UD_PKT_CNT, 874 HNS_ROCE_HW_TX_XRC_PKT_CNT, 875 HNS_ROCE_HW_TX_PKT_CNT, 876 HNS_ROCE_HW_TX_ERR_PKT_CNT, 877 HNS_ROCE_HW_TX_CNP_PKT_CNT, 878 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT, 879 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT, 880 HNS_ROCE_HW_ECN_DB_CNT, 881 HNS_ROCE_HW_RX_BUF_CNT, 882 HNS_ROCE_HW_TRP_RX_SOF_CNT, 883 HNS_ROCE_HW_CQ_CQE_CNT, 884 HNS_ROCE_HW_CQ_POE_CNT, 885 HNS_ROCE_HW_CQ_NOTIFY_CNT, 886 HNS_ROCE_HW_CNT_TOTAL 887 }; 888 889 enum hns_roce_sw_dfx_stat_index { 890 HNS_ROCE_DFX_AEQE_CNT, 891 HNS_ROCE_DFX_CEQE_CNT, 892 HNS_ROCE_DFX_CMDS_CNT, 893 HNS_ROCE_DFX_CMDS_ERR_CNT, 894 HNS_ROCE_DFX_MBX_POSTED_CNT, 895 HNS_ROCE_DFX_MBX_POLLED_CNT, 896 HNS_ROCE_DFX_MBX_EVENT_CNT, 897 HNS_ROCE_DFX_QP_CREATE_ERR_CNT, 898 HNS_ROCE_DFX_QP_MODIFY_ERR_CNT, 899 HNS_ROCE_DFX_CQ_CREATE_ERR_CNT, 900 HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT, 901 HNS_ROCE_DFX_SRQ_CREATE_ERR_CNT, 902 HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT, 903 HNS_ROCE_DFX_XRCD_ALLOC_ERR_CNT, 904 HNS_ROCE_DFX_MR_REG_ERR_CNT, 905 HNS_ROCE_DFX_MR_REREG_ERR_CNT, 906 HNS_ROCE_DFX_AH_CREATE_ERR_CNT, 907 HNS_ROCE_DFX_MMAP_ERR_CNT, 908 HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT, 909 HNS_ROCE_DFX_CNT_TOTAL 910 }; 911 912 struct hns_roce_hw { 913 int (*cmq_init)(struct hns_roce_dev *hr_dev); 914 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 915 int (*hw_profile)(struct hns_roce_dev *hr_dev); 916 int (*hw_init)(struct hns_roce_dev *hr_dev); 917 void (*hw_exit)(struct hns_roce_dev *hr_dev); 918 int (*post_mbox)(struct hns_roce_dev *hr_dev, 919 struct hns_roce_mbox_msg *mbox_msg); 920 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); 921 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 922 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, 923 const union ib_gid *gid, const struct ib_gid_attr *attr); 924 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, 925 const u8 *addr); 926 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 927 struct hns_roce_mr *mr); 928 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 929 struct hns_roce_mr *mr, int flags, 930 void *mb_buf); 931 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); 932 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 933 void (*write_cqc)(struct hns_roce_dev *hr_dev, 934 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 935 dma_addr_t dma_handle); 936 int (*set_hem)(struct hns_roce_dev *hr_dev, 937 struct hns_roce_hem_table *table, int obj, u32 step_idx); 938 int (*clear_hem)(struct hns_roce_dev *hr_dev, 939 struct hns_roce_hem_table *table, int obj, 940 u32 step_idx); 941 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 942 int attr_mask, enum ib_qp_state cur_state, 943 enum ib_qp_state new_state, struct ib_udata *udata); 944 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 945 struct hns_roce_qp *hr_qp); 946 void (*dereg_mr)(struct hns_roce_dev *hr_dev); 947 int (*init_eq)(struct hns_roce_dev *hr_dev); 948 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 949 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 950 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 951 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 952 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 953 int (*query_srqc)(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer); 954 int (*query_sccc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 955 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 956 u64 *stats, u32 port, int *hw_counters); 957 int (*get_dscp)(struct hns_roce_dev *hr_dev, u8 dscp, 958 u8 *tc_mode, u8 *priority); 959 const struct ib_device_ops *hns_roce_dev_ops; 960 const struct ib_device_ops *hns_roce_dev_srq_ops; 961 }; 962 963 struct hns_roce_dev { 964 struct ib_device ib_dev; 965 struct pci_dev *pci_dev; 966 struct device *dev; 967 struct hns_roce_uar priv_uar; 968 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 969 spinlock_t sm_lock; 970 bool active; 971 bool is_reset; 972 bool dis_db; 973 unsigned long reset_cnt; 974 struct hns_roce_ib_iboe iboe; 975 enum hns_roce_device_state state; 976 struct list_head qp_list; /* list of all qps on this dev */ 977 spinlock_t qp_list_lock; /* protect qp_list */ 978 struct list_head dip_list; /* list of all dest ips on this dev */ 979 spinlock_t dip_list_lock; /* protect dip_list */ 980 981 struct list_head pgdir_list; 982 struct mutex pgdir_mutex; 983 int irq[HNS_ROCE_MAX_IRQ_NUM]; 984 u8 __iomem *reg_base; 985 void __iomem *mem_base; 986 struct hns_roce_caps caps; 987 struct xarray qp_table_xa; 988 989 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 990 u64 sys_image_guid; 991 u32 vendor_id; 992 u32 vendor_part_id; 993 u32 hw_rev; 994 void __iomem *priv_addr; 995 996 struct hns_roce_cmdq cmd; 997 struct hns_roce_ida pd_ida; 998 struct hns_roce_ida xrcd_ida; 999 struct hns_roce_ida uar_ida; 1000 struct hns_roce_mr_table mr_table; 1001 struct hns_roce_cq_table cq_table; 1002 struct hns_roce_srq_table srq_table; 1003 struct hns_roce_qp_table qp_table; 1004 struct hns_roce_eq_table eq_table; 1005 struct hns_roce_hem_table qpc_timer_table; 1006 struct hns_roce_hem_table cqc_timer_table; 1007 /* GMV is the memory area that the driver allocates for the hardware 1008 * to store SGID, SMAC and VLAN information. 1009 */ 1010 struct hns_roce_hem_table gmv_table; 1011 1012 int cmd_mod; 1013 int loop_idc; 1014 u32 sdb_offset; 1015 u32 odb_offset; 1016 const struct hns_roce_hw *hw; 1017 void *priv; 1018 struct workqueue_struct *irq_workq; 1019 struct work_struct ecc_work; 1020 u32 func_num; 1021 u32 is_vf; 1022 u32 cong_algo_tmpl_id; 1023 u64 dwqe_page; 1024 struct hns_roce_dev_debugfs dbgfs; 1025 atomic64_t *dfx_cnt; 1026 }; 1027 1028 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1029 { 1030 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1031 } 1032 1033 static inline struct hns_roce_ucontext 1034 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1035 { 1036 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1037 } 1038 1039 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1040 { 1041 return container_of(ibpd, struct hns_roce_pd, ibpd); 1042 } 1043 1044 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 1045 { 1046 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1047 } 1048 1049 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1050 { 1051 return container_of(ibah, struct hns_roce_ah, ibah); 1052 } 1053 1054 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1055 { 1056 return container_of(ibmr, struct hns_roce_mr, ibmr); 1057 } 1058 1059 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1060 { 1061 return container_of(ibmw, struct hns_roce_mw, ibmw); 1062 } 1063 1064 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1065 { 1066 return container_of(ibqp, struct hns_roce_qp, ibqp); 1067 } 1068 1069 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1070 { 1071 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1072 } 1073 1074 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1075 { 1076 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1077 } 1078 1079 static inline struct hns_user_mmap_entry * 1080 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) 1081 { 1082 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); 1083 } 1084 1085 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1086 { 1087 writeq(*(u64 *)val, dest); 1088 } 1089 1090 static inline struct hns_roce_qp 1091 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1092 { 1093 return xa_load(&hr_dev->qp_table_xa, qpn); 1094 } 1095 1096 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1097 unsigned int offset) 1098 { 1099 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1100 (offset & ((1 << buf->trunk_shift) - 1)); 1101 } 1102 1103 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1104 unsigned int offset) 1105 { 1106 return buf->trunk_list[offset >> buf->trunk_shift].map + 1107 (offset & ((1 << buf->trunk_shift) - 1)); 1108 } 1109 1110 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1111 { 1112 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1113 } 1114 1115 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1116 1117 static inline u64 to_hr_hw_page_addr(u64 addr) 1118 { 1119 return addr >> HNS_HW_PAGE_SHIFT; 1120 } 1121 1122 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1123 { 1124 return page_shift - HNS_HW_PAGE_SHIFT; 1125 } 1126 1127 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1128 { 1129 if (count > 0) 1130 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1131 1132 return 0; 1133 } 1134 1135 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1136 { 1137 return hr_hw_page_align(count << buf_shift); 1138 } 1139 1140 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1141 { 1142 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1143 } 1144 1145 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1146 { 1147 if (!count) 1148 return 0; 1149 1150 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1151 } 1152 1153 #define DSCP_SHIFT 2 1154 1155 static inline u8 get_tclass(const struct ib_global_route *grh) 1156 { 1157 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1158 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1159 } 1160 1161 void hns_roce_init_uar_table(struct hns_roce_dev *dev); 1162 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1163 1164 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1165 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1166 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1167 u64 out_param); 1168 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1169 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1170 1171 /* hns roce hw need current block and next block addr from mtt */ 1172 #define MTT_MIN_COUNT 2 1173 static inline dma_addr_t hns_roce_get_mtr_ba(struct hns_roce_mtr *mtr) 1174 { 1175 return mtr->hem_cfg.root_ba; 1176 } 1177 1178 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1179 u32 offset, u64 *mtt_buf, int mtt_max); 1180 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1181 struct hns_roce_buf_attr *buf_attr, 1182 unsigned int page_shift, struct ib_udata *udata, 1183 unsigned long user_addr); 1184 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1185 struct hns_roce_mtr *mtr); 1186 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1187 dma_addr_t *pages, unsigned int page_cnt); 1188 1189 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1190 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1191 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1192 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1193 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1194 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1195 1196 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1197 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1198 1199 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1200 1201 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1202 struct ib_udata *udata); 1203 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1204 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1205 { 1206 return 0; 1207 } 1208 1209 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1210 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1211 1212 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1213 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1214 u64 virt_addr, int access_flags, 1215 struct ib_udata *udata); 1216 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1217 u64 length, u64 virt_addr, 1218 int mr_access_flags, struct ib_pd *pd, 1219 struct ib_udata *udata); 1220 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1221 u32 max_num_sg); 1222 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1223 unsigned int *sg_offset); 1224 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1225 unsigned long key_to_hw_index(u32 key); 1226 1227 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1228 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1229 1230 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1231 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1232 u32 page_shift, u32 flags); 1233 1234 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1235 int buf_cnt, struct hns_roce_buf *buf, 1236 unsigned int page_shift); 1237 int hns_roce_get_umem_bufs(dma_addr_t *bufs, 1238 int buf_cnt, struct ib_umem *umem, 1239 unsigned int page_shift); 1240 1241 int hns_roce_create_srq(struct ib_srq *srq, 1242 struct ib_srq_init_attr *srq_init_attr, 1243 struct ib_udata *udata); 1244 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1245 1246 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1247 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1248 1249 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, 1250 struct ib_udata *udata); 1251 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1252 int attr_mask, struct ib_udata *udata); 1253 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1254 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1255 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1256 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1257 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1258 struct ib_cq *ib_cq); 1259 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1260 struct hns_roce_cq *recv_cq); 1261 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1262 struct hns_roce_cq *recv_cq); 1263 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1264 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1265 struct ib_udata *udata); 1266 __be32 send_ieth(const struct ib_send_wr *wr); 1267 int to_hr_qp_type(int qp_type); 1268 1269 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1270 struct ib_udata *udata); 1271 1272 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1273 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1274 struct hns_roce_db *db); 1275 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1276 struct hns_roce_db *db); 1277 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1278 int order); 1279 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1280 1281 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1282 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1283 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1284 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1285 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1286 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1287 int hns_roce_init(struct hns_roce_dev *hr_dev); 1288 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1289 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq); 1290 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq); 1291 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp); 1292 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1293 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1294 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1295 int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq); 1296 int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq); 1297 struct hns_user_mmap_entry * 1298 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1299 size_t length, 1300 enum hns_roce_mmap_type mmap_type); 1301 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl); 1302 1303 #endif /* _HNS_ROCE_DEVICE_H */ 1304