1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/pci.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/uverbs_ioctl.h> 36 #include "hns_roce_device.h" 37 #include "hns_roce_cmd.h" 38 #include "hns_roce_hem.h" 39 #include "hns_roce_common.h" 40 41 void hns_roce_put_cq_bankid_for_uctx(struct hns_roce_ucontext *uctx) 42 { 43 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->ibucontext.device); 44 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 45 46 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) 47 return; 48 49 mutex_lock(&cq_table->bank_mutex); 50 cq_table->ctx_num[uctx->cq_bank_id]--; 51 mutex_unlock(&cq_table->bank_mutex); 52 } 53 54 void hns_roce_get_cq_bankid_for_uctx(struct hns_roce_ucontext *uctx) 55 { 56 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->ibucontext.device); 57 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 58 u32 least_load = cq_table->ctx_num[0]; 59 u8 bankid = 0; 60 u8 i; 61 62 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) 63 return; 64 65 mutex_lock(&cq_table->bank_mutex); 66 for (i = 1; i < HNS_ROCE_CQ_BANK_NUM; i++) { 67 if (cq_table->ctx_num[i] < least_load) { 68 least_load = cq_table->ctx_num[i]; 69 bankid = i; 70 } 71 } 72 cq_table->ctx_num[bankid]++; 73 mutex_unlock(&cq_table->bank_mutex); 74 75 uctx->cq_bank_id = bankid; 76 } 77 78 static u8 get_least_load_bankid_for_cq(struct hns_roce_bank *bank) 79 { 80 u32 least_load = bank[0].inuse; 81 u8 bankid = 0; 82 u32 bankcnt; 83 u8 i; 84 85 for (i = 1; i < HNS_ROCE_CQ_BANK_NUM; i++) { 86 bankcnt = bank[i].inuse; 87 if (bankcnt < least_load) { 88 least_load = bankcnt; 89 bankid = i; 90 } 91 } 92 93 return bankid; 94 } 95 96 static u8 select_cq_bankid(struct hns_roce_dev *hr_dev, 97 struct hns_roce_bank *bank, struct ib_udata *udata) 98 { 99 struct hns_roce_ucontext *uctx = udata ? 100 rdma_udata_to_drv_context(udata, struct hns_roce_ucontext, 101 ibucontext) : NULL; 102 103 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 104 return uctx ? uctx->cq_bank_id : 0; 105 106 return get_least_load_bankid_for_cq(bank); 107 } 108 109 static int alloc_cqn(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq, 110 struct ib_udata *udata) 111 { 112 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 113 struct hns_roce_bank *bank; 114 u8 bankid; 115 int id; 116 117 mutex_lock(&cq_table->bank_mutex); 118 bankid = select_cq_bankid(hr_dev, cq_table->bank, udata); 119 bank = &cq_table->bank[bankid]; 120 121 id = ida_alloc_range(&bank->ida, bank->min, bank->max, GFP_KERNEL); 122 if (id < 0) { 123 mutex_unlock(&cq_table->bank_mutex); 124 return id; 125 } 126 127 /* the lower 2 bits is bankid */ 128 hr_cq->cqn = (id << CQ_BANKID_SHIFT) | bankid; 129 bank->inuse++; 130 mutex_unlock(&cq_table->bank_mutex); 131 132 return 0; 133 } 134 135 static inline u8 get_cq_bankid(unsigned long cqn) 136 { 137 /* The lower 2 bits of CQN are used to hash to different banks */ 138 return (u8)(cqn & GENMASK(1, 0)); 139 } 140 141 static void free_cqn(struct hns_roce_dev *hr_dev, unsigned long cqn) 142 { 143 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 144 struct hns_roce_bank *bank; 145 146 bank = &cq_table->bank[get_cq_bankid(cqn)]; 147 148 ida_free(&bank->ida, cqn >> CQ_BANKID_SHIFT); 149 150 mutex_lock(&cq_table->bank_mutex); 151 bank->inuse--; 152 mutex_unlock(&cq_table->bank_mutex); 153 } 154 155 static int hns_roce_create_cqc(struct hns_roce_dev *hr_dev, 156 struct hns_roce_cq *hr_cq, 157 u64 *mtts, dma_addr_t dma_handle) 158 { 159 struct ib_device *ibdev = &hr_dev->ib_dev; 160 struct hns_roce_cmd_mailbox *mailbox; 161 int ret; 162 163 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 164 if (IS_ERR(mailbox)) { 165 ibdev_err(ibdev, "failed to alloc mailbox for CQC.\n"); 166 return PTR_ERR(mailbox); 167 } 168 169 hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle); 170 171 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, HNS_ROCE_CMD_CREATE_CQC, 172 hr_cq->cqn); 173 if (ret) 174 ibdev_err(ibdev, 175 "failed to send create cmd for CQ(0x%lx), ret = %d.\n", 176 hr_cq->cqn, ret); 177 178 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 179 180 return ret; 181 } 182 183 static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) 184 { 185 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 186 struct ib_device *ibdev = &hr_dev->ib_dev; 187 u64 mtts[MTT_MIN_COUNT] = {}; 188 int ret; 189 190 ret = hns_roce_mtr_find(hr_dev, &hr_cq->mtr, 0, mtts, ARRAY_SIZE(mtts)); 191 if (ret) { 192 ibdev_err(ibdev, "failed to find CQ mtr, ret = %d.\n", ret); 193 return ret; 194 } 195 196 /* Get CQC memory HEM(Hardware Entry Memory) table */ 197 ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn); 198 if (ret) { 199 ibdev_err(ibdev, "failed to get CQ(0x%lx) context, ret = %d.\n", 200 hr_cq->cqn, ret); 201 return ret; 202 } 203 204 ret = xa_err(xa_store_irq(&cq_table->array, hr_cq->cqn, hr_cq, GFP_KERNEL)); 205 if (ret) { 206 ibdev_err(ibdev, "failed to xa_store CQ, ret = %d.\n", ret); 207 goto err_put; 208 } 209 210 ret = hns_roce_create_cqc(hr_dev, hr_cq, mtts, 211 hns_roce_get_mtr_ba(&hr_cq->mtr)); 212 if (ret) 213 goto err_xa; 214 215 return 0; 216 217 err_xa: 218 xa_erase_irq(&cq_table->array, hr_cq->cqn); 219 err_put: 220 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); 221 222 return ret; 223 } 224 225 static void free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) 226 { 227 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 228 struct device *dev = hr_dev->dev; 229 int ret; 230 231 ret = hns_roce_destroy_hw_ctx(hr_dev, HNS_ROCE_CMD_DESTROY_CQC, 232 hr_cq->cqn); 233 if (ret) 234 dev_err_ratelimited(dev, "DESTROY_CQ failed (%d) for CQN %06lx\n", 235 ret, hr_cq->cqn); 236 237 xa_erase_irq(&cq_table->array, hr_cq->cqn); 238 239 /* Waiting interrupt process procedure carried out */ 240 synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq); 241 242 /* wait for all interrupt processed */ 243 if (refcount_dec_and_test(&hr_cq->refcount)) 244 complete(&hr_cq->free); 245 wait_for_completion(&hr_cq->free); 246 247 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); 248 } 249 250 static int alloc_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq, 251 struct ib_udata *udata, unsigned long addr) 252 { 253 struct ib_device *ibdev = &hr_dev->ib_dev; 254 struct hns_roce_buf_attr buf_attr = {}; 255 int ret; 256 257 buf_attr.page_shift = hr_dev->caps.cqe_buf_pg_sz + PAGE_SHIFT; 258 buf_attr.region[0].size = hr_cq->cq_depth * hr_cq->cqe_size; 259 buf_attr.region[0].hopnum = hr_dev->caps.cqe_hop_num; 260 buf_attr.region_count = 1; 261 262 ret = hns_roce_mtr_create(hr_dev, &hr_cq->mtr, &buf_attr, 263 hr_dev->caps.cqe_ba_pg_sz + PAGE_SHIFT, 264 udata, addr); 265 if (ret) 266 ibdev_err(ibdev, "failed to alloc CQ mtr, ret = %d.\n", ret); 267 268 return ret; 269 } 270 271 static void free_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) 272 { 273 hns_roce_mtr_destroy(hr_dev, &hr_cq->mtr); 274 } 275 276 static int alloc_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq, 277 struct ib_udata *udata, unsigned long addr, 278 struct hns_roce_ib_create_cq_resp *resp) 279 { 280 bool has_db = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB; 281 struct hns_roce_ucontext *uctx; 282 int err; 283 284 if (udata) { 285 if (has_db && 286 udata->outlen >= offsetofend(typeof(*resp), cap_flags)) { 287 uctx = rdma_udata_to_drv_context(udata, 288 struct hns_roce_ucontext, ibucontext); 289 err = hns_roce_db_map_user(uctx, addr, &hr_cq->db); 290 if (err) 291 return err; 292 hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB; 293 resp->cap_flags |= HNS_ROCE_CQ_FLAG_RECORD_DB; 294 } 295 } else { 296 if (has_db) { 297 err = hns_roce_alloc_db(hr_dev, &hr_cq->db, 1); 298 if (err) 299 return err; 300 hr_cq->set_ci_db = hr_cq->db.db_record; 301 *hr_cq->set_ci_db = 0; 302 hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB; 303 } 304 hr_cq->db_reg = hr_dev->reg_base + hr_dev->odb_offset + 305 DB_REG_OFFSET * hr_dev->priv_uar.index; 306 } 307 308 return 0; 309 } 310 311 static void free_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq, 312 struct ib_udata *udata) 313 { 314 struct hns_roce_ucontext *uctx; 315 316 if (!(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) 317 return; 318 319 hr_cq->flags &= ~HNS_ROCE_CQ_FLAG_RECORD_DB; 320 if (udata) { 321 uctx = rdma_udata_to_drv_context(udata, 322 struct hns_roce_ucontext, 323 ibucontext); 324 hns_roce_db_unmap_user(uctx, &hr_cq->db); 325 } else { 326 hns_roce_free_db(hr_dev, &hr_cq->db); 327 } 328 } 329 330 static int verify_cq_create_attr(struct hns_roce_dev *hr_dev, 331 const struct ib_cq_init_attr *attr) 332 { 333 struct ib_device *ibdev = &hr_dev->ib_dev; 334 335 if (!attr->cqe || attr->cqe > hr_dev->caps.max_cqes) { 336 ibdev_err(ibdev, "failed to check CQ count %u, max = %u.\n", 337 attr->cqe, hr_dev->caps.max_cqes); 338 return -EINVAL; 339 } 340 341 if (attr->comp_vector >= hr_dev->caps.num_comp_vectors) { 342 ibdev_err(ibdev, "failed to check CQ vector = %u, max = %d.\n", 343 attr->comp_vector, hr_dev->caps.num_comp_vectors); 344 return -EINVAL; 345 } 346 347 return 0; 348 } 349 350 static int get_cq_ucmd(struct hns_roce_cq *hr_cq, struct ib_udata *udata, 351 struct hns_roce_ib_create_cq *ucmd) 352 { 353 struct ib_device *ibdev = hr_cq->ib_cq.device; 354 int ret; 355 356 ret = ib_copy_from_udata(ucmd, udata, min(udata->inlen, sizeof(*ucmd))); 357 if (ret) { 358 ibdev_err(ibdev, "failed to copy CQ udata, ret = %d.\n", ret); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static void set_cq_param(struct hns_roce_cq *hr_cq, u32 cq_entries, int vector, 366 struct hns_roce_ib_create_cq *ucmd) 367 { 368 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 369 370 cq_entries = max(cq_entries, hr_dev->caps.min_cqes); 371 cq_entries = roundup_pow_of_two(cq_entries); 372 hr_cq->ib_cq.cqe = cq_entries - 1; /* used as cqe index */ 373 hr_cq->cq_depth = cq_entries; 374 hr_cq->vector = vector; 375 376 spin_lock_init(&hr_cq->lock); 377 INIT_LIST_HEAD(&hr_cq->sq_list); 378 INIT_LIST_HEAD(&hr_cq->rq_list); 379 } 380 381 static int set_cqe_size(struct hns_roce_cq *hr_cq, struct ib_udata *udata, 382 struct hns_roce_ib_create_cq *ucmd) 383 { 384 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 385 386 if (!udata) { 387 hr_cq->cqe_size = hr_dev->caps.cqe_sz; 388 return 0; 389 } 390 391 if (udata->inlen >= offsetofend(typeof(*ucmd), cqe_size)) { 392 if (ucmd->cqe_size != HNS_ROCE_V2_CQE_SIZE && 393 ucmd->cqe_size != HNS_ROCE_V3_CQE_SIZE) { 394 ibdev_err(&hr_dev->ib_dev, 395 "invalid cqe size %u.\n", ucmd->cqe_size); 396 return -EINVAL; 397 } 398 399 hr_cq->cqe_size = ucmd->cqe_size; 400 } else { 401 hr_cq->cqe_size = HNS_ROCE_V2_CQE_SIZE; 402 } 403 404 return 0; 405 } 406 407 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 408 struct uverbs_attr_bundle *attrs) 409 { 410 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device); 411 struct ib_udata *udata = &attrs->driver_udata; 412 struct hns_roce_ib_create_cq_resp resp = {}; 413 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq); 414 struct ib_device *ibdev = &hr_dev->ib_dev; 415 struct hns_roce_ib_create_cq ucmd = {}; 416 int ret; 417 418 if (attr->flags) { 419 ret = -EOPNOTSUPP; 420 goto err_out; 421 } 422 423 ret = verify_cq_create_attr(hr_dev, attr); 424 if (ret) 425 goto err_out; 426 427 if (udata) { 428 ret = get_cq_ucmd(hr_cq, udata, &ucmd); 429 if (ret) 430 goto err_out; 431 } 432 433 set_cq_param(hr_cq, attr->cqe, attr->comp_vector, &ucmd); 434 435 ret = set_cqe_size(hr_cq, udata, &ucmd); 436 if (ret) 437 goto err_out; 438 439 ret = alloc_cq_buf(hr_dev, hr_cq, udata, ucmd.buf_addr); 440 if (ret) { 441 ibdev_err(ibdev, "failed to alloc CQ buf, ret = %d.\n", ret); 442 goto err_out; 443 } 444 445 ret = alloc_cq_db(hr_dev, hr_cq, udata, ucmd.db_addr, &resp); 446 if (ret) { 447 ibdev_err(ibdev, "failed to alloc CQ db, ret = %d.\n", ret); 448 goto err_cq_buf; 449 } 450 451 ret = alloc_cqn(hr_dev, hr_cq, udata); 452 if (ret) { 453 ibdev_err(ibdev, "failed to alloc CQN, ret = %d.\n", ret); 454 goto err_cq_db; 455 } 456 457 ret = alloc_cqc(hr_dev, hr_cq); 458 if (ret) { 459 ibdev_err(ibdev, 460 "failed to alloc CQ context, ret = %d.\n", ret); 461 goto err_cqn; 462 } 463 464 if (udata) { 465 resp.cqn = hr_cq->cqn; 466 ret = ib_copy_to_udata(udata, &resp, 467 min(udata->outlen, sizeof(resp))); 468 if (ret) 469 goto err_cqc; 470 } 471 472 hr_cq->cons_index = 0; 473 hr_cq->arm_sn = 1; 474 refcount_set(&hr_cq->refcount, 1); 475 init_completion(&hr_cq->free); 476 477 return 0; 478 479 err_cqc: 480 free_cqc(hr_dev, hr_cq); 481 err_cqn: 482 free_cqn(hr_dev, hr_cq->cqn); 483 err_cq_db: 484 free_cq_db(hr_dev, hr_cq, udata); 485 err_cq_buf: 486 free_cq_buf(hr_dev, hr_cq); 487 err_out: 488 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_CREATE_ERR_CNT]); 489 490 return ret; 491 } 492 493 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 494 { 495 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device); 496 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq); 497 498 free_cqc(hr_dev, hr_cq); 499 free_cqn(hr_dev, hr_cq->cqn); 500 free_cq_db(hr_dev, hr_cq, udata); 501 free_cq_buf(hr_dev, hr_cq); 502 503 return 0; 504 } 505 506 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn) 507 { 508 struct hns_roce_cq *hr_cq; 509 struct ib_cq *ibcq; 510 511 hr_cq = xa_load(&hr_dev->cq_table.array, 512 cqn & (hr_dev->caps.num_cqs - 1)); 513 if (!hr_cq) { 514 dev_warn(hr_dev->dev, "completion event for bogus CQ 0x%06x\n", 515 cqn); 516 return; 517 } 518 519 ++hr_cq->arm_sn; 520 ibcq = &hr_cq->ib_cq; 521 if (ibcq->comp_handler) 522 ibcq->comp_handler(ibcq, ibcq->cq_context); 523 } 524 525 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type) 526 { 527 struct device *dev = hr_dev->dev; 528 struct hns_roce_cq *hr_cq; 529 struct ib_event event; 530 struct ib_cq *ibcq; 531 532 if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID && 533 event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR && 534 event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) { 535 dev_err(dev, "unexpected event type 0x%x on CQ 0x%06x\n", 536 event_type, cqn); 537 return; 538 } 539 540 xa_lock(&hr_dev->cq_table.array); 541 hr_cq = xa_load(&hr_dev->cq_table.array, 542 cqn & (hr_dev->caps.num_cqs - 1)); 543 if (hr_cq) 544 refcount_inc(&hr_cq->refcount); 545 xa_unlock(&hr_dev->cq_table.array); 546 if (!hr_cq) { 547 dev_warn(dev, "async event for bogus CQ 0x%06x\n", cqn); 548 return; 549 } 550 551 ibcq = &hr_cq->ib_cq; 552 if (ibcq->event_handler) { 553 event.device = ibcq->device; 554 event.element.cq = ibcq; 555 event.event = IB_EVENT_CQ_ERR; 556 ibcq->event_handler(&event, ibcq->cq_context); 557 } 558 559 if (refcount_dec_and_test(&hr_cq->refcount)) 560 complete(&hr_cq->free); 561 } 562 563 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev) 564 { 565 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 566 unsigned int reserved_from_bot; 567 unsigned int i; 568 569 mutex_init(&cq_table->bank_mutex); 570 xa_init(&cq_table->array); 571 572 reserved_from_bot = hr_dev->caps.reserved_cqs; 573 574 for (i = 0; i < reserved_from_bot; i++) { 575 cq_table->bank[get_cq_bankid(i)].inuse++; 576 cq_table->bank[get_cq_bankid(i)].min++; 577 } 578 579 for (i = 0; i < HNS_ROCE_CQ_BANK_NUM; i++) { 580 ida_init(&cq_table->bank[i].ida); 581 cq_table->bank[i].max = hr_dev->caps.num_cqs / 582 HNS_ROCE_CQ_BANK_NUM - 1; 583 } 584 } 585 586 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev) 587 { 588 int i; 589 590 for (i = 0; i < HNS_ROCE_CQ_BANK_NUM; i++) 591 ida_destroy(&hr_dev->cq_table.bank[i].ida); 592 xa_destroy(&hr_dev->cq_table.array); 593 mutex_destroy(&hr_dev->cq_table.bank_mutex); 594 } 595