1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_COMMON_H 34 #define _HNS_ROCE_COMMON_H 35 #include <linux/bitfield.h> 36 37 #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) 38 #define roce_read(dev, reg) readl((dev)->reg_base + (reg)) 39 #define roce_raw_write(value, addr) \ 40 __raw_writel((__force u32)cpu_to_le32(value), (addr)) 41 42 #define roce_get_field(origin, mask, shift) \ 43 ((le32_to_cpu(origin) & (mask)) >> (u32)(shift)) 44 45 #define roce_get_bit(origin, shift) \ 46 roce_get_field((origin), (1ul << (shift)), (shift)) 47 48 #define roce_set_field(origin, mask, shift, val) \ 49 do { \ 50 (origin) &= ~cpu_to_le32(mask); \ 51 (origin) |= cpu_to_le32(((u32)(val) << (u32)(shift)) & (mask)); \ 52 } while (0) 53 54 #define roce_set_bit(origin, shift, val) \ 55 roce_set_field((origin), (1ul << (shift)), (shift), (val)) 56 57 #define FIELD_LOC(field_type, field_h, field_l) field_type, field_h, field_l 58 59 #define _hr_reg_enable(ptr, field_type, field_h, field_l) \ 60 ({ \ 61 const field_type *_ptr = ptr; \ 62 *((__le32 *)_ptr + (field_h) / 32) |= \ 63 cpu_to_le32(BIT((field_l) % 32)) + \ 64 BUILD_BUG_ON_ZERO((field_h) != (field_l)); \ 65 }) 66 67 #define hr_reg_enable(ptr, field) _hr_reg_enable(ptr, field) 68 69 #define _hr_reg_clear(ptr, field_type, field_h, field_l) \ 70 ({ \ 71 const field_type *_ptr = ptr; \ 72 *((__le32 *)_ptr + (field_h) / 32) &= \ 73 cpu_to_le32( \ 74 ~GENMASK((field_h) % 32, (field_l) % 32)) + \ 75 BUILD_BUG_ON_ZERO(((field_h) / 32) != \ 76 ((field_l) / 32)); \ 77 }) 78 79 #define hr_reg_clear(ptr, field) _hr_reg_clear(ptr, field) 80 81 #define _hr_reg_write(ptr, field_type, field_h, field_l, val) \ 82 ({ \ 83 _hr_reg_clear(ptr, field_type, field_h, field_l); \ 84 *((__le32 *)ptr + (field_h) / 32) |= cpu_to_le32(FIELD_PREP( \ 85 GENMASK((field_h) % 32, (field_l) % 32), val)); \ 86 }) 87 88 #define hr_reg_write(ptr, field, val) _hr_reg_write(ptr, field, val) 89 90 #define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3 91 #define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4 92 93 #define ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S 5 94 95 #define ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S 6 96 97 #define ROCEE_GLB_CFG_ROCEE_PORT_ST_S 10 98 #define ROCEE_GLB_CFG_ROCEE_PORT_ST_M \ 99 (((1UL << 6) - 1) << ROCEE_GLB_CFG_ROCEE_PORT_ST_S) 100 101 #define ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S 16 102 103 #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S 0 104 #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M \ 105 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S) 106 107 #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S 24 108 #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M \ 109 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S) 110 111 #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S 0 112 #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M \ 113 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S) 114 115 #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S 24 116 #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M \ 117 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S) 118 119 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S 0 120 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M \ 121 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S) 122 123 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S 16 124 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M \ 125 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S) 126 127 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S 0 128 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M \ 129 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S) 130 131 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S 16 132 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M \ 133 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S) 134 135 #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_S 0 136 #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_M \ 137 (((1UL << 8) - 1) << ROCEE_RAQ_WL_ROCEE_RAQ_WL_S) 138 139 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S 0 140 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M \ 141 (((1UL << 15) - 1) << \ 142 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S) 143 144 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S 16 145 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M \ 146 (((1UL << 4) - 1) << \ 147 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S) 148 149 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S 20 150 151 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE 21 152 153 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S 0 154 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M \ 155 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S) 156 157 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S 5 158 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M \ 159 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S) 160 161 #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S 0 162 #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M \ 163 (((1UL << 5) - 1) << ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S) 164 165 #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S 5 166 #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M \ 167 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S) 168 169 #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S 0 170 #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M \ 171 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S) 172 173 #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S 8 174 #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M \ 175 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S) 176 177 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S 0 178 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M \ 179 (((1UL << 19) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S) 180 181 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_S 19 182 183 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S 20 184 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M \ 185 (((1UL << 2) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S) 186 187 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S 22 188 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M \ 189 (((1UL << 5) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S) 190 191 #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S 31 192 193 #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S 0 194 #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M \ 195 (((1UL << 3) - 1) << ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S) 196 197 #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S 0 198 #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M \ 199 (((1UL << 15) - 1) << ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S) 200 201 #define ROCEE_MB6_ROCEE_MB_CMD_S 0 202 #define ROCEE_MB6_ROCEE_MB_CMD_M \ 203 (((1UL << 8) - 1) << ROCEE_MB6_ROCEE_MB_CMD_S) 204 205 #define ROCEE_MB6_ROCEE_MB_CMD_MDF_S 8 206 #define ROCEE_MB6_ROCEE_MB_CMD_MDF_M \ 207 (((1UL << 4) - 1) << ROCEE_MB6_ROCEE_MB_CMD_MDF_S) 208 209 #define ROCEE_MB6_ROCEE_MB_EVENT_S 14 210 211 #define ROCEE_MB6_ROCEE_MB_HW_RUN_S 15 212 213 #define ROCEE_MB6_ROCEE_MB_TOKEN_S 16 214 #define ROCEE_MB6_ROCEE_MB_TOKEN_M \ 215 (((1UL << 16) - 1) << ROCEE_MB6_ROCEE_MB_TOKEN_S) 216 217 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S 0 218 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M \ 219 (((1UL << 24) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S) 220 221 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S 24 222 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M \ 223 (((1UL << 4) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S) 224 225 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S 28 226 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M \ 227 (((1UL << 3) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S) 228 229 #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S 31 230 231 #define ROCEE_SMAC_H_ROCEE_SMAC_H_S 0 232 #define ROCEE_SMAC_H_ROCEE_SMAC_H_M \ 233 (((1UL << 16) - 1) << ROCEE_SMAC_H_ROCEE_SMAC_H_S) 234 235 #define ROCEE_SMAC_H_ROCEE_PORT_MTU_S 16 236 #define ROCEE_SMAC_H_ROCEE_PORT_MTU_M \ 237 (((1UL << 4) - 1) << ROCEE_SMAC_H_ROCEE_PORT_MTU_S) 238 239 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S 0 240 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M \ 241 (((1UL << 2) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S) 242 243 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S 8 244 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M \ 245 (((1UL << 4) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S) 246 247 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S 17 248 249 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S 0 250 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M \ 251 (((1UL << 5) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S) 252 253 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S 16 254 #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M \ 255 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S) 256 257 #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S 0 258 #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M \ 259 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S) 260 261 #define ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S 16 262 #define ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S 1 263 #define ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S 0 264 265 #define ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S 0 266 #define ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S 1 267 268 #define ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S 0 269 270 #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S 0 271 #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M \ 272 (((1UL << 28) - 1) << ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) 273 274 #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S 0 275 #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M \ 276 (((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) 277 278 #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0 279 #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M \ 280 (((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S) 281 282 #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S 0 283 #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M \ 284 (((1UL << 16) - 1) << ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S) 285 286 #define ROCEE_SDB_CNT_CMP_BITS 16 287 288 #define ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S 20 289 290 #define ROCEE_CNT_CLR_CE_CNT_CLR_CE_S 0 291 292 /*************ROCEE_REG DEFINITION****************/ 293 #define ROCEE_VENDOR_ID_REG 0x0 294 #define ROCEE_VENDOR_PART_ID_REG 0x4 295 296 #define ROCEE_SYS_IMAGE_GUID_L_REG 0xC 297 #define ROCEE_SYS_IMAGE_GUID_H_REG 0x10 298 299 #define ROCEE_PORT_GID_L_0_REG 0x50 300 #define ROCEE_PORT_GID_ML_0_REG 0x54 301 #define ROCEE_PORT_GID_MH_0_REG 0x58 302 #define ROCEE_PORT_GID_H_0_REG 0x5C 303 304 #define ROCEE_BT_CMD_H_REG 0x204 305 306 #define ROCEE_SMAC_L_0_REG 0x240 307 #define ROCEE_SMAC_H_0_REG 0x244 308 309 #define ROCEE_QP1C_CFG3_0_REG 0x27C 310 311 #define ROCEE_CAEP_AEQE_CONS_IDX_REG 0x3AC 312 #define ROCEE_CAEP_CEQC_CONS_IDX_0_REG 0x3BC 313 314 #define ROCEE_ECC_UCERR_ALM1_REG 0xB38 315 #define ROCEE_ECC_UCERR_ALM2_REG 0xB3C 316 #define ROCEE_ECC_CERR_ALM1_REG 0xB44 317 #define ROCEE_ECC_CERR_ALM2_REG 0xB48 318 319 #define ROCEE_ACK_DELAY_REG 0x14 320 #define ROCEE_GLB_CFG_REG 0x18 321 322 #define ROCEE_DMAE_USER_CFG1_REG 0x40 323 #define ROCEE_DMAE_USER_CFG2_REG 0x44 324 325 #define ROCEE_DB_SQ_WL_REG 0x154 326 #define ROCEE_DB_OTHERS_WL_REG 0x158 327 #define ROCEE_RAQ_WL_REG 0x15C 328 #define ROCEE_WRMS_POL_TIME_INTERVAL_REG 0x160 329 #define ROCEE_EXT_DB_SQ_REG 0x164 330 #define ROCEE_EXT_DB_SQ_H_REG 0x168 331 #define ROCEE_EXT_DB_OTH_REG 0x16C 332 333 #define ROCEE_EXT_DB_OTH_H_REG 0x170 334 #define ROCEE_EXT_DB_SQ_WL_EMPTY_REG 0x174 335 #define ROCEE_EXT_DB_SQ_WL_REG 0x178 336 #define ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG 0x17C 337 #define ROCEE_EXT_DB_OTHERS_WL_REG 0x180 338 #define ROCEE_EXT_RAQ_REG 0x184 339 #define ROCEE_EXT_RAQ_H_REG 0x188 340 341 #define ROCEE_CAEP_CE_INTERVAL_CFG_REG 0x190 342 #define ROCEE_CAEP_CE_BURST_NUM_CFG_REG 0x194 343 #define ROCEE_BT_CMD_L_REG 0x200 344 345 #define ROCEE_MB1_REG 0x210 346 #define ROCEE_MB6_REG 0x224 347 #define ROCEE_DB_SQ_L_0_REG 0x230 348 #define ROCEE_DB_OTHERS_L_0_REG 0x238 349 #define ROCEE_QP1C_CFG0_0_REG 0x270 350 351 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_REG 0x3A0 352 #define ROCEE_CAEP_CEQC_SHIFT_0_REG 0x3B0 353 #define ROCEE_CAEP_CE_IRQ_MASK_0_REG 0x3C0 354 #define ROCEE_CAEP_CEQ_ALM_OVF_0_REG 0x3C4 355 #define ROCEE_CAEP_AE_MASK_REG 0x6C8 356 #define ROCEE_CAEP_AE_ST_REG 0x6CC 357 358 #define ROCEE_CAEP_CQE_WCMD_EMPTY 0x850 359 #define ROCEE_SCAEP_WR_CQE_CNT 0x8D0 360 #define ROCEE_ECC_UCERR_ALM0_REG 0xB34 361 #define ROCEE_ECC_CERR_ALM0_REG 0xB40 362 363 /* V2 ROCEE REG */ 364 #define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000 365 #define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004 366 #define ROCEE_TX_CMQ_DEPTH_REG 0x07008 367 #define ROCEE_TX_CMQ_HEAD_REG 0x07010 368 #define ROCEE_TX_CMQ_TAIL_REG 0x07014 369 370 #define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018 371 #define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c 372 #define ROCEE_RX_CMQ_DEPTH_REG 0x07020 373 #define ROCEE_RX_CMQ_TAIL_REG 0x07024 374 #define ROCEE_RX_CMQ_HEAD_REG 0x07028 375 376 #define ROCEE_VF_EQ_DB_CFG0_REG 0x238 377 #define ROCEE_VF_EQ_DB_CFG1_REG 0x23C 378 379 #define ROCEE_VF_ABN_INT_CFG_REG 0x13000 380 #define ROCEE_VF_ABN_INT_ST_REG 0x13004 381 #define ROCEE_VF_ABN_INT_EN_REG 0x13008 382 #define ROCEE_VF_EVENT_INT_EN_REG 0x1300c 383 384 #endif /* _HNS_ROCE_COMMON_H */ 385