1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright(c) 2015 - 2020 Intel Corporation. 4 */ 5 6 #include <rdma/ib_mad.h> 7 #include <rdma/ib_user_verbs.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/utsname.h> 11 #include <linux/rculist.h> 12 #include <linux/mm.h> 13 #include <linux/vmalloc.h> 14 #include <rdma/opa_addr.h> 15 #include <linux/nospec.h> 16 17 #include "hfi.h" 18 #include "common.h" 19 #include "device.h" 20 #include "trace.h" 21 #include "qp.h" 22 #include "verbs_txreq.h" 23 #include "debugfs.h" 24 #include "fault.h" 25 #include "affinity.h" 26 #include "ipoib.h" 27 28 static unsigned int hfi1_lkey_table_size = 16; 29 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint, 30 S_IRUGO); 31 MODULE_PARM_DESC(lkey_table_size, 32 "LKEY table size in bits (2^n, 1 <= n <= 23)"); 33 34 static unsigned int hfi1_max_pds = 0xFFFF; 35 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO); 36 MODULE_PARM_DESC(max_pds, 37 "Maximum number of protection domains to support"); 38 39 static unsigned int hfi1_max_ahs = 0xFFFF; 40 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO); 41 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support"); 42 43 unsigned int hfi1_max_cqes = 0x2FFFFF; 44 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO); 45 MODULE_PARM_DESC(max_cqes, 46 "Maximum number of completion queue entries to support"); 47 48 unsigned int hfi1_max_cqs = 0x1FFFF; 49 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO); 50 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support"); 51 52 unsigned int hfi1_max_qp_wrs = 0x3FFF; 53 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO); 54 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support"); 55 56 unsigned int hfi1_max_qps = 32768; 57 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO); 58 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support"); 59 60 unsigned int hfi1_max_sges = 0x60; 61 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO); 62 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support"); 63 64 unsigned int hfi1_max_mcast_grps = 16384; 65 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO); 66 MODULE_PARM_DESC(max_mcast_grps, 67 "Maximum number of multicast groups to support"); 68 69 unsigned int hfi1_max_mcast_qp_attached = 16; 70 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached, 71 uint, S_IRUGO); 72 MODULE_PARM_DESC(max_mcast_qp_attached, 73 "Maximum number of attached QPs to support"); 74 75 unsigned int hfi1_max_srqs = 1024; 76 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO); 77 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support"); 78 79 unsigned int hfi1_max_srq_sges = 128; 80 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO); 81 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support"); 82 83 unsigned int hfi1_max_srq_wrs = 0x1FFFF; 84 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO); 85 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support"); 86 87 unsigned short piothreshold = 256; 88 module_param(piothreshold, ushort, S_IRUGO); 89 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio"); 90 91 static unsigned int sge_copy_mode; 92 module_param(sge_copy_mode, uint, S_IRUGO); 93 MODULE_PARM_DESC(sge_copy_mode, 94 "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS"); 95 96 static void verbs_sdma_complete( 97 struct sdma_txreq *cookie, 98 int status); 99 100 static int pio_wait(struct rvt_qp *qp, 101 struct send_context *sc, 102 struct hfi1_pkt_state *ps, 103 u32 flag); 104 105 /* Length of buffer to create verbs txreq cache name */ 106 #define TXREQ_NAME_LEN 24 107 108 static uint wss_threshold = 80; 109 module_param(wss_threshold, uint, S_IRUGO); 110 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy"); 111 static uint wss_clean_period = 256; 112 module_param(wss_clean_period, uint, S_IRUGO); 113 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned"); 114 115 /* 116 * Translate ib_wr_opcode into ib_wc_opcode. 117 */ 118 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = { 119 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE, 120 [IB_WR_TID_RDMA_WRITE] = IB_WC_RDMA_WRITE, 121 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE, 122 [IB_WR_SEND] = IB_WC_SEND, 123 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND, 124 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ, 125 [IB_WR_TID_RDMA_READ] = IB_WC_RDMA_READ, 126 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP, 127 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD, 128 [IB_WR_SEND_WITH_INV] = IB_WC_SEND, 129 [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV, 130 [IB_WR_REG_MR] = IB_WC_REG_MR 131 }; 132 133 /* 134 * Length of header by opcode, 0 --> not supported 135 */ 136 const u8 hdr_len_by_opcode[256] = { 137 /* RC */ 138 [IB_OPCODE_RC_SEND_FIRST] = 12 + 8, 139 [IB_OPCODE_RC_SEND_MIDDLE] = 12 + 8, 140 [IB_OPCODE_RC_SEND_LAST] = 12 + 8, 141 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 142 [IB_OPCODE_RC_SEND_ONLY] = 12 + 8, 143 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4, 144 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = 12 + 8 + 16, 145 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = 12 + 8, 146 [IB_OPCODE_RC_RDMA_WRITE_LAST] = 12 + 8, 147 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 148 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = 12 + 8 + 16, 149 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20, 150 [IB_OPCODE_RC_RDMA_READ_REQUEST] = 12 + 8 + 16, 151 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = 12 + 8 + 4, 152 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = 12 + 8, 153 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = 12 + 8 + 4, 154 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = 12 + 8 + 4, 155 [IB_OPCODE_RC_ACKNOWLEDGE] = 12 + 8 + 4, 156 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = 12 + 8 + 4 + 8, 157 [IB_OPCODE_RC_COMPARE_SWAP] = 12 + 8 + 28, 158 [IB_OPCODE_RC_FETCH_ADD] = 12 + 8 + 28, 159 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = 12 + 8 + 4, 160 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = 12 + 8 + 4, 161 [IB_OPCODE_TID_RDMA_READ_REQ] = 12 + 8 + 36, 162 [IB_OPCODE_TID_RDMA_READ_RESP] = 12 + 8 + 36, 163 [IB_OPCODE_TID_RDMA_WRITE_REQ] = 12 + 8 + 36, 164 [IB_OPCODE_TID_RDMA_WRITE_RESP] = 12 + 8 + 36, 165 [IB_OPCODE_TID_RDMA_WRITE_DATA] = 12 + 8 + 36, 166 [IB_OPCODE_TID_RDMA_WRITE_DATA_LAST] = 12 + 8 + 36, 167 [IB_OPCODE_TID_RDMA_ACK] = 12 + 8 + 36, 168 [IB_OPCODE_TID_RDMA_RESYNC] = 12 + 8 + 36, 169 /* UC */ 170 [IB_OPCODE_UC_SEND_FIRST] = 12 + 8, 171 [IB_OPCODE_UC_SEND_MIDDLE] = 12 + 8, 172 [IB_OPCODE_UC_SEND_LAST] = 12 + 8, 173 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 174 [IB_OPCODE_UC_SEND_ONLY] = 12 + 8, 175 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4, 176 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = 12 + 8 + 16, 177 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = 12 + 8, 178 [IB_OPCODE_UC_RDMA_WRITE_LAST] = 12 + 8, 179 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4, 180 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = 12 + 8 + 16, 181 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20, 182 /* UD */ 183 [IB_OPCODE_UD_SEND_ONLY] = 12 + 8 + 8, 184 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 12 185 }; 186 187 static const opcode_handler opcode_handler_tbl[256] = { 188 /* RC */ 189 [IB_OPCODE_RC_SEND_FIRST] = &hfi1_rc_rcv, 190 [IB_OPCODE_RC_SEND_MIDDLE] = &hfi1_rc_rcv, 191 [IB_OPCODE_RC_SEND_LAST] = &hfi1_rc_rcv, 192 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv, 193 [IB_OPCODE_RC_SEND_ONLY] = &hfi1_rc_rcv, 194 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv, 195 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = &hfi1_rc_rcv, 196 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = &hfi1_rc_rcv, 197 [IB_OPCODE_RC_RDMA_WRITE_LAST] = &hfi1_rc_rcv, 198 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv, 199 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = &hfi1_rc_rcv, 200 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv, 201 [IB_OPCODE_RC_RDMA_READ_REQUEST] = &hfi1_rc_rcv, 202 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = &hfi1_rc_rcv, 203 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = &hfi1_rc_rcv, 204 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = &hfi1_rc_rcv, 205 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = &hfi1_rc_rcv, 206 [IB_OPCODE_RC_ACKNOWLEDGE] = &hfi1_rc_rcv, 207 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = &hfi1_rc_rcv, 208 [IB_OPCODE_RC_COMPARE_SWAP] = &hfi1_rc_rcv, 209 [IB_OPCODE_RC_FETCH_ADD] = &hfi1_rc_rcv, 210 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = &hfi1_rc_rcv, 211 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = &hfi1_rc_rcv, 212 213 /* TID RDMA has separate handlers for different opcodes.*/ 214 [IB_OPCODE_TID_RDMA_WRITE_REQ] = &hfi1_rc_rcv_tid_rdma_write_req, 215 [IB_OPCODE_TID_RDMA_WRITE_RESP] = &hfi1_rc_rcv_tid_rdma_write_resp, 216 [IB_OPCODE_TID_RDMA_WRITE_DATA] = &hfi1_rc_rcv_tid_rdma_write_data, 217 [IB_OPCODE_TID_RDMA_WRITE_DATA_LAST] = &hfi1_rc_rcv_tid_rdma_write_data, 218 [IB_OPCODE_TID_RDMA_READ_REQ] = &hfi1_rc_rcv_tid_rdma_read_req, 219 [IB_OPCODE_TID_RDMA_READ_RESP] = &hfi1_rc_rcv_tid_rdma_read_resp, 220 [IB_OPCODE_TID_RDMA_RESYNC] = &hfi1_rc_rcv_tid_rdma_resync, 221 [IB_OPCODE_TID_RDMA_ACK] = &hfi1_rc_rcv_tid_rdma_ack, 222 223 /* UC */ 224 [IB_OPCODE_UC_SEND_FIRST] = &hfi1_uc_rcv, 225 [IB_OPCODE_UC_SEND_MIDDLE] = &hfi1_uc_rcv, 226 [IB_OPCODE_UC_SEND_LAST] = &hfi1_uc_rcv, 227 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv, 228 [IB_OPCODE_UC_SEND_ONLY] = &hfi1_uc_rcv, 229 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv, 230 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = &hfi1_uc_rcv, 231 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = &hfi1_uc_rcv, 232 [IB_OPCODE_UC_RDMA_WRITE_LAST] = &hfi1_uc_rcv, 233 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv, 234 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = &hfi1_uc_rcv, 235 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv, 236 /* UD */ 237 [IB_OPCODE_UD_SEND_ONLY] = &hfi1_ud_rcv, 238 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_ud_rcv, 239 /* CNP */ 240 [IB_OPCODE_CNP] = &hfi1_cnp_rcv 241 }; 242 243 #define OPMASK 0x1f 244 245 static const u32 pio_opmask[BIT(3)] = { 246 /* RC */ 247 [IB_OPCODE_RC >> 5] = 248 BIT(RC_OP(SEND_ONLY) & OPMASK) | 249 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) | 250 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) | 251 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) | 252 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) | 253 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) | 254 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) | 255 BIT(RC_OP(COMPARE_SWAP) & OPMASK) | 256 BIT(RC_OP(FETCH_ADD) & OPMASK), 257 /* UC */ 258 [IB_OPCODE_UC >> 5] = 259 BIT(UC_OP(SEND_ONLY) & OPMASK) | 260 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) | 261 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) | 262 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK), 263 }; 264 265 /* 266 * System image GUID. 267 */ 268 __be64 ib_hfi1_sys_image_guid; 269 270 /* 271 * Make sure the QP is ready and able to accept the given opcode. 272 */ 273 static inline opcode_handler qp_ok(struct hfi1_packet *packet) 274 { 275 if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK)) 276 return NULL; 277 if (((packet->opcode & RVT_OPCODE_QP_MASK) == 278 packet->qp->allowed_ops) || 279 (packet->opcode == IB_OPCODE_CNP)) 280 return opcode_handler_tbl[packet->opcode]; 281 282 return NULL; 283 } 284 285 static u64 hfi1_fault_tx(struct rvt_qp *qp, u8 opcode, u64 pbc) 286 { 287 #ifdef CONFIG_FAULT_INJECTION 288 if ((opcode & IB_OPCODE_MSP) == IB_OPCODE_MSP) { 289 /* 290 * In order to drop non-IB traffic we 291 * set PbcInsertHrc to NONE (0x2). 292 * The packet will still be delivered 293 * to the receiving node but a 294 * KHdrHCRCErr (KDETH packet with a bad 295 * HCRC) will be triggered and the 296 * packet will not be delivered to the 297 * correct context. 298 */ 299 pbc &= ~PBC_INSERT_HCRC_SMASK; 300 pbc |= (u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT; 301 } else { 302 /* 303 * In order to drop regular verbs 304 * traffic we set the PbcTestEbp 305 * flag. The packet will still be 306 * delivered to the receiving node but 307 * a 'late ebp error' will be 308 * triggered and will be dropped. 309 */ 310 pbc |= PBC_TEST_EBP; 311 } 312 #endif 313 return pbc; 314 } 315 316 static opcode_handler tid_qp_ok(int opcode, struct hfi1_packet *packet) 317 { 318 if (packet->qp->ibqp.qp_type != IB_QPT_RC || 319 !(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK)) 320 return NULL; 321 if ((opcode & RVT_OPCODE_QP_MASK) == IB_OPCODE_TID_RDMA) 322 return opcode_handler_tbl[opcode]; 323 return NULL; 324 } 325 326 void hfi1_kdeth_eager_rcv(struct hfi1_packet *packet) 327 { 328 struct hfi1_ctxtdata *rcd = packet->rcd; 329 struct ib_header *hdr = packet->hdr; 330 u32 tlen = packet->tlen; 331 struct hfi1_pportdata *ppd = rcd->ppd; 332 struct hfi1_ibport *ibp = &ppd->ibport_data; 333 struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi; 334 opcode_handler opcode_handler; 335 unsigned long flags; 336 u32 qp_num; 337 int lnh; 338 u8 opcode; 339 340 /* DW == LRH (2) + BTH (3) + KDETH (9) + CRC (1) */ 341 if (unlikely(tlen < 15 * sizeof(u32))) 342 goto drop; 343 344 lnh = be16_to_cpu(hdr->lrh[0]) & 3; 345 if (lnh != HFI1_LRH_BTH) 346 goto drop; 347 348 packet->ohdr = &hdr->u.oth; 349 trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf))); 350 351 opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24); 352 inc_opstats(tlen, &rcd->opstats->stats[opcode]); 353 354 /* verbs_qp can be picked up from any tid_rdma header struct */ 355 qp_num = be32_to_cpu(packet->ohdr->u.tid_rdma.r_req.verbs_qp) & 356 RVT_QPN_MASK; 357 358 rcu_read_lock(); 359 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num); 360 if (!packet->qp) 361 goto drop_rcu; 362 spin_lock_irqsave(&packet->qp->r_lock, flags); 363 opcode_handler = tid_qp_ok(opcode, packet); 364 if (likely(opcode_handler)) 365 opcode_handler(packet); 366 else 367 goto drop_unlock; 368 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 369 rcu_read_unlock(); 370 371 return; 372 drop_unlock: 373 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 374 drop_rcu: 375 rcu_read_unlock(); 376 drop: 377 ibp->rvp.n_pkt_drops++; 378 } 379 380 void hfi1_kdeth_expected_rcv(struct hfi1_packet *packet) 381 { 382 struct hfi1_ctxtdata *rcd = packet->rcd; 383 struct ib_header *hdr = packet->hdr; 384 u32 tlen = packet->tlen; 385 struct hfi1_pportdata *ppd = rcd->ppd; 386 struct hfi1_ibport *ibp = &ppd->ibport_data; 387 struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi; 388 opcode_handler opcode_handler; 389 unsigned long flags; 390 u32 qp_num; 391 int lnh; 392 u8 opcode; 393 394 /* DW == LRH (2) + BTH (3) + KDETH (9) + CRC (1) */ 395 if (unlikely(tlen < 15 * sizeof(u32))) 396 goto drop; 397 398 lnh = be16_to_cpu(hdr->lrh[0]) & 3; 399 if (lnh != HFI1_LRH_BTH) 400 goto drop; 401 402 packet->ohdr = &hdr->u.oth; 403 trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf))); 404 405 opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24); 406 inc_opstats(tlen, &rcd->opstats->stats[opcode]); 407 408 /* verbs_qp can be picked up from any tid_rdma header struct */ 409 qp_num = be32_to_cpu(packet->ohdr->u.tid_rdma.r_rsp.verbs_qp) & 410 RVT_QPN_MASK; 411 412 rcu_read_lock(); 413 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num); 414 if (!packet->qp) 415 goto drop_rcu; 416 spin_lock_irqsave(&packet->qp->r_lock, flags); 417 opcode_handler = tid_qp_ok(opcode, packet); 418 if (likely(opcode_handler)) 419 opcode_handler(packet); 420 else 421 goto drop_unlock; 422 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 423 rcu_read_unlock(); 424 425 return; 426 drop_unlock: 427 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 428 drop_rcu: 429 rcu_read_unlock(); 430 drop: 431 ibp->rvp.n_pkt_drops++; 432 } 433 434 static int hfi1_do_pkey_check(struct hfi1_packet *packet) 435 { 436 struct hfi1_ctxtdata *rcd = packet->rcd; 437 struct hfi1_pportdata *ppd = rcd->ppd; 438 struct hfi1_16b_header *hdr = packet->hdr; 439 u16 pkey; 440 441 /* Pkey check needed only for bypass packets */ 442 if (packet->etype != RHF_RCV_TYPE_BYPASS) 443 return 0; 444 445 /* Perform pkey check */ 446 pkey = hfi1_16B_get_pkey(hdr); 447 return ingress_pkey_check(ppd, pkey, packet->sc, 448 packet->qp->s_pkey_index, 449 packet->slid, true); 450 } 451 452 static inline void hfi1_handle_packet(struct hfi1_packet *packet, 453 bool is_mcast) 454 { 455 u32 qp_num; 456 struct hfi1_ctxtdata *rcd = packet->rcd; 457 struct hfi1_pportdata *ppd = rcd->ppd; 458 struct hfi1_ibport *ibp = rcd_to_iport(rcd); 459 struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi; 460 opcode_handler packet_handler; 461 unsigned long flags; 462 463 inc_opstats(packet->tlen, &rcd->opstats->stats[packet->opcode]); 464 465 if (unlikely(is_mcast)) { 466 struct rvt_mcast *mcast; 467 struct rvt_mcast_qp *p; 468 469 if (!packet->grh) 470 goto drop; 471 mcast = rvt_mcast_find(&ibp->rvp, 472 &packet->grh->dgid, 473 opa_get_lid(packet->dlid, 9B)); 474 if (!mcast) 475 goto drop; 476 rcu_read_lock(); 477 list_for_each_entry_rcu(p, &mcast->qp_list, list) { 478 packet->qp = p->qp; 479 if (hfi1_do_pkey_check(packet)) 480 goto unlock_drop; 481 spin_lock_irqsave(&packet->qp->r_lock, flags); 482 packet_handler = qp_ok(packet); 483 if (likely(packet_handler)) 484 packet_handler(packet); 485 else 486 ibp->rvp.n_pkt_drops++; 487 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 488 } 489 rcu_read_unlock(); 490 /* 491 * Notify rvt_multicast_detach() if it is waiting for us 492 * to finish. 493 */ 494 if (atomic_dec_return(&mcast->refcount) <= 1) 495 wake_up(&mcast->wait); 496 } else { 497 /* Get the destination QP number. */ 498 if (packet->etype == RHF_RCV_TYPE_BYPASS && 499 hfi1_16B_get_l4(packet->hdr) == OPA_16B_L4_FM) 500 qp_num = hfi1_16B_get_dest_qpn(packet->mgmt); 501 else 502 qp_num = ib_bth_get_qpn(packet->ohdr); 503 504 rcu_read_lock(); 505 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num); 506 if (!packet->qp) 507 goto unlock_drop; 508 509 if (hfi1_do_pkey_check(packet)) 510 goto unlock_drop; 511 512 spin_lock_irqsave(&packet->qp->r_lock, flags); 513 packet_handler = qp_ok(packet); 514 if (likely(packet_handler)) 515 packet_handler(packet); 516 else 517 ibp->rvp.n_pkt_drops++; 518 spin_unlock_irqrestore(&packet->qp->r_lock, flags); 519 rcu_read_unlock(); 520 } 521 return; 522 unlock_drop: 523 rcu_read_unlock(); 524 drop: 525 ibp->rvp.n_pkt_drops++; 526 } 527 528 /** 529 * hfi1_ib_rcv - process an incoming packet 530 * @packet: data packet information 531 * 532 * This is called to process an incoming packet at interrupt level. 533 */ 534 void hfi1_ib_rcv(struct hfi1_packet *packet) 535 { 536 struct hfi1_ctxtdata *rcd = packet->rcd; 537 538 trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf))); 539 hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid)); 540 } 541 542 void hfi1_16B_rcv(struct hfi1_packet *packet) 543 { 544 struct hfi1_ctxtdata *rcd = packet->rcd; 545 546 trace_input_ibhdr(rcd->dd, packet, false); 547 hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid)); 548 } 549 550 /* 551 * This is called from a timer to check for QPs 552 * which need kernel memory in order to send a packet. 553 */ 554 static void mem_timer(struct timer_list *t) 555 { 556 struct hfi1_ibdev *dev = timer_container_of(dev, t, mem_timer); 557 struct list_head *list = &dev->memwait; 558 struct rvt_qp *qp = NULL; 559 struct iowait *wait; 560 unsigned long flags; 561 struct hfi1_qp_priv *priv; 562 563 write_seqlock_irqsave(&dev->iowait_lock, flags); 564 if (!list_empty(list)) { 565 wait = list_first_entry(list, struct iowait, list); 566 qp = iowait_to_qp(wait); 567 priv = qp->priv; 568 list_del_init(&priv->s_iowait.list); 569 priv->s_iowait.lock = NULL; 570 /* refcount held until actual wake up */ 571 if (!list_empty(list)) 572 mod_timer(&dev->mem_timer, jiffies + 1); 573 } 574 write_sequnlock_irqrestore(&dev->iowait_lock, flags); 575 576 if (qp) 577 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM); 578 } 579 580 /* 581 * This is called with progress side lock held. 582 */ 583 /* New API */ 584 static void verbs_sdma_complete( 585 struct sdma_txreq *cookie, 586 int status) 587 { 588 struct verbs_txreq *tx = 589 container_of(cookie, struct verbs_txreq, txreq); 590 struct rvt_qp *qp = tx->qp; 591 592 spin_lock(&qp->s_lock); 593 if (tx->wqe) { 594 rvt_send_complete(qp, tx->wqe, IB_WC_SUCCESS); 595 } else if (qp->ibqp.qp_type == IB_QPT_RC) { 596 struct hfi1_opa_header *hdr; 597 598 hdr = &tx->phdr.hdr; 599 if (unlikely(status == SDMA_TXREQ_S_ABORTED)) 600 hfi1_rc_verbs_aborted(qp, hdr); 601 hfi1_rc_send_complete(qp, hdr); 602 } 603 spin_unlock(&qp->s_lock); 604 605 hfi1_put_txreq(tx); 606 } 607 608 void hfi1_wait_kmem(struct rvt_qp *qp) 609 { 610 struct hfi1_qp_priv *priv = qp->priv; 611 struct ib_qp *ibqp = &qp->ibqp; 612 struct ib_device *ibdev = ibqp->device; 613 struct hfi1_ibdev *dev = to_idev(ibdev); 614 615 if (list_empty(&priv->s_iowait.list)) { 616 if (list_empty(&dev->memwait)) 617 mod_timer(&dev->mem_timer, jiffies + 1); 618 qp->s_flags |= RVT_S_WAIT_KMEM; 619 list_add_tail(&priv->s_iowait.list, &dev->memwait); 620 priv->s_iowait.lock = &dev->iowait_lock; 621 trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM); 622 rvt_get_qp(qp); 623 } 624 } 625 626 static int wait_kmem(struct hfi1_ibdev *dev, 627 struct rvt_qp *qp, 628 struct hfi1_pkt_state *ps) 629 { 630 unsigned long flags; 631 int ret = 0; 632 633 spin_lock_irqsave(&qp->s_lock, flags); 634 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) { 635 write_seqlock(&dev->iowait_lock); 636 list_add_tail(&ps->s_txreq->txreq.list, 637 &ps->wait->tx_head); 638 hfi1_wait_kmem(qp); 639 write_sequnlock(&dev->iowait_lock); 640 hfi1_qp_unbusy(qp, ps->wait); 641 ret = -EBUSY; 642 } 643 spin_unlock_irqrestore(&qp->s_lock, flags); 644 645 return ret; 646 } 647 648 /* 649 * This routine calls txadds for each sg entry. 650 * 651 * Add failures will revert the sge cursor 652 */ 653 static noinline int build_verbs_ulp_payload( 654 struct sdma_engine *sde, 655 u32 length, 656 struct verbs_txreq *tx) 657 { 658 struct rvt_sge_state *ss = tx->ss; 659 struct rvt_sge *sg_list = ss->sg_list; 660 struct rvt_sge sge = ss->sge; 661 u8 num_sge = ss->num_sge; 662 u32 len; 663 int ret = 0; 664 665 while (length) { 666 len = rvt_get_sge_length(&ss->sge, length); 667 WARN_ON_ONCE(len == 0); 668 ret = sdma_txadd_kvaddr( 669 sde->dd, 670 &tx->txreq, 671 ss->sge.vaddr, 672 len); 673 if (ret) 674 goto bail_txadd; 675 rvt_update_sge(ss, len, false); 676 length -= len; 677 } 678 return ret; 679 bail_txadd: 680 /* unwind cursor */ 681 ss->sge = sge; 682 ss->num_sge = num_sge; 683 ss->sg_list = sg_list; 684 return ret; 685 } 686 687 /** 688 * update_tx_opstats - record stats by opcode 689 * @qp: the qp 690 * @ps: transmit packet state 691 * @plen: the plen in dwords 692 * 693 * This is a routine to record the tx opstats after a 694 * packet has been presented to the egress mechanism. 695 */ 696 static void update_tx_opstats(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 697 u32 plen) 698 { 699 #ifdef CONFIG_DEBUG_FS 700 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 701 struct hfi1_opcode_stats_perctx *s = get_cpu_ptr(dd->tx_opstats); 702 703 inc_opstats(plen * 4, &s->stats[ps->opcode]); 704 put_cpu_ptr(s); 705 #endif 706 } 707 708 /* 709 * Build the number of DMA descriptors needed to send length bytes of data. 710 * 711 * NOTE: DMA mapping is held in the tx until completed in the ring or 712 * the tx desc is freed without having been submitted to the ring 713 * 714 * This routine ensures all the helper routine calls succeed. 715 */ 716 /* New API */ 717 static int build_verbs_tx_desc( 718 struct sdma_engine *sde, 719 u32 length, 720 struct verbs_txreq *tx, 721 struct hfi1_ahg_info *ahg_info, 722 u64 pbc) 723 { 724 int ret = 0; 725 struct hfi1_sdma_header *phdr = &tx->phdr; 726 u16 hdrbytes = (tx->hdr_dwords + sizeof(pbc) / 4) << 2; 727 u8 extra_bytes = 0; 728 729 if (tx->phdr.hdr.hdr_type) { 730 /* 731 * hdrbytes accounts for PBC. Need to subtract 8 bytes 732 * before calculating padding. 733 */ 734 extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) + 735 (SIZE_OF_CRC << 2) + SIZE_OF_LT; 736 } 737 if (!ahg_info->ahgcount) { 738 ret = sdma_txinit_ahg( 739 &tx->txreq, 740 ahg_info->tx_flags, 741 hdrbytes + length + 742 extra_bytes, 743 ahg_info->ahgidx, 744 0, 745 NULL, 746 0, 747 verbs_sdma_complete); 748 if (ret) 749 goto bail_txadd; 750 phdr->pbc = cpu_to_le64(pbc); 751 ret = sdma_txadd_kvaddr( 752 sde->dd, 753 &tx->txreq, 754 phdr, 755 hdrbytes); 756 if (ret) 757 goto bail_txadd; 758 } else { 759 ret = sdma_txinit_ahg( 760 &tx->txreq, 761 ahg_info->tx_flags, 762 length, 763 ahg_info->ahgidx, 764 ahg_info->ahgcount, 765 ahg_info->ahgdesc, 766 hdrbytes, 767 verbs_sdma_complete); 768 if (ret) 769 goto bail_txadd; 770 } 771 /* add the ulp payload - if any. tx->ss can be NULL for acks */ 772 if (tx->ss) { 773 ret = build_verbs_ulp_payload(sde, length, tx); 774 if (ret) 775 goto bail_txadd; 776 } 777 778 /* add icrc, lt byte, and padding to flit */ 779 if (extra_bytes) 780 ret = sdma_txadd_daddr(sde->dd, &tx->txreq, sde->dd->sdma_pad_phys, 781 extra_bytes); 782 783 bail_txadd: 784 return ret; 785 } 786 787 static u64 update_hcrc(u8 opcode, u64 pbc) 788 { 789 if ((opcode & IB_OPCODE_TID_RDMA) == IB_OPCODE_TID_RDMA) { 790 pbc &= ~PBC_INSERT_HCRC_SMASK; 791 pbc |= (u64)PBC_IHCRC_LKDETH << PBC_INSERT_HCRC_SHIFT; 792 } 793 return pbc; 794 } 795 796 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 797 u64 pbc) 798 { 799 struct hfi1_qp_priv *priv = qp->priv; 800 struct hfi1_ahg_info *ahg_info = priv->s_ahg; 801 u32 hdrwords = ps->s_txreq->hdr_dwords; 802 u32 len = ps->s_txreq->s_cur_size; 803 u32 plen; 804 struct hfi1_ibdev *dev = ps->dev; 805 struct hfi1_pportdata *ppd = ps->ppd; 806 struct verbs_txreq *tx; 807 u8 sc5 = priv->s_sc; 808 int ret; 809 u32 dwords; 810 811 if (ps->s_txreq->phdr.hdr.hdr_type) { 812 u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len); 813 814 dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) + 815 SIZE_OF_LT) >> 2; 816 } else { 817 dwords = (len + 3) >> 2; 818 } 819 plen = hdrwords + dwords + sizeof(pbc) / 4; 820 821 tx = ps->s_txreq; 822 if (!sdma_txreq_built(&tx->txreq)) { 823 if (likely(pbc == 0)) { 824 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5); 825 826 /* No vl15 here */ 827 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */ 828 if (ps->s_txreq->phdr.hdr.hdr_type) 829 pbc |= PBC_PACKET_BYPASS | 830 PBC_INSERT_BYPASS_ICRC; 831 else 832 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT); 833 834 pbc = create_pbc(ppd, 835 pbc, 836 qp->srate_mbps, 837 vl, 838 plen); 839 840 if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode))) 841 pbc = hfi1_fault_tx(qp, ps->opcode, pbc); 842 else 843 /* Update HCRC based on packet opcode */ 844 pbc = update_hcrc(ps->opcode, pbc); 845 } 846 tx->wqe = qp->s_wqe; 847 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc); 848 if (unlikely(ret)) 849 goto bail_build; 850 } 851 ret = sdma_send_txreq(tx->sde, ps->wait, &tx->txreq, ps->pkts_sent); 852 if (unlikely(ret < 0)) { 853 if (ret == -ECOMM) 854 goto bail_ecomm; 855 return ret; 856 } 857 858 update_tx_opstats(qp, ps, plen); 859 trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device), 860 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5)); 861 return ret; 862 863 bail_ecomm: 864 /* The current one got "sent" */ 865 return 0; 866 bail_build: 867 ret = wait_kmem(dev, qp, ps); 868 if (!ret) { 869 /* free txreq - bad state */ 870 hfi1_put_txreq(ps->s_txreq); 871 ps->s_txreq = NULL; 872 } 873 return ret; 874 } 875 876 /* 877 * If we are now in the error state, return zero to flush the 878 * send work request. 879 */ 880 static int pio_wait(struct rvt_qp *qp, 881 struct send_context *sc, 882 struct hfi1_pkt_state *ps, 883 u32 flag) 884 { 885 struct hfi1_qp_priv *priv = qp->priv; 886 struct hfi1_devdata *dd = sc->dd; 887 unsigned long flags; 888 int ret = 0; 889 890 /* 891 * Note that as soon as want_buffer() is called and 892 * possibly before it returns, sc_piobufavail() 893 * could be called. Therefore, put QP on the I/O wait list before 894 * enabling the PIO avail interrupt. 895 */ 896 spin_lock_irqsave(&qp->s_lock, flags); 897 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) { 898 write_seqlock(&sc->waitlock); 899 list_add_tail(&ps->s_txreq->txreq.list, 900 &ps->wait->tx_head); 901 if (list_empty(&priv->s_iowait.list)) { 902 struct hfi1_ibdev *dev = &dd->verbs_dev; 903 int was_empty; 904 905 dev->n_piowait += !!(flag & RVT_S_WAIT_PIO); 906 dev->n_piodrain += !!(flag & HFI1_S_WAIT_PIO_DRAIN); 907 qp->s_flags |= flag; 908 was_empty = list_empty(&sc->piowait); 909 iowait_get_priority(&priv->s_iowait); 910 iowait_queue(ps->pkts_sent, &priv->s_iowait, 911 &sc->piowait); 912 priv->s_iowait.lock = &sc->waitlock; 913 trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO); 914 rvt_get_qp(qp); 915 /* counting: only call wantpiobuf_intr if first user */ 916 if (was_empty) 917 hfi1_sc_wantpiobuf_intr(sc, 1); 918 } 919 write_sequnlock(&sc->waitlock); 920 hfi1_qp_unbusy(qp, ps->wait); 921 ret = -EBUSY; 922 } 923 spin_unlock_irqrestore(&qp->s_lock, flags); 924 return ret; 925 } 926 927 static void verbs_pio_complete(void *arg, int code) 928 { 929 struct rvt_qp *qp = (struct rvt_qp *)arg; 930 struct hfi1_qp_priv *priv = qp->priv; 931 932 if (iowait_pio_dec(&priv->s_iowait)) 933 iowait_drain_wakeup(&priv->s_iowait); 934 } 935 936 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 937 u64 pbc) 938 { 939 struct hfi1_qp_priv *priv = qp->priv; 940 u32 hdrwords = ps->s_txreq->hdr_dwords; 941 struct rvt_sge_state *ss = ps->s_txreq->ss; 942 u32 len = ps->s_txreq->s_cur_size; 943 u32 dwords; 944 u32 plen; 945 struct hfi1_pportdata *ppd = ps->ppd; 946 u32 *hdr; 947 u8 sc5; 948 unsigned long flags = 0; 949 struct send_context *sc; 950 struct pio_buf *pbuf; 951 int wc_status = IB_WC_SUCCESS; 952 int ret = 0; 953 pio_release_cb cb = NULL; 954 u8 extra_bytes = 0; 955 956 if (ps->s_txreq->phdr.hdr.hdr_type) { 957 u8 pad_size = hfi1_get_16b_padding((hdrwords << 2), len); 958 959 extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT; 960 dwords = (len + extra_bytes) >> 2; 961 hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah; 962 } else { 963 dwords = (len + 3) >> 2; 964 hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh; 965 } 966 plen = hdrwords + dwords + sizeof(pbc) / 4; 967 968 /* only RC/UC use complete */ 969 switch (qp->ibqp.qp_type) { 970 case IB_QPT_RC: 971 case IB_QPT_UC: 972 cb = verbs_pio_complete; 973 break; 974 default: 975 break; 976 } 977 978 /* vl15 special case taken care of in ud.c */ 979 sc5 = priv->s_sc; 980 sc = ps->s_txreq->psc; 981 982 if (likely(pbc == 0)) { 983 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5); 984 985 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */ 986 if (ps->s_txreq->phdr.hdr.hdr_type) 987 pbc |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC; 988 else 989 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT); 990 991 pbc = create_pbc(ppd, pbc, qp->srate_mbps, vl, plen); 992 if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode))) 993 pbc = hfi1_fault_tx(qp, ps->opcode, pbc); 994 else 995 /* Update HCRC based on packet opcode */ 996 pbc = update_hcrc(ps->opcode, pbc); 997 } 998 if (cb) 999 iowait_pio_inc(&priv->s_iowait); 1000 pbuf = sc_buffer_alloc(sc, plen, cb, qp); 1001 if (IS_ERR_OR_NULL(pbuf)) { 1002 if (cb) 1003 verbs_pio_complete(qp, 0); 1004 if (IS_ERR(pbuf)) { 1005 /* 1006 * If we have filled the PIO buffers to capacity and are 1007 * not in an active state this request is not going to 1008 * go out to so just complete it with an error or else a 1009 * ULP or the core may be stuck waiting. 1010 */ 1011 hfi1_cdbg( 1012 PIO, 1013 "alloc failed. state not active, completing"); 1014 wc_status = IB_WC_GENERAL_ERR; 1015 goto pio_bail; 1016 } else { 1017 /* 1018 * This is a normal occurrence. The PIO buffs are full 1019 * up but we are still happily sending, well we could be 1020 * so lets continue to queue the request. 1021 */ 1022 hfi1_cdbg(PIO, "alloc failed. state active, queuing"); 1023 ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO); 1024 if (!ret) 1025 /* txreq not queued - free */ 1026 goto bail; 1027 /* tx consumed in wait */ 1028 return ret; 1029 } 1030 } 1031 1032 if (dwords == 0) { 1033 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords); 1034 } else { 1035 seg_pio_copy_start(pbuf, pbc, 1036 hdr, hdrwords * 4); 1037 if (ss) { 1038 while (len) { 1039 void *addr = ss->sge.vaddr; 1040 u32 slen = rvt_get_sge_length(&ss->sge, len); 1041 1042 rvt_update_sge(ss, slen, false); 1043 seg_pio_copy_mid(pbuf, addr, slen); 1044 len -= slen; 1045 } 1046 } 1047 /* add icrc, lt byte, and padding to flit */ 1048 if (extra_bytes) 1049 seg_pio_copy_mid(pbuf, ppd->dd->sdma_pad_dma, 1050 extra_bytes); 1051 1052 seg_pio_copy_end(pbuf); 1053 } 1054 1055 update_tx_opstats(qp, ps, plen); 1056 trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device), 1057 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5)); 1058 1059 pio_bail: 1060 spin_lock_irqsave(&qp->s_lock, flags); 1061 if (qp->s_wqe) { 1062 rvt_send_complete(qp, qp->s_wqe, wc_status); 1063 } else if (qp->ibqp.qp_type == IB_QPT_RC) { 1064 if (unlikely(wc_status == IB_WC_GENERAL_ERR)) 1065 hfi1_rc_verbs_aborted(qp, &ps->s_txreq->phdr.hdr); 1066 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr); 1067 } 1068 spin_unlock_irqrestore(&qp->s_lock, flags); 1069 1070 ret = 0; 1071 1072 bail: 1073 hfi1_put_txreq(ps->s_txreq); 1074 return ret; 1075 } 1076 1077 /* 1078 * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent 1079 * being an entry from the partition key table), return 0 1080 * otherwise. Use the matching criteria for egress partition keys 1081 * specified in the OPAv1 spec., section 9.1l.7. 1082 */ 1083 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent) 1084 { 1085 u16 mkey = pkey & PKEY_LOW_15_MASK; 1086 u16 mentry = ent & PKEY_LOW_15_MASK; 1087 1088 if (mkey == mentry) { 1089 /* 1090 * If pkey[15] is set (full partition member), 1091 * is bit 15 in the corresponding table element 1092 * clear (limited member)? 1093 */ 1094 if (pkey & PKEY_MEMBER_MASK) 1095 return !!(ent & PKEY_MEMBER_MASK); 1096 return 1; 1097 } 1098 return 0; 1099 } 1100 1101 /** 1102 * egress_pkey_check - check P_KEY of a packet 1103 * @ppd: Physical IB port data 1104 * @slid: SLID for packet 1105 * @pkey: PKEY for header 1106 * @sc5: SC for packet 1107 * @s_pkey_index: It will be used for look up optimization for kernel contexts 1108 * only. If it is negative value, then it means user contexts is calling this 1109 * function. 1110 * 1111 * It checks if hdr's pkey is valid. 1112 * 1113 * Return: 0 on success, otherwise, 1 1114 */ 1115 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey, 1116 u8 sc5, int8_t s_pkey_index) 1117 { 1118 struct hfi1_devdata *dd; 1119 int i; 1120 int is_user_ctxt_mechanism = (s_pkey_index < 0); 1121 1122 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT)) 1123 return 0; 1124 1125 /* If SC15, pkey[0:14] must be 0x7fff */ 1126 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1127 goto bad; 1128 1129 /* Is the pkey = 0x0, or 0x8000? */ 1130 if ((pkey & PKEY_LOW_15_MASK) == 0) 1131 goto bad; 1132 1133 /* 1134 * For the kernel contexts only, if a qp is passed into the function, 1135 * the most likely matching pkey has index qp->s_pkey_index 1136 */ 1137 if (!is_user_ctxt_mechanism && 1138 egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) { 1139 return 0; 1140 } 1141 1142 for (i = 0; i < MAX_PKEY_VALUES; i++) { 1143 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i])) 1144 return 0; 1145 } 1146 bad: 1147 /* 1148 * For the user-context mechanism, the P_KEY check would only happen 1149 * once per SDMA request, not once per packet. Therefore, there's no 1150 * need to increment the counter for the user-context mechanism. 1151 */ 1152 if (!is_user_ctxt_mechanism) { 1153 incr_cntr64(&ppd->port_xmit_constraint_errors); 1154 dd = ppd->dd; 1155 if (!(dd->err_info_xmit_constraint.status & 1156 OPA_EI_STATUS_SMASK)) { 1157 dd->err_info_xmit_constraint.status |= 1158 OPA_EI_STATUS_SMASK; 1159 dd->err_info_xmit_constraint.slid = slid; 1160 dd->err_info_xmit_constraint.pkey = pkey; 1161 } 1162 } 1163 return 1; 1164 } 1165 1166 /* 1167 * get_send_routine - choose an egress routine 1168 * 1169 * Choose an egress routine based on QP type 1170 * and size 1171 */ 1172 static inline send_routine get_send_routine(struct rvt_qp *qp, 1173 struct hfi1_pkt_state *ps) 1174 { 1175 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 1176 struct hfi1_qp_priv *priv = qp->priv; 1177 struct verbs_txreq *tx = ps->s_txreq; 1178 1179 if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA))) 1180 return dd->process_pio_send; 1181 switch (qp->ibqp.qp_type) { 1182 case IB_QPT_SMI: 1183 return dd->process_pio_send; 1184 case IB_QPT_GSI: 1185 case IB_QPT_UD: 1186 break; 1187 case IB_QPT_UC: 1188 case IB_QPT_RC: 1189 priv->s_running_pkt_size = 1190 (tx->s_cur_size + priv->s_running_pkt_size) / 2; 1191 if (piothreshold && 1192 priv->s_running_pkt_size <= min(piothreshold, qp->pmtu) && 1193 (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) && 1194 iowait_sdma_pending(&priv->s_iowait) == 0 && 1195 !sdma_txreq_built(&tx->txreq)) 1196 return dd->process_pio_send; 1197 break; 1198 default: 1199 break; 1200 } 1201 return dd->process_dma_send; 1202 } 1203 1204 /** 1205 * hfi1_verbs_send - send a packet 1206 * @qp: the QP to send on 1207 * @ps: the state of the packet to send 1208 * 1209 * Return zero if packet is sent or queued OK. 1210 * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise. 1211 */ 1212 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps) 1213 { 1214 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device); 1215 struct hfi1_qp_priv *priv = qp->priv; 1216 struct ib_other_headers *ohdr = NULL; 1217 send_routine sr; 1218 int ret; 1219 u16 pkey; 1220 u32 slid; 1221 u8 l4 = 0; 1222 1223 /* locate the pkey within the headers */ 1224 if (ps->s_txreq->phdr.hdr.hdr_type) { 1225 struct hfi1_16b_header *hdr = &ps->s_txreq->phdr.hdr.opah; 1226 1227 l4 = hfi1_16B_get_l4(hdr); 1228 if (l4 == OPA_16B_L4_IB_LOCAL) 1229 ohdr = &hdr->u.oth; 1230 else if (l4 == OPA_16B_L4_IB_GLOBAL) 1231 ohdr = &hdr->u.l.oth; 1232 1233 slid = hfi1_16B_get_slid(hdr); 1234 pkey = hfi1_16B_get_pkey(hdr); 1235 } else { 1236 struct ib_header *hdr = &ps->s_txreq->phdr.hdr.ibh; 1237 u8 lnh = ib_get_lnh(hdr); 1238 1239 if (lnh == HFI1_LRH_GRH) 1240 ohdr = &hdr->u.l.oth; 1241 else 1242 ohdr = &hdr->u.oth; 1243 slid = ib_get_slid(hdr); 1244 pkey = ib_bth_get_pkey(ohdr); 1245 } 1246 1247 if (likely(l4 != OPA_16B_L4_FM)) 1248 ps->opcode = ib_bth_get_opcode(ohdr); 1249 else 1250 ps->opcode = IB_OPCODE_UD_SEND_ONLY; 1251 1252 sr = get_send_routine(qp, ps); 1253 ret = egress_pkey_check(dd->pport, slid, pkey, 1254 priv->s_sc, qp->s_pkey_index); 1255 if (unlikely(ret)) { 1256 /* 1257 * The value we are returning here does not get propagated to 1258 * the verbs caller. Thus we need to complete the request with 1259 * error otherwise the caller could be sitting waiting on the 1260 * completion event. Only do this for PIO. SDMA has its own 1261 * mechanism for handling the errors. So for SDMA we can just 1262 * return. 1263 */ 1264 if (sr == dd->process_pio_send) { 1265 unsigned long flags; 1266 1267 hfi1_cdbg(PIO, "%s() Failed. Completing with err", 1268 __func__); 1269 spin_lock_irqsave(&qp->s_lock, flags); 1270 rvt_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR); 1271 spin_unlock_irqrestore(&qp->s_lock, flags); 1272 } 1273 return -EINVAL; 1274 } 1275 if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait)) 1276 return pio_wait(qp, 1277 ps->s_txreq->psc, 1278 ps, 1279 HFI1_S_WAIT_PIO_DRAIN); 1280 return sr(qp, ps, 0); 1281 } 1282 1283 /** 1284 * hfi1_fill_device_attr - Fill in rvt dev info device attributes. 1285 * @dd: the device data structure 1286 */ 1287 static void hfi1_fill_device_attr(struct hfi1_devdata *dd) 1288 { 1289 struct rvt_dev_info *rdi = &dd->verbs_dev.rdi; 1290 u32 ver = dd->dc8051_ver; 1291 1292 memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props)); 1293 1294 rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) | 1295 ((u64)(dc8051_ver_min(ver)) << 16) | 1296 (u64)dc8051_ver_patch(ver); 1297 1298 rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR | 1299 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT | 1300 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN | 1301 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE | 1302 IB_DEVICE_MEM_MGT_EXTENSIONS; 1303 rdi->dparms.props.kernel_cap_flags = IBK_RDMA_NETDEV_OPA; 1304 rdi->dparms.props.page_size_cap = PAGE_SIZE; 1305 rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3; 1306 rdi->dparms.props.vendor_part_id = dd->pcidev->device; 1307 rdi->dparms.props.hw_ver = dd->minrev; 1308 rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid; 1309 rdi->dparms.props.max_mr_size = U64_MAX; 1310 rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX; 1311 rdi->dparms.props.max_qp = hfi1_max_qps; 1312 rdi->dparms.props.max_qp_wr = 1313 (hfi1_max_qp_wrs >= HFI1_QP_WQE_INVALID ? 1314 HFI1_QP_WQE_INVALID - 1 : hfi1_max_qp_wrs); 1315 rdi->dparms.props.max_send_sge = hfi1_max_sges; 1316 rdi->dparms.props.max_recv_sge = hfi1_max_sges; 1317 rdi->dparms.props.max_sge_rd = hfi1_max_sges; 1318 rdi->dparms.props.max_cq = hfi1_max_cqs; 1319 rdi->dparms.props.max_ah = hfi1_max_ahs; 1320 rdi->dparms.props.max_cqe = hfi1_max_cqes; 1321 rdi->dparms.props.max_pd = hfi1_max_pds; 1322 rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC; 1323 rdi->dparms.props.max_qp_init_rd_atom = 255; 1324 rdi->dparms.props.max_srq = hfi1_max_srqs; 1325 rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs; 1326 rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges; 1327 rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB; 1328 rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd); 1329 rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps; 1330 rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached; 1331 rdi->dparms.props.max_total_mcast_qp_attach = 1332 rdi->dparms.props.max_mcast_qp_attach * 1333 rdi->dparms.props.max_mcast_grp; 1334 } 1335 1336 static inline u16 opa_speed_to_ib(u16 in) 1337 { 1338 u16 out = 0; 1339 1340 if (in & OPA_LINK_SPEED_25G) 1341 out |= IB_SPEED_EDR; 1342 if (in & OPA_LINK_SPEED_12_5G) 1343 out |= IB_SPEED_FDR; 1344 1345 return out; 1346 } 1347 1348 /* 1349 * Convert a single OPA link width (no multiple flags) to an IB value. 1350 * A zero OPA link width means link down, which means the IB width value 1351 * is a don't care. 1352 */ 1353 static inline u16 opa_width_to_ib(u16 in) 1354 { 1355 switch (in) { 1356 case OPA_LINK_WIDTH_1X: 1357 /* map 2x and 3x to 1x as they don't exist in IB */ 1358 case OPA_LINK_WIDTH_2X: 1359 case OPA_LINK_WIDTH_3X: 1360 return IB_WIDTH_1X; 1361 default: /* link down or unknown, return our largest width */ 1362 case OPA_LINK_WIDTH_4X: 1363 return IB_WIDTH_4X; 1364 } 1365 } 1366 1367 static int query_port(struct rvt_dev_info *rdi, u32 port_num, 1368 struct ib_port_attr *props) 1369 { 1370 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi); 1371 struct hfi1_devdata *dd = dd_from_dev(verbs_dev); 1372 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1]; 1373 u32 lid = ppd->lid; 1374 1375 /* props being zeroed by the caller, avoid zeroing it here */ 1376 props->lid = lid ? lid : 0; 1377 props->lmc = ppd->lmc; 1378 /* OPA logical states match IB logical states */ 1379 props->state = driver_lstate(ppd); 1380 props->phys_state = driver_pstate(ppd); 1381 props->gid_tbl_len = HFI1_GUIDS_PER_PORT; 1382 props->active_width = (u8)opa_width_to_ib(ppd->link_width_active); 1383 /* see rate_show() in ib core/sysfs.c */ 1384 props->active_speed = opa_speed_to_ib(ppd->link_speed_active); 1385 props->max_vl_num = ppd->vls_supported; 1386 1387 /* Once we are a "first class" citizen and have added the OPA MTUs to 1388 * the core we can advertise the larger MTU enum to the ULPs, for now 1389 * advertise only 4K. 1390 * 1391 * Those applications which are either OPA aware or pass the MTU enum 1392 * from the Path Records to us will get the new 8k MTU. Those that 1393 * attempt to process the MTU enum may fail in various ways. 1394 */ 1395 props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ? 1396 4096 : hfi1_max_mtu), IB_MTU_4096); 1397 props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu : 1398 mtu_to_enum(ppd->ibmtu, IB_MTU_4096); 1399 props->phys_mtu = hfi1_max_mtu; 1400 1401 return 0; 1402 } 1403 1404 static int modify_device(struct ib_device *device, 1405 int device_modify_mask, 1406 struct ib_device_modify *device_modify) 1407 { 1408 struct hfi1_devdata *dd = dd_from_ibdev(device); 1409 unsigned i; 1410 int ret; 1411 1412 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID | 1413 IB_DEVICE_MODIFY_NODE_DESC)) { 1414 ret = -EOPNOTSUPP; 1415 goto bail; 1416 } 1417 1418 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) { 1419 memcpy(device->node_desc, device_modify->node_desc, 1420 IB_DEVICE_NODE_DESC_MAX); 1421 for (i = 0; i < dd->num_pports; i++) { 1422 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data; 1423 1424 hfi1_node_desc_chg(ibp); 1425 } 1426 } 1427 1428 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) { 1429 ib_hfi1_sys_image_guid = 1430 cpu_to_be64(device_modify->sys_image_guid); 1431 for (i = 0; i < dd->num_pports; i++) { 1432 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data; 1433 1434 hfi1_sys_guid_chg(ibp); 1435 } 1436 } 1437 1438 ret = 0; 1439 1440 bail: 1441 return ret; 1442 } 1443 1444 static int shut_down_port(struct rvt_dev_info *rdi, u32 port_num) 1445 { 1446 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi); 1447 struct hfi1_devdata *dd = dd_from_dev(verbs_dev); 1448 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1]; 1449 1450 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0, 1451 OPA_LINKDOWN_REASON_UNKNOWN); 1452 return set_link_state(ppd, HLS_DN_DOWNDEF); 1453 } 1454 1455 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp, 1456 int guid_index, __be64 *guid) 1457 { 1458 struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp); 1459 1460 if (guid_index >= HFI1_GUIDS_PER_PORT) 1461 return -EINVAL; 1462 1463 *guid = get_sguid(ibp, guid_index); 1464 return 0; 1465 } 1466 1467 /* 1468 * convert ah port,sl to sc 1469 */ 1470 u8 ah_to_sc(struct ib_device *ibdev, struct rdma_ah_attr *ah) 1471 { 1472 struct hfi1_ibport *ibp = to_iport(ibdev, rdma_ah_get_port_num(ah)); 1473 1474 return ibp->sl_to_sc[rdma_ah_get_sl(ah)]; 1475 } 1476 1477 static int hfi1_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr) 1478 { 1479 struct hfi1_ibport *ibp; 1480 struct hfi1_pportdata *ppd; 1481 struct hfi1_devdata *dd; 1482 u8 sc5; 1483 u8 sl; 1484 1485 if (hfi1_check_mcast(rdma_ah_get_dlid(ah_attr)) && 1486 !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) 1487 return -EINVAL; 1488 1489 /* test the mapping for validity */ 1490 ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr)); 1491 ppd = ppd_from_ibp(ibp); 1492 dd = dd_from_ppd(ppd); 1493 1494 sl = rdma_ah_get_sl(ah_attr); 1495 if (sl >= ARRAY_SIZE(ibp->sl_to_sc)) 1496 return -EINVAL; 1497 sl = array_index_nospec(sl, ARRAY_SIZE(ibp->sl_to_sc)); 1498 1499 sc5 = ibp->sl_to_sc[sl]; 1500 if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf) 1501 return -EINVAL; 1502 return 0; 1503 } 1504 1505 static void hfi1_notify_new_ah(struct ib_device *ibdev, 1506 struct rdma_ah_attr *ah_attr, 1507 struct rvt_ah *ah) 1508 { 1509 struct hfi1_ibport *ibp; 1510 struct hfi1_pportdata *ppd; 1511 struct hfi1_devdata *dd; 1512 u8 sc5; 1513 struct rdma_ah_attr *attr = &ah->attr; 1514 1515 /* 1516 * Do not trust reading anything from rvt_ah at this point as it is not 1517 * done being setup. We can however modify things which we need to set. 1518 */ 1519 1520 ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr)); 1521 ppd = ppd_from_ibp(ibp); 1522 sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)]; 1523 hfi1_update_ah_attr(ibdev, attr); 1524 hfi1_make_opa_lid(attr); 1525 dd = dd_from_ppd(ppd); 1526 ah->vl = sc_to_vlt(dd, sc5); 1527 if (ah->vl < num_vls || ah->vl == 15) 1528 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu); 1529 } 1530 1531 /** 1532 * hfi1_get_npkeys - return the size of the PKEY table for context 0 1533 * @dd: the hfi1_ib device 1534 */ 1535 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd) 1536 { 1537 return ARRAY_SIZE(dd->pport[0].pkeys); 1538 } 1539 1540 static void init_ibport(struct hfi1_pportdata *ppd) 1541 { 1542 struct hfi1_ibport *ibp = &ppd->ibport_data; 1543 size_t sz = ARRAY_SIZE(ibp->sl_to_sc); 1544 int i; 1545 1546 for (i = 0; i < sz; i++) { 1547 ibp->sl_to_sc[i] = i; 1548 ibp->sc_to_sl[i] = i; 1549 } 1550 1551 for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++) 1552 INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list); 1553 timer_setup(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 0); 1554 1555 spin_lock_init(&ibp->rvp.lock); 1556 /* Set the prefix to the default value (see ch. 4.1.1) */ 1557 ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX; 1558 ibp->rvp.sm_lid = 0; 1559 /* 1560 * Below should only set bits defined in OPA PortInfo.CapabilityMask 1561 * and PortInfo.CapabilityMask3 1562 */ 1563 ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP | 1564 IB_PORT_CAP_MASK_NOTICE_SUP; 1565 ibp->rvp.port_cap3_flags = OPA_CAP_MASK3_IsSharedSpaceSupported; 1566 ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA; 1567 ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA; 1568 ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS; 1569 ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS; 1570 ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT; 1571 1572 RCU_INIT_POINTER(ibp->rvp.qp[0], NULL); 1573 RCU_INIT_POINTER(ibp->rvp.qp[1], NULL); 1574 } 1575 1576 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str) 1577 { 1578 struct rvt_dev_info *rdi = ib_to_rvt(ibdev); 1579 struct hfi1_ibdev *dev = dev_from_rdi(rdi); 1580 u32 ver = dd_from_dev(dev)->dc8051_ver; 1581 1582 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u", dc8051_ver_maj(ver), 1583 dc8051_ver_min(ver), dc8051_ver_patch(ver)); 1584 } 1585 1586 static const char * const driver_cntr_names[] = { 1587 /* must be element 0*/ 1588 "DRIVER_KernIntr", 1589 "DRIVER_ErrorIntr", 1590 "DRIVER_Tx_Errs", 1591 "DRIVER_Rcv_Errs", 1592 "DRIVER_HW_Errs", 1593 "DRIVER_NoPIOBufs", 1594 "DRIVER_CtxtsOpen", 1595 "DRIVER_RcvLen_Errs", 1596 "DRIVER_EgrBufFull", 1597 "DRIVER_EgrHdrFull" 1598 }; 1599 1600 static struct rdma_stat_desc *dev_cntr_descs; 1601 static struct rdma_stat_desc *port_cntr_descs; 1602 int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names); 1603 static int num_dev_cntrs; 1604 static int num_port_cntrs; 1605 1606 /* 1607 * Convert a list of names separated by '\n' into an array of NULL terminated 1608 * strings. Optionally some entries can be reserved in the array to hold extra 1609 * external strings. 1610 */ 1611 static int init_cntr_names(const char *names_in, const size_t names_len, 1612 int num_extra_names, int *num_cntrs, 1613 struct rdma_stat_desc **cntr_descs) 1614 { 1615 struct rdma_stat_desc *names_out; 1616 char *p; 1617 int i, n; 1618 1619 n = 0; 1620 for (i = 0; i < names_len; i++) 1621 if (names_in[i] == '\n') 1622 n++; 1623 1624 names_out = kzalloc((n + num_extra_names) * sizeof(*names_out) 1625 + names_len, 1626 GFP_KERNEL); 1627 if (!names_out) { 1628 *num_cntrs = 0; 1629 *cntr_descs = NULL; 1630 return -ENOMEM; 1631 } 1632 1633 p = (char *)&names_out[n + num_extra_names]; 1634 memcpy(p, names_in, names_len); 1635 1636 for (i = 0; i < n; i++) { 1637 names_out[i].name = p; 1638 p = strchr(p, '\n'); 1639 *p++ = '\0'; 1640 } 1641 1642 *num_cntrs = n; 1643 *cntr_descs = names_out; 1644 return 0; 1645 } 1646 1647 static struct rdma_hw_stats *hfi1_alloc_hw_device_stats(struct ib_device *ibdev) 1648 { 1649 if (!dev_cntr_descs) { 1650 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1651 int i, err; 1652 1653 err = init_cntr_names(dd->cntrnames, dd->cntrnameslen, 1654 num_driver_cntrs, 1655 &num_dev_cntrs, &dev_cntr_descs); 1656 if (err) 1657 return NULL; 1658 1659 for (i = 0; i < num_driver_cntrs; i++) 1660 dev_cntr_descs[num_dev_cntrs + i].name = 1661 driver_cntr_names[i]; 1662 } 1663 return rdma_alloc_hw_stats_struct(dev_cntr_descs, 1664 num_dev_cntrs + num_driver_cntrs, 1665 RDMA_HW_STATS_DEFAULT_LIFESPAN); 1666 } 1667 1668 static struct rdma_hw_stats *hfi_alloc_hw_port_stats(struct ib_device *ibdev, 1669 u32 port_num) 1670 { 1671 if (!port_cntr_descs) { 1672 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1673 int err; 1674 1675 err = init_cntr_names(dd->portcntrnames, dd->portcntrnameslen, 1676 0, 1677 &num_port_cntrs, &port_cntr_descs); 1678 if (err) 1679 return NULL; 1680 } 1681 return rdma_alloc_hw_stats_struct(port_cntr_descs, num_port_cntrs, 1682 RDMA_HW_STATS_DEFAULT_LIFESPAN); 1683 } 1684 1685 static u64 hfi1_sps_ints(void) 1686 { 1687 unsigned long index, flags; 1688 struct hfi1_devdata *dd; 1689 u64 sps_ints = 0; 1690 1691 xa_lock_irqsave(&hfi1_dev_table, flags); 1692 xa_for_each(&hfi1_dev_table, index, dd) { 1693 sps_ints += get_all_cpu_total(dd->int_counter); 1694 } 1695 xa_unlock_irqrestore(&hfi1_dev_table, flags); 1696 return sps_ints; 1697 } 1698 1699 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats, 1700 u32 port, int index) 1701 { 1702 u64 *values; 1703 int count; 1704 1705 if (!port) { 1706 u64 *stats = (u64 *)&hfi1_stats; 1707 int i; 1708 1709 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values); 1710 values[num_dev_cntrs] = hfi1_sps_ints(); 1711 for (i = 1; i < num_driver_cntrs; i++) 1712 values[num_dev_cntrs + i] = stats[i]; 1713 count = num_dev_cntrs + num_driver_cntrs; 1714 } else { 1715 struct hfi1_ibport *ibp = to_iport(ibdev, port); 1716 1717 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values); 1718 count = num_port_cntrs; 1719 } 1720 1721 memcpy(stats->value, values, count * sizeof(u64)); 1722 return count; 1723 } 1724 1725 static const struct ib_device_ops hfi1_dev_ops = { 1726 .owner = THIS_MODULE, 1727 .driver_id = RDMA_DRIVER_HFI1, 1728 1729 .alloc_hw_device_stats = hfi1_alloc_hw_device_stats, 1730 .alloc_hw_port_stats = hfi_alloc_hw_port_stats, 1731 .device_group = &ib_hfi1_attr_group, 1732 .get_dev_fw_str = hfi1_get_dev_fw_str, 1733 .get_hw_stats = get_hw_stats, 1734 .modify_device = modify_device, 1735 .port_groups = hfi1_attr_port_groups, 1736 /* keep process mad in the driver */ 1737 .process_mad = hfi1_process_mad, 1738 .rdma_netdev_get_params = hfi1_ipoib_rn_get_params, 1739 }; 1740 1741 /** 1742 * hfi1_register_ib_device - register our device with the infiniband core 1743 * @dd: the device data structure 1744 * Return 0 if successful, errno if unsuccessful. 1745 */ 1746 int hfi1_register_ib_device(struct hfi1_devdata *dd) 1747 { 1748 struct hfi1_ibdev *dev = &dd->verbs_dev; 1749 struct ib_device *ibdev = &dev->rdi.ibdev; 1750 struct hfi1_pportdata *ppd = dd->pport; 1751 struct hfi1_ibport *ibp = &ppd->ibport_data; 1752 unsigned i; 1753 int ret; 1754 1755 for (i = 0; i < dd->num_pports; i++) 1756 init_ibport(ppd + i); 1757 1758 /* Only need to initialize non-zero fields. */ 1759 1760 timer_setup(&dev->mem_timer, mem_timer, 0); 1761 1762 seqlock_init(&dev->iowait_lock); 1763 seqlock_init(&dev->txwait_lock); 1764 INIT_LIST_HEAD(&dev->txwait); 1765 INIT_LIST_HEAD(&dev->memwait); 1766 1767 ret = verbs_txreq_init(dev); 1768 if (ret) 1769 goto err_verbs_txreq; 1770 1771 /* Use first-port GUID as node guid */ 1772 ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX); 1773 1774 /* 1775 * The system image GUID is supposed to be the same for all 1776 * HFIs in a single system but since there can be other 1777 * device types in the system, we can't be sure this is unique. 1778 */ 1779 if (!ib_hfi1_sys_image_guid) 1780 ib_hfi1_sys_image_guid = ibdev->node_guid; 1781 ibdev->phys_port_cnt = dd->num_pports; 1782 ibdev->dev.parent = &dd->pcidev->dev; 1783 1784 ib_set_device_ops(ibdev, &hfi1_dev_ops); 1785 1786 strscpy(ibdev->node_desc, init_utsname()->nodename, 1787 sizeof(ibdev->node_desc)); 1788 1789 /* 1790 * Fill in rvt info object. 1791 */ 1792 dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev; 1793 dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah; 1794 dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah; 1795 dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be; 1796 dd->verbs_dev.rdi.driver_f.query_port_state = query_port; 1797 dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port; 1798 dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg; 1799 /* 1800 * Fill in rvt info device attributes. 1801 */ 1802 hfi1_fill_device_attr(dd); 1803 1804 /* queue pair */ 1805 dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size; 1806 dd->verbs_dev.rdi.dparms.qpn_start = 0; 1807 dd->verbs_dev.rdi.dparms.qpn_inc = 1; 1808 dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift; 1809 dd->verbs_dev.rdi.dparms.qpn_res_start = RVT_KDETH_QP_BASE; 1810 dd->verbs_dev.rdi.dparms.qpn_res_end = RVT_AIP_QP_MAX; 1811 dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC; 1812 dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK; 1813 dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT; 1814 dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK; 1815 dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA | 1816 RDMA_CORE_CAP_OPA_AH; 1817 dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE; 1818 1819 dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc; 1820 dd->verbs_dev.rdi.driver_f.qp_priv_init = hfi1_qp_priv_init; 1821 dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free; 1822 dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps; 1823 dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset; 1824 dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt; 1825 dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send; 1826 dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send; 1827 dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr; 1828 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp; 1829 dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters; 1830 dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue; 1831 dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp; 1832 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp; 1833 dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp; 1834 dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu; 1835 dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp; 1836 dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp; 1837 dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc; 1838 dd->verbs_dev.rdi.driver_f.setup_wqe = hfi1_setup_wqe; 1839 dd->verbs_dev.rdi.driver_f.comp_vect_cpu_lookup = 1840 hfi1_comp_vect_mappings_lookup; 1841 1842 /* completeion queue */ 1843 dd->verbs_dev.rdi.ibdev.num_comp_vectors = dd->comp_vect_possible_cpus; 1844 dd->verbs_dev.rdi.dparms.node = dd->node; 1845 1846 /* misc settings */ 1847 dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */ 1848 dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size; 1849 dd->verbs_dev.rdi.dparms.nports = dd->num_pports; 1850 dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd); 1851 dd->verbs_dev.rdi.dparms.sge_copy_mode = sge_copy_mode; 1852 dd->verbs_dev.rdi.dparms.wss_threshold = wss_threshold; 1853 dd->verbs_dev.rdi.dparms.wss_clean_period = wss_clean_period; 1854 dd->verbs_dev.rdi.dparms.reserved_operations = 1; 1855 dd->verbs_dev.rdi.dparms.extra_rdma_atomic = HFI1_TID_RDMA_WRITE_CNT; 1856 1857 /* post send table */ 1858 dd->verbs_dev.rdi.post_parms = hfi1_post_parms; 1859 1860 /* opcode translation table */ 1861 dd->verbs_dev.rdi.wc_opcode = ib_hfi1_wc_opcode; 1862 1863 ppd = dd->pport; 1864 for (i = 0; i < dd->num_pports; i++, ppd++) 1865 rvt_init_port(&dd->verbs_dev.rdi, 1866 &ppd->ibport_data.rvp, 1867 i, 1868 ppd->pkeys); 1869 1870 ret = rvt_register_device(&dd->verbs_dev.rdi); 1871 if (ret) 1872 goto err_verbs_txreq; 1873 1874 ret = hfi1_verbs_register_sysfs(dd); 1875 if (ret) 1876 goto err_class; 1877 1878 return ret; 1879 1880 err_class: 1881 rvt_unregister_device(&dd->verbs_dev.rdi); 1882 err_verbs_txreq: 1883 verbs_txreq_exit(dev); 1884 dd_dev_err(dd, "cannot register verbs: %d!\n", -ret); 1885 return ret; 1886 } 1887 1888 void hfi1_unregister_ib_device(struct hfi1_devdata *dd) 1889 { 1890 struct hfi1_ibdev *dev = &dd->verbs_dev; 1891 1892 hfi1_verbs_unregister_sysfs(dd); 1893 1894 rvt_unregister_device(&dd->verbs_dev.rdi); 1895 1896 if (!list_empty(&dev->txwait)) 1897 dd_dev_err(dd, "txwait list not empty!\n"); 1898 if (!list_empty(&dev->memwait)) 1899 dd_dev_err(dd, "memwait list not empty!\n"); 1900 1901 timer_delete_sync(&dev->mem_timer); 1902 verbs_txreq_exit(dev); 1903 1904 kfree(dev_cntr_descs); 1905 kfree(port_cntr_descs); 1906 dev_cntr_descs = NULL; 1907 port_cntr_descs = NULL; 1908 } 1909 1910 void hfi1_cnp_rcv(struct hfi1_packet *packet) 1911 { 1912 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd); 1913 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1914 struct ib_header *hdr = packet->hdr; 1915 struct rvt_qp *qp = packet->qp; 1916 u32 lqpn, rqpn = 0; 1917 u16 rlid = 0; 1918 u8 sl, sc5, svc_type; 1919 1920 switch (packet->qp->ibqp.qp_type) { 1921 case IB_QPT_UC: 1922 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr); 1923 rqpn = qp->remote_qpn; 1924 svc_type = IB_CC_SVCTYPE_UC; 1925 break; 1926 case IB_QPT_RC: 1927 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr); 1928 rqpn = qp->remote_qpn; 1929 svc_type = IB_CC_SVCTYPE_RC; 1930 break; 1931 case IB_QPT_SMI: 1932 case IB_QPT_GSI: 1933 case IB_QPT_UD: 1934 svc_type = IB_CC_SVCTYPE_UD; 1935 break; 1936 default: 1937 ibp->rvp.n_pkt_drops++; 1938 return; 1939 } 1940 1941 sc5 = hfi1_9B_get_sc5(hdr, packet->rhf); 1942 sl = ibp->sc_to_sl[sc5]; 1943 lqpn = qp->ibqp.qp_num; 1944 1945 process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type); 1946 } 1947