1 /* 2 * Copyright(c) 2015, 2016 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/spinlock.h> 49 #include <linux/seqlock.h> 50 #include <linux/netdevice.h> 51 #include <linux/moduleparam.h> 52 #include <linux/bitops.h> 53 #include <linux/timer.h> 54 #include <linux/vmalloc.h> 55 #include <linux/highmem.h> 56 57 #include "hfi.h" 58 #include "common.h" 59 #include "qp.h" 60 #include "sdma.h" 61 #include "iowait.h" 62 #include "trace.h" 63 64 /* must be a power of 2 >= 64 <= 32768 */ 65 #define SDMA_DESCQ_CNT 2048 66 #define SDMA_DESC_INTR 64 67 #define INVALID_TAIL 0xffff 68 69 static uint sdma_descq_cnt = SDMA_DESCQ_CNT; 70 module_param(sdma_descq_cnt, uint, S_IRUGO); 71 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries"); 72 73 static uint sdma_idle_cnt = 250; 74 module_param(sdma_idle_cnt, uint, S_IRUGO); 75 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)"); 76 77 uint mod_num_sdma; 78 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO); 79 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use"); 80 81 static uint sdma_desct_intr = SDMA_DESC_INTR; 82 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR); 83 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt"); 84 85 #define SDMA_WAIT_BATCH_SIZE 20 86 /* max wait time for a SDMA engine to indicate it has halted */ 87 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */ 88 /* all SDMA engine errors that cause a halt */ 89 90 #define SD(name) SEND_DMA_##name 91 #define ALL_SDMA_ENG_HALT_ERRS \ 92 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \ 93 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \ 94 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \ 95 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \ 96 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \ 97 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \ 98 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \ 99 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \ 100 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \ 101 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \ 102 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \ 103 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \ 104 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \ 105 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \ 106 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \ 107 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \ 108 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \ 109 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK)) 110 111 /* sdma_sendctrl operations */ 112 #define SDMA_SENDCTRL_OP_ENABLE BIT(0) 113 #define SDMA_SENDCTRL_OP_INTENABLE BIT(1) 114 #define SDMA_SENDCTRL_OP_HALT BIT(2) 115 #define SDMA_SENDCTRL_OP_CLEANUP BIT(3) 116 117 /* handle long defines */ 118 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \ 119 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK 120 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \ 121 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT 122 123 static const char * const sdma_state_names[] = { 124 [sdma_state_s00_hw_down] = "s00_HwDown", 125 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait", 126 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait", 127 [sdma_state_s20_idle] = "s20_Idle", 128 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait", 129 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait", 130 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait", 131 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait", 132 [sdma_state_s80_hw_freeze] = "s80_HwFreeze", 133 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean", 134 [sdma_state_s99_running] = "s99_Running", 135 }; 136 137 #ifdef CONFIG_SDMA_VERBOSITY 138 static const char * const sdma_event_names[] = { 139 [sdma_event_e00_go_hw_down] = "e00_GoHwDown", 140 [sdma_event_e10_go_hw_start] = "e10_GoHwStart", 141 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone", 142 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone", 143 [sdma_event_e30_go_running] = "e30_GoRunning", 144 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned", 145 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned", 146 [sdma_event_e60_hw_halted] = "e60_HwHalted", 147 [sdma_event_e70_go_idle] = "e70_GoIdle", 148 [sdma_event_e80_hw_freeze] = "e80_HwFreeze", 149 [sdma_event_e81_hw_frozen] = "e81_HwFrozen", 150 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze", 151 [sdma_event_e85_link_down] = "e85_LinkDown", 152 [sdma_event_e90_sw_halted] = "e90_SwHalted", 153 }; 154 #endif 155 156 static const struct sdma_set_state_action sdma_action_table[] = { 157 [sdma_state_s00_hw_down] = { 158 .go_s99_running_tofalse = 1, 159 .op_enable = 0, 160 .op_intenable = 0, 161 .op_halt = 0, 162 .op_cleanup = 0, 163 }, 164 [sdma_state_s10_hw_start_up_halt_wait] = { 165 .op_enable = 0, 166 .op_intenable = 0, 167 .op_halt = 1, 168 .op_cleanup = 0, 169 }, 170 [sdma_state_s15_hw_start_up_clean_wait] = { 171 .op_enable = 0, 172 .op_intenable = 1, 173 .op_halt = 0, 174 .op_cleanup = 1, 175 }, 176 [sdma_state_s20_idle] = { 177 .op_enable = 0, 178 .op_intenable = 1, 179 .op_halt = 0, 180 .op_cleanup = 0, 181 }, 182 [sdma_state_s30_sw_clean_up_wait] = { 183 .op_enable = 0, 184 .op_intenable = 0, 185 .op_halt = 0, 186 .op_cleanup = 0, 187 }, 188 [sdma_state_s40_hw_clean_up_wait] = { 189 .op_enable = 0, 190 .op_intenable = 0, 191 .op_halt = 0, 192 .op_cleanup = 1, 193 }, 194 [sdma_state_s50_hw_halt_wait] = { 195 .op_enable = 0, 196 .op_intenable = 0, 197 .op_halt = 0, 198 .op_cleanup = 0, 199 }, 200 [sdma_state_s60_idle_halt_wait] = { 201 .go_s99_running_tofalse = 1, 202 .op_enable = 0, 203 .op_intenable = 0, 204 .op_halt = 1, 205 .op_cleanup = 0, 206 }, 207 [sdma_state_s80_hw_freeze] = { 208 .op_enable = 0, 209 .op_intenable = 0, 210 .op_halt = 0, 211 .op_cleanup = 0, 212 }, 213 [sdma_state_s82_freeze_sw_clean] = { 214 .op_enable = 0, 215 .op_intenable = 0, 216 .op_halt = 0, 217 .op_cleanup = 0, 218 }, 219 [sdma_state_s99_running] = { 220 .op_enable = 1, 221 .op_intenable = 1, 222 .op_halt = 0, 223 .op_cleanup = 0, 224 .go_s99_running_totrue = 1, 225 }, 226 }; 227 228 #define SDMA_TAIL_UPDATE_THRESH 0x1F 229 230 /* declare all statics here rather than keep sorting */ 231 static void sdma_complete(struct kref *); 232 static void sdma_finalput(struct sdma_state *); 233 static void sdma_get(struct sdma_state *); 234 static void sdma_hw_clean_up_task(unsigned long); 235 static void sdma_put(struct sdma_state *); 236 static void sdma_set_state(struct sdma_engine *, enum sdma_states); 237 static void sdma_start_hw_clean_up(struct sdma_engine *); 238 static void sdma_sw_clean_up_task(unsigned long); 239 static void sdma_sendctrl(struct sdma_engine *, unsigned); 240 static void init_sdma_regs(struct sdma_engine *, u32, uint); 241 static void sdma_process_event( 242 struct sdma_engine *sde, 243 enum sdma_events event); 244 static void __sdma_process_event( 245 struct sdma_engine *sde, 246 enum sdma_events event); 247 static void dump_sdma_state(struct sdma_engine *sde); 248 static void sdma_make_progress(struct sdma_engine *sde, u64 status); 249 static void sdma_desc_avail(struct sdma_engine *sde, uint avail); 250 static void sdma_flush_descq(struct sdma_engine *sde); 251 252 /** 253 * sdma_state_name() - return state string from enum 254 * @state: state 255 */ 256 static const char *sdma_state_name(enum sdma_states state) 257 { 258 return sdma_state_names[state]; 259 } 260 261 static void sdma_get(struct sdma_state *ss) 262 { 263 kref_get(&ss->kref); 264 } 265 266 static void sdma_complete(struct kref *kref) 267 { 268 struct sdma_state *ss = 269 container_of(kref, struct sdma_state, kref); 270 271 complete(&ss->comp); 272 } 273 274 static void sdma_put(struct sdma_state *ss) 275 { 276 kref_put(&ss->kref, sdma_complete); 277 } 278 279 static void sdma_finalput(struct sdma_state *ss) 280 { 281 sdma_put(ss); 282 wait_for_completion(&ss->comp); 283 } 284 285 static inline void write_sde_csr( 286 struct sdma_engine *sde, 287 u32 offset0, 288 u64 value) 289 { 290 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value); 291 } 292 293 static inline u64 read_sde_csr( 294 struct sdma_engine *sde, 295 u32 offset0) 296 { 297 return read_kctxt_csr(sde->dd, sde->this_idx, offset0); 298 } 299 300 /* 301 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for 302 * sdma engine 'sde' to drop to 0. 303 */ 304 static void sdma_wait_for_packet_egress(struct sdma_engine *sde, 305 int pause) 306 { 307 u64 off = 8 * sde->this_idx; 308 struct hfi1_devdata *dd = sde->dd; 309 int lcnt = 0; 310 u64 reg_prev; 311 u64 reg = 0; 312 313 while (1) { 314 reg_prev = reg; 315 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); 316 317 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK; 318 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT; 319 if (reg == 0) 320 break; 321 /* counter is reest if accupancy count changes */ 322 if (reg != reg_prev) 323 lcnt = 0; 324 if (lcnt++ > 500) { 325 /* timed out - bounce the link */ 326 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n", 327 __func__, sde->this_idx, (u32)reg); 328 queue_work(dd->pport->link_wq, 329 &dd->pport->link_bounce_work); 330 break; 331 } 332 udelay(1); 333 } 334 } 335 336 /* 337 * sdma_wait() - wait for packet egress to complete for all SDMA engines, 338 * and pause for credit return. 339 */ 340 void sdma_wait(struct hfi1_devdata *dd) 341 { 342 int i; 343 344 for (i = 0; i < dd->num_sdma; i++) { 345 struct sdma_engine *sde = &dd->per_sdma[i]; 346 347 sdma_wait_for_packet_egress(sde, 0); 348 } 349 } 350 351 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt) 352 { 353 u64 reg; 354 355 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT)) 356 return; 357 reg = cnt; 358 reg &= SD(DESC_CNT_CNT_MASK); 359 reg <<= SD(DESC_CNT_CNT_SHIFT); 360 write_sde_csr(sde, SD(DESC_CNT), reg); 361 } 362 363 static inline void complete_tx(struct sdma_engine *sde, 364 struct sdma_txreq *tx, 365 int res) 366 { 367 /* protect against complete modifying */ 368 struct iowait *wait = tx->wait; 369 callback_t complete = tx->complete; 370 371 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 372 trace_hfi1_sdma_out_sn(sde, tx->sn); 373 if (WARN_ON_ONCE(sde->head_sn != tx->sn)) 374 dd_dev_err(sde->dd, "expected %llu got %llu\n", 375 sde->head_sn, tx->sn); 376 sde->head_sn++; 377 #endif 378 __sdma_txclean(sde->dd, tx); 379 if (complete) 380 (*complete)(tx, res); 381 if (wait && iowait_sdma_dec(wait)) 382 iowait_drain_wakeup(wait); 383 } 384 385 /* 386 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status 387 * 388 * Depending on timing there can be txreqs in two places: 389 * - in the descq ring 390 * - in the flush list 391 * 392 * To avoid ordering issues the descq ring needs to be flushed 393 * first followed by the flush list. 394 * 395 * This routine is called from two places 396 * - From a work queue item 397 * - Directly from the state machine just before setting the 398 * state to running 399 * 400 * Must be called with head_lock held 401 * 402 */ 403 static void sdma_flush(struct sdma_engine *sde) 404 { 405 struct sdma_txreq *txp, *txp_next; 406 LIST_HEAD(flushlist); 407 unsigned long flags; 408 409 /* flush from head to tail */ 410 sdma_flush_descq(sde); 411 spin_lock_irqsave(&sde->flushlist_lock, flags); 412 /* copy flush list */ 413 list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) { 414 list_del_init(&txp->list); 415 list_add_tail(&txp->list, &flushlist); 416 } 417 spin_unlock_irqrestore(&sde->flushlist_lock, flags); 418 /* flush from flush list */ 419 list_for_each_entry_safe(txp, txp_next, &flushlist, list) 420 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED); 421 } 422 423 /* 424 * Fields a work request for flushing the descq ring 425 * and the flush list 426 * 427 * If the engine has been brought to running during 428 * the scheduling delay, the flush is ignored, assuming 429 * that the process of bringing the engine to running 430 * would have done this flush prior to going to running. 431 * 432 */ 433 static void sdma_field_flush(struct work_struct *work) 434 { 435 unsigned long flags; 436 struct sdma_engine *sde = 437 container_of(work, struct sdma_engine, flush_worker); 438 439 write_seqlock_irqsave(&sde->head_lock, flags); 440 if (!__sdma_running(sde)) 441 sdma_flush(sde); 442 write_sequnlock_irqrestore(&sde->head_lock, flags); 443 } 444 445 static void sdma_err_halt_wait(struct work_struct *work) 446 { 447 struct sdma_engine *sde = container_of(work, struct sdma_engine, 448 err_halt_worker); 449 u64 statuscsr; 450 unsigned long timeout; 451 452 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT); 453 while (1) { 454 statuscsr = read_sde_csr(sde, SD(STATUS)); 455 statuscsr &= SD(STATUS_ENG_HALTED_SMASK); 456 if (statuscsr) 457 break; 458 if (time_after(jiffies, timeout)) { 459 dd_dev_err(sde->dd, 460 "SDMA engine %d - timeout waiting for engine to halt\n", 461 sde->this_idx); 462 /* 463 * Continue anyway. This could happen if there was 464 * an uncorrectable error in the wrong spot. 465 */ 466 break; 467 } 468 usleep_range(80, 120); 469 } 470 471 sdma_process_event(sde, sdma_event_e15_hw_halt_done); 472 } 473 474 static void sdma_err_progress_check_schedule(struct sdma_engine *sde) 475 { 476 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) { 477 unsigned index; 478 struct hfi1_devdata *dd = sde->dd; 479 480 for (index = 0; index < dd->num_sdma; index++) { 481 struct sdma_engine *curr_sdma = &dd->per_sdma[index]; 482 483 if (curr_sdma != sde) 484 curr_sdma->progress_check_head = 485 curr_sdma->descq_head; 486 } 487 dd_dev_err(sde->dd, 488 "SDMA engine %d - check scheduled\n", 489 sde->this_idx); 490 mod_timer(&sde->err_progress_check_timer, jiffies + 10); 491 } 492 } 493 494 static void sdma_err_progress_check(struct timer_list *t) 495 { 496 unsigned index; 497 struct sdma_engine *sde = from_timer(sde, t, err_progress_check_timer); 498 499 dd_dev_err(sde->dd, "SDE progress check event\n"); 500 for (index = 0; index < sde->dd->num_sdma; index++) { 501 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index]; 502 unsigned long flags; 503 504 /* check progress on each engine except the current one */ 505 if (curr_sde == sde) 506 continue; 507 /* 508 * We must lock interrupts when acquiring sde->lock, 509 * to avoid a deadlock if interrupt triggers and spins on 510 * the same lock on same CPU 511 */ 512 spin_lock_irqsave(&curr_sde->tail_lock, flags); 513 write_seqlock(&curr_sde->head_lock); 514 515 /* skip non-running queues */ 516 if (curr_sde->state.current_state != sdma_state_s99_running) { 517 write_sequnlock(&curr_sde->head_lock); 518 spin_unlock_irqrestore(&curr_sde->tail_lock, flags); 519 continue; 520 } 521 522 if ((curr_sde->descq_head != curr_sde->descq_tail) && 523 (curr_sde->descq_head == 524 curr_sde->progress_check_head)) 525 __sdma_process_event(curr_sde, 526 sdma_event_e90_sw_halted); 527 write_sequnlock(&curr_sde->head_lock); 528 spin_unlock_irqrestore(&curr_sde->tail_lock, flags); 529 } 530 schedule_work(&sde->err_halt_worker); 531 } 532 533 static void sdma_hw_clean_up_task(unsigned long opaque) 534 { 535 struct sdma_engine *sde = (struct sdma_engine *)opaque; 536 u64 statuscsr; 537 538 while (1) { 539 #ifdef CONFIG_SDMA_VERBOSITY 540 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 541 sde->this_idx, slashstrip(__FILE__), __LINE__, 542 __func__); 543 #endif 544 statuscsr = read_sde_csr(sde, SD(STATUS)); 545 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK); 546 if (statuscsr) 547 break; 548 udelay(10); 549 } 550 551 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done); 552 } 553 554 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde) 555 { 556 return sde->tx_ring[sde->tx_head & sde->sdma_mask]; 557 } 558 559 /* 560 * flush ring for recovery 561 */ 562 static void sdma_flush_descq(struct sdma_engine *sde) 563 { 564 u16 head, tail; 565 int progress = 0; 566 struct sdma_txreq *txp = get_txhead(sde); 567 568 /* The reason for some of the complexity of this code is that 569 * not all descriptors have corresponding txps. So, we have to 570 * be able to skip over descs until we wander into the range of 571 * the next txp on the list. 572 */ 573 head = sde->descq_head & sde->sdma_mask; 574 tail = sde->descq_tail & sde->sdma_mask; 575 while (head != tail) { 576 /* advance head, wrap if needed */ 577 head = ++sde->descq_head & sde->sdma_mask; 578 /* if now past this txp's descs, do the callback */ 579 if (txp && txp->next_descq_idx == head) { 580 /* remove from list */ 581 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; 582 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED); 583 trace_hfi1_sdma_progress(sde, head, tail, txp); 584 txp = get_txhead(sde); 585 } 586 progress++; 587 } 588 if (progress) 589 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 590 } 591 592 static void sdma_sw_clean_up_task(unsigned long opaque) 593 { 594 struct sdma_engine *sde = (struct sdma_engine *)opaque; 595 unsigned long flags; 596 597 spin_lock_irqsave(&sde->tail_lock, flags); 598 write_seqlock(&sde->head_lock); 599 600 /* 601 * At this point, the following should always be true: 602 * - We are halted, so no more descriptors are getting retired. 603 * - We are not running, so no one is submitting new work. 604 * - Only we can send the e40_sw_cleaned, so we can't start 605 * running again until we say so. So, the active list and 606 * descq are ours to play with. 607 */ 608 609 /* 610 * In the error clean up sequence, software clean must be called 611 * before the hardware clean so we can use the hardware head in 612 * the progress routine. A hardware clean or SPC unfreeze will 613 * reset the hardware head. 614 * 615 * Process all retired requests. The progress routine will use the 616 * latest physical hardware head - we are not running so speed does 617 * not matter. 618 */ 619 sdma_make_progress(sde, 0); 620 621 sdma_flush(sde); 622 623 /* 624 * Reset our notion of head and tail. 625 * Note that the HW registers have been reset via an earlier 626 * clean up. 627 */ 628 sde->descq_tail = 0; 629 sde->descq_head = 0; 630 sde->desc_avail = sdma_descq_freecnt(sde); 631 *sde->head_dma = 0; 632 633 __sdma_process_event(sde, sdma_event_e40_sw_cleaned); 634 635 write_sequnlock(&sde->head_lock); 636 spin_unlock_irqrestore(&sde->tail_lock, flags); 637 } 638 639 static void sdma_sw_tear_down(struct sdma_engine *sde) 640 { 641 struct sdma_state *ss = &sde->state; 642 643 /* Releasing this reference means the state machine has stopped. */ 644 sdma_put(ss); 645 646 /* stop waiting for all unfreeze events to complete */ 647 atomic_set(&sde->dd->sdma_unfreeze_count, -1); 648 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 649 } 650 651 static void sdma_start_hw_clean_up(struct sdma_engine *sde) 652 { 653 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task); 654 } 655 656 static void sdma_set_state(struct sdma_engine *sde, 657 enum sdma_states next_state) 658 { 659 struct sdma_state *ss = &sde->state; 660 const struct sdma_set_state_action *action = sdma_action_table; 661 unsigned op = 0; 662 663 trace_hfi1_sdma_state( 664 sde, 665 sdma_state_names[ss->current_state], 666 sdma_state_names[next_state]); 667 668 /* debugging bookkeeping */ 669 ss->previous_state = ss->current_state; 670 ss->previous_op = ss->current_op; 671 ss->current_state = next_state; 672 673 if (ss->previous_state != sdma_state_s99_running && 674 next_state == sdma_state_s99_running) 675 sdma_flush(sde); 676 677 if (action[next_state].op_enable) 678 op |= SDMA_SENDCTRL_OP_ENABLE; 679 680 if (action[next_state].op_intenable) 681 op |= SDMA_SENDCTRL_OP_INTENABLE; 682 683 if (action[next_state].op_halt) 684 op |= SDMA_SENDCTRL_OP_HALT; 685 686 if (action[next_state].op_cleanup) 687 op |= SDMA_SENDCTRL_OP_CLEANUP; 688 689 if (action[next_state].go_s99_running_tofalse) 690 ss->go_s99_running = 0; 691 692 if (action[next_state].go_s99_running_totrue) 693 ss->go_s99_running = 1; 694 695 ss->current_op = op; 696 sdma_sendctrl(sde, ss->current_op); 697 } 698 699 /** 700 * sdma_get_descq_cnt() - called when device probed 701 * 702 * Return a validated descq count. 703 * 704 * This is currently only used in the verbs initialization to build the tx 705 * list. 706 * 707 * This will probably be deleted in favor of a more scalable approach to 708 * alloc tx's. 709 * 710 */ 711 u16 sdma_get_descq_cnt(void) 712 { 713 u16 count = sdma_descq_cnt; 714 715 if (!count) 716 return SDMA_DESCQ_CNT; 717 /* count must be a power of 2 greater than 64 and less than 718 * 32768. Otherwise return default. 719 */ 720 if (!is_power_of_2(count)) 721 return SDMA_DESCQ_CNT; 722 if (count < 64 || count > 32768) 723 return SDMA_DESCQ_CNT; 724 return count; 725 } 726 727 /** 728 * sdma_engine_get_vl() - return vl for a given sdma engine 729 * @sde: sdma engine 730 * 731 * This function returns the vl mapped to a given engine, or an error if 732 * the mapping can't be found. The mapping fields are protected by RCU. 733 */ 734 int sdma_engine_get_vl(struct sdma_engine *sde) 735 { 736 struct hfi1_devdata *dd = sde->dd; 737 struct sdma_vl_map *m; 738 u8 vl; 739 740 if (sde->this_idx >= TXE_NUM_SDMA_ENGINES) 741 return -EINVAL; 742 743 rcu_read_lock(); 744 m = rcu_dereference(dd->sdma_map); 745 if (unlikely(!m)) { 746 rcu_read_unlock(); 747 return -EINVAL; 748 } 749 vl = m->engine_to_vl[sde->this_idx]; 750 rcu_read_unlock(); 751 752 return vl; 753 } 754 755 /** 756 * sdma_select_engine_vl() - select sdma engine 757 * @dd: devdata 758 * @selector: a spreading factor 759 * @vl: this vl 760 * 761 * 762 * This function returns an engine based on the selector and a vl. The 763 * mapping fields are protected by RCU. 764 */ 765 struct sdma_engine *sdma_select_engine_vl( 766 struct hfi1_devdata *dd, 767 u32 selector, 768 u8 vl) 769 { 770 struct sdma_vl_map *m; 771 struct sdma_map_elem *e; 772 struct sdma_engine *rval; 773 774 /* NOTE This should only happen if SC->VL changed after the initial 775 * checks on the QP/AH 776 * Default will return engine 0 below 777 */ 778 if (vl >= num_vls) { 779 rval = NULL; 780 goto done; 781 } 782 783 rcu_read_lock(); 784 m = rcu_dereference(dd->sdma_map); 785 if (unlikely(!m)) { 786 rcu_read_unlock(); 787 return &dd->per_sdma[0]; 788 } 789 e = m->map[vl & m->mask]; 790 rval = e->sde[selector & e->mask]; 791 rcu_read_unlock(); 792 793 done: 794 rval = !rval ? &dd->per_sdma[0] : rval; 795 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx); 796 return rval; 797 } 798 799 /** 800 * sdma_select_engine_sc() - select sdma engine 801 * @dd: devdata 802 * @selector: a spreading factor 803 * @sc5: the 5 bit sc 804 * 805 * 806 * This function returns an engine based on the selector and an sc. 807 */ 808 struct sdma_engine *sdma_select_engine_sc( 809 struct hfi1_devdata *dd, 810 u32 selector, 811 u8 sc5) 812 { 813 u8 vl = sc_to_vlt(dd, sc5); 814 815 return sdma_select_engine_vl(dd, selector, vl); 816 } 817 818 struct sdma_rht_map_elem { 819 u32 mask; 820 u8 ctr; 821 struct sdma_engine *sde[0]; 822 }; 823 824 struct sdma_rht_node { 825 unsigned long cpu_id; 826 struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED]; 827 struct rhash_head node; 828 }; 829 830 #define NR_CPUS_HINT 192 831 832 static const struct rhashtable_params sdma_rht_params = { 833 .nelem_hint = NR_CPUS_HINT, 834 .head_offset = offsetof(struct sdma_rht_node, node), 835 .key_offset = offsetof(struct sdma_rht_node, cpu_id), 836 .key_len = FIELD_SIZEOF(struct sdma_rht_node, cpu_id), 837 .max_size = NR_CPUS, 838 .min_size = 8, 839 .automatic_shrinking = true, 840 }; 841 842 /* 843 * sdma_select_user_engine() - select sdma engine based on user setup 844 * @dd: devdata 845 * @selector: a spreading factor 846 * @vl: this vl 847 * 848 * This function returns an sdma engine for a user sdma request. 849 * User defined sdma engine affinity setting is honored when applicable, 850 * otherwise system default sdma engine mapping is used. To ensure correct 851 * ordering, the mapping from <selector, vl> to sde must remain unchanged. 852 */ 853 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd, 854 u32 selector, u8 vl) 855 { 856 struct sdma_rht_node *rht_node; 857 struct sdma_engine *sde = NULL; 858 const struct cpumask *current_mask = ¤t->cpus_allowed; 859 unsigned long cpu_id; 860 861 /* 862 * To ensure that always the same sdma engine(s) will be 863 * selected make sure the process is pinned to this CPU only. 864 */ 865 if (cpumask_weight(current_mask) != 1) 866 goto out; 867 868 cpu_id = smp_processor_id(); 869 rcu_read_lock(); 870 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu_id, 871 sdma_rht_params); 872 873 if (rht_node && rht_node->map[vl]) { 874 struct sdma_rht_map_elem *map = rht_node->map[vl]; 875 876 sde = map->sde[selector & map->mask]; 877 } 878 rcu_read_unlock(); 879 880 if (sde) 881 return sde; 882 883 out: 884 return sdma_select_engine_vl(dd, selector, vl); 885 } 886 887 static void sdma_populate_sde_map(struct sdma_rht_map_elem *map) 888 { 889 int i; 890 891 for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++) 892 map->sde[map->ctr + i] = map->sde[i]; 893 } 894 895 static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map, 896 struct sdma_engine *sde) 897 { 898 unsigned int i, pow; 899 900 /* only need to check the first ctr entries for a match */ 901 for (i = 0; i < map->ctr; i++) { 902 if (map->sde[i] == sde) { 903 memmove(&map->sde[i], &map->sde[i + 1], 904 (map->ctr - i - 1) * sizeof(map->sde[0])); 905 map->ctr--; 906 pow = roundup_pow_of_two(map->ctr ? : 1); 907 map->mask = pow - 1; 908 sdma_populate_sde_map(map); 909 break; 910 } 911 } 912 } 913 914 /* 915 * Prevents concurrent reads and writes of the sdma engine cpu_mask 916 */ 917 static DEFINE_MUTEX(process_to_sde_mutex); 918 919 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf, 920 size_t count) 921 { 922 struct hfi1_devdata *dd = sde->dd; 923 cpumask_var_t mask, new_mask; 924 unsigned long cpu; 925 int ret, vl, sz; 926 927 vl = sdma_engine_get_vl(sde); 928 if (unlikely(vl < 0)) 929 return -EINVAL; 930 931 ret = zalloc_cpumask_var(&mask, GFP_KERNEL); 932 if (!ret) 933 return -ENOMEM; 934 935 ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL); 936 if (!ret) { 937 free_cpumask_var(mask); 938 return -ENOMEM; 939 } 940 ret = cpulist_parse(buf, mask); 941 if (ret) 942 goto out_free; 943 944 if (!cpumask_subset(mask, cpu_online_mask)) { 945 dd_dev_warn(sde->dd, "Invalid CPU mask\n"); 946 ret = -EINVAL; 947 goto out_free; 948 } 949 950 sz = sizeof(struct sdma_rht_map_elem) + 951 (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *)); 952 953 mutex_lock(&process_to_sde_mutex); 954 955 for_each_cpu(cpu, mask) { 956 struct sdma_rht_node *rht_node; 957 958 /* Check if we have this already mapped */ 959 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) { 960 cpumask_set_cpu(cpu, new_mask); 961 continue; 962 } 963 964 if (vl >= ARRAY_SIZE(rht_node->map)) { 965 ret = -EINVAL; 966 goto out; 967 } 968 969 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu, 970 sdma_rht_params); 971 if (!rht_node) { 972 rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL); 973 if (!rht_node) { 974 ret = -ENOMEM; 975 goto out; 976 } 977 978 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL); 979 if (!rht_node->map[vl]) { 980 kfree(rht_node); 981 ret = -ENOMEM; 982 goto out; 983 } 984 rht_node->cpu_id = cpu; 985 rht_node->map[vl]->mask = 0; 986 rht_node->map[vl]->ctr = 1; 987 rht_node->map[vl]->sde[0] = sde; 988 989 ret = rhashtable_insert_fast(dd->sdma_rht, 990 &rht_node->node, 991 sdma_rht_params); 992 if (ret) { 993 kfree(rht_node->map[vl]); 994 kfree(rht_node); 995 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n", 996 cpu); 997 goto out; 998 } 999 1000 } else { 1001 int ctr, pow; 1002 1003 /* Add new user mappings */ 1004 if (!rht_node->map[vl]) 1005 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL); 1006 1007 if (!rht_node->map[vl]) { 1008 ret = -ENOMEM; 1009 goto out; 1010 } 1011 1012 rht_node->map[vl]->ctr++; 1013 ctr = rht_node->map[vl]->ctr; 1014 rht_node->map[vl]->sde[ctr - 1] = sde; 1015 pow = roundup_pow_of_two(ctr); 1016 rht_node->map[vl]->mask = pow - 1; 1017 1018 /* Populate the sde map table */ 1019 sdma_populate_sde_map(rht_node->map[vl]); 1020 } 1021 cpumask_set_cpu(cpu, new_mask); 1022 } 1023 1024 /* Clean up old mappings */ 1025 for_each_cpu(cpu, cpu_online_mask) { 1026 struct sdma_rht_node *rht_node; 1027 1028 /* Don't cleanup sdes that are set in the new mask */ 1029 if (cpumask_test_cpu(cpu, mask)) 1030 continue; 1031 1032 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu, 1033 sdma_rht_params); 1034 if (rht_node) { 1035 bool empty = true; 1036 int i; 1037 1038 /* Remove mappings for old sde */ 1039 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1040 if (rht_node->map[i]) 1041 sdma_cleanup_sde_map(rht_node->map[i], 1042 sde); 1043 1044 /* Free empty hash table entries */ 1045 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) { 1046 if (!rht_node->map[i]) 1047 continue; 1048 1049 if (rht_node->map[i]->ctr) { 1050 empty = false; 1051 break; 1052 } 1053 } 1054 1055 if (empty) { 1056 ret = rhashtable_remove_fast(dd->sdma_rht, 1057 &rht_node->node, 1058 sdma_rht_params); 1059 WARN_ON(ret); 1060 1061 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1062 kfree(rht_node->map[i]); 1063 1064 kfree(rht_node); 1065 } 1066 } 1067 } 1068 1069 cpumask_copy(&sde->cpu_mask, new_mask); 1070 out: 1071 mutex_unlock(&process_to_sde_mutex); 1072 out_free: 1073 free_cpumask_var(mask); 1074 free_cpumask_var(new_mask); 1075 return ret ? : strnlen(buf, PAGE_SIZE); 1076 } 1077 1078 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf) 1079 { 1080 mutex_lock(&process_to_sde_mutex); 1081 if (cpumask_empty(&sde->cpu_mask)) 1082 snprintf(buf, PAGE_SIZE, "%s\n", "empty"); 1083 else 1084 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask); 1085 mutex_unlock(&process_to_sde_mutex); 1086 return strnlen(buf, PAGE_SIZE); 1087 } 1088 1089 static void sdma_rht_free(void *ptr, void *arg) 1090 { 1091 struct sdma_rht_node *rht_node = ptr; 1092 int i; 1093 1094 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) 1095 kfree(rht_node->map[i]); 1096 1097 kfree(rht_node); 1098 } 1099 1100 /** 1101 * sdma_seqfile_dump_cpu_list() - debugfs dump the cpu to sdma mappings 1102 * @s: seq file 1103 * @dd: hfi1_devdata 1104 * @cpuid: cpu id 1105 * 1106 * This routine dumps the process to sde mappings per cpu 1107 */ 1108 void sdma_seqfile_dump_cpu_list(struct seq_file *s, 1109 struct hfi1_devdata *dd, 1110 unsigned long cpuid) 1111 { 1112 struct sdma_rht_node *rht_node; 1113 int i, j; 1114 1115 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpuid, 1116 sdma_rht_params); 1117 if (!rht_node) 1118 return; 1119 1120 seq_printf(s, "cpu%3lu: ", cpuid); 1121 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) { 1122 if (!rht_node->map[i] || !rht_node->map[i]->ctr) 1123 continue; 1124 1125 seq_printf(s, " vl%d: [", i); 1126 1127 for (j = 0; j < rht_node->map[i]->ctr; j++) { 1128 if (!rht_node->map[i]->sde[j]) 1129 continue; 1130 1131 if (j > 0) 1132 seq_puts(s, ","); 1133 1134 seq_printf(s, " sdma%2d", 1135 rht_node->map[i]->sde[j]->this_idx); 1136 } 1137 seq_puts(s, " ]"); 1138 } 1139 1140 seq_puts(s, "\n"); 1141 } 1142 1143 /* 1144 * Free the indicated map struct 1145 */ 1146 static void sdma_map_free(struct sdma_vl_map *m) 1147 { 1148 int i; 1149 1150 for (i = 0; m && i < m->actual_vls; i++) 1151 kfree(m->map[i]); 1152 kfree(m); 1153 } 1154 1155 /* 1156 * Handle RCU callback 1157 */ 1158 static void sdma_map_rcu_callback(struct rcu_head *list) 1159 { 1160 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list); 1161 1162 sdma_map_free(m); 1163 } 1164 1165 /** 1166 * sdma_map_init - called when # vls change 1167 * @dd: hfi1_devdata 1168 * @port: port number 1169 * @num_vls: number of vls 1170 * @vl_engines: per vl engine mapping (optional) 1171 * 1172 * This routine changes the mapping based on the number of vls. 1173 * 1174 * vl_engines is used to specify a non-uniform vl/engine loading. NULL 1175 * implies auto computing the loading and giving each VLs a uniform 1176 * distribution of engines per VL. 1177 * 1178 * The auto algorithm computes the sde_per_vl and the number of extra 1179 * engines. Any extra engines are added from the last VL on down. 1180 * 1181 * rcu locking is used here to control access to the mapping fields. 1182 * 1183 * If either the num_vls or num_sdma are non-power of 2, the array sizes 1184 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded 1185 * up to the next highest power of 2 and the first entry is reused 1186 * in a round robin fashion. 1187 * 1188 * If an error occurs the map change is not done and the mapping is 1189 * not changed. 1190 * 1191 */ 1192 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines) 1193 { 1194 int i, j; 1195 int extra, sde_per_vl; 1196 int engine = 0; 1197 u8 lvl_engines[OPA_MAX_VLS]; 1198 struct sdma_vl_map *oldmap, *newmap; 1199 1200 if (!(dd->flags & HFI1_HAS_SEND_DMA)) 1201 return 0; 1202 1203 if (!vl_engines) { 1204 /* truncate divide */ 1205 sde_per_vl = dd->num_sdma / num_vls; 1206 /* extras */ 1207 extra = dd->num_sdma % num_vls; 1208 vl_engines = lvl_engines; 1209 /* add extras from last vl down */ 1210 for (i = num_vls - 1; i >= 0; i--, extra--) 1211 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0); 1212 } 1213 /* build new map */ 1214 newmap = kzalloc( 1215 sizeof(struct sdma_vl_map) + 1216 roundup_pow_of_two(num_vls) * 1217 sizeof(struct sdma_map_elem *), 1218 GFP_KERNEL); 1219 if (!newmap) 1220 goto bail; 1221 newmap->actual_vls = num_vls; 1222 newmap->vls = roundup_pow_of_two(num_vls); 1223 newmap->mask = (1 << ilog2(newmap->vls)) - 1; 1224 /* initialize back-map */ 1225 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++) 1226 newmap->engine_to_vl[i] = -1; 1227 for (i = 0; i < newmap->vls; i++) { 1228 /* save for wrap around */ 1229 int first_engine = engine; 1230 1231 if (i < newmap->actual_vls) { 1232 int sz = roundup_pow_of_two(vl_engines[i]); 1233 1234 /* only allocate once */ 1235 newmap->map[i] = kzalloc( 1236 sizeof(struct sdma_map_elem) + 1237 sz * sizeof(struct sdma_engine *), 1238 GFP_KERNEL); 1239 if (!newmap->map[i]) 1240 goto bail; 1241 newmap->map[i]->mask = (1 << ilog2(sz)) - 1; 1242 /* assign engines */ 1243 for (j = 0; j < sz; j++) { 1244 newmap->map[i]->sde[j] = 1245 &dd->per_sdma[engine]; 1246 if (++engine >= first_engine + vl_engines[i]) 1247 /* wrap back to first engine */ 1248 engine = first_engine; 1249 } 1250 /* assign back-map */ 1251 for (j = 0; j < vl_engines[i]; j++) 1252 newmap->engine_to_vl[first_engine + j] = i; 1253 } else { 1254 /* just re-use entry without allocating */ 1255 newmap->map[i] = newmap->map[i % num_vls]; 1256 } 1257 engine = first_engine + vl_engines[i]; 1258 } 1259 /* newmap in hand, save old map */ 1260 spin_lock_irq(&dd->sde_map_lock); 1261 oldmap = rcu_dereference_protected(dd->sdma_map, 1262 lockdep_is_held(&dd->sde_map_lock)); 1263 1264 /* publish newmap */ 1265 rcu_assign_pointer(dd->sdma_map, newmap); 1266 1267 spin_unlock_irq(&dd->sde_map_lock); 1268 /* success, free any old map after grace period */ 1269 if (oldmap) 1270 call_rcu(&oldmap->list, sdma_map_rcu_callback); 1271 return 0; 1272 bail: 1273 /* free any partial allocation */ 1274 sdma_map_free(newmap); 1275 return -ENOMEM; 1276 } 1277 1278 /* 1279 * Clean up allocated memory. 1280 * 1281 * This routine is can be called regardless of the success of sdma_init() 1282 * 1283 */ 1284 static void sdma_clean(struct hfi1_devdata *dd, size_t num_engines) 1285 { 1286 size_t i; 1287 struct sdma_engine *sde; 1288 1289 if (dd->sdma_pad_dma) { 1290 dma_free_coherent(&dd->pcidev->dev, 4, 1291 (void *)dd->sdma_pad_dma, 1292 dd->sdma_pad_phys); 1293 dd->sdma_pad_dma = NULL; 1294 dd->sdma_pad_phys = 0; 1295 } 1296 if (dd->sdma_heads_dma) { 1297 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size, 1298 (void *)dd->sdma_heads_dma, 1299 dd->sdma_heads_phys); 1300 dd->sdma_heads_dma = NULL; 1301 dd->sdma_heads_phys = 0; 1302 } 1303 for (i = 0; dd->per_sdma && i < num_engines; ++i) { 1304 sde = &dd->per_sdma[i]; 1305 1306 sde->head_dma = NULL; 1307 sde->head_phys = 0; 1308 1309 if (sde->descq) { 1310 dma_free_coherent( 1311 &dd->pcidev->dev, 1312 sde->descq_cnt * sizeof(u64[2]), 1313 sde->descq, 1314 sde->descq_phys 1315 ); 1316 sde->descq = NULL; 1317 sde->descq_phys = 0; 1318 } 1319 kvfree(sde->tx_ring); 1320 sde->tx_ring = NULL; 1321 } 1322 spin_lock_irq(&dd->sde_map_lock); 1323 sdma_map_free(rcu_access_pointer(dd->sdma_map)); 1324 RCU_INIT_POINTER(dd->sdma_map, NULL); 1325 spin_unlock_irq(&dd->sde_map_lock); 1326 synchronize_rcu(); 1327 kfree(dd->per_sdma); 1328 dd->per_sdma = NULL; 1329 1330 if (dd->sdma_rht) { 1331 rhashtable_free_and_destroy(dd->sdma_rht, sdma_rht_free, NULL); 1332 kfree(dd->sdma_rht); 1333 dd->sdma_rht = NULL; 1334 } 1335 } 1336 1337 /** 1338 * sdma_init() - called when device probed 1339 * @dd: hfi1_devdata 1340 * @port: port number (currently only zero) 1341 * 1342 * Initializes each sde and its csrs. 1343 * Interrupts are not required to be enabled. 1344 * 1345 * Returns: 1346 * 0 - success, -errno on failure 1347 */ 1348 int sdma_init(struct hfi1_devdata *dd, u8 port) 1349 { 1350 unsigned this_idx; 1351 struct sdma_engine *sde; 1352 struct rhashtable *tmp_sdma_rht; 1353 u16 descq_cnt; 1354 void *curr_head; 1355 struct hfi1_pportdata *ppd = dd->pport + port; 1356 u32 per_sdma_credits; 1357 uint idle_cnt = sdma_idle_cnt; 1358 size_t num_engines = dd->chip_sdma_engines; 1359 int ret = -ENOMEM; 1360 1361 if (!HFI1_CAP_IS_KSET(SDMA)) { 1362 HFI1_CAP_CLEAR(SDMA_AHG); 1363 return 0; 1364 } 1365 if (mod_num_sdma && 1366 /* can't exceed chip support */ 1367 mod_num_sdma <= dd->chip_sdma_engines && 1368 /* count must be >= vls */ 1369 mod_num_sdma >= num_vls) 1370 num_engines = mod_num_sdma; 1371 1372 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma); 1373 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines); 1374 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n", 1375 dd->chip_sdma_mem_size); 1376 1377 per_sdma_credits = 1378 dd->chip_sdma_mem_size / (num_engines * SDMA_BLOCK_SIZE); 1379 1380 /* set up freeze waitqueue */ 1381 init_waitqueue_head(&dd->sdma_unfreeze_wq); 1382 atomic_set(&dd->sdma_unfreeze_count, 0); 1383 1384 descq_cnt = sdma_get_descq_cnt(); 1385 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n", 1386 num_engines, descq_cnt); 1387 1388 /* alloc memory for array of send engines */ 1389 dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL); 1390 if (!dd->per_sdma) 1391 return ret; 1392 1393 idle_cnt = ns_to_cclock(dd, idle_cnt); 1394 if (idle_cnt) 1395 dd->default_desc1 = 1396 SDMA_DESC1_HEAD_TO_HOST_FLAG; 1397 else 1398 dd->default_desc1 = 1399 SDMA_DESC1_INT_REQ_FLAG; 1400 1401 if (!sdma_desct_intr) 1402 sdma_desct_intr = SDMA_DESC_INTR; 1403 1404 /* Allocate memory for SendDMA descriptor FIFOs */ 1405 for (this_idx = 0; this_idx < num_engines; ++this_idx) { 1406 sde = &dd->per_sdma[this_idx]; 1407 sde->dd = dd; 1408 sde->ppd = ppd; 1409 sde->this_idx = this_idx; 1410 sde->descq_cnt = descq_cnt; 1411 sde->desc_avail = sdma_descq_freecnt(sde); 1412 sde->sdma_shift = ilog2(descq_cnt); 1413 sde->sdma_mask = (1 << sde->sdma_shift) - 1; 1414 1415 /* Create a mask specifically for each interrupt source */ 1416 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES + 1417 this_idx); 1418 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES + 1419 this_idx); 1420 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES + 1421 this_idx); 1422 /* Create a combined mask to cover all 3 interrupt sources */ 1423 sde->imask = sde->int_mask | sde->progress_mask | 1424 sde->idle_mask; 1425 1426 spin_lock_init(&sde->tail_lock); 1427 seqlock_init(&sde->head_lock); 1428 spin_lock_init(&sde->senddmactrl_lock); 1429 spin_lock_init(&sde->flushlist_lock); 1430 /* insure there is always a zero bit */ 1431 sde->ahg_bits = 0xfffffffe00000000ULL; 1432 1433 sdma_set_state(sde, sdma_state_s00_hw_down); 1434 1435 /* set up reference counting */ 1436 kref_init(&sde->state.kref); 1437 init_completion(&sde->state.comp); 1438 1439 INIT_LIST_HEAD(&sde->flushlist); 1440 INIT_LIST_HEAD(&sde->dmawait); 1441 1442 sde->tail_csr = 1443 get_kctxt_csr_addr(dd, this_idx, SD(TAIL)); 1444 1445 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task, 1446 (unsigned long)sde); 1447 1448 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task, 1449 (unsigned long)sde); 1450 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait); 1451 INIT_WORK(&sde->flush_worker, sdma_field_flush); 1452 1453 sde->progress_check_head = 0; 1454 1455 timer_setup(&sde->err_progress_check_timer, 1456 sdma_err_progress_check, 0); 1457 1458 sde->descq = dma_zalloc_coherent( 1459 &dd->pcidev->dev, 1460 descq_cnt * sizeof(u64[2]), 1461 &sde->descq_phys, 1462 GFP_KERNEL 1463 ); 1464 if (!sde->descq) 1465 goto bail; 1466 sde->tx_ring = 1467 kvzalloc_node(sizeof(struct sdma_txreq *) * descq_cnt, 1468 GFP_KERNEL, dd->node); 1469 if (!sde->tx_ring) 1470 goto bail; 1471 } 1472 1473 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines; 1474 /* Allocate memory for DMA of head registers to memory */ 1475 dd->sdma_heads_dma = dma_zalloc_coherent( 1476 &dd->pcidev->dev, 1477 dd->sdma_heads_size, 1478 &dd->sdma_heads_phys, 1479 GFP_KERNEL 1480 ); 1481 if (!dd->sdma_heads_dma) { 1482 dd_dev_err(dd, "failed to allocate SendDMA head memory\n"); 1483 goto bail; 1484 } 1485 1486 /* Allocate memory for pad */ 1487 dd->sdma_pad_dma = dma_zalloc_coherent( 1488 &dd->pcidev->dev, 1489 sizeof(u32), 1490 &dd->sdma_pad_phys, 1491 GFP_KERNEL 1492 ); 1493 if (!dd->sdma_pad_dma) { 1494 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n"); 1495 goto bail; 1496 } 1497 1498 /* assign each engine to different cacheline and init registers */ 1499 curr_head = (void *)dd->sdma_heads_dma; 1500 for (this_idx = 0; this_idx < num_engines; ++this_idx) { 1501 unsigned long phys_offset; 1502 1503 sde = &dd->per_sdma[this_idx]; 1504 1505 sde->head_dma = curr_head; 1506 curr_head += L1_CACHE_BYTES; 1507 phys_offset = (unsigned long)sde->head_dma - 1508 (unsigned long)dd->sdma_heads_dma; 1509 sde->head_phys = dd->sdma_heads_phys + phys_offset; 1510 init_sdma_regs(sde, per_sdma_credits, idle_cnt); 1511 } 1512 dd->flags |= HFI1_HAS_SEND_DMA; 1513 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0; 1514 dd->num_sdma = num_engines; 1515 ret = sdma_map_init(dd, port, ppd->vls_operational, NULL); 1516 if (ret < 0) 1517 goto bail; 1518 1519 tmp_sdma_rht = kzalloc(sizeof(*tmp_sdma_rht), GFP_KERNEL); 1520 if (!tmp_sdma_rht) { 1521 ret = -ENOMEM; 1522 goto bail; 1523 } 1524 1525 ret = rhashtable_init(tmp_sdma_rht, &sdma_rht_params); 1526 if (ret < 0) 1527 goto bail; 1528 dd->sdma_rht = tmp_sdma_rht; 1529 1530 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma); 1531 return 0; 1532 1533 bail: 1534 sdma_clean(dd, num_engines); 1535 return ret; 1536 } 1537 1538 /** 1539 * sdma_all_running() - called when the link goes up 1540 * @dd: hfi1_devdata 1541 * 1542 * This routine moves all engines to the running state. 1543 */ 1544 void sdma_all_running(struct hfi1_devdata *dd) 1545 { 1546 struct sdma_engine *sde; 1547 unsigned int i; 1548 1549 /* move all engines to running */ 1550 for (i = 0; i < dd->num_sdma; ++i) { 1551 sde = &dd->per_sdma[i]; 1552 sdma_process_event(sde, sdma_event_e30_go_running); 1553 } 1554 } 1555 1556 /** 1557 * sdma_all_idle() - called when the link goes down 1558 * @dd: hfi1_devdata 1559 * 1560 * This routine moves all engines to the idle state. 1561 */ 1562 void sdma_all_idle(struct hfi1_devdata *dd) 1563 { 1564 struct sdma_engine *sde; 1565 unsigned int i; 1566 1567 /* idle all engines */ 1568 for (i = 0; i < dd->num_sdma; ++i) { 1569 sde = &dd->per_sdma[i]; 1570 sdma_process_event(sde, sdma_event_e70_go_idle); 1571 } 1572 } 1573 1574 /** 1575 * sdma_start() - called to kick off state processing for all engines 1576 * @dd: hfi1_devdata 1577 * 1578 * This routine is for kicking off the state processing for all required 1579 * sdma engines. Interrupts need to be working at this point. 1580 * 1581 */ 1582 void sdma_start(struct hfi1_devdata *dd) 1583 { 1584 unsigned i; 1585 struct sdma_engine *sde; 1586 1587 /* kick off the engines state processing */ 1588 for (i = 0; i < dd->num_sdma; ++i) { 1589 sde = &dd->per_sdma[i]; 1590 sdma_process_event(sde, sdma_event_e10_go_hw_start); 1591 } 1592 } 1593 1594 /** 1595 * sdma_exit() - used when module is removed 1596 * @dd: hfi1_devdata 1597 */ 1598 void sdma_exit(struct hfi1_devdata *dd) 1599 { 1600 unsigned this_idx; 1601 struct sdma_engine *sde; 1602 1603 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma; 1604 ++this_idx) { 1605 sde = &dd->per_sdma[this_idx]; 1606 if (!list_empty(&sde->dmawait)) 1607 dd_dev_err(dd, "sde %u: dmawait list not empty!\n", 1608 sde->this_idx); 1609 sdma_process_event(sde, sdma_event_e00_go_hw_down); 1610 1611 del_timer_sync(&sde->err_progress_check_timer); 1612 1613 /* 1614 * This waits for the state machine to exit so it is not 1615 * necessary to kill the sdma_sw_clean_up_task to make sure 1616 * it is not running. 1617 */ 1618 sdma_finalput(&sde->state); 1619 } 1620 sdma_clean(dd, dd->num_sdma); 1621 } 1622 1623 /* 1624 * unmap the indicated descriptor 1625 */ 1626 static inline void sdma_unmap_desc( 1627 struct hfi1_devdata *dd, 1628 struct sdma_desc *descp) 1629 { 1630 switch (sdma_mapping_type(descp)) { 1631 case SDMA_MAP_SINGLE: 1632 dma_unmap_single( 1633 &dd->pcidev->dev, 1634 sdma_mapping_addr(descp), 1635 sdma_mapping_len(descp), 1636 DMA_TO_DEVICE); 1637 break; 1638 case SDMA_MAP_PAGE: 1639 dma_unmap_page( 1640 &dd->pcidev->dev, 1641 sdma_mapping_addr(descp), 1642 sdma_mapping_len(descp), 1643 DMA_TO_DEVICE); 1644 break; 1645 } 1646 } 1647 1648 /* 1649 * return the mode as indicated by the first 1650 * descriptor in the tx. 1651 */ 1652 static inline u8 ahg_mode(struct sdma_txreq *tx) 1653 { 1654 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK) 1655 >> SDMA_DESC1_HEADER_MODE_SHIFT; 1656 } 1657 1658 /** 1659 * __sdma_txclean() - clean tx of mappings, descp *kmalloc's 1660 * @dd: hfi1_devdata for unmapping 1661 * @tx: tx request to clean 1662 * 1663 * This is used in the progress routine to clean the tx or 1664 * by the ULP to toss an in-process tx build. 1665 * 1666 * The code can be called multiple times without issue. 1667 * 1668 */ 1669 void __sdma_txclean( 1670 struct hfi1_devdata *dd, 1671 struct sdma_txreq *tx) 1672 { 1673 u16 i; 1674 1675 if (tx->num_desc) { 1676 u8 skip = 0, mode = ahg_mode(tx); 1677 1678 /* unmap first */ 1679 sdma_unmap_desc(dd, &tx->descp[0]); 1680 /* determine number of AHG descriptors to skip */ 1681 if (mode > SDMA_AHG_APPLY_UPDATE1) 1682 skip = mode >> 1; 1683 for (i = 1 + skip; i < tx->num_desc; i++) 1684 sdma_unmap_desc(dd, &tx->descp[i]); 1685 tx->num_desc = 0; 1686 } 1687 kfree(tx->coalesce_buf); 1688 tx->coalesce_buf = NULL; 1689 /* kmalloc'ed descp */ 1690 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) { 1691 tx->desc_limit = ARRAY_SIZE(tx->descs); 1692 kfree(tx->descp); 1693 } 1694 } 1695 1696 static inline u16 sdma_gethead(struct sdma_engine *sde) 1697 { 1698 struct hfi1_devdata *dd = sde->dd; 1699 int use_dmahead; 1700 u16 hwhead; 1701 1702 #ifdef CONFIG_SDMA_VERBOSITY 1703 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 1704 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 1705 #endif 1706 1707 retry: 1708 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) && 1709 (dd->flags & HFI1_HAS_SDMA_TIMEOUT); 1710 hwhead = use_dmahead ? 1711 (u16)le64_to_cpu(*sde->head_dma) : 1712 (u16)read_sde_csr(sde, SD(HEAD)); 1713 1714 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) { 1715 u16 cnt; 1716 u16 swtail; 1717 u16 swhead; 1718 int sane; 1719 1720 swhead = sde->descq_head & sde->sdma_mask; 1721 /* this code is really bad for cache line trading */ 1722 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask; 1723 cnt = sde->descq_cnt; 1724 1725 if (swhead < swtail) 1726 /* not wrapped */ 1727 sane = (hwhead >= swhead) & (hwhead <= swtail); 1728 else if (swhead > swtail) 1729 /* wrapped around */ 1730 sane = ((hwhead >= swhead) && (hwhead < cnt)) || 1731 (hwhead <= swtail); 1732 else 1733 /* empty */ 1734 sane = (hwhead == swhead); 1735 1736 if (unlikely(!sane)) { 1737 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n", 1738 sde->this_idx, 1739 use_dmahead ? "dma" : "kreg", 1740 hwhead, swhead, swtail, cnt); 1741 if (use_dmahead) { 1742 /* try one more time, using csr */ 1743 use_dmahead = 0; 1744 goto retry; 1745 } 1746 /* proceed as if no progress */ 1747 hwhead = swhead; 1748 } 1749 } 1750 return hwhead; 1751 } 1752 1753 /* 1754 * This is called when there are send DMA descriptors that might be 1755 * available. 1756 * 1757 * This is called with head_lock held. 1758 */ 1759 static void sdma_desc_avail(struct sdma_engine *sde, uint avail) 1760 { 1761 struct iowait *wait, *nw; 1762 struct iowait *waits[SDMA_WAIT_BATCH_SIZE]; 1763 uint i, n = 0, seq, max_idx = 0; 1764 struct sdma_txreq *stx; 1765 struct hfi1_ibdev *dev = &sde->dd->verbs_dev; 1766 u8 max_starved_cnt = 0; 1767 1768 #ifdef CONFIG_SDMA_VERBOSITY 1769 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, 1770 slashstrip(__FILE__), __LINE__, __func__); 1771 dd_dev_err(sde->dd, "avail: %u\n", avail); 1772 #endif 1773 1774 do { 1775 seq = read_seqbegin(&dev->iowait_lock); 1776 if (!list_empty(&sde->dmawait)) { 1777 /* at least one item */ 1778 write_seqlock(&dev->iowait_lock); 1779 /* Harvest waiters wanting DMA descriptors */ 1780 list_for_each_entry_safe( 1781 wait, 1782 nw, 1783 &sde->dmawait, 1784 list) { 1785 u16 num_desc = 0; 1786 1787 if (!wait->wakeup) 1788 continue; 1789 if (n == ARRAY_SIZE(waits)) 1790 break; 1791 if (!list_empty(&wait->tx_head)) { 1792 stx = list_first_entry( 1793 &wait->tx_head, 1794 struct sdma_txreq, 1795 list); 1796 num_desc = stx->num_desc; 1797 } 1798 if (num_desc > avail) 1799 break; 1800 avail -= num_desc; 1801 /* Find the most starved wait memeber */ 1802 iowait_starve_find_max(wait, &max_starved_cnt, 1803 n, &max_idx); 1804 list_del_init(&wait->list); 1805 waits[n++] = wait; 1806 } 1807 write_sequnlock(&dev->iowait_lock); 1808 break; 1809 } 1810 } while (read_seqretry(&dev->iowait_lock, seq)); 1811 1812 /* Schedule the most starved one first */ 1813 if (n) 1814 waits[max_idx]->wakeup(waits[max_idx], SDMA_AVAIL_REASON); 1815 1816 for (i = 0; i < n; i++) 1817 if (i != max_idx) 1818 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON); 1819 } 1820 1821 /* head_lock must be held */ 1822 static void sdma_make_progress(struct sdma_engine *sde, u64 status) 1823 { 1824 struct sdma_txreq *txp = NULL; 1825 int progress = 0; 1826 u16 hwhead, swhead; 1827 int idle_check_done = 0; 1828 1829 hwhead = sdma_gethead(sde); 1830 1831 /* The reason for some of the complexity of this code is that 1832 * not all descriptors have corresponding txps. So, we have to 1833 * be able to skip over descs until we wander into the range of 1834 * the next txp on the list. 1835 */ 1836 1837 retry: 1838 txp = get_txhead(sde); 1839 swhead = sde->descq_head & sde->sdma_mask; 1840 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); 1841 while (swhead != hwhead) { 1842 /* advance head, wrap if needed */ 1843 swhead = ++sde->descq_head & sde->sdma_mask; 1844 1845 /* if now past this txp's descs, do the callback */ 1846 if (txp && txp->next_descq_idx == swhead) { 1847 /* remove from list */ 1848 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; 1849 complete_tx(sde, txp, SDMA_TXREQ_S_OK); 1850 /* see if there is another txp */ 1851 txp = get_txhead(sde); 1852 } 1853 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); 1854 progress++; 1855 } 1856 1857 /* 1858 * The SDMA idle interrupt is not guaranteed to be ordered with respect 1859 * to updates to the the dma_head location in host memory. The head 1860 * value read might not be fully up to date. If there are pending 1861 * descriptors and the SDMA idle interrupt fired then read from the 1862 * CSR SDMA head instead to get the latest value from the hardware. 1863 * The hardware SDMA head should be read at most once in this invocation 1864 * of sdma_make_progress(..) which is ensured by idle_check_done flag 1865 */ 1866 if ((status & sde->idle_mask) && !idle_check_done) { 1867 u16 swtail; 1868 1869 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask; 1870 if (swtail != hwhead) { 1871 hwhead = (u16)read_sde_csr(sde, SD(HEAD)); 1872 idle_check_done = 1; 1873 goto retry; 1874 } 1875 } 1876 1877 sde->last_status = status; 1878 if (progress) 1879 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 1880 } 1881 1882 /* 1883 * sdma_engine_interrupt() - interrupt handler for engine 1884 * @sde: sdma engine 1885 * @status: sdma interrupt reason 1886 * 1887 * Status is a mask of the 3 possible interrupts for this engine. It will 1888 * contain bits _only_ for this SDMA engine. It will contain at least one 1889 * bit, it may contain more. 1890 */ 1891 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status) 1892 { 1893 trace_hfi1_sdma_engine_interrupt(sde, status); 1894 write_seqlock(&sde->head_lock); 1895 sdma_set_desc_cnt(sde, sdma_desct_intr); 1896 if (status & sde->idle_mask) 1897 sde->idle_int_cnt++; 1898 else if (status & sde->progress_mask) 1899 sde->progress_int_cnt++; 1900 else if (status & sde->int_mask) 1901 sde->sdma_int_cnt++; 1902 sdma_make_progress(sde, status); 1903 write_sequnlock(&sde->head_lock); 1904 } 1905 1906 /** 1907 * sdma_engine_error() - error handler for engine 1908 * @sde: sdma engine 1909 * @status: sdma interrupt reason 1910 */ 1911 void sdma_engine_error(struct sdma_engine *sde, u64 status) 1912 { 1913 unsigned long flags; 1914 1915 #ifdef CONFIG_SDMA_VERBOSITY 1916 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n", 1917 sde->this_idx, 1918 (unsigned long long)status, 1919 sdma_state_names[sde->state.current_state]); 1920 #endif 1921 spin_lock_irqsave(&sde->tail_lock, flags); 1922 write_seqlock(&sde->head_lock); 1923 if (status & ALL_SDMA_ENG_HALT_ERRS) 1924 __sdma_process_event(sde, sdma_event_e60_hw_halted); 1925 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) { 1926 dd_dev_err(sde->dd, 1927 "SDMA (%u) engine error: 0x%llx state %s\n", 1928 sde->this_idx, 1929 (unsigned long long)status, 1930 sdma_state_names[sde->state.current_state]); 1931 dump_sdma_state(sde); 1932 } 1933 write_sequnlock(&sde->head_lock); 1934 spin_unlock_irqrestore(&sde->tail_lock, flags); 1935 } 1936 1937 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op) 1938 { 1939 u64 set_senddmactrl = 0; 1940 u64 clr_senddmactrl = 0; 1941 unsigned long flags; 1942 1943 #ifdef CONFIG_SDMA_VERBOSITY 1944 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n", 1945 sde->this_idx, 1946 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0, 1947 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0, 1948 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0, 1949 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0); 1950 #endif 1951 1952 if (op & SDMA_SENDCTRL_OP_ENABLE) 1953 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); 1954 else 1955 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); 1956 1957 if (op & SDMA_SENDCTRL_OP_INTENABLE) 1958 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); 1959 else 1960 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); 1961 1962 if (op & SDMA_SENDCTRL_OP_HALT) 1963 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); 1964 else 1965 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); 1966 1967 spin_lock_irqsave(&sde->senddmactrl_lock, flags); 1968 1969 sde->p_senddmactrl |= set_senddmactrl; 1970 sde->p_senddmactrl &= ~clr_senddmactrl; 1971 1972 if (op & SDMA_SENDCTRL_OP_CLEANUP) 1973 write_sde_csr(sde, SD(CTRL), 1974 sde->p_senddmactrl | 1975 SD(CTRL_SDMA_CLEANUP_SMASK)); 1976 else 1977 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl); 1978 1979 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags); 1980 1981 #ifdef CONFIG_SDMA_VERBOSITY 1982 sdma_dumpstate(sde); 1983 #endif 1984 } 1985 1986 static void sdma_setlengen(struct sdma_engine *sde) 1987 { 1988 #ifdef CONFIG_SDMA_VERBOSITY 1989 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 1990 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 1991 #endif 1992 1993 /* 1994 * Set SendDmaLenGen and clear-then-set the MSB of the generation 1995 * count to enable generation checking and load the internal 1996 * generation counter. 1997 */ 1998 write_sde_csr(sde, SD(LEN_GEN), 1999 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)); 2000 write_sde_csr(sde, SD(LEN_GEN), 2001 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) | 2002 (4ULL << SD(LEN_GEN_GENERATION_SHIFT))); 2003 } 2004 2005 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail) 2006 { 2007 /* Commit writes to memory and advance the tail on the chip */ 2008 smp_wmb(); /* see get_txhead() */ 2009 writeq(tail, sde->tail_csr); 2010 } 2011 2012 /* 2013 * This is called when changing to state s10_hw_start_up_halt_wait as 2014 * a result of send buffer errors or send DMA descriptor errors. 2015 */ 2016 static void sdma_hw_start_up(struct sdma_engine *sde) 2017 { 2018 u64 reg; 2019 2020 #ifdef CONFIG_SDMA_VERBOSITY 2021 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", 2022 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 2023 #endif 2024 2025 sdma_setlengen(sde); 2026 sdma_update_tail(sde, 0); /* Set SendDmaTail */ 2027 *sde->head_dma = 0; 2028 2029 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) << 2030 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT); 2031 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg); 2032 } 2033 2034 /* 2035 * set_sdma_integrity 2036 * 2037 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'. 2038 */ 2039 static void set_sdma_integrity(struct sdma_engine *sde) 2040 { 2041 struct hfi1_devdata *dd = sde->dd; 2042 2043 write_sde_csr(sde, SD(CHECK_ENABLE), 2044 hfi1_pkt_base_sdma_integrity(dd)); 2045 } 2046 2047 static void init_sdma_regs( 2048 struct sdma_engine *sde, 2049 u32 credits, 2050 uint idle_cnt) 2051 { 2052 u8 opval, opmask; 2053 #ifdef CONFIG_SDMA_VERBOSITY 2054 struct hfi1_devdata *dd = sde->dd; 2055 2056 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", 2057 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); 2058 #endif 2059 2060 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys); 2061 sdma_setlengen(sde); 2062 sdma_update_tail(sde, 0); /* Set SendDmaTail */ 2063 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt); 2064 write_sde_csr(sde, SD(DESC_CNT), 0); 2065 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys); 2066 write_sde_csr(sde, SD(MEMORY), 2067 ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) | 2068 ((u64)(credits * sde->this_idx) << 2069 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT))); 2070 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull); 2071 set_sdma_integrity(sde); 2072 opmask = OPCODE_CHECK_MASK_DISABLED; 2073 opval = OPCODE_CHECK_VAL_DISABLED; 2074 write_sde_csr(sde, SD(CHECK_OPCODE), 2075 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) | 2076 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT)); 2077 } 2078 2079 #ifdef CONFIG_SDMA_VERBOSITY 2080 2081 #define sdma_dumpstate_helper0(reg) do { \ 2082 csr = read_csr(sde->dd, reg); \ 2083 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \ 2084 } while (0) 2085 2086 #define sdma_dumpstate_helper(reg) do { \ 2087 csr = read_sde_csr(sde, reg); \ 2088 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \ 2089 #reg, sde->this_idx, csr); \ 2090 } while (0) 2091 2092 #define sdma_dumpstate_helper2(reg) do { \ 2093 csr = read_csr(sde->dd, reg + (8 * i)); \ 2094 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \ 2095 #reg, i, csr); \ 2096 } while (0) 2097 2098 void sdma_dumpstate(struct sdma_engine *sde) 2099 { 2100 u64 csr; 2101 unsigned i; 2102 2103 sdma_dumpstate_helper(SD(CTRL)); 2104 sdma_dumpstate_helper(SD(STATUS)); 2105 sdma_dumpstate_helper0(SD(ERR_STATUS)); 2106 sdma_dumpstate_helper0(SD(ERR_MASK)); 2107 sdma_dumpstate_helper(SD(ENG_ERR_STATUS)); 2108 sdma_dumpstate_helper(SD(ENG_ERR_MASK)); 2109 2110 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) { 2111 sdma_dumpstate_helper2(CCE_INT_STATUS); 2112 sdma_dumpstate_helper2(CCE_INT_MASK); 2113 sdma_dumpstate_helper2(CCE_INT_BLOCKED); 2114 } 2115 2116 sdma_dumpstate_helper(SD(TAIL)); 2117 sdma_dumpstate_helper(SD(HEAD)); 2118 sdma_dumpstate_helper(SD(PRIORITY_THLD)); 2119 sdma_dumpstate_helper(SD(IDLE_CNT)); 2120 sdma_dumpstate_helper(SD(RELOAD_CNT)); 2121 sdma_dumpstate_helper(SD(DESC_CNT)); 2122 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT)); 2123 sdma_dumpstate_helper(SD(MEMORY)); 2124 sdma_dumpstate_helper0(SD(ENGINES)); 2125 sdma_dumpstate_helper0(SD(MEM_SIZE)); 2126 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */ 2127 sdma_dumpstate_helper(SD(BASE_ADDR)); 2128 sdma_dumpstate_helper(SD(LEN_GEN)); 2129 sdma_dumpstate_helper(SD(HEAD_ADDR)); 2130 sdma_dumpstate_helper(SD(CHECK_ENABLE)); 2131 sdma_dumpstate_helper(SD(CHECK_VL)); 2132 sdma_dumpstate_helper(SD(CHECK_JOB_KEY)); 2133 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY)); 2134 sdma_dumpstate_helper(SD(CHECK_SLID)); 2135 sdma_dumpstate_helper(SD(CHECK_OPCODE)); 2136 } 2137 #endif 2138 2139 static void dump_sdma_state(struct sdma_engine *sde) 2140 { 2141 struct hw_sdma_desc *descqp; 2142 u64 desc[2]; 2143 u64 addr; 2144 u8 gen; 2145 u16 len; 2146 u16 head, tail, cnt; 2147 2148 head = sde->descq_head & sde->sdma_mask; 2149 tail = sde->descq_tail & sde->sdma_mask; 2150 cnt = sdma_descq_freecnt(sde); 2151 2152 dd_dev_err(sde->dd, 2153 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n", 2154 sde->this_idx, head, tail, cnt, 2155 !list_empty(&sde->flushlist)); 2156 2157 /* print info for each entry in the descriptor queue */ 2158 while (head != tail) { 2159 char flags[6] = { 'x', 'x', 'x', 'x', 0 }; 2160 2161 descqp = &sde->descq[head]; 2162 desc[0] = le64_to_cpu(descqp->qw[0]); 2163 desc[1] = le64_to_cpu(descqp->qw[1]); 2164 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; 2165 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? 2166 'H' : '-'; 2167 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; 2168 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; 2169 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) 2170 & SDMA_DESC0_PHY_ADDR_MASK; 2171 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) 2172 & SDMA_DESC1_GENERATION_MASK; 2173 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) 2174 & SDMA_DESC0_BYTE_COUNT_MASK; 2175 dd_dev_err(sde->dd, 2176 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", 2177 head, flags, addr, gen, len); 2178 dd_dev_err(sde->dd, 2179 "\tdesc0:0x%016llx desc1 0x%016llx\n", 2180 desc[0], desc[1]); 2181 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) 2182 dd_dev_err(sde->dd, 2183 "\taidx: %u amode: %u alen: %u\n", 2184 (u8)((desc[1] & 2185 SDMA_DESC1_HEADER_INDEX_SMASK) >> 2186 SDMA_DESC1_HEADER_INDEX_SHIFT), 2187 (u8)((desc[1] & 2188 SDMA_DESC1_HEADER_MODE_SMASK) >> 2189 SDMA_DESC1_HEADER_MODE_SHIFT), 2190 (u8)((desc[1] & 2191 SDMA_DESC1_HEADER_DWS_SMASK) >> 2192 SDMA_DESC1_HEADER_DWS_SHIFT)); 2193 head++; 2194 head &= sde->sdma_mask; 2195 } 2196 } 2197 2198 #define SDE_FMT \ 2199 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n" 2200 /** 2201 * sdma_seqfile_dump_sde() - debugfs dump of sde 2202 * @s: seq file 2203 * @sde: send dma engine to dump 2204 * 2205 * This routine dumps the sde to the indicated seq file. 2206 */ 2207 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde) 2208 { 2209 u16 head, tail; 2210 struct hw_sdma_desc *descqp; 2211 u64 desc[2]; 2212 u64 addr; 2213 u8 gen; 2214 u16 len; 2215 2216 head = sde->descq_head & sde->sdma_mask; 2217 tail = READ_ONCE(sde->descq_tail) & sde->sdma_mask; 2218 seq_printf(s, SDE_FMT, sde->this_idx, 2219 sde->cpu, 2220 sdma_state_name(sde->state.current_state), 2221 (unsigned long long)read_sde_csr(sde, SD(CTRL)), 2222 (unsigned long long)read_sde_csr(sde, SD(STATUS)), 2223 (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)), 2224 (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail, 2225 (unsigned long long)read_sde_csr(sde, SD(HEAD)), head, 2226 (unsigned long long)le64_to_cpu(*sde->head_dma), 2227 (unsigned long long)read_sde_csr(sde, SD(MEMORY)), 2228 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)), 2229 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)), 2230 (unsigned long long)sde->last_status, 2231 (unsigned long long)sde->ahg_bits, 2232 sde->tx_tail, 2233 sde->tx_head, 2234 sde->descq_tail, 2235 sde->descq_head, 2236 !list_empty(&sde->flushlist), 2237 sde->descq_full_count, 2238 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID)); 2239 2240 /* print info for each entry in the descriptor queue */ 2241 while (head != tail) { 2242 char flags[6] = { 'x', 'x', 'x', 'x', 0 }; 2243 2244 descqp = &sde->descq[head]; 2245 desc[0] = le64_to_cpu(descqp->qw[0]); 2246 desc[1] = le64_to_cpu(descqp->qw[1]); 2247 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; 2248 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? 2249 'H' : '-'; 2250 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; 2251 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; 2252 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) 2253 & SDMA_DESC0_PHY_ADDR_MASK; 2254 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) 2255 & SDMA_DESC1_GENERATION_MASK; 2256 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) 2257 & SDMA_DESC0_BYTE_COUNT_MASK; 2258 seq_printf(s, 2259 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", 2260 head, flags, addr, gen, len); 2261 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) 2262 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n", 2263 (u8)((desc[1] & 2264 SDMA_DESC1_HEADER_INDEX_SMASK) >> 2265 SDMA_DESC1_HEADER_INDEX_SHIFT), 2266 (u8)((desc[1] & 2267 SDMA_DESC1_HEADER_MODE_SMASK) >> 2268 SDMA_DESC1_HEADER_MODE_SHIFT)); 2269 head = (head + 1) & sde->sdma_mask; 2270 } 2271 } 2272 2273 /* 2274 * add the generation number into 2275 * the qw1 and return 2276 */ 2277 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1) 2278 { 2279 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3; 2280 2281 qw1 &= ~SDMA_DESC1_GENERATION_SMASK; 2282 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK) 2283 << SDMA_DESC1_GENERATION_SHIFT; 2284 return qw1; 2285 } 2286 2287 /* 2288 * This routine submits the indicated tx 2289 * 2290 * Space has already been guaranteed and 2291 * tail side of ring is locked. 2292 * 2293 * The hardware tail update is done 2294 * in the caller and that is facilitated 2295 * by returning the new tail. 2296 * 2297 * There is special case logic for ahg 2298 * to not add the generation number for 2299 * up to 2 descriptors that follow the 2300 * first descriptor. 2301 * 2302 */ 2303 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx) 2304 { 2305 int i; 2306 u16 tail; 2307 struct sdma_desc *descp = tx->descp; 2308 u8 skip = 0, mode = ahg_mode(tx); 2309 2310 tail = sde->descq_tail & sde->sdma_mask; 2311 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); 2312 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1])); 2313 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1], 2314 tail, &sde->descq[tail]); 2315 tail = ++sde->descq_tail & sde->sdma_mask; 2316 descp++; 2317 if (mode > SDMA_AHG_APPLY_UPDATE1) 2318 skip = mode >> 1; 2319 for (i = 1; i < tx->num_desc; i++, descp++) { 2320 u64 qw1; 2321 2322 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); 2323 if (skip) { 2324 /* edits don't have generation */ 2325 qw1 = descp->qw[1]; 2326 skip--; 2327 } else { 2328 /* replace generation with real one for non-edits */ 2329 qw1 = add_gen(sde, descp->qw[1]); 2330 } 2331 sde->descq[tail].qw[1] = cpu_to_le64(qw1); 2332 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1, 2333 tail, &sde->descq[tail]); 2334 tail = ++sde->descq_tail & sde->sdma_mask; 2335 } 2336 tx->next_descq_idx = tail; 2337 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2338 tx->sn = sde->tail_sn++; 2339 trace_hfi1_sdma_in_sn(sde, tx->sn); 2340 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]); 2341 #endif 2342 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx; 2343 sde->desc_avail -= tx->num_desc; 2344 return tail; 2345 } 2346 2347 /* 2348 * Check for progress 2349 */ 2350 static int sdma_check_progress( 2351 struct sdma_engine *sde, 2352 struct iowait *wait, 2353 struct sdma_txreq *tx, 2354 bool pkts_sent) 2355 { 2356 int ret; 2357 2358 sde->desc_avail = sdma_descq_freecnt(sde); 2359 if (tx->num_desc <= sde->desc_avail) 2360 return -EAGAIN; 2361 /* pulse the head_lock */ 2362 if (wait && wait->sleep) { 2363 unsigned seq; 2364 2365 seq = raw_seqcount_begin( 2366 (const seqcount_t *)&sde->head_lock.seqcount); 2367 ret = wait->sleep(sde, wait, tx, seq, pkts_sent); 2368 if (ret == -EAGAIN) 2369 sde->desc_avail = sdma_descq_freecnt(sde); 2370 } else { 2371 ret = -EBUSY; 2372 } 2373 return ret; 2374 } 2375 2376 /** 2377 * sdma_send_txreq() - submit a tx req to ring 2378 * @sde: sdma engine to use 2379 * @wait: wait structure to use when full (may be NULL) 2380 * @tx: sdma_txreq to submit 2381 * @pkts_sent: has any packet been sent yet? 2382 * 2383 * The call submits the tx into the ring. If a iowait structure is non-NULL 2384 * the packet will be queued to the list in wait. 2385 * 2386 * Return: 2387 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in 2388 * ring (wait == NULL) 2389 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state 2390 */ 2391 int sdma_send_txreq(struct sdma_engine *sde, 2392 struct iowait *wait, 2393 struct sdma_txreq *tx, 2394 bool pkts_sent) 2395 { 2396 int ret = 0; 2397 u16 tail; 2398 unsigned long flags; 2399 2400 /* user should have supplied entire packet */ 2401 if (unlikely(tx->tlen)) 2402 return -EINVAL; 2403 tx->wait = wait; 2404 spin_lock_irqsave(&sde->tail_lock, flags); 2405 retry: 2406 if (unlikely(!__sdma_running(sde))) 2407 goto unlock_noconn; 2408 if (unlikely(tx->num_desc > sde->desc_avail)) 2409 goto nodesc; 2410 tail = submit_tx(sde, tx); 2411 if (wait) 2412 iowait_sdma_inc(wait); 2413 sdma_update_tail(sde, tail); 2414 unlock: 2415 spin_unlock_irqrestore(&sde->tail_lock, flags); 2416 return ret; 2417 unlock_noconn: 2418 if (wait) 2419 iowait_sdma_inc(wait); 2420 tx->next_descq_idx = 0; 2421 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2422 tx->sn = sde->tail_sn++; 2423 trace_hfi1_sdma_in_sn(sde, tx->sn); 2424 #endif 2425 spin_lock(&sde->flushlist_lock); 2426 list_add_tail(&tx->list, &sde->flushlist); 2427 spin_unlock(&sde->flushlist_lock); 2428 if (wait) { 2429 wait->tx_count++; 2430 wait->count += tx->num_desc; 2431 } 2432 schedule_work(&sde->flush_worker); 2433 ret = -ECOMM; 2434 goto unlock; 2435 nodesc: 2436 ret = sdma_check_progress(sde, wait, tx, pkts_sent); 2437 if (ret == -EAGAIN) { 2438 ret = 0; 2439 goto retry; 2440 } 2441 sde->descq_full_count++; 2442 goto unlock; 2443 } 2444 2445 /** 2446 * sdma_send_txlist() - submit a list of tx req to ring 2447 * @sde: sdma engine to use 2448 * @wait: wait structure to use when full (may be NULL) 2449 * @tx_list: list of sdma_txreqs to submit 2450 * @count: pointer to a u32 which, after return will contain the total number of 2451 * sdma_txreqs removed from the tx_list. This will include sdma_txreqs 2452 * whose SDMA descriptors are submitted to the ring and the sdma_txreqs 2453 * which are added to SDMA engine flush list if the SDMA engine state is 2454 * not running. 2455 * 2456 * The call submits the list into the ring. 2457 * 2458 * If the iowait structure is non-NULL and not equal to the iowait list 2459 * the unprocessed part of the list will be appended to the list in wait. 2460 * 2461 * In all cases, the tx_list will be updated so the head of the tx_list is 2462 * the list of descriptors that have yet to be transmitted. 2463 * 2464 * The intent of this call is to provide a more efficient 2465 * way of submitting multiple packets to SDMA while holding the tail 2466 * side locking. 2467 * 2468 * Return: 2469 * 0 - Success, 2470 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL) 2471 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state 2472 */ 2473 int sdma_send_txlist(struct sdma_engine *sde, struct iowait *wait, 2474 struct list_head *tx_list, u32 *count_out) 2475 { 2476 struct sdma_txreq *tx, *tx_next; 2477 int ret = 0; 2478 unsigned long flags; 2479 u16 tail = INVALID_TAIL; 2480 u32 submit_count = 0, flush_count = 0, total_count; 2481 2482 spin_lock_irqsave(&sde->tail_lock, flags); 2483 retry: 2484 list_for_each_entry_safe(tx, tx_next, tx_list, list) { 2485 tx->wait = wait; 2486 if (unlikely(!__sdma_running(sde))) 2487 goto unlock_noconn; 2488 if (unlikely(tx->num_desc > sde->desc_avail)) 2489 goto nodesc; 2490 if (unlikely(tx->tlen)) { 2491 ret = -EINVAL; 2492 goto update_tail; 2493 } 2494 list_del_init(&tx->list); 2495 tail = submit_tx(sde, tx); 2496 submit_count++; 2497 if (tail != INVALID_TAIL && 2498 (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) { 2499 sdma_update_tail(sde, tail); 2500 tail = INVALID_TAIL; 2501 } 2502 } 2503 update_tail: 2504 total_count = submit_count + flush_count; 2505 if (wait) { 2506 iowait_sdma_add(wait, total_count); 2507 iowait_starve_clear(submit_count > 0, wait); 2508 } 2509 if (tail != INVALID_TAIL) 2510 sdma_update_tail(sde, tail); 2511 spin_unlock_irqrestore(&sde->tail_lock, flags); 2512 *count_out = total_count; 2513 return ret; 2514 unlock_noconn: 2515 spin_lock(&sde->flushlist_lock); 2516 list_for_each_entry_safe(tx, tx_next, tx_list, list) { 2517 tx->wait = wait; 2518 list_del_init(&tx->list); 2519 tx->next_descq_idx = 0; 2520 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER 2521 tx->sn = sde->tail_sn++; 2522 trace_hfi1_sdma_in_sn(sde, tx->sn); 2523 #endif 2524 list_add_tail(&tx->list, &sde->flushlist); 2525 flush_count++; 2526 if (wait) { 2527 wait->tx_count++; 2528 wait->count += tx->num_desc; 2529 } 2530 } 2531 spin_unlock(&sde->flushlist_lock); 2532 schedule_work(&sde->flush_worker); 2533 ret = -ECOMM; 2534 goto update_tail; 2535 nodesc: 2536 ret = sdma_check_progress(sde, wait, tx, submit_count > 0); 2537 if (ret == -EAGAIN) { 2538 ret = 0; 2539 goto retry; 2540 } 2541 sde->descq_full_count++; 2542 goto update_tail; 2543 } 2544 2545 static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event) 2546 { 2547 unsigned long flags; 2548 2549 spin_lock_irqsave(&sde->tail_lock, flags); 2550 write_seqlock(&sde->head_lock); 2551 2552 __sdma_process_event(sde, event); 2553 2554 if (sde->state.current_state == sdma_state_s99_running) 2555 sdma_desc_avail(sde, sdma_descq_freecnt(sde)); 2556 2557 write_sequnlock(&sde->head_lock); 2558 spin_unlock_irqrestore(&sde->tail_lock, flags); 2559 } 2560 2561 static void __sdma_process_event(struct sdma_engine *sde, 2562 enum sdma_events event) 2563 { 2564 struct sdma_state *ss = &sde->state; 2565 int need_progress = 0; 2566 2567 /* CONFIG SDMA temporary */ 2568 #ifdef CONFIG_SDMA_VERBOSITY 2569 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx, 2570 sdma_state_names[ss->current_state], 2571 sdma_event_names[event]); 2572 #endif 2573 2574 switch (ss->current_state) { 2575 case sdma_state_s00_hw_down: 2576 switch (event) { 2577 case sdma_event_e00_go_hw_down: 2578 break; 2579 case sdma_event_e30_go_running: 2580 /* 2581 * If down, but running requested (usually result 2582 * of link up, then we need to start up. 2583 * This can happen when hw down is requested while 2584 * bringing the link up with traffic active on 2585 * 7220, e.g. 2586 */ 2587 ss->go_s99_running = 1; 2588 /* fall through -- and start dma engine */ 2589 case sdma_event_e10_go_hw_start: 2590 /* This reference means the state machine is started */ 2591 sdma_get(&sde->state); 2592 sdma_set_state(sde, 2593 sdma_state_s10_hw_start_up_halt_wait); 2594 break; 2595 case sdma_event_e15_hw_halt_done: 2596 break; 2597 case sdma_event_e25_hw_clean_up_done: 2598 break; 2599 case sdma_event_e40_sw_cleaned: 2600 sdma_sw_tear_down(sde); 2601 break; 2602 case sdma_event_e50_hw_cleaned: 2603 break; 2604 case sdma_event_e60_hw_halted: 2605 break; 2606 case sdma_event_e70_go_idle: 2607 break; 2608 case sdma_event_e80_hw_freeze: 2609 break; 2610 case sdma_event_e81_hw_frozen: 2611 break; 2612 case sdma_event_e82_hw_unfreeze: 2613 break; 2614 case sdma_event_e85_link_down: 2615 break; 2616 case sdma_event_e90_sw_halted: 2617 break; 2618 } 2619 break; 2620 2621 case sdma_state_s10_hw_start_up_halt_wait: 2622 switch (event) { 2623 case sdma_event_e00_go_hw_down: 2624 sdma_set_state(sde, sdma_state_s00_hw_down); 2625 sdma_sw_tear_down(sde); 2626 break; 2627 case sdma_event_e10_go_hw_start: 2628 break; 2629 case sdma_event_e15_hw_halt_done: 2630 sdma_set_state(sde, 2631 sdma_state_s15_hw_start_up_clean_wait); 2632 sdma_start_hw_clean_up(sde); 2633 break; 2634 case sdma_event_e25_hw_clean_up_done: 2635 break; 2636 case sdma_event_e30_go_running: 2637 ss->go_s99_running = 1; 2638 break; 2639 case sdma_event_e40_sw_cleaned: 2640 break; 2641 case sdma_event_e50_hw_cleaned: 2642 break; 2643 case sdma_event_e60_hw_halted: 2644 schedule_work(&sde->err_halt_worker); 2645 break; 2646 case sdma_event_e70_go_idle: 2647 ss->go_s99_running = 0; 2648 break; 2649 case sdma_event_e80_hw_freeze: 2650 break; 2651 case sdma_event_e81_hw_frozen: 2652 break; 2653 case sdma_event_e82_hw_unfreeze: 2654 break; 2655 case sdma_event_e85_link_down: 2656 break; 2657 case sdma_event_e90_sw_halted: 2658 break; 2659 } 2660 break; 2661 2662 case sdma_state_s15_hw_start_up_clean_wait: 2663 switch (event) { 2664 case sdma_event_e00_go_hw_down: 2665 sdma_set_state(sde, sdma_state_s00_hw_down); 2666 sdma_sw_tear_down(sde); 2667 break; 2668 case sdma_event_e10_go_hw_start: 2669 break; 2670 case sdma_event_e15_hw_halt_done: 2671 break; 2672 case sdma_event_e25_hw_clean_up_done: 2673 sdma_hw_start_up(sde); 2674 sdma_set_state(sde, ss->go_s99_running ? 2675 sdma_state_s99_running : 2676 sdma_state_s20_idle); 2677 break; 2678 case sdma_event_e30_go_running: 2679 ss->go_s99_running = 1; 2680 break; 2681 case sdma_event_e40_sw_cleaned: 2682 break; 2683 case sdma_event_e50_hw_cleaned: 2684 break; 2685 case sdma_event_e60_hw_halted: 2686 break; 2687 case sdma_event_e70_go_idle: 2688 ss->go_s99_running = 0; 2689 break; 2690 case sdma_event_e80_hw_freeze: 2691 break; 2692 case sdma_event_e81_hw_frozen: 2693 break; 2694 case sdma_event_e82_hw_unfreeze: 2695 break; 2696 case sdma_event_e85_link_down: 2697 break; 2698 case sdma_event_e90_sw_halted: 2699 break; 2700 } 2701 break; 2702 2703 case sdma_state_s20_idle: 2704 switch (event) { 2705 case sdma_event_e00_go_hw_down: 2706 sdma_set_state(sde, sdma_state_s00_hw_down); 2707 sdma_sw_tear_down(sde); 2708 break; 2709 case sdma_event_e10_go_hw_start: 2710 break; 2711 case sdma_event_e15_hw_halt_done: 2712 break; 2713 case sdma_event_e25_hw_clean_up_done: 2714 break; 2715 case sdma_event_e30_go_running: 2716 sdma_set_state(sde, sdma_state_s99_running); 2717 ss->go_s99_running = 1; 2718 break; 2719 case sdma_event_e40_sw_cleaned: 2720 break; 2721 case sdma_event_e50_hw_cleaned: 2722 break; 2723 case sdma_event_e60_hw_halted: 2724 sdma_set_state(sde, sdma_state_s50_hw_halt_wait); 2725 schedule_work(&sde->err_halt_worker); 2726 break; 2727 case sdma_event_e70_go_idle: 2728 break; 2729 case sdma_event_e85_link_down: 2730 /* fall through */ 2731 case sdma_event_e80_hw_freeze: 2732 sdma_set_state(sde, sdma_state_s80_hw_freeze); 2733 atomic_dec(&sde->dd->sdma_unfreeze_count); 2734 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 2735 break; 2736 case sdma_event_e81_hw_frozen: 2737 break; 2738 case sdma_event_e82_hw_unfreeze: 2739 break; 2740 case sdma_event_e90_sw_halted: 2741 break; 2742 } 2743 break; 2744 2745 case sdma_state_s30_sw_clean_up_wait: 2746 switch (event) { 2747 case sdma_event_e00_go_hw_down: 2748 sdma_set_state(sde, sdma_state_s00_hw_down); 2749 break; 2750 case sdma_event_e10_go_hw_start: 2751 break; 2752 case sdma_event_e15_hw_halt_done: 2753 break; 2754 case sdma_event_e25_hw_clean_up_done: 2755 break; 2756 case sdma_event_e30_go_running: 2757 ss->go_s99_running = 1; 2758 break; 2759 case sdma_event_e40_sw_cleaned: 2760 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait); 2761 sdma_start_hw_clean_up(sde); 2762 break; 2763 case sdma_event_e50_hw_cleaned: 2764 break; 2765 case sdma_event_e60_hw_halted: 2766 break; 2767 case sdma_event_e70_go_idle: 2768 ss->go_s99_running = 0; 2769 break; 2770 case sdma_event_e80_hw_freeze: 2771 break; 2772 case sdma_event_e81_hw_frozen: 2773 break; 2774 case sdma_event_e82_hw_unfreeze: 2775 break; 2776 case sdma_event_e85_link_down: 2777 ss->go_s99_running = 0; 2778 break; 2779 case sdma_event_e90_sw_halted: 2780 break; 2781 } 2782 break; 2783 2784 case sdma_state_s40_hw_clean_up_wait: 2785 switch (event) { 2786 case sdma_event_e00_go_hw_down: 2787 sdma_set_state(sde, sdma_state_s00_hw_down); 2788 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2789 break; 2790 case sdma_event_e10_go_hw_start: 2791 break; 2792 case sdma_event_e15_hw_halt_done: 2793 break; 2794 case sdma_event_e25_hw_clean_up_done: 2795 sdma_hw_start_up(sde); 2796 sdma_set_state(sde, ss->go_s99_running ? 2797 sdma_state_s99_running : 2798 sdma_state_s20_idle); 2799 break; 2800 case sdma_event_e30_go_running: 2801 ss->go_s99_running = 1; 2802 break; 2803 case sdma_event_e40_sw_cleaned: 2804 break; 2805 case sdma_event_e50_hw_cleaned: 2806 break; 2807 case sdma_event_e60_hw_halted: 2808 break; 2809 case sdma_event_e70_go_idle: 2810 ss->go_s99_running = 0; 2811 break; 2812 case sdma_event_e80_hw_freeze: 2813 break; 2814 case sdma_event_e81_hw_frozen: 2815 break; 2816 case sdma_event_e82_hw_unfreeze: 2817 break; 2818 case sdma_event_e85_link_down: 2819 ss->go_s99_running = 0; 2820 break; 2821 case sdma_event_e90_sw_halted: 2822 break; 2823 } 2824 break; 2825 2826 case sdma_state_s50_hw_halt_wait: 2827 switch (event) { 2828 case sdma_event_e00_go_hw_down: 2829 sdma_set_state(sde, sdma_state_s00_hw_down); 2830 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2831 break; 2832 case sdma_event_e10_go_hw_start: 2833 break; 2834 case sdma_event_e15_hw_halt_done: 2835 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); 2836 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2837 break; 2838 case sdma_event_e25_hw_clean_up_done: 2839 break; 2840 case sdma_event_e30_go_running: 2841 ss->go_s99_running = 1; 2842 break; 2843 case sdma_event_e40_sw_cleaned: 2844 break; 2845 case sdma_event_e50_hw_cleaned: 2846 break; 2847 case sdma_event_e60_hw_halted: 2848 schedule_work(&sde->err_halt_worker); 2849 break; 2850 case sdma_event_e70_go_idle: 2851 ss->go_s99_running = 0; 2852 break; 2853 case sdma_event_e80_hw_freeze: 2854 break; 2855 case sdma_event_e81_hw_frozen: 2856 break; 2857 case sdma_event_e82_hw_unfreeze: 2858 break; 2859 case sdma_event_e85_link_down: 2860 ss->go_s99_running = 0; 2861 break; 2862 case sdma_event_e90_sw_halted: 2863 break; 2864 } 2865 break; 2866 2867 case sdma_state_s60_idle_halt_wait: 2868 switch (event) { 2869 case sdma_event_e00_go_hw_down: 2870 sdma_set_state(sde, sdma_state_s00_hw_down); 2871 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2872 break; 2873 case sdma_event_e10_go_hw_start: 2874 break; 2875 case sdma_event_e15_hw_halt_done: 2876 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); 2877 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2878 break; 2879 case sdma_event_e25_hw_clean_up_done: 2880 break; 2881 case sdma_event_e30_go_running: 2882 ss->go_s99_running = 1; 2883 break; 2884 case sdma_event_e40_sw_cleaned: 2885 break; 2886 case sdma_event_e50_hw_cleaned: 2887 break; 2888 case sdma_event_e60_hw_halted: 2889 schedule_work(&sde->err_halt_worker); 2890 break; 2891 case sdma_event_e70_go_idle: 2892 ss->go_s99_running = 0; 2893 break; 2894 case sdma_event_e80_hw_freeze: 2895 break; 2896 case sdma_event_e81_hw_frozen: 2897 break; 2898 case sdma_event_e82_hw_unfreeze: 2899 break; 2900 case sdma_event_e85_link_down: 2901 break; 2902 case sdma_event_e90_sw_halted: 2903 break; 2904 } 2905 break; 2906 2907 case sdma_state_s80_hw_freeze: 2908 switch (event) { 2909 case sdma_event_e00_go_hw_down: 2910 sdma_set_state(sde, sdma_state_s00_hw_down); 2911 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2912 break; 2913 case sdma_event_e10_go_hw_start: 2914 break; 2915 case sdma_event_e15_hw_halt_done: 2916 break; 2917 case sdma_event_e25_hw_clean_up_done: 2918 break; 2919 case sdma_event_e30_go_running: 2920 ss->go_s99_running = 1; 2921 break; 2922 case sdma_event_e40_sw_cleaned: 2923 break; 2924 case sdma_event_e50_hw_cleaned: 2925 break; 2926 case sdma_event_e60_hw_halted: 2927 break; 2928 case sdma_event_e70_go_idle: 2929 ss->go_s99_running = 0; 2930 break; 2931 case sdma_event_e80_hw_freeze: 2932 break; 2933 case sdma_event_e81_hw_frozen: 2934 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean); 2935 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2936 break; 2937 case sdma_event_e82_hw_unfreeze: 2938 break; 2939 case sdma_event_e85_link_down: 2940 break; 2941 case sdma_event_e90_sw_halted: 2942 break; 2943 } 2944 break; 2945 2946 case sdma_state_s82_freeze_sw_clean: 2947 switch (event) { 2948 case sdma_event_e00_go_hw_down: 2949 sdma_set_state(sde, sdma_state_s00_hw_down); 2950 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2951 break; 2952 case sdma_event_e10_go_hw_start: 2953 break; 2954 case sdma_event_e15_hw_halt_done: 2955 break; 2956 case sdma_event_e25_hw_clean_up_done: 2957 break; 2958 case sdma_event_e30_go_running: 2959 ss->go_s99_running = 1; 2960 break; 2961 case sdma_event_e40_sw_cleaned: 2962 /* notify caller this engine is done cleaning */ 2963 atomic_dec(&sde->dd->sdma_unfreeze_count); 2964 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 2965 break; 2966 case sdma_event_e50_hw_cleaned: 2967 break; 2968 case sdma_event_e60_hw_halted: 2969 break; 2970 case sdma_event_e70_go_idle: 2971 ss->go_s99_running = 0; 2972 break; 2973 case sdma_event_e80_hw_freeze: 2974 break; 2975 case sdma_event_e81_hw_frozen: 2976 break; 2977 case sdma_event_e82_hw_unfreeze: 2978 sdma_hw_start_up(sde); 2979 sdma_set_state(sde, ss->go_s99_running ? 2980 sdma_state_s99_running : 2981 sdma_state_s20_idle); 2982 break; 2983 case sdma_event_e85_link_down: 2984 break; 2985 case sdma_event_e90_sw_halted: 2986 break; 2987 } 2988 break; 2989 2990 case sdma_state_s99_running: 2991 switch (event) { 2992 case sdma_event_e00_go_hw_down: 2993 sdma_set_state(sde, sdma_state_s00_hw_down); 2994 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); 2995 break; 2996 case sdma_event_e10_go_hw_start: 2997 break; 2998 case sdma_event_e15_hw_halt_done: 2999 break; 3000 case sdma_event_e25_hw_clean_up_done: 3001 break; 3002 case sdma_event_e30_go_running: 3003 break; 3004 case sdma_event_e40_sw_cleaned: 3005 break; 3006 case sdma_event_e50_hw_cleaned: 3007 break; 3008 case sdma_event_e60_hw_halted: 3009 need_progress = 1; 3010 sdma_err_progress_check_schedule(sde); 3011 /* fall through */ 3012 case sdma_event_e90_sw_halted: 3013 /* 3014 * SW initiated halt does not perform engines 3015 * progress check 3016 */ 3017 sdma_set_state(sde, sdma_state_s50_hw_halt_wait); 3018 schedule_work(&sde->err_halt_worker); 3019 break; 3020 case sdma_event_e70_go_idle: 3021 sdma_set_state(sde, sdma_state_s60_idle_halt_wait); 3022 break; 3023 case sdma_event_e85_link_down: 3024 ss->go_s99_running = 0; 3025 /* fall through */ 3026 case sdma_event_e80_hw_freeze: 3027 sdma_set_state(sde, sdma_state_s80_hw_freeze); 3028 atomic_dec(&sde->dd->sdma_unfreeze_count); 3029 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); 3030 break; 3031 case sdma_event_e81_hw_frozen: 3032 break; 3033 case sdma_event_e82_hw_unfreeze: 3034 break; 3035 } 3036 break; 3037 } 3038 3039 ss->last_event = event; 3040 if (need_progress) 3041 sdma_make_progress(sde, 0); 3042 } 3043 3044 /* 3045 * _extend_sdma_tx_descs() - helper to extend txreq 3046 * 3047 * This is called once the initial nominal allocation 3048 * of descriptors in the sdma_txreq is exhausted. 3049 * 3050 * The code will bump the allocation up to the max 3051 * of MAX_DESC (64) descriptors. There doesn't seem 3052 * much point in an interim step. The last descriptor 3053 * is reserved for coalesce buffer in order to support 3054 * cases where input packet has >MAX_DESC iovecs. 3055 * 3056 */ 3057 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) 3058 { 3059 int i; 3060 3061 /* Handle last descriptor */ 3062 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) { 3063 /* if tlen is 0, it is for padding, release last descriptor */ 3064 if (!tx->tlen) { 3065 tx->desc_limit = MAX_DESC; 3066 } else if (!tx->coalesce_buf) { 3067 /* allocate coalesce buffer with space for padding */ 3068 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32), 3069 GFP_ATOMIC); 3070 if (!tx->coalesce_buf) 3071 goto enomem; 3072 tx->coalesce_idx = 0; 3073 } 3074 return 0; 3075 } 3076 3077 if (unlikely(tx->num_desc == MAX_DESC)) 3078 goto enomem; 3079 3080 tx->descp = kmalloc_array( 3081 MAX_DESC, 3082 sizeof(struct sdma_desc), 3083 GFP_ATOMIC); 3084 if (!tx->descp) 3085 goto enomem; 3086 3087 /* reserve last descriptor for coalescing */ 3088 tx->desc_limit = MAX_DESC - 1; 3089 /* copy ones already built */ 3090 for (i = 0; i < tx->num_desc; i++) 3091 tx->descp[i] = tx->descs[i]; 3092 return 0; 3093 enomem: 3094 __sdma_txclean(dd, tx); 3095 return -ENOMEM; 3096 } 3097 3098 /* 3099 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors 3100 * 3101 * This is called once the initial nominal allocation of descriptors 3102 * in the sdma_txreq is exhausted. 3103 * 3104 * This function calls _extend_sdma_tx_descs to extend or allocate 3105 * coalesce buffer. If there is a allocated coalesce buffer, it will 3106 * copy the input packet data into the coalesce buffer. It also adds 3107 * coalesce buffer descriptor once when whole packet is received. 3108 * 3109 * Return: 3110 * <0 - error 3111 * 0 - coalescing, don't populate descriptor 3112 * 1 - continue with populating descriptor 3113 */ 3114 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx, 3115 int type, void *kvaddr, struct page *page, 3116 unsigned long offset, u16 len) 3117 { 3118 int pad_len, rval; 3119 dma_addr_t addr; 3120 3121 rval = _extend_sdma_tx_descs(dd, tx); 3122 if (rval) { 3123 __sdma_txclean(dd, tx); 3124 return rval; 3125 } 3126 3127 /* If coalesce buffer is allocated, copy data into it */ 3128 if (tx->coalesce_buf) { 3129 if (type == SDMA_MAP_NONE) { 3130 __sdma_txclean(dd, tx); 3131 return -EINVAL; 3132 } 3133 3134 if (type == SDMA_MAP_PAGE) { 3135 kvaddr = kmap(page); 3136 kvaddr += offset; 3137 } else if (WARN_ON(!kvaddr)) { 3138 __sdma_txclean(dd, tx); 3139 return -EINVAL; 3140 } 3141 3142 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len); 3143 tx->coalesce_idx += len; 3144 if (type == SDMA_MAP_PAGE) 3145 kunmap(page); 3146 3147 /* If there is more data, return */ 3148 if (tx->tlen - tx->coalesce_idx) 3149 return 0; 3150 3151 /* Whole packet is received; add any padding */ 3152 pad_len = tx->packet_len & (sizeof(u32) - 1); 3153 if (pad_len) { 3154 pad_len = sizeof(u32) - pad_len; 3155 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len); 3156 /* padding is taken care of for coalescing case */ 3157 tx->packet_len += pad_len; 3158 tx->tlen += pad_len; 3159 } 3160 3161 /* dma map the coalesce buffer */ 3162 addr = dma_map_single(&dd->pcidev->dev, 3163 tx->coalesce_buf, 3164 tx->tlen, 3165 DMA_TO_DEVICE); 3166 3167 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 3168 __sdma_txclean(dd, tx); 3169 return -ENOSPC; 3170 } 3171 3172 /* Add descriptor for coalesce buffer */ 3173 tx->desc_limit = MAX_DESC; 3174 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx, 3175 addr, tx->tlen); 3176 } 3177 3178 return 1; 3179 } 3180 3181 /* Update sdes when the lmc changes */ 3182 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid) 3183 { 3184 struct sdma_engine *sde; 3185 int i; 3186 u64 sreg; 3187 3188 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) << 3189 SD(CHECK_SLID_MASK_SHIFT)) | 3190 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) << 3191 SD(CHECK_SLID_VALUE_SHIFT)); 3192 3193 for (i = 0; i < dd->num_sdma; i++) { 3194 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x", 3195 i, (u32)sreg); 3196 sde = &dd->per_sdma[i]; 3197 write_sde_csr(sde, SD(CHECK_SLID), sreg); 3198 } 3199 } 3200 3201 /* tx not dword sized - pad */ 3202 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) 3203 { 3204 int rval = 0; 3205 3206 tx->num_desc++; 3207 if ((unlikely(tx->num_desc == tx->desc_limit))) { 3208 rval = _extend_sdma_tx_descs(dd, tx); 3209 if (rval) { 3210 __sdma_txclean(dd, tx); 3211 return rval; 3212 } 3213 } 3214 /* finish the one just added */ 3215 make_tx_sdma_desc( 3216 tx, 3217 SDMA_MAP_NONE, 3218 dd->sdma_pad_phys, 3219 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1))); 3220 _sdma_close_tx(dd, tx); 3221 return rval; 3222 } 3223 3224 /* 3225 * Add ahg to the sdma_txreq 3226 * 3227 * The logic will consume up to 3 3228 * descriptors at the beginning of 3229 * sdma_txreq. 3230 */ 3231 void _sdma_txreq_ahgadd( 3232 struct sdma_txreq *tx, 3233 u8 num_ahg, 3234 u8 ahg_entry, 3235 u32 *ahg, 3236 u8 ahg_hlen) 3237 { 3238 u32 i, shift = 0, desc = 0; 3239 u8 mode; 3240 3241 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4); 3242 /* compute mode */ 3243 if (num_ahg == 1) 3244 mode = SDMA_AHG_APPLY_UPDATE1; 3245 else if (num_ahg <= 5) 3246 mode = SDMA_AHG_APPLY_UPDATE2; 3247 else 3248 mode = SDMA_AHG_APPLY_UPDATE3; 3249 tx->num_desc++; 3250 /* initialize to consumed descriptors to zero */ 3251 switch (mode) { 3252 case SDMA_AHG_APPLY_UPDATE3: 3253 tx->num_desc++; 3254 tx->descs[2].qw[0] = 0; 3255 tx->descs[2].qw[1] = 0; 3256 /* FALLTHROUGH */ 3257 case SDMA_AHG_APPLY_UPDATE2: 3258 tx->num_desc++; 3259 tx->descs[1].qw[0] = 0; 3260 tx->descs[1].qw[1] = 0; 3261 break; 3262 } 3263 ahg_hlen >>= 2; 3264 tx->descs[0].qw[1] |= 3265 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK) 3266 << SDMA_DESC1_HEADER_INDEX_SHIFT) | 3267 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK) 3268 << SDMA_DESC1_HEADER_DWS_SHIFT) | 3269 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK) 3270 << SDMA_DESC1_HEADER_MODE_SHIFT) | 3271 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK) 3272 << SDMA_DESC1_HEADER_UPDATE1_SHIFT); 3273 for (i = 0; i < (num_ahg - 1); i++) { 3274 if (!shift && !(i & 2)) 3275 desc++; 3276 tx->descs[desc].qw[!!(i & 2)] |= 3277 (((u64)ahg[i + 1]) 3278 << shift); 3279 shift = (shift + 32) & 63; 3280 } 3281 } 3282 3283 /** 3284 * sdma_ahg_alloc - allocate an AHG entry 3285 * @sde: engine to allocate from 3286 * 3287 * Return: 3288 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled, 3289 * -ENOSPC if an entry is not available 3290 */ 3291 int sdma_ahg_alloc(struct sdma_engine *sde) 3292 { 3293 int nr; 3294 int oldbit; 3295 3296 if (!sde) { 3297 trace_hfi1_ahg_allocate(sde, -EINVAL); 3298 return -EINVAL; 3299 } 3300 while (1) { 3301 nr = ffz(READ_ONCE(sde->ahg_bits)); 3302 if (nr > 31) { 3303 trace_hfi1_ahg_allocate(sde, -ENOSPC); 3304 return -ENOSPC; 3305 } 3306 oldbit = test_and_set_bit(nr, &sde->ahg_bits); 3307 if (!oldbit) 3308 break; 3309 cpu_relax(); 3310 } 3311 trace_hfi1_ahg_allocate(sde, nr); 3312 return nr; 3313 } 3314 3315 /** 3316 * sdma_ahg_free - free an AHG entry 3317 * @sde: engine to return AHG entry 3318 * @ahg_index: index to free 3319 * 3320 * This routine frees the indicate AHG entry. 3321 */ 3322 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index) 3323 { 3324 if (!sde) 3325 return; 3326 trace_hfi1_ahg_deallocate(sde, ahg_index); 3327 if (ahg_index < 0 || ahg_index > 31) 3328 return; 3329 clear_bit(ahg_index, &sde->ahg_bits); 3330 } 3331 3332 /* 3333 * SPC freeze handling for SDMA engines. Called when the driver knows 3334 * the SPC is going into a freeze but before the freeze is fully 3335 * settled. Generally an error interrupt. 3336 * 3337 * This event will pull the engine out of running so no more entries can be 3338 * added to the engine's queue. 3339 */ 3340 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down) 3341 { 3342 int i; 3343 enum sdma_events event = link_down ? sdma_event_e85_link_down : 3344 sdma_event_e80_hw_freeze; 3345 3346 /* set up the wait but do not wait here */ 3347 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); 3348 3349 /* tell all engines to stop running and wait */ 3350 for (i = 0; i < dd->num_sdma; i++) 3351 sdma_process_event(&dd->per_sdma[i], event); 3352 3353 /* sdma_freeze() will wait for all engines to have stopped */ 3354 } 3355 3356 /* 3357 * SPC freeze handling for SDMA engines. Called when the driver knows 3358 * the SPC is fully frozen. 3359 */ 3360 void sdma_freeze(struct hfi1_devdata *dd) 3361 { 3362 int i; 3363 int ret; 3364 3365 /* 3366 * Make sure all engines have moved out of the running state before 3367 * continuing. 3368 */ 3369 ret = wait_event_interruptible(dd->sdma_unfreeze_wq, 3370 atomic_read(&dd->sdma_unfreeze_count) <= 3371 0); 3372 /* interrupted or count is negative, then unloading - just exit */ 3373 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0) 3374 return; 3375 3376 /* set up the count for the next wait */ 3377 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); 3378 3379 /* tell all engines that the SPC is frozen, they can start cleaning */ 3380 for (i = 0; i < dd->num_sdma; i++) 3381 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen); 3382 3383 /* 3384 * Wait for everyone to finish software clean before exiting. The 3385 * software clean will read engine CSRs, so must be completed before 3386 * the next step, which will clear the engine CSRs. 3387 */ 3388 (void)wait_event_interruptible(dd->sdma_unfreeze_wq, 3389 atomic_read(&dd->sdma_unfreeze_count) <= 0); 3390 /* no need to check results - done no matter what */ 3391 } 3392 3393 /* 3394 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen. 3395 * 3396 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All 3397 * that is left is a software clean. We could do it after the SPC is fully 3398 * frozen, but then we'd have to add another state to wait for the unfreeze. 3399 * Instead, just defer the software clean until the unfreeze step. 3400 */ 3401 void sdma_unfreeze(struct hfi1_devdata *dd) 3402 { 3403 int i; 3404 3405 /* tell all engines start freeze clean up */ 3406 for (i = 0; i < dd->num_sdma; i++) 3407 sdma_process_event(&dd->per_sdma[i], 3408 sdma_event_e82_hw_unfreeze); 3409 } 3410 3411 /** 3412 * _sdma_engine_progress_schedule() - schedule progress on engine 3413 * @sde: sdma_engine to schedule progress 3414 * 3415 */ 3416 void _sdma_engine_progress_schedule( 3417 struct sdma_engine *sde) 3418 { 3419 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask); 3420 /* assume we have selected a good cpu */ 3421 write_csr(sde->dd, 3422 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)), 3423 sde->progress_mask); 3424 } 3425