1 /* 2 * Copyright(c) 2015 - 2019 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/pci.h> 49 #include <linux/io.h> 50 #include <linux/delay.h> 51 #include <linux/vmalloc.h> 52 #include <linux/aer.h> 53 #include <linux/module.h> 54 55 #include "hfi.h" 56 #include "chip_registers.h" 57 #include "aspm.h" 58 59 /* 60 * This file contains PCIe utility routines. 61 */ 62 63 /* 64 * Do all the common PCIe setup and initialization. 65 */ 66 int hfi1_pcie_init(struct hfi1_devdata *dd) 67 { 68 int ret; 69 struct pci_dev *pdev = dd->pcidev; 70 71 ret = pci_enable_device(pdev); 72 if (ret) { 73 /* 74 * This can happen (in theory) iff: 75 * We did a chip reset, and then failed to reprogram the 76 * BAR, or the chip reset due to an internal error. We then 77 * unloaded the driver and reloaded it. 78 * 79 * Both reset cases set the BAR back to initial state. For 80 * the latter case, the AER sticky error bit at offset 0x718 81 * should be set, but the Linux kernel doesn't yet know 82 * about that, it appears. If the original BAR was retained 83 * in the kernel data structures, this may be OK. 84 */ 85 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); 86 return ret; 87 } 88 89 ret = pci_request_regions(pdev, DRIVER_NAME); 90 if (ret) { 91 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); 92 goto bail; 93 } 94 95 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 96 if (ret) { 97 /* 98 * If the 64 bit setup fails, try 32 bit. Some systems 99 * do not setup 64 bit maps on systems with 2GB or less 100 * memory installed. 101 */ 102 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 103 if (ret) { 104 dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret); 105 goto bail; 106 } 107 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 108 } else { 109 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 110 } 111 if (ret) { 112 dd_dev_err(dd, "Unable to set DMA consistent mask: %d\n", ret); 113 goto bail; 114 } 115 116 pci_set_master(pdev); 117 (void)pci_enable_pcie_error_reporting(pdev); 118 return 0; 119 120 bail: 121 hfi1_pcie_cleanup(pdev); 122 return ret; 123 } 124 125 /* 126 * Clean what was done in hfi1_pcie_init() 127 */ 128 void hfi1_pcie_cleanup(struct pci_dev *pdev) 129 { 130 pci_disable_device(pdev); 131 /* 132 * Release regions should be called after the disable. OK to 133 * call if request regions has not been called or failed. 134 */ 135 pci_release_regions(pdev); 136 } 137 138 /* 139 * Do remaining PCIe setup, once dd is allocated, and save away 140 * fields required to re-initialize after a chip reset, or for 141 * various other purposes 142 */ 143 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) 144 { 145 unsigned long len; 146 resource_size_t addr; 147 int ret = 0; 148 u32 rcv_array_count; 149 150 addr = pci_resource_start(pdev, 0); 151 len = pci_resource_len(pdev, 0); 152 153 /* 154 * The TXE PIO buffers are at the tail end of the chip space. 155 * Cut them off and map them separately. 156 */ 157 158 /* sanity check vs expectations */ 159 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { 160 dd_dev_err(dd, "chip PIO range does not match\n"); 161 return -EINVAL; 162 } 163 164 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY); 165 if (!dd->kregbase1) { 166 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); 167 return -ENOMEM; 168 } 169 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); 170 171 /* verify that reads actually work, save revision for reset check */ 172 dd->revision = readq(dd->kregbase1 + CCE_REVISION); 173 if (dd->revision == ~(u64)0) { 174 dd_dev_err(dd, "Cannot read chip CSRs\n"); 175 goto nomem; 176 } 177 178 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); 179 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count); 180 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; 181 182 dd->kregbase2 = ioremap_nocache( 183 addr + dd->base2_start, 184 TXE_PIO_SEND - dd->base2_start); 185 if (!dd->kregbase2) { 186 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); 187 goto nomem; 188 } 189 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, 190 TXE_PIO_SEND - dd->base2_start); 191 192 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); 193 if (!dd->piobase) { 194 dd_dev_err(dd, "WC mapping of send buffers failed\n"); 195 goto nomem; 196 } 197 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); 198 199 dd->physaddr = addr; /* used for io_remap, etc. */ 200 201 /* 202 * Map the chip's RcvArray as write-combining to allow us 203 * to write an entire cacheline worth of entries in one shot. 204 */ 205 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, 206 rcv_array_count * 8); 207 if (!dd->rcvarray_wc) { 208 dd_dev_err(dd, "WC mapping of receive array failed\n"); 209 goto nomem; 210 } 211 dd_dev_info(dd, "WC RcvArray: %p for %x\n", 212 dd->rcvarray_wc, rcv_array_count * 8); 213 214 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ 215 return 0; 216 nomem: 217 ret = -ENOMEM; 218 hfi1_pcie_ddcleanup(dd); 219 return ret; 220 } 221 222 /* 223 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior 224 * to releasing the dd memory. 225 * Void because all of the core pcie cleanup functions are void. 226 */ 227 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) 228 { 229 dd->flags &= ~HFI1_PRESENT; 230 if (dd->kregbase1) 231 iounmap(dd->kregbase1); 232 dd->kregbase1 = NULL; 233 if (dd->kregbase2) 234 iounmap(dd->kregbase2); 235 dd->kregbase2 = NULL; 236 if (dd->rcvarray_wc) 237 iounmap(dd->rcvarray_wc); 238 dd->rcvarray_wc = NULL; 239 if (dd->piobase) 240 iounmap(dd->piobase); 241 dd->piobase = NULL; 242 } 243 244 /* return the PCIe link speed from the given link status */ 245 static u32 extract_speed(u16 linkstat) 246 { 247 u32 speed; 248 249 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 250 default: /* not defined, assume Gen1 */ 251 case PCI_EXP_LNKSTA_CLS_2_5GB: 252 speed = 2500; /* Gen 1, 2.5GHz */ 253 break; 254 case PCI_EXP_LNKSTA_CLS_5_0GB: 255 speed = 5000; /* Gen 2, 5GHz */ 256 break; 257 case PCI_EXP_LNKSTA_CLS_8_0GB: 258 speed = 8000; /* Gen 3, 8GHz */ 259 break; 260 } 261 return speed; 262 } 263 264 /* return the PCIe link speed from the given link status */ 265 static u32 extract_width(u16 linkstat) 266 { 267 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 268 } 269 270 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 271 static void update_lbus_info(struct hfi1_devdata *dd) 272 { 273 u16 linkstat; 274 int ret; 275 276 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 277 if (ret) { 278 dd_dev_err(dd, "Unable to read from PCI config\n"); 279 return; 280 } 281 282 dd->lbus_width = extract_width(linkstat); 283 dd->lbus_speed = extract_speed(linkstat); 284 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 285 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 286 } 287 288 /* 289 * Read in the current PCIe link width and speed. Find if the link is 290 * Gen3 capable. 291 */ 292 int pcie_speeds(struct hfi1_devdata *dd) 293 { 294 u32 linkcap; 295 struct pci_dev *parent = dd->pcidev->bus->self; 296 int ret; 297 298 if (!pci_is_pcie(dd->pcidev)) { 299 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 300 return -EINVAL; 301 } 302 303 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 304 dd->link_gen3_capable = 1; 305 306 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 307 if (ret) { 308 dd_dev_err(dd, "Unable to read from PCI config\n"); 309 return ret; 310 } 311 312 if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GB) { 313 dd_dev_info(dd, 314 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 315 linkcap & PCI_EXP_LNKCAP_SLS); 316 dd->link_gen3_capable = 0; 317 } 318 319 /* 320 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 321 */ 322 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { 323 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 324 dd->link_gen3_capable = 0; 325 } 326 327 /* obtain the link width and current speed */ 328 update_lbus_info(dd); 329 330 dd_dev_info(dd, "%s\n", dd->lbus_info); 331 332 return 0; 333 } 334 335 /* restore command and BARs after a reset has wiped them out */ 336 int restore_pci_variables(struct hfi1_devdata *dd) 337 { 338 int ret = 0; 339 340 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); 341 if (ret) 342 goto error; 343 344 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 345 dd->pcibar0); 346 if (ret) 347 goto error; 348 349 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 350 dd->pcibar1); 351 if (ret) 352 goto error; 353 354 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); 355 if (ret) 356 goto error; 357 358 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, 359 dd->pcie_devctl); 360 if (ret) 361 goto error; 362 363 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, 364 dd->pcie_lnkctl); 365 if (ret) 366 goto error; 367 368 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, 369 dd->pcie_devctl2); 370 if (ret) 371 goto error; 372 373 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); 374 if (ret) 375 goto error; 376 377 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { 378 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, 379 dd->pci_tph2); 380 if (ret) 381 goto error; 382 } 383 return 0; 384 385 error: 386 dd_dev_err(dd, "Unable to write to PCI config\n"); 387 return ret; 388 } 389 390 /* Save BARs and command to rewrite after device reset */ 391 int save_pci_variables(struct hfi1_devdata *dd) 392 { 393 int ret = 0; 394 395 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 396 &dd->pcibar0); 397 if (ret) 398 goto error; 399 400 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 401 &dd->pcibar1); 402 if (ret) 403 goto error; 404 405 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); 406 if (ret) 407 goto error; 408 409 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); 410 if (ret) 411 goto error; 412 413 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, 414 &dd->pcie_devctl); 415 if (ret) 416 goto error; 417 418 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, 419 &dd->pcie_lnkctl); 420 if (ret) 421 goto error; 422 423 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, 424 &dd->pcie_devctl2); 425 if (ret) 426 goto error; 427 428 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); 429 if (ret) 430 goto error; 431 432 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { 433 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, 434 &dd->pci_tph2); 435 if (ret) 436 goto error; 437 } 438 return 0; 439 440 error: 441 dd_dev_err(dd, "Unable to read from PCI config\n"); 442 return ret; 443 } 444 445 /* 446 * BIOS may not set PCIe bus-utilization parameters for best performance. 447 * Check and optionally adjust them to maximize our throughput. 448 */ 449 static int hfi1_pcie_caps; 450 module_param_named(pcie_caps, hfi1_pcie_caps, int, 0444); 451 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 452 453 /** 454 * tune_pcie_caps() - Code to adjust PCIe capabilities. 455 * @dd: Valid device data structure 456 * 457 */ 458 void tune_pcie_caps(struct hfi1_devdata *dd) 459 { 460 struct pci_dev *parent; 461 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 462 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; 463 int ret; 464 465 /* 466 * Turn on extended tags in DevCtl in case the BIOS has turned it off 467 * to improve WFR SDMA bandwidth 468 */ 469 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); 470 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { 471 dd_dev_info(dd, "Enabling PCIe extended tags\n"); 472 ectl |= PCI_EXP_DEVCTL_EXT_TAG; 473 ret = pcie_capability_write_word(dd->pcidev, 474 PCI_EXP_DEVCTL, ectl); 475 if (ret) 476 dd_dev_info(dd, "Unable to write to PCI config\n"); 477 } 478 /* Find out supported and configured values for parent (root) */ 479 parent = dd->pcidev->bus->self; 480 /* 481 * The driver cannot perform the tuning if it does not have 482 * access to the upstream component. 483 */ 484 if (!parent) { 485 dd_dev_info(dd, "Parent not found\n"); 486 return; 487 } 488 if (!pci_is_root_bus(parent->bus)) { 489 dd_dev_info(dd, "Parent not root\n"); 490 return; 491 } 492 if (!pci_is_pcie(parent)) { 493 dd_dev_info(dd, "Parent is not PCI Express capable\n"); 494 return; 495 } 496 if (!pci_is_pcie(dd->pcidev)) { 497 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); 498 return; 499 } 500 rc_mpss = parent->pcie_mpss; 501 rc_mps = ffs(pcie_get_mps(parent)) - 8; 502 /* Find out supported and configured values for endpoint (us) */ 503 ep_mpss = dd->pcidev->pcie_mpss; 504 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 505 506 /* Find max payload supported by root, endpoint */ 507 if (rc_mpss > ep_mpss) 508 rc_mpss = ep_mpss; 509 510 /* If Supported greater than limit in module param, limit it */ 511 if (rc_mpss > (hfi1_pcie_caps & 7)) 512 rc_mpss = hfi1_pcie_caps & 7; 513 /* If less than (allowed, supported), bump root payload */ 514 if (rc_mpss > rc_mps) { 515 rc_mps = rc_mpss; 516 pcie_set_mps(parent, 128 << rc_mps); 517 } 518 /* If less than (allowed, supported), bump endpoint payload */ 519 if (rc_mpss > ep_mps) { 520 ep_mps = rc_mpss; 521 pcie_set_mps(dd->pcidev, 128 << ep_mps); 522 } 523 524 /* 525 * Now the Read Request size. 526 * No field for max supported, but PCIe spec limits it to 4096, 527 * which is code '5' (log2(4096) - 7) 528 */ 529 max_mrrs = 5; 530 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) 531 max_mrrs = (hfi1_pcie_caps >> 4) & 7; 532 533 max_mrrs = 128 << max_mrrs; 534 rc_mrrs = pcie_get_readrq(parent); 535 ep_mrrs = pcie_get_readrq(dd->pcidev); 536 537 if (max_mrrs > rc_mrrs) { 538 rc_mrrs = max_mrrs; 539 pcie_set_readrq(parent, rc_mrrs); 540 } 541 if (max_mrrs > ep_mrrs) { 542 ep_mrrs = max_mrrs; 543 pcie_set_readrq(dd->pcidev, ep_mrrs); 544 } 545 } 546 547 /* End of PCIe capability tuning */ 548 549 /* 550 * From here through hfi1_pci_err_handler definition is invoked via 551 * PCI error infrastructure, registered via pci 552 */ 553 static pci_ers_result_t 554 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 555 { 556 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 557 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 558 559 switch (state) { 560 case pci_channel_io_normal: 561 dd_dev_info(dd, "State Normal, ignoring\n"); 562 break; 563 564 case pci_channel_io_frozen: 565 dd_dev_info(dd, "State Frozen, requesting reset\n"); 566 pci_disable_device(pdev); 567 ret = PCI_ERS_RESULT_NEED_RESET; 568 break; 569 570 case pci_channel_io_perm_failure: 571 if (dd) { 572 dd_dev_info(dd, "State Permanent Failure, disabling\n"); 573 /* no more register accesses! */ 574 dd->flags &= ~HFI1_PRESENT; 575 hfi1_disable_after_error(dd); 576 } 577 /* else early, or other problem */ 578 ret = PCI_ERS_RESULT_DISCONNECT; 579 break; 580 581 default: /* shouldn't happen */ 582 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", 583 state); 584 break; 585 } 586 return ret; 587 } 588 589 static pci_ers_result_t 590 pci_mmio_enabled(struct pci_dev *pdev) 591 { 592 u64 words = 0U; 593 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 594 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 595 596 if (dd && dd->pport) { 597 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); 598 if (words == ~0ULL) 599 ret = PCI_ERS_RESULT_NEED_RESET; 600 dd_dev_info(dd, 601 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n", 602 words, ret); 603 } 604 return ret; 605 } 606 607 static pci_ers_result_t 608 pci_slot_reset(struct pci_dev *pdev) 609 { 610 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 611 612 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); 613 return PCI_ERS_RESULT_CAN_RECOVER; 614 } 615 616 static void 617 pci_resume(struct pci_dev *pdev) 618 { 619 struct hfi1_devdata *dd = pci_get_drvdata(pdev); 620 621 dd_dev_info(dd, "HFI1 resume function called\n"); 622 /* 623 * Running jobs will fail, since it's asynchronous 624 * unlike sysfs-requested reset. Better than 625 * doing nothing. 626 */ 627 hfi1_init(dd, 1); /* same as re-init after reset */ 628 } 629 630 const struct pci_error_handlers hfi1_pci_err_handler = { 631 .error_detected = pci_error_detected, 632 .mmio_enabled = pci_mmio_enabled, 633 .slot_reset = pci_slot_reset, 634 .resume = pci_resume, 635 }; 636 637 /*============================================================================*/ 638 /* PCIe Gen3 support */ 639 640 /* 641 * This code is separated out because it is expected to be removed in the 642 * final shipping product. If not, then it will be revisited and items 643 * will be moved to more standard locations. 644 */ 645 646 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ 647 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ 648 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ 649 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ 650 651 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ 652 #define DL_ERR_NONE 0x0 /* no error */ 653 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ 654 /* or response data */ 655 #define DL_ERR_DISABLED 0x2 /* hfi disabled */ 656 #define DL_ERR_SECURITY 0x3 /* security check failed */ 657 #define DL_ERR_SBUS 0x4 /* SBus status error */ 658 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ 659 660 /* gasket block secondary bus reset delay */ 661 #define SBR_DELAY_US 200000 /* 200ms */ 662 663 static uint pcie_target = 3; 664 module_param(pcie_target, uint, S_IRUGO); 665 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); 666 667 static uint pcie_force; 668 module_param(pcie_force, uint, S_IRUGO); 669 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); 670 671 static uint pcie_retry = 5; 672 module_param(pcie_retry, uint, S_IRUGO); 673 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); 674 675 #define UNSET_PSET 255 676 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ 677 #define DEFAULT_MCP_PSET 6 /* MCP HFI */ 678 static uint pcie_pset = UNSET_PSET; 679 module_param(pcie_pset, uint, S_IRUGO); 680 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); 681 682 static uint pcie_ctle = 3; /* discrete on, integrated on */ 683 module_param(pcie_ctle, uint, S_IRUGO); 684 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); 685 686 /* equalization columns */ 687 #define PREC 0 688 #define ATTN 1 689 #define POST 2 690 691 /* discrete silicon preliminary equalization values */ 692 static const u8 discrete_preliminary_eq[11][3] = { 693 /* prec attn post */ 694 { 0x00, 0x00, 0x12 }, /* p0 */ 695 { 0x00, 0x00, 0x0c }, /* p1 */ 696 { 0x00, 0x00, 0x0f }, /* p2 */ 697 { 0x00, 0x00, 0x09 }, /* p3 */ 698 { 0x00, 0x00, 0x00 }, /* p4 */ 699 { 0x06, 0x00, 0x00 }, /* p5 */ 700 { 0x09, 0x00, 0x00 }, /* p6 */ 701 { 0x06, 0x00, 0x0f }, /* p7 */ 702 { 0x09, 0x00, 0x09 }, /* p8 */ 703 { 0x0c, 0x00, 0x00 }, /* p9 */ 704 { 0x00, 0x00, 0x18 }, /* p10 */ 705 }; 706 707 /* integrated silicon preliminary equalization values */ 708 static const u8 integrated_preliminary_eq[11][3] = { 709 /* prec attn post */ 710 { 0x00, 0x1e, 0x07 }, /* p0 */ 711 { 0x00, 0x1e, 0x05 }, /* p1 */ 712 { 0x00, 0x1e, 0x06 }, /* p2 */ 713 { 0x00, 0x1e, 0x04 }, /* p3 */ 714 { 0x00, 0x1e, 0x00 }, /* p4 */ 715 { 0x03, 0x1e, 0x00 }, /* p5 */ 716 { 0x04, 0x1e, 0x00 }, /* p6 */ 717 { 0x03, 0x1e, 0x06 }, /* p7 */ 718 { 0x03, 0x1e, 0x04 }, /* p8 */ 719 { 0x05, 0x1e, 0x00 }, /* p9 */ 720 { 0x00, 0x1e, 0x0a }, /* p10 */ 721 }; 722 723 static const u8 discrete_ctle_tunings[11][4] = { 724 /* DC LF HF BW */ 725 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ 726 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ 727 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ 728 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ 729 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ 730 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ 731 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ 732 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 733 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ 734 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ 735 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ 736 }; 737 738 static const u8 integrated_ctle_tunings[11][4] = { 739 /* DC LF HF BW */ 740 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ 741 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ 742 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ 743 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ 744 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ 745 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ 746 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ 747 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ 748 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ 749 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ 750 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ 751 }; 752 753 /* helper to format the value to write to hardware */ 754 #define eq_value(pre, curr, post) \ 755 ((((u32)(pre)) << \ 756 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ 757 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ 758 | (((u32)(post)) << \ 759 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) 760 761 /* 762 * Load the given EQ preset table into the PCIe hardware. 763 */ 764 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, 765 u8 div) 766 { 767 struct pci_dev *pdev = dd->pcidev; 768 u32 hit_error = 0; 769 u32 violation; 770 u32 i; 771 u8 c_minus1, c0, c_plus1; 772 int ret; 773 774 for (i = 0; i < 11; i++) { 775 /* set index */ 776 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); 777 /* write the value */ 778 c_minus1 = eq[i][PREC] / div; 779 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); 780 c_plus1 = eq[i][POST] / div; 781 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, 782 eq_value(c_minus1, c0, c_plus1)); 783 /* check if these coefficients violate EQ rules */ 784 ret = pci_read_config_dword(dd->pcidev, 785 PCIE_CFG_REG_PL105, &violation); 786 if (ret) { 787 dd_dev_err(dd, "Unable to read from PCI config\n"); 788 hit_error = 1; 789 break; 790 } 791 792 if (violation 793 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ 794 if (hit_error == 0) { 795 dd_dev_err(dd, 796 "Gen3 EQ Table Coefficient rule violations\n"); 797 dd_dev_err(dd, " prec attn post\n"); 798 } 799 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", 800 i, (u32)eq[i][0], (u32)eq[i][1], 801 (u32)eq[i][2]); 802 dd_dev_err(dd, " %02x %02x %02x\n", 803 (u32)c_minus1, (u32)c0, (u32)c_plus1); 804 hit_error = 1; 805 } 806 } 807 if (hit_error) 808 return -EINVAL; 809 return 0; 810 } 811 812 /* 813 * Steps to be done after the PCIe firmware is downloaded and 814 * before the SBR for the Pcie Gen3. 815 * The SBus resource is already being held. 816 */ 817 static void pcie_post_steps(struct hfi1_devdata *dd) 818 { 819 int i; 820 821 set_sbus_fast_mode(dd); 822 /* 823 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. 824 * This avoids a spurious framing error that can otherwise be 825 * generated by the MAC layer. 826 * 827 * Use individual addresses since no broadcast is set up. 828 */ 829 for (i = 0; i < NUM_PCIE_SERDES; i++) { 830 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], 831 0x03, WRITE_SBUS_RECEIVER, 0x00022132); 832 } 833 834 clear_sbus_fast_mode(dd); 835 } 836 837 /* 838 * Trigger a secondary bus reset (SBR) on ourselves using our parent. 839 * 840 * Based on pci_parent_bus_reset() which is not exported by the 841 * kernel core. 842 */ 843 static int trigger_sbr(struct hfi1_devdata *dd) 844 { 845 struct pci_dev *dev = dd->pcidev; 846 struct pci_dev *pdev; 847 848 /* need a parent */ 849 if (!dev->bus->self) { 850 dd_dev_err(dd, "%s: no parent device\n", __func__); 851 return -ENOTTY; 852 } 853 854 /* should not be anyone else on the bus */ 855 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 856 if (pdev != dev) { 857 dd_dev_err(dd, 858 "%s: another device is on the same bus\n", 859 __func__); 860 return -ENOTTY; 861 } 862 863 /* 864 * This is an end around to do an SBR during probe time. A new API needs 865 * to be implemented to have cleaner interface but this fixes the 866 * current brokenness 867 */ 868 return pci_bridge_secondary_bus_reset(dev->bus->self); 869 } 870 871 /* 872 * Write the given gasket interrupt register. 873 */ 874 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, 875 u16 code, u16 data) 876 { 877 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), 878 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | 879 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); 880 } 881 882 /* 883 * Tell the gasket logic how to react to the reset. 884 */ 885 static void arm_gasket_logic(struct hfi1_devdata *dd) 886 { 887 u64 reg; 888 889 reg = (((u64)1 << dd->hfi1_id) << 890 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | 891 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << 892 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | 893 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | 894 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << 895 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); 896 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); 897 /* read back to push the write */ 898 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); 899 } 900 901 /* 902 * CCE_PCIE_CTRL long name helpers 903 * We redefine these shorter macros to use in the code while leaving 904 * chip_registers.h to be autogenerated from the hardware spec. 905 */ 906 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 907 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 908 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 909 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 910 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 911 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 912 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 913 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 914 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 915 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 916 917 /* 918 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). 919 */ 920 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) 921 { 922 u64 pcie_ctrl; 923 u64 xmt_margin; 924 u64 xmt_margin_oe; 925 u64 lane_delay; 926 u64 lane_bundle; 927 928 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); 929 930 /* 931 * For Discrete, use full-swing. 932 * - PCIe TX defaults to full-swing. 933 * Leave this register as default. 934 * For Integrated, use half-swing 935 * - Copy xmt_margin and xmt_margin_oe 936 * from Gen1/Gen2 to Gen3. 937 */ 938 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ 939 /* extract initial fields */ 940 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) 941 & MARGIN_GEN1_GEN2_MASK; 942 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) 943 & MARGIN_G1_G2_OVERWRITE_MASK; 944 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; 945 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) 946 & LANE_BUNDLE_MASK; 947 948 /* 949 * For A0, EFUSE values are not set. Override with the 950 * correct values. 951 */ 952 if (is_ax(dd)) { 953 /* 954 * xmt_margin and OverwiteEnabel should be the 955 * same for Gen1/Gen2 and Gen3 956 */ 957 xmt_margin = 0x5; 958 xmt_margin_oe = 0x1; 959 lane_delay = 0xF; /* Delay 240ns. */ 960 lane_bundle = 0x0; /* Set to 1 lane. */ 961 } 962 963 /* overwrite existing values */ 964 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) 965 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) 966 | (xmt_margin << MARGIN_SHIFT) 967 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) 968 | (lane_delay << LANE_DELAY_SHIFT) 969 | (lane_bundle << LANE_BUNDLE_SHIFT); 970 971 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); 972 } 973 974 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", 975 fname, pcie_ctrl); 976 } 977 978 /* 979 * Do all the steps needed to transition the PCIe link to Gen3 speed. 980 */ 981 int do_pcie_gen3_transition(struct hfi1_devdata *dd) 982 { 983 struct pci_dev *parent = dd->pcidev->bus->self; 984 u64 fw_ctrl; 985 u64 reg, therm; 986 u32 reg32, fs, lf; 987 u32 status, err; 988 int ret; 989 int do_retry, retry_count = 0; 990 int intnum = 0; 991 uint default_pset; 992 uint pset = pcie_pset; 993 u16 target_vector, target_speed; 994 u16 lnkctl2, vendor; 995 u8 div; 996 const u8 (*eq)[3]; 997 const u8 (*ctle_tunings)[4]; 998 uint static_ctle_mode; 999 int return_error = 0; 1000 u32 target_width; 1001 1002 /* PCIe Gen3 is for the ASIC only */ 1003 if (dd->icode != ICODE_RTL_SILICON) 1004 return 0; 1005 1006 if (pcie_target == 1) { /* target Gen1 */ 1007 target_vector = PCI_EXP_LNKCTL2_TLS_2_5GT; 1008 target_speed = 2500; 1009 } else if (pcie_target == 2) { /* target Gen2 */ 1010 target_vector = PCI_EXP_LNKCTL2_TLS_5_0GT; 1011 target_speed = 5000; 1012 } else if (pcie_target == 3) { /* target Gen3 */ 1013 target_vector = PCI_EXP_LNKCTL2_TLS_8_0GT; 1014 target_speed = 8000; 1015 } else { 1016 /* off or invalid target - skip */ 1017 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); 1018 return 0; 1019 } 1020 1021 /* if already at target speed, done (unless forced) */ 1022 if (dd->lbus_speed == target_speed) { 1023 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, 1024 pcie_target, 1025 pcie_force ? "re-doing anyway" : "skipping"); 1026 if (!pcie_force) 1027 return 0; 1028 } 1029 1030 /* 1031 * The driver cannot do the transition if it has no access to the 1032 * upstream component 1033 */ 1034 if (!parent) { 1035 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", 1036 __func__); 1037 return 0; 1038 } 1039 1040 /* Previous Gen1/Gen2 bus width */ 1041 target_width = dd->lbus_width; 1042 1043 /* 1044 * Do the Gen3 transition. Steps are those of the PCIe Gen3 1045 * recipe. 1046 */ 1047 1048 /* step 1: pcie link working in gen1/gen2 */ 1049 1050 /* step 2: if either side is not capable of Gen3, done */ 1051 if (pcie_target == 3 && !dd->link_gen3_capable) { 1052 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); 1053 ret = -ENOSYS; 1054 goto done_no_mutex; 1055 } 1056 1057 /* hold the SBus resource across the firmware download and SBR */ 1058 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1059 if (ret) { 1060 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", 1061 __func__); 1062 return ret; 1063 } 1064 1065 /* make sure thermal polling is not causing interrupts */ 1066 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); 1067 if (therm) { 1068 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); 1069 msleep(100); 1070 dd_dev_info(dd, "%s: Disabled therm polling\n", 1071 __func__); 1072 } 1073 1074 retry: 1075 /* the SBus download will reset the spico for thermal */ 1076 1077 /* step 3: download SBus Master firmware */ 1078 /* step 4: download PCIe Gen3 SerDes firmware */ 1079 dd_dev_info(dd, "%s: downloading firmware\n", __func__); 1080 ret = load_pcie_firmware(dd); 1081 if (ret) { 1082 /* do not proceed if the firmware cannot be downloaded */ 1083 return_error = 1; 1084 goto done; 1085 } 1086 1087 /* step 5: set up device parameter settings */ 1088 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); 1089 1090 /* 1091 * PcieCfgSpcie1 - Link Control 3 1092 * Leave at reset value. No need to set PerfEq - link equalization 1093 * will be performed automatically after the SBR when the target 1094 * speed is 8GT/s. 1095 */ 1096 1097 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ 1098 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); 1099 1100 /* step 5a: Set Synopsys Port Logic registers */ 1101 1102 /* 1103 * PcieCfgRegPl2 - Port Force Link 1104 * 1105 * Set the low power field to 0x10 to avoid unnecessary power 1106 * management messages. All other fields are zero. 1107 */ 1108 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; 1109 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); 1110 1111 /* 1112 * PcieCfgRegPl100 - Gen3 Control 1113 * 1114 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl 1115 * turn on PcieCfgRegPl100.EqEieosCnt 1116 * Everything else zero. 1117 */ 1118 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; 1119 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); 1120 1121 /* 1122 * PcieCfgRegPl101 - Gen3 EQ FS and LF 1123 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping 1124 * PcieCfgRegPl103 - Gen3 EQ Preset Index 1125 * PcieCfgRegPl105 - Gen3 EQ Status 1126 * 1127 * Give initial EQ settings. 1128 */ 1129 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ 1130 /* 1000mV, FS=24, LF = 8 */ 1131 fs = 24; 1132 lf = 8; 1133 div = 3; 1134 eq = discrete_preliminary_eq; 1135 default_pset = DEFAULT_DISCRETE_PSET; 1136 ctle_tunings = discrete_ctle_tunings; 1137 /* bit 0 - discrete on/off */ 1138 static_ctle_mode = pcie_ctle & 0x1; 1139 } else { 1140 /* 400mV, FS=29, LF = 9 */ 1141 fs = 29; 1142 lf = 9; 1143 div = 1; 1144 eq = integrated_preliminary_eq; 1145 default_pset = DEFAULT_MCP_PSET; 1146 ctle_tunings = integrated_ctle_tunings; 1147 /* bit 1 - integrated on/off */ 1148 static_ctle_mode = (pcie_ctle >> 1) & 0x1; 1149 } 1150 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, 1151 (fs << 1152 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | 1153 (lf << 1154 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); 1155 ret = load_eq_table(dd, eq, fs, div); 1156 if (ret) 1157 goto done; 1158 1159 /* 1160 * PcieCfgRegPl106 - Gen3 EQ Control 1161 * 1162 * Set Gen3EqPsetReqVec, leave other fields 0. 1163 */ 1164 if (pset == UNSET_PSET) 1165 pset = default_pset; 1166 if (pset > 10) { /* valid range is 0-10, inclusive */ 1167 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", 1168 __func__, pset, default_pset); 1169 pset = default_pset; 1170 } 1171 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); 1172 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, 1173 ((1 << pset) << 1174 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | 1175 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | 1176 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); 1177 1178 /* 1179 * step 5b: Do post firmware download steps via SBus 1180 */ 1181 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); 1182 pcie_post_steps(dd); 1183 1184 /* 1185 * step 5c: Program gasket interrupts 1186 */ 1187 /* set the Rx Bit Rate to REFCLK ratio */ 1188 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); 1189 /* disable pCal for PCIe Gen3 RX equalization */ 1190 /* select adaptive or static CTLE */ 1191 write_gasket_interrupt(dd, intnum++, 0x0026, 1192 0x5b01 | (static_ctle_mode << 3)); 1193 /* 1194 * Enable iCal for PCIe Gen3 RX equalization, and set which 1195 * evaluation of RX_EQ_EVAL will launch the iCal procedure. 1196 */ 1197 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); 1198 1199 if (static_ctle_mode) { 1200 /* apply static CTLE tunings */ 1201 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; 1202 1203 pcie_dc = ctle_tunings[pset][0]; 1204 pcie_lf = ctle_tunings[pset][1]; 1205 pcie_hf = ctle_tunings[pset][2]; 1206 pcie_bw = ctle_tunings[pset][3]; 1207 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); 1208 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); 1209 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); 1210 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); 1211 } 1212 1213 /* terminate list */ 1214 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); 1215 1216 /* 1217 * step 5d: program XMT margin 1218 */ 1219 write_xmt_margin(dd, __func__); 1220 1221 /* 1222 * step 5e: disable active state power management (ASPM). It 1223 * will be enabled if required later 1224 */ 1225 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); 1226 aspm_hw_disable_l1(dd); 1227 1228 /* 1229 * step 5f: clear DirectSpeedChange 1230 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the 1231 * change in the speed target from starting before we are ready. 1232 * This field defaults to 0 and we are not changing it, so nothing 1233 * needs to be done. 1234 */ 1235 1236 /* step 5g: Set target link speed */ 1237 /* 1238 * Set target link speed to be target on both device and parent. 1239 * On setting the parent: Some system BIOSs "helpfully" set the 1240 * parent target speed to Gen2 to match the ASIC's initial speed. 1241 * We can set the target Gen3 because we have already checked 1242 * that it is Gen3 capable earlier. 1243 */ 1244 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); 1245 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); 1246 if (ret) { 1247 dd_dev_err(dd, "Unable to read from PCI config\n"); 1248 return_error = 1; 1249 goto done; 1250 } 1251 1252 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1253 (u32)lnkctl2); 1254 /* only write to parent if target is not as high as ours */ 1255 if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) { 1256 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 1257 lnkctl2 |= target_vector; 1258 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1259 (u32)lnkctl2); 1260 ret = pcie_capability_write_word(parent, 1261 PCI_EXP_LNKCTL2, lnkctl2); 1262 if (ret) { 1263 dd_dev_err(dd, "Unable to write to PCI config\n"); 1264 return_error = 1; 1265 goto done; 1266 } 1267 } else { 1268 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); 1269 } 1270 1271 dd_dev_info(dd, "%s: setting target link speed\n", __func__); 1272 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); 1273 if (ret) { 1274 dd_dev_err(dd, "Unable to read from PCI config\n"); 1275 return_error = 1; 1276 goto done; 1277 } 1278 1279 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, 1280 (u32)lnkctl2); 1281 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; 1282 lnkctl2 |= target_vector; 1283 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, 1284 (u32)lnkctl2); 1285 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); 1286 if (ret) { 1287 dd_dev_err(dd, "Unable to write to PCI config\n"); 1288 return_error = 1; 1289 goto done; 1290 } 1291 1292 /* step 5h: arm gasket logic */ 1293 /* hold DC in reset across the SBR */ 1294 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); 1295 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ 1296 /* save firmware control across the SBR */ 1297 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); 1298 1299 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); 1300 arm_gasket_logic(dd); 1301 1302 /* 1303 * step 6: quiesce PCIe link 1304 * The chip has already been reset, so there will be no traffic 1305 * from the chip. Linux has no easy way to enforce that it will 1306 * not try to access the device, so we just need to hope it doesn't 1307 * do it while we are doing the reset. 1308 */ 1309 1310 /* 1311 * step 7: initiate the secondary bus reset (SBR) 1312 * step 8: hardware brings the links back up 1313 * step 9: wait for link speed transition to be complete 1314 */ 1315 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); 1316 ret = trigger_sbr(dd); 1317 if (ret) 1318 goto done; 1319 1320 /* step 10: decide what to do next */ 1321 1322 /* check if we can read PCI space */ 1323 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); 1324 if (ret) { 1325 dd_dev_info(dd, 1326 "%s: read of VendorID failed after SBR, err %d\n", 1327 __func__, ret); 1328 return_error = 1; 1329 goto done; 1330 } 1331 if (vendor == 0xffff) { 1332 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); 1333 return_error = 1; 1334 ret = -EIO; 1335 goto done; 1336 } 1337 1338 /* restore PCI space registers we know were reset */ 1339 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); 1340 ret = restore_pci_variables(dd); 1341 if (ret) { 1342 dd_dev_err(dd, "%s: Could not restore PCI variables\n", 1343 __func__); 1344 return_error = 1; 1345 goto done; 1346 } 1347 1348 /* restore firmware control */ 1349 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); 1350 1351 /* 1352 * Check the gasket block status. 1353 * 1354 * This is the first CSR read after the SBR. If the read returns 1355 * all 1s (fails), the link did not make it back. 1356 * 1357 * Once we're sure we can read and write, clear the DC reset after 1358 * the SBR. Then check for any per-lane errors. Then look over 1359 * the status. 1360 */ 1361 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); 1362 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); 1363 if (reg == ~0ull) { /* PCIe read failed/timeout */ 1364 dd_dev_err(dd, "SBR failed - unable to read from device\n"); 1365 return_error = 1; 1366 ret = -ENOSYS; 1367 goto done; 1368 } 1369 1370 /* clear the DC reset */ 1371 write_csr(dd, CCE_DC_CTRL, 0); 1372 1373 /* Set the LED off */ 1374 setextled(dd, 0); 1375 1376 /* check for any per-lane errors */ 1377 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); 1378 if (ret) { 1379 dd_dev_err(dd, "Unable to read from PCI config\n"); 1380 return_error = 1; 1381 goto done; 1382 } 1383 1384 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); 1385 1386 /* extract status, look for our HFI */ 1387 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) 1388 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; 1389 if ((status & (1 << dd->hfi1_id)) == 0) { 1390 dd_dev_err(dd, 1391 "%s: gasket status 0x%x, expecting 0x%x\n", 1392 __func__, status, 1 << dd->hfi1_id); 1393 ret = -EIO; 1394 goto done; 1395 } 1396 1397 /* extract error */ 1398 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) 1399 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; 1400 if (err) { 1401 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); 1402 ret = -EIO; 1403 goto done; 1404 } 1405 1406 /* update our link information cache */ 1407 update_lbus_info(dd); 1408 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, 1409 dd->lbus_info); 1410 1411 if (dd->lbus_speed != target_speed || 1412 dd->lbus_width < target_width) { /* not target */ 1413 /* maybe retry */ 1414 do_retry = retry_count < pcie_retry; 1415 dd_dev_err(dd, "PCIe link speed or width did not match target%s\n", 1416 do_retry ? ", retrying" : ""); 1417 retry_count++; 1418 if (do_retry) { 1419 msleep(100); /* allow time to settle */ 1420 goto retry; 1421 } 1422 ret = -EIO; 1423 } 1424 1425 done: 1426 if (therm) { 1427 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); 1428 msleep(100); 1429 dd_dev_info(dd, "%s: Re-enable therm polling\n", 1430 __func__); 1431 } 1432 release_chip_resource(dd, CR_SBUS); 1433 done_no_mutex: 1434 /* return no error if it is OK to be at current speed */ 1435 if (ret && !return_error) { 1436 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); 1437 ret = 0; 1438 } 1439 1440 dd_dev_info(dd, "%s: done\n", __func__); 1441 return ret; 1442 } 1443