xref: /linux/drivers/infiniband/hw/hfi1/hfi.h (revision bfd5bb6f90af092aa345b15cd78143956a13c2a8)
1 #ifndef _HFI1_KERNEL_H
2 #define _HFI1_KERNEL_H
3 /*
4  * Copyright(c) 2015-2018 Intel Corporation.
5  *
6  * This file is provided under a dual BSD/GPLv2 license.  When using or
7  * redistributing this file, you may do so under either license.
8  *
9  * GPL LICENSE SUMMARY
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of version 2 of the GNU General Public License as
13  * published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope that it will be useful, but
16  * WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * General Public License for more details.
19  *
20  * BSD LICENSE
21  *
22  * Redistribution and use in source and binary forms, with or without
23  * modification, are permitted provided that the following conditions
24  * are met:
25  *
26  *  - Redistributions of source code must retain the above copyright
27  *    notice, this list of conditions and the following disclaimer.
28  *  - Redistributions in binary form must reproduce the above copyright
29  *    notice, this list of conditions and the following disclaimer in
30  *    the documentation and/or other materials provided with the
31  *    distribution.
32  *  - Neither the name of Intel Corporation nor the names of its
33  *    contributors may be used to endorse or promote products derived
34  *    from this software without specific prior written permission.
35  *
36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47  *
48  */
49 
50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/idr.h>
58 #include <linux/io.h>
59 #include <linux/fs.h>
60 #include <linux/completion.h>
61 #include <linux/kref.h>
62 #include <linux/sched.h>
63 #include <linux/cdev.h>
64 #include <linux/delay.h>
65 #include <linux/kthread.h>
66 #include <linux/i2c.h>
67 #include <linux/i2c-algo-bit.h>
68 #include <rdma/ib_hdrs.h>
69 #include <rdma/opa_addr.h>
70 #include <linux/rhashtable.h>
71 #include <linux/netdevice.h>
72 #include <rdma/rdma_vt.h>
73 
74 #include "chip_registers.h"
75 #include "common.h"
76 #include "verbs.h"
77 #include "pio.h"
78 #include "chip.h"
79 #include "mad.h"
80 #include "qsfp.h"
81 #include "platform.h"
82 #include "affinity.h"
83 
84 /* bumped 1 from s/w major version of TrueScale */
85 #define HFI1_CHIP_VERS_MAJ 3U
86 
87 /* don't care about this except printing */
88 #define HFI1_CHIP_VERS_MIN 0U
89 
90 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
91 #define HFI1_OUI 0x001175
92 #define HFI1_OUI_LSB 40
93 
94 #define DROP_PACKET_OFF		0
95 #define DROP_PACKET_ON		1
96 
97 #define NEIGHBOR_TYPE_HFI		0
98 #define NEIGHBOR_TYPE_SWITCH	1
99 
100 extern unsigned long hfi1_cap_mask;
101 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
102 #define HFI1_CAP_UGET_MASK(mask, cap) \
103 	(((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
104 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
105 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
106 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
107 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
108 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
109 			HFI1_CAP_MISC_MASK)
110 /* Offline Disabled Reason is 4-bits */
111 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
112 
113 /*
114  * Control context is always 0 and handles the error packets.
115  * It also handles the VL15 and multicast packets.
116  */
117 #define HFI1_CTRL_CTXT    0
118 
119 /*
120  * Driver context will store software counters for each of the events
121  * associated with these status registers
122  */
123 #define NUM_CCE_ERR_STATUS_COUNTERS 41
124 #define NUM_RCV_ERR_STATUS_COUNTERS 64
125 #define NUM_MISC_ERR_STATUS_COUNTERS 13
126 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
127 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
128 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
129 #define NUM_SEND_ERR_STATUS_COUNTERS 3
130 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
131 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
132 
133 /*
134  * per driver stats, either not device nor port-specific, or
135  * summed over all of the devices and ports.
136  * They are described by name via ipathfs filesystem, so layout
137  * and number of elements can change without breaking compatibility.
138  * If members are added or deleted hfi1_statnames[] in debugfs.c must
139  * change to match.
140  */
141 struct hfi1_ib_stats {
142 	__u64 sps_ints; /* number of interrupts handled */
143 	__u64 sps_errints; /* number of error interrupts */
144 	__u64 sps_txerrs; /* tx-related packet errors */
145 	__u64 sps_rcverrs; /* non-crc rcv packet errors */
146 	__u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
147 	__u64 sps_nopiobufs; /* no pio bufs avail from kernel */
148 	__u64 sps_ctxts; /* number of contexts currently open */
149 	__u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
150 	__u64 sps_buffull;
151 	__u64 sps_hdrfull;
152 };
153 
154 extern struct hfi1_ib_stats hfi1_stats;
155 extern const struct pci_error_handlers hfi1_pci_err_handler;
156 
157 /*
158  * First-cut criterion for "device is active" is
159  * two thousand dwords combined Tx, Rx traffic per
160  * 5-second interval. SMA packets are 64 dwords,
161  * and occur "a few per second", presumably each way.
162  */
163 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
164 
165 /*
166  * Below contains all data related to a single context (formerly called port).
167  */
168 
169 struct hfi1_opcode_stats_perctx;
170 
171 struct ctxt_eager_bufs {
172 	ssize_t size;            /* total size of eager buffers */
173 	u32 count;               /* size of buffers array */
174 	u32 numbufs;             /* number of buffers allocated */
175 	u32 alloced;             /* number of rcvarray entries used */
176 	u32 rcvtid_size;         /* size of each eager rcv tid */
177 	u32 threshold;           /* head update threshold */
178 	struct eager_buffer {
179 		void *addr;
180 		dma_addr_t dma;
181 		ssize_t len;
182 	} *buffers;
183 	struct {
184 		void *addr;
185 		dma_addr_t dma;
186 	} *rcvtids;
187 };
188 
189 struct exp_tid_set {
190 	struct list_head list;
191 	u32 count;
192 };
193 
194 struct hfi1_ctxtdata {
195 	/* shadow the ctxt's RcvCtrl register */
196 	u64 rcvctrl;
197 	/* rcvhdrq base, needs mmap before useful */
198 	void *rcvhdrq;
199 	/* kernel virtual address where hdrqtail is updated */
200 	volatile __le64 *rcvhdrtail_kvaddr;
201 	/* when waiting for rcv or pioavail */
202 	wait_queue_head_t wait;
203 	/* rcvhdrq size (for freeing) */
204 	size_t rcvhdrq_size;
205 	/* number of rcvhdrq entries */
206 	u16 rcvhdrq_cnt;
207 	/* size of each of the rcvhdrq entries */
208 	u16 rcvhdrqentsize;
209 	/* mmap of hdrq, must fit in 44 bits */
210 	dma_addr_t rcvhdrq_dma;
211 	dma_addr_t rcvhdrqtailaddr_dma;
212 	struct ctxt_eager_bufs egrbufs;
213 	/* this receive context's assigned PIO ACK send context */
214 	struct send_context *sc;
215 
216 	/* dynamic receive available interrupt timeout */
217 	u32 rcvavail_timeout;
218 	/* Reference count the base context usage */
219 	struct kref kref;
220 
221 	/* Device context index */
222 	u16 ctxt;
223 	/*
224 	 * non-zero if ctxt can be shared, and defines the maximum number of
225 	 * sub-contexts for this device context.
226 	 */
227 	u16 subctxt_cnt;
228 	/* non-zero if ctxt is being shared. */
229 	u16 subctxt_id;
230 	u8 uuid[16];
231 	/* job key */
232 	u16 jkey;
233 	/* number of RcvArray groups for this context. */
234 	u16 rcv_array_groups;
235 	/* index of first eager TID entry. */
236 	u16 eager_base;
237 	/* number of expected TID entries */
238 	u16 expected_count;
239 	/* index of first expected TID entry. */
240 	u16 expected_base;
241 	/* array of tid_groups */
242 	struct tid_group  *groups;
243 
244 	struct exp_tid_set tid_group_list;
245 	struct exp_tid_set tid_used_list;
246 	struct exp_tid_set tid_full_list;
247 
248 	/* lock protecting all Expected TID data of user contexts */
249 	struct mutex exp_mutex;
250 	/* per-context configuration flags */
251 	unsigned long flags;
252 	/* per-context event flags for fileops/intr communication */
253 	unsigned long event_flags;
254 	/* total number of polled urgent packets */
255 	u32 urgent;
256 	/* saved total number of polled urgent packets for poll edge trigger */
257 	u32 urgent_poll;
258 	/* same size as task_struct .comm[], command that opened context */
259 	char comm[TASK_COMM_LEN];
260 	/* so file ops can get at unit */
261 	struct hfi1_devdata *dd;
262 	/* so functions that need physical port can get it easily */
263 	struct hfi1_pportdata *ppd;
264 	/* associated msix interrupt */
265 	u32 msix_intr;
266 	/* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
267 	void *subctxt_uregbase;
268 	/* An array of pages for the eager receive buffers * N */
269 	void *subctxt_rcvegrbuf;
270 	/* An array of pages for the eager header queue entries * N */
271 	void *subctxt_rcvhdr_base;
272 	/* Bitmask of in use context(s) */
273 	DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
274 	/* The version of the library which opened this ctxt */
275 	u32 userversion;
276 	/* Type of packets or conditions we want to poll for */
277 	u16 poll_type;
278 	/* receive packet sequence counter */
279 	u8 seq_cnt;
280 	/* ctxt rcvhdrq head offset */
281 	u32 head;
282 	/* QPs waiting for context processing */
283 	struct list_head qp_wait_list;
284 	/* interrupt handling */
285 	u64 imask;	/* clear interrupt mask */
286 	int ireg;	/* clear interrupt register */
287 	int numa_id; /* numa node of this context */
288 	/* verbs rx_stats per rcd */
289 	struct hfi1_opcode_stats_perctx *opstats;
290 
291 	/* Is ASPM interrupt supported for this context */
292 	bool aspm_intr_supported;
293 	/* ASPM state (enabled/disabled) for this context */
294 	bool aspm_enabled;
295 	/* Timer for re-enabling ASPM if interrupt activity quietens down */
296 	struct timer_list aspm_timer;
297 	/* Lock to serialize between intr, timer intr and user threads */
298 	spinlock_t aspm_lock;
299 	/* Is ASPM processing enabled for this context (in intr context) */
300 	bool aspm_intr_enable;
301 	/* Last interrupt timestamp */
302 	ktime_t aspm_ts_last_intr;
303 	/* Last timestamp at which we scheduled a timer for this context */
304 	ktime_t aspm_ts_timer_sched;
305 
306 	/*
307 	 * The interrupt handler for a particular receive context can vary
308 	 * throughout it's lifetime. This is not a lock protected data member so
309 	 * it must be updated atomically and the prev and new value must always
310 	 * be valid. Worst case is we process an extra interrupt and up to 64
311 	 * packets with the wrong interrupt handler.
312 	 */
313 	int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
314 
315 	/* Indicates that this is vnic context */
316 	bool is_vnic;
317 
318 	/* vnic queue index this context is mapped to */
319 	u8 vnic_q_idx;
320 };
321 
322 /*
323  * Represents a single packet at a high level. Put commonly computed things in
324  * here so we do not have to keep doing them over and over. The rule of thumb is
325  * if something is used one time to derive some value, store that something in
326  * here. If it is used multiple times, then store the result of that derivation
327  * in here.
328  */
329 struct hfi1_packet {
330 	void *ebuf;
331 	void *hdr;
332 	void *payload;
333 	struct hfi1_ctxtdata *rcd;
334 	__le32 *rhf_addr;
335 	struct rvt_qp *qp;
336 	struct ib_other_headers *ohdr;
337 	struct ib_grh *grh;
338 	struct opa_16b_mgmt *mgmt;
339 	u64 rhf;
340 	u32 maxcnt;
341 	u32 rhqoff;
342 	u32 dlid;
343 	u32 slid;
344 	u16 tlen;
345 	s16 etail;
346 	u16 pkey;
347 	u8 hlen;
348 	u8 numpkt;
349 	u8 rsize;
350 	u8 updegr;
351 	u8 etype;
352 	u8 extra_byte;
353 	u8 pad;
354 	u8 sc;
355 	u8 sl;
356 	u8 opcode;
357 	bool migrated;
358 };
359 
360 /* Packet types */
361 #define HFI1_PKT_TYPE_9B  0
362 #define HFI1_PKT_TYPE_16B 1
363 
364 /*
365  * OPA 16B Header
366  */
367 #define OPA_16B_L4_MASK		0xFFull
368 #define OPA_16B_SC_MASK		0x1F00000ull
369 #define OPA_16B_SC_SHIFT	20
370 #define OPA_16B_LID_MASK	0xFFFFFull
371 #define OPA_16B_DLID_MASK	0xF000ull
372 #define OPA_16B_DLID_SHIFT	20
373 #define OPA_16B_DLID_HIGH_SHIFT	12
374 #define OPA_16B_SLID_MASK	0xF00ull
375 #define OPA_16B_SLID_SHIFT	20
376 #define OPA_16B_SLID_HIGH_SHIFT	8
377 #define OPA_16B_BECN_MASK       0x80000000ull
378 #define OPA_16B_BECN_SHIFT      31
379 #define OPA_16B_FECN_MASK       0x10000000ull
380 #define OPA_16B_FECN_SHIFT      28
381 #define OPA_16B_L2_MASK		0x60000000ull
382 #define OPA_16B_L2_SHIFT	29
383 #define OPA_16B_PKEY_MASK	0xFFFF0000ull
384 #define OPA_16B_PKEY_SHIFT	16
385 #define OPA_16B_LEN_MASK	0x7FF00000ull
386 #define OPA_16B_LEN_SHIFT	20
387 #define OPA_16B_RC_MASK		0xE000000ull
388 #define OPA_16B_RC_SHIFT	25
389 #define OPA_16B_AGE_MASK	0xFF0000ull
390 #define OPA_16B_AGE_SHIFT	16
391 #define OPA_16B_ENTROPY_MASK	0xFFFFull
392 
393 /*
394  * OPA 16B L2/L4 Encodings
395  */
396 #define OPA_16B_L4_9B		0x00
397 #define OPA_16B_L2_TYPE		0x02
398 #define OPA_16B_L4_FM		0x08
399 #define OPA_16B_L4_IB_LOCAL	0x09
400 #define OPA_16B_L4_IB_GLOBAL	0x0A
401 #define OPA_16B_L4_ETHR		OPA_VNIC_L4_ETHR
402 
403 /*
404  * OPA 16B Management
405  */
406 #define OPA_16B_L4_FM_PAD	3  /* fixed 3B pad */
407 #define OPA_16B_L4_FM_HLEN	24 /* 16B(16) + L4_FM(8) */
408 
409 static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
410 {
411 	return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
412 }
413 
414 static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
415 {
416 	return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
417 }
418 
419 static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
420 {
421 	return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
422 		     (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
423 		     OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
424 }
425 
426 static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
427 {
428 	return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
429 		     (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
430 		     OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
431 }
432 
433 static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
434 {
435 	return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
436 }
437 
438 static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
439 {
440 	return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
441 }
442 
443 static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
444 {
445 	return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
446 }
447 
448 static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
449 {
450 	return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
451 }
452 
453 static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
454 {
455 	return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
456 }
457 
458 static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
459 {
460 	return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
461 }
462 
463 static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
464 {
465 	return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
466 }
467 
468 static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
469 {
470 	return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
471 }
472 
473 #define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
474 
475 /*
476  * BTH
477  */
478 #define OPA_16B_BTH_PAD_MASK	7
479 static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
480 {
481 	return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
482 		   OPA_16B_BTH_PAD_MASK);
483 }
484 
485 /*
486  * 16B Management
487  */
488 #define OPA_16B_MGMT_QPN_MASK	0xFFFFFF
489 static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt)
490 {
491 	return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK;
492 }
493 
494 static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt)
495 {
496 	return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK;
497 }
498 
499 static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt,
500 				    u32 dest_qp, u32 src_qp)
501 {
502 	mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK);
503 	mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK);
504 }
505 
506 struct rvt_sge_state;
507 
508 /*
509  * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
510  * Mostly for MADs that set or query link parameters, also ipath
511  * config interfaces
512  */
513 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
514 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
515 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
516 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
517 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
518 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
519 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
520 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
521 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
522 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
523 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
524 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
525 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
526 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
527 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
528 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
529 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
530 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
531 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
532 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
533 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
534 
535 /*
536  * HFI or Host Link States
537  *
538  * These describe the states the driver thinks the logical and physical
539  * states are in.  Used as an argument to set_link_state().  Implemented
540  * as bits for easy multi-state checking.  The actual state can only be
541  * one.
542  */
543 #define __HLS_UP_INIT_BP	0
544 #define __HLS_UP_ARMED_BP	1
545 #define __HLS_UP_ACTIVE_BP	2
546 #define __HLS_DN_DOWNDEF_BP	3	/* link down default */
547 #define __HLS_DN_POLL_BP	4
548 #define __HLS_DN_DISABLE_BP	5
549 #define __HLS_DN_OFFLINE_BP	6
550 #define __HLS_VERIFY_CAP_BP	7
551 #define __HLS_GOING_UP_BP	8
552 #define __HLS_GOING_OFFLINE_BP  9
553 #define __HLS_LINK_COOLDOWN_BP 10
554 
555 #define HLS_UP_INIT	  BIT(__HLS_UP_INIT_BP)
556 #define HLS_UP_ARMED	  BIT(__HLS_UP_ARMED_BP)
557 #define HLS_UP_ACTIVE	  BIT(__HLS_UP_ACTIVE_BP)
558 #define HLS_DN_DOWNDEF	  BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
559 #define HLS_DN_POLL	  BIT(__HLS_DN_POLL_BP)
560 #define HLS_DN_DISABLE	  BIT(__HLS_DN_DISABLE_BP)
561 #define HLS_DN_OFFLINE	  BIT(__HLS_DN_OFFLINE_BP)
562 #define HLS_VERIFY_CAP	  BIT(__HLS_VERIFY_CAP_BP)
563 #define HLS_GOING_UP	  BIT(__HLS_GOING_UP_BP)
564 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
565 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
566 
567 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
568 #define HLS_DOWN ~(HLS_UP)
569 
570 #define HLS_DEFAULT HLS_DN_POLL
571 
572 /* use this MTU size if none other is given */
573 #define HFI1_DEFAULT_ACTIVE_MTU 10240
574 /* use this MTU size as the default maximum */
575 #define HFI1_DEFAULT_MAX_MTU 10240
576 /* default partition key */
577 #define DEFAULT_PKEY 0xffff
578 
579 /*
580  * Possible fabric manager config parameters for fm_{get,set}_table()
581  */
582 #define FM_TBL_VL_HIGH_ARB		1 /* Get/set VL high prio weights */
583 #define FM_TBL_VL_LOW_ARB		2 /* Get/set VL low prio weights */
584 #define FM_TBL_BUFFER_CONTROL		3 /* Get/set Buffer Control */
585 #define FM_TBL_SC2VLNT			4 /* Get/set SC->VLnt */
586 #define FM_TBL_VL_PREEMPT_ELEMS		5 /* Get (no set) VL preempt elems */
587 #define FM_TBL_VL_PREEMPT_MATRIX	6 /* Get (no set) VL preempt matrix */
588 
589 /*
590  * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
591  * these are bits so they can be combined, e.g.
592  * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
593  */
594 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
595 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
596 #define HFI1_RCVCTRL_CTXT_ENB 0x04
597 #define HFI1_RCVCTRL_CTXT_DIS 0x08
598 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
599 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
600 #define HFI1_RCVCTRL_PKEY_ENB 0x40  /* Note, default is enabled */
601 #define HFI1_RCVCTRL_PKEY_DIS 0x80
602 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
603 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
604 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
605 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
606 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
607 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
608 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
609 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
610 
611 /* partition enforcement flags */
612 #define HFI1_PART_ENFORCE_IN	0x1
613 #define HFI1_PART_ENFORCE_OUT	0x2
614 
615 /* how often we check for synthetic counter wrap around */
616 #define SYNTH_CNT_TIME 3
617 
618 /* Counter flags */
619 #define CNTR_NORMAL		0x0 /* Normal counters, just read register */
620 #define CNTR_SYNTH		0x1 /* Synthetic counters, saturate at all 1s */
621 #define CNTR_DISABLED		0x2 /* Disable this counter */
622 #define CNTR_32BIT		0x4 /* Simulate 64 bits for this counter */
623 #define CNTR_VL			0x8 /* Per VL counter */
624 #define CNTR_SDMA              0x10
625 #define CNTR_INVALID_VL		-1  /* Specifies invalid VL */
626 #define CNTR_MODE_W		0x0
627 #define CNTR_MODE_R		0x1
628 
629 /* VLs Supported/Operational */
630 #define HFI1_MIN_VLS_SUPPORTED 1
631 #define HFI1_MAX_VLS_SUPPORTED 8
632 
633 #define HFI1_GUIDS_PER_PORT  5
634 #define HFI1_PORT_GUID_INDEX 0
635 
636 static inline void incr_cntr64(u64 *cntr)
637 {
638 	if (*cntr < (u64)-1LL)
639 		(*cntr)++;
640 }
641 
642 static inline void incr_cntr32(u32 *cntr)
643 {
644 	if (*cntr < (u32)-1LL)
645 		(*cntr)++;
646 }
647 
648 #define MAX_NAME_SIZE 64
649 struct hfi1_msix_entry {
650 	enum irq_type type;
651 	int irq;
652 	void *arg;
653 	cpumask_t mask;
654 	struct irq_affinity_notify notify;
655 };
656 
657 /* per-SL CCA information */
658 struct cca_timer {
659 	struct hrtimer hrtimer;
660 	struct hfi1_pportdata *ppd; /* read-only */
661 	int sl; /* read-only */
662 	u16 ccti; /* read/write - current value of CCTI */
663 };
664 
665 struct link_down_reason {
666 	/*
667 	 * SMA-facing value.  Should be set from .latest when
668 	 * HLS_UP_* -> HLS_DN_* transition actually occurs.
669 	 */
670 	u8 sma;
671 	u8 latest;
672 };
673 
674 enum {
675 	LO_PRIO_TABLE,
676 	HI_PRIO_TABLE,
677 	MAX_PRIO_TABLE
678 };
679 
680 struct vl_arb_cache {
681 	/* protect vl arb cache */
682 	spinlock_t lock;
683 	struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
684 };
685 
686 /*
687  * The structure below encapsulates data relevant to a physical IB Port.
688  * Current chips support only one such port, but the separation
689  * clarifies things a bit. Note that to conform to IB conventions,
690  * port-numbers are one-based. The first or only port is port1.
691  */
692 struct hfi1_pportdata {
693 	struct hfi1_ibport ibport_data;
694 
695 	struct hfi1_devdata *dd;
696 	struct kobject pport_cc_kobj;
697 	struct kobject sc2vl_kobj;
698 	struct kobject sl2sc_kobj;
699 	struct kobject vl2mtu_kobj;
700 
701 	/* PHY support */
702 	struct qsfp_data qsfp_info;
703 	/* Values for SI tuning of SerDes */
704 	u32 port_type;
705 	u32 tx_preset_eq;
706 	u32 tx_preset_noeq;
707 	u32 rx_preset;
708 	u8  local_atten;
709 	u8  remote_atten;
710 	u8  default_atten;
711 	u8  max_power_class;
712 
713 	/* did we read platform config from scratch registers? */
714 	bool config_from_scratch;
715 
716 	/* GUIDs for this interface, in host order, guids[0] is a port guid */
717 	u64 guids[HFI1_GUIDS_PER_PORT];
718 
719 	/* GUID for peer interface, in host order */
720 	u64 neighbor_guid;
721 
722 	/* up or down physical link state */
723 	u32 linkup;
724 
725 	/*
726 	 * this address is mapped read-only into user processes so they can
727 	 * get status cheaply, whenever they want.  One qword of status per port
728 	 */
729 	u64 *statusp;
730 
731 	/* SendDMA related entries */
732 
733 	struct workqueue_struct *hfi1_wq;
734 	struct workqueue_struct *link_wq;
735 
736 	/* move out of interrupt context */
737 	struct work_struct link_vc_work;
738 	struct work_struct link_up_work;
739 	struct work_struct link_down_work;
740 	struct work_struct sma_message_work;
741 	struct work_struct freeze_work;
742 	struct work_struct link_downgrade_work;
743 	struct work_struct link_bounce_work;
744 	struct delayed_work start_link_work;
745 	/* host link state variables */
746 	struct mutex hls_lock;
747 	u32 host_link_state;
748 
749 	/* these are the "32 bit" regs */
750 
751 	u32 ibmtu; /* The MTU programmed for this unit */
752 	/*
753 	 * Current max size IB packet (in bytes) including IB headers, that
754 	 * we can send. Changes when ibmtu changes.
755 	 */
756 	u32 ibmaxlen;
757 	u32 current_egress_rate; /* units [10^6 bits/sec] */
758 	/* LID programmed for this instance */
759 	u32 lid;
760 	/* list of pkeys programmed; 0 if not set */
761 	u16 pkeys[MAX_PKEY_VALUES];
762 	u16 link_width_supported;
763 	u16 link_width_downgrade_supported;
764 	u16 link_speed_supported;
765 	u16 link_width_enabled;
766 	u16 link_width_downgrade_enabled;
767 	u16 link_speed_enabled;
768 	u16 link_width_active;
769 	u16 link_width_downgrade_tx_active;
770 	u16 link_width_downgrade_rx_active;
771 	u16 link_speed_active;
772 	u8 vls_supported;
773 	u8 vls_operational;
774 	u8 actual_vls_operational;
775 	/* LID mask control */
776 	u8 lmc;
777 	/* Rx Polarity inversion (compensate for ~tx on partner) */
778 	u8 rx_pol_inv;
779 
780 	u8 hw_pidx;     /* physical port index */
781 	u8 port;        /* IB port number and index into dd->pports - 1 */
782 	/* type of neighbor node */
783 	u8 neighbor_type;
784 	u8 neighbor_normal;
785 	u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
786 	u8 neighbor_port_number;
787 	u8 is_sm_config_started;
788 	u8 offline_disabled_reason;
789 	u8 is_active_optimize_enabled;
790 	u8 driver_link_ready;	/* driver ready for active link */
791 	u8 link_enabled;	/* link enabled? */
792 	u8 linkinit_reason;
793 	u8 local_tx_rate;	/* rate given to 8051 firmware */
794 	u8 qsfp_retry_count;
795 
796 	/* placeholders for IB MAD packet settings */
797 	u8 overrun_threshold;
798 	u8 phy_error_threshold;
799 	unsigned int is_link_down_queued;
800 
801 	/* Used to override LED behavior for things like maintenance beaconing*/
802 	/*
803 	 * Alternates per phase of blink
804 	 * [0] holds LED off duration, [1] holds LED on duration
805 	 */
806 	unsigned long led_override_vals[2];
807 	u8 led_override_phase; /* LSB picks from vals[] */
808 	atomic_t led_override_timer_active;
809 	/* Used to flash LEDs in override mode */
810 	struct timer_list led_override_timer;
811 
812 	u32 sm_trap_qp;
813 	u32 sa_qp;
814 
815 	/*
816 	 * cca_timer_lock protects access to the per-SL cca_timer
817 	 * structures (specifically the ccti member).
818 	 */
819 	spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
820 	struct cca_timer cca_timer[OPA_MAX_SLS];
821 
822 	/* List of congestion control table entries */
823 	struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
824 
825 	/* congestion entries, each entry corresponding to a SL */
826 	struct opa_congestion_setting_entry_shadow
827 		congestion_entries[OPA_MAX_SLS];
828 
829 	/*
830 	 * cc_state_lock protects (write) access to the per-port
831 	 * struct cc_state.
832 	 */
833 	spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
834 
835 	struct cc_state __rcu *cc_state;
836 
837 	/* Total number of congestion control table entries */
838 	u16 total_cct_entry;
839 
840 	/* Bit map identifying service level */
841 	u32 cc_sl_control_map;
842 
843 	/* CA's max number of 64 entry units in the congestion control table */
844 	u8 cc_max_table_entries;
845 
846 	/*
847 	 * begin congestion log related entries
848 	 * cc_log_lock protects all congestion log related data
849 	 */
850 	spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
851 	u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
852 	u16 threshold_event_counter;
853 	struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
854 	int cc_log_idx; /* index for logging events */
855 	int cc_mad_idx; /* index for reporting events */
856 	/* end congestion log related entries */
857 
858 	struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
859 
860 	/* port relative counter buffer */
861 	u64 *cntrs;
862 	/* port relative synthetic counter buffer */
863 	u64 *scntrs;
864 	/* port_xmit_discards are synthesized from different egress errors */
865 	u64 port_xmit_discards;
866 	u64 port_xmit_discards_vl[C_VL_COUNT];
867 	u64 port_xmit_constraint_errors;
868 	u64 port_rcv_constraint_errors;
869 	/* count of 'link_err' interrupts from DC */
870 	u64 link_downed;
871 	/* number of times link retrained successfully */
872 	u64 link_up;
873 	/* number of times a link unknown frame was reported */
874 	u64 unknown_frame_count;
875 	/* port_ltp_crc_mode is returned in 'portinfo' MADs */
876 	u16 port_ltp_crc_mode;
877 	/* port_crc_mode_enabled is the crc we support */
878 	u8 port_crc_mode_enabled;
879 	/* mgmt_allowed is also returned in 'portinfo' MADs */
880 	u8 mgmt_allowed;
881 	u8 part_enforce; /* partition enforcement flags */
882 	struct link_down_reason local_link_down_reason;
883 	struct link_down_reason neigh_link_down_reason;
884 	/* Value to be sent to link peer on LinkDown .*/
885 	u8 remote_link_down_reason;
886 	/* Error events that will cause a port bounce. */
887 	u32 port_error_action;
888 	struct work_struct linkstate_active_work;
889 	/* Does this port need to prescan for FECNs */
890 	bool cc_prescan;
891 	/*
892 	 * Sample sendWaitCnt & sendWaitVlCnt during link transition
893 	 * and counter request.
894 	 */
895 	u64 port_vl_xmit_wait_last[C_VL_COUNT + 1];
896 	u16 prev_link_width;
897 	u64 vl_xmit_flit_cnt[C_VL_COUNT + 1];
898 };
899 
900 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
901 
902 typedef void (*opcode_handler)(struct hfi1_packet *packet);
903 typedef void (*hfi1_make_req)(struct rvt_qp *qp,
904 			      struct hfi1_pkt_state *ps,
905 			      struct rvt_swqe *wqe);
906 
907 
908 /* return values for the RHF receive functions */
909 #define RHF_RCV_CONTINUE  0	/* keep going */
910 #define RHF_RCV_DONE	  1	/* stop, this packet processed */
911 #define RHF_RCV_REPROCESS 2	/* stop. retain this packet */
912 
913 struct rcv_array_data {
914 	u16 ngroups;
915 	u16 nctxt_extra;
916 	u8 group_size;
917 };
918 
919 struct per_vl_data {
920 	u16 mtu;
921 	struct send_context *sc;
922 };
923 
924 /* 16 to directly index */
925 #define PER_VL_SEND_CONTEXTS 16
926 
927 struct err_info_rcvport {
928 	u8 status_and_code;
929 	u64 packet_flit1;
930 	u64 packet_flit2;
931 };
932 
933 struct err_info_constraint {
934 	u8 status;
935 	u16 pkey;
936 	u32 slid;
937 };
938 
939 struct hfi1_temp {
940 	unsigned int curr;       /* current temperature */
941 	unsigned int lo_lim;     /* low temperature limit */
942 	unsigned int hi_lim;     /* high temperature limit */
943 	unsigned int crit_lim;   /* critical temperature limit */
944 	u8 triggers;      /* temperature triggers */
945 };
946 
947 struct hfi1_i2c_bus {
948 	struct hfi1_devdata *controlling_dd; /* current controlling device */
949 	struct i2c_adapter adapter;	/* bus details */
950 	struct i2c_algo_bit_data algo;	/* bus algorithm details */
951 	int num;			/* bus number, 0 or 1 */
952 };
953 
954 /* common data between shared ASIC HFIs */
955 struct hfi1_asic_data {
956 	struct hfi1_devdata *dds[2];	/* back pointers */
957 	struct mutex asic_resource_mutex;
958 	struct hfi1_i2c_bus *i2c_bus0;
959 	struct hfi1_i2c_bus *i2c_bus1;
960 };
961 
962 /* sizes for both the QP and RSM map tables */
963 #define NUM_MAP_ENTRIES	 256
964 #define NUM_MAP_REGS      32
965 
966 /*
967  * Number of VNIC contexts used. Ensure it is less than or equal to
968  * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
969  */
970 #define HFI1_NUM_VNIC_CTXT   8
971 
972 /* Number of VNIC RSM entries */
973 #define NUM_VNIC_MAP_ENTRIES 8
974 
975 /* Virtual NIC information */
976 struct hfi1_vnic_data {
977 	struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
978 	struct kmem_cache *txreq_cache;
979 	u8 num_vports;
980 	struct idr vesw_idr;
981 	u8 rmt_start;
982 	u8 num_ctxt;
983 	u32 msix_idx;
984 };
985 
986 struct hfi1_vnic_vport_info;
987 
988 /* device data struct now contains only "general per-device" info.
989  * fields related to a physical IB port are in a hfi1_pportdata struct.
990  */
991 struct sdma_engine;
992 struct sdma_vl_map;
993 
994 #define BOARD_VERS_MAX 96 /* how long the version string can be */
995 #define SERIAL_MAX 16 /* length of the serial number */
996 
997 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
998 struct hfi1_devdata {
999 	struct hfi1_ibdev verbs_dev;     /* must be first */
1000 	struct list_head list;
1001 	/* pointers to related structs for this device */
1002 	/* pci access data structure */
1003 	struct pci_dev *pcidev;
1004 	struct cdev user_cdev;
1005 	struct cdev diag_cdev;
1006 	struct cdev ui_cdev;
1007 	struct device *user_device;
1008 	struct device *diag_device;
1009 	struct device *ui_device;
1010 
1011 	/* first mapping up to RcvArray */
1012 	u8 __iomem *kregbase1;
1013 	resource_size_t physaddr;
1014 
1015 	/* second uncached mapping from RcvArray to pio send buffers */
1016 	u8 __iomem *kregbase2;
1017 	/* for detecting offset above kregbase2 address */
1018 	u32 base2_start;
1019 
1020 	/* Per VL data. Enough for all VLs but not all elements are set/used. */
1021 	struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
1022 	/* send context data */
1023 	struct send_context_info *send_contexts;
1024 	/* map hardware send contexts to software index */
1025 	u8 *hw_to_sw;
1026 	/* spinlock for allocating and releasing send context resources */
1027 	spinlock_t sc_lock;
1028 	/* lock for pio_map */
1029 	spinlock_t pio_map_lock;
1030 	/* Send Context initialization lock. */
1031 	spinlock_t sc_init_lock;
1032 	/* lock for sdma_map */
1033 	spinlock_t                          sde_map_lock;
1034 	/* array of kernel send contexts */
1035 	struct send_context **kernel_send_context;
1036 	/* array of vl maps */
1037 	struct pio_vl_map __rcu *pio_map;
1038 	/* default flags to last descriptor */
1039 	u64 default_desc1;
1040 
1041 	/* fields common to all SDMA engines */
1042 
1043 	volatile __le64                    *sdma_heads_dma; /* DMA'ed by chip */
1044 	dma_addr_t                          sdma_heads_phys;
1045 	void                               *sdma_pad_dma; /* DMA'ed by chip */
1046 	dma_addr_t                          sdma_pad_phys;
1047 	/* for deallocation */
1048 	size_t                              sdma_heads_size;
1049 	/* number from the chip */
1050 	u32                                 chip_sdma_engines;
1051 	/* num used */
1052 	u32                                 num_sdma;
1053 	/* array of engines sized by num_sdma */
1054 	struct sdma_engine                 *per_sdma;
1055 	/* array of vl maps */
1056 	struct sdma_vl_map __rcu           *sdma_map;
1057 	/* SPC freeze waitqueue and variable */
1058 	wait_queue_head_t		  sdma_unfreeze_wq;
1059 	atomic_t			  sdma_unfreeze_count;
1060 
1061 	u32 lcb_access_count;		/* count of LCB users */
1062 
1063 	/* common data between shared ASIC HFIs in this OS */
1064 	struct hfi1_asic_data *asic_data;
1065 
1066 	/* mem-mapped pointer to base of PIO buffers */
1067 	void __iomem *piobase;
1068 	/*
1069 	 * write-combining mem-mapped pointer to base of RcvArray
1070 	 * memory.
1071 	 */
1072 	void __iomem *rcvarray_wc;
1073 	/*
1074 	 * credit return base - a per-NUMA range of DMA address that
1075 	 * the chip will use to update the per-context free counter
1076 	 */
1077 	struct credit_return_base *cr_base;
1078 
1079 	/* send context numbers and sizes for each type */
1080 	struct sc_config_sizes sc_sizes[SC_MAX];
1081 
1082 	char *boardname; /* human readable board info */
1083 
1084 	/* reset value */
1085 	u64 z_int_counter;
1086 	u64 z_rcv_limit;
1087 	u64 z_send_schedule;
1088 
1089 	u64 __percpu *send_schedule;
1090 	/* number of reserved contexts for VNIC usage */
1091 	u16 num_vnic_contexts;
1092 	/* number of receive contexts in use by the driver */
1093 	u32 num_rcv_contexts;
1094 	/* number of pio send contexts in use by the driver */
1095 	u32 num_send_contexts;
1096 	/*
1097 	 * number of ctxts available for PSM open
1098 	 */
1099 	u32 freectxts;
1100 	/* total number of available user/PSM contexts */
1101 	u32 num_user_contexts;
1102 	/* base receive interrupt timeout, in CSR units */
1103 	u32 rcv_intr_timeout_csr;
1104 
1105 	u32 freezelen; /* max length of freezemsg */
1106 	u64 __iomem *egrtidbase;
1107 	spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
1108 	spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
1109 	spinlock_t uctxt_lock; /* protect rcd changes */
1110 	struct mutex dc8051_lock; /* exclusive access to 8051 */
1111 	struct workqueue_struct *update_cntr_wq;
1112 	struct work_struct update_cntr_work;
1113 	/* exclusive access to 8051 memory */
1114 	spinlock_t dc8051_memlock;
1115 	int dc8051_timed_out;	/* remember if the 8051 timed out */
1116 	/*
1117 	 * A page that will hold event notification bitmaps for all
1118 	 * contexts. This page will be mapped into all processes.
1119 	 */
1120 	unsigned long *events;
1121 	/*
1122 	 * per unit status, see also portdata statusp
1123 	 * mapped read-only into user processes so they can get unit and
1124 	 * IB link status cheaply
1125 	 */
1126 	struct hfi1_status *status;
1127 
1128 	/* revision register shadow */
1129 	u64 revision;
1130 	/* Base GUID for device (network order) */
1131 	u64 base_guid;
1132 
1133 	/* these are the "32 bit" regs */
1134 
1135 	/* value we put in kr_rcvhdrsize */
1136 	u32 rcvhdrsize;
1137 	/* number of receive contexts the chip supports */
1138 	u32 chip_rcv_contexts;
1139 	/* number of receive array entries */
1140 	u32 chip_rcv_array_count;
1141 	/* number of PIO send contexts the chip supports */
1142 	u32 chip_send_contexts;
1143 	/* number of bytes in the PIO memory buffer */
1144 	u32 chip_pio_mem_size;
1145 	/* number of bytes in the SDMA memory buffer */
1146 	u32 chip_sdma_mem_size;
1147 
1148 	/* size of each rcvegrbuffer */
1149 	u32 rcvegrbufsize;
1150 	/* log2 of above */
1151 	u16 rcvegrbufsize_shift;
1152 	/* both sides of the PCIe link are gen3 capable */
1153 	u8 link_gen3_capable;
1154 	u8 dc_shutdown;
1155 	/* localbus width (1, 2,4,8,16,32) from config space  */
1156 	u32 lbus_width;
1157 	/* localbus speed in MHz */
1158 	u32 lbus_speed;
1159 	int unit; /* unit # of this chip */
1160 	int node; /* home node of this chip */
1161 
1162 	/* save these PCI fields to restore after a reset */
1163 	u32 pcibar0;
1164 	u32 pcibar1;
1165 	u32 pci_rom;
1166 	u16 pci_command;
1167 	u16 pcie_devctl;
1168 	u16 pcie_lnkctl;
1169 	u16 pcie_devctl2;
1170 	u32 pci_msix0;
1171 	u32 pci_tph2;
1172 
1173 	/*
1174 	 * ASCII serial number, from flash, large enough for original
1175 	 * all digit strings, and longer serial number format
1176 	 */
1177 	u8 serial[SERIAL_MAX];
1178 	/* human readable board version */
1179 	u8 boardversion[BOARD_VERS_MAX];
1180 	u8 lbus_info[32]; /* human readable localbus info */
1181 	/* chip major rev, from CceRevision */
1182 	u8 majrev;
1183 	/* chip minor rev, from CceRevision */
1184 	u8 minrev;
1185 	/* hardware ID */
1186 	u8 hfi1_id;
1187 	/* implementation code */
1188 	u8 icode;
1189 	/* vAU of this device */
1190 	u8 vau;
1191 	/* vCU of this device */
1192 	u8 vcu;
1193 	/* link credits of this device */
1194 	u16 link_credits;
1195 	/* initial vl15 credits to use */
1196 	u16 vl15_init;
1197 
1198 	/*
1199 	 * Cached value for vl15buf, read during verify cap interrupt. VL15
1200 	 * credits are to be kept at 0 and set when handling the link-up
1201 	 * interrupt. This removes the possibility of receiving VL15 MAD
1202 	 * packets before this HFI is ready.
1203 	 */
1204 	u16 vl15buf_cached;
1205 
1206 	/* Misc small ints */
1207 	u8 n_krcv_queues;
1208 	u8 qos_shift;
1209 
1210 	u16 irev;	/* implementation revision */
1211 	u32 dc8051_ver; /* 8051 firmware version */
1212 
1213 	spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1214 	struct platform_config platform_config;
1215 	struct platform_config_cache pcfg_cache;
1216 
1217 	struct diag_client *diag_client;
1218 
1219 	/* MSI-X information */
1220 	struct hfi1_msix_entry *msix_entries;
1221 	u32 num_msix_entries;
1222 	u32 first_dyn_msix_idx;
1223 
1224 	/* INTx information */
1225 	u32 requested_intx_irq;		/* did we request one? */
1226 
1227 	/* general interrupt: mask of handled interrupts */
1228 	u64 gi_mask[CCE_NUM_INT_CSRS];
1229 
1230 	struct rcv_array_data rcv_entries;
1231 
1232 	/* cycle length of PS* counters in HW (in picoseconds) */
1233 	u16 psxmitwait_check_rate;
1234 
1235 	/*
1236 	 * 64 bit synthetic counters
1237 	 */
1238 	struct timer_list synth_stats_timer;
1239 
1240 	/*
1241 	 * device counters
1242 	 */
1243 	char *cntrnames;
1244 	size_t cntrnameslen;
1245 	size_t ndevcntrs;
1246 	u64 *cntrs;
1247 	u64 *scntrs;
1248 
1249 	/*
1250 	 * remembered values for synthetic counters
1251 	 */
1252 	u64 last_tx;
1253 	u64 last_rx;
1254 
1255 	/*
1256 	 * per-port counters
1257 	 */
1258 	size_t nportcntrs;
1259 	char *portcntrnames;
1260 	size_t portcntrnameslen;
1261 
1262 	struct err_info_rcvport err_info_rcvport;
1263 	struct err_info_constraint err_info_rcv_constraint;
1264 	struct err_info_constraint err_info_xmit_constraint;
1265 
1266 	atomic_t drop_packet;
1267 	u8 do_drop;
1268 	u8 err_info_uncorrectable;
1269 	u8 err_info_fmconfig;
1270 
1271 	/*
1272 	 * Software counters for the status bits defined by the
1273 	 * associated error status registers
1274 	 */
1275 	u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1276 	u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1277 	u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1278 	u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1279 	u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1280 	u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1281 	u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1282 
1283 	/* Software counter that spans all contexts */
1284 	u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1285 	/* Software counter that spans all DMA engines */
1286 	u64 sw_send_dma_eng_err_status_cnt[
1287 		NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1288 	/* Software counter that aggregates all cce_err_status errors */
1289 	u64 sw_cce_err_status_aggregate;
1290 	/* Software counter that aggregates all bypass packet rcv errors */
1291 	u64 sw_rcv_bypass_packet_errors;
1292 	/* receive interrupt function */
1293 	rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1294 
1295 	/* Save the enabled LCB error bits */
1296 	u64 lcb_err_en;
1297 	struct cpu_mask_set *comp_vect;
1298 	int *comp_vect_mappings;
1299 	u32 comp_vect_possible_cpus;
1300 
1301 	/*
1302 	 * Capability to have different send engines simply by changing a
1303 	 * pointer value.
1304 	 */
1305 	send_routine process_pio_send ____cacheline_aligned_in_smp;
1306 	send_routine process_dma_send;
1307 	void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1308 				u64 pbc, const void *from, size_t count);
1309 	int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1310 				     struct hfi1_vnic_vport_info *vinfo,
1311 				     struct sk_buff *skb, u64 pbc, u8 plen);
1312 	/* hfi1_pportdata, points to array of (physical) port-specific
1313 	 * data structs, indexed by pidx (0..n-1)
1314 	 */
1315 	struct hfi1_pportdata *pport;
1316 	/* receive context data */
1317 	struct hfi1_ctxtdata **rcd;
1318 	u64 __percpu *int_counter;
1319 	/* verbs tx opcode stats */
1320 	struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1321 	/* device (not port) flags, basically device capabilities */
1322 	u16 flags;
1323 	/* Number of physical ports available */
1324 	u8 num_pports;
1325 	/* Lowest context number which can be used by user processes or VNIC */
1326 	u8 first_dyn_alloc_ctxt;
1327 	/* adding a new field here would make it part of this cacheline */
1328 
1329 	/* seqlock for sc2vl */
1330 	seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1331 	u64 sc2vl[4];
1332 	/* receive interrupt functions */
1333 	rhf_rcv_function_ptr *rhf_rcv_function_map;
1334 	u64 __percpu *rcv_limit;
1335 	u16 rhf_offset; /* offset of RHF within receive header entry */
1336 	/* adding a new field here would make it part of this cacheline */
1337 
1338 	/* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1339 	u8 oui1;
1340 	u8 oui2;
1341 	u8 oui3;
1342 
1343 	/* Timer and counter used to detect RcvBufOvflCnt changes */
1344 	struct timer_list rcverr_timer;
1345 
1346 	wait_queue_head_t event_queue;
1347 
1348 	/* receive context tail dummy address */
1349 	__le64 *rcvhdrtail_dummy_kvaddr;
1350 	dma_addr_t rcvhdrtail_dummy_dma;
1351 
1352 	u32 rcv_ovfl_cnt;
1353 	/* Serialize ASPM enable/disable between multiple verbs contexts */
1354 	spinlock_t aspm_lock;
1355 	/* Number of verbs contexts which have disabled ASPM */
1356 	atomic_t aspm_disabled_cnt;
1357 	/* Keeps track of user space clients */
1358 	atomic_t user_refcount;
1359 	/* Used to wait for outstanding user space clients before dev removal */
1360 	struct completion user_comp;
1361 
1362 	bool eprom_available;	/* true if EPROM is available for this device */
1363 	bool aspm_supported;	/* Does HW support ASPM */
1364 	bool aspm_enabled;	/* ASPM state: enabled/disabled */
1365 	struct rhashtable *sdma_rht;
1366 
1367 	struct kobject kobj;
1368 
1369 	/* vnic data */
1370 	struct hfi1_vnic_data vnic;
1371 };
1372 
1373 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1374 {
1375 	return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1376 }
1377 
1378 /* 8051 firmware version helper */
1379 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1380 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1381 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1382 #define dc8051_ver_patch(a) ((a) & 0x0000ff)
1383 
1384 /* f_put_tid types */
1385 #define PT_EXPECTED       0
1386 #define PT_EAGER          1
1387 #define PT_INVALID_FLUSH  2
1388 #define PT_INVALID        3
1389 
1390 struct tid_rb_node;
1391 struct mmu_rb_node;
1392 struct mmu_rb_handler;
1393 
1394 /* Private data for file operations */
1395 struct hfi1_filedata {
1396 	struct hfi1_devdata *dd;
1397 	struct hfi1_ctxtdata *uctxt;
1398 	struct hfi1_user_sdma_comp_q *cq;
1399 	struct hfi1_user_sdma_pkt_q *pq;
1400 	u16 subctxt;
1401 	/* for cpu affinity; -1 if none */
1402 	int rec_cpu_num;
1403 	u32 tid_n_pinned;
1404 	struct mmu_rb_handler *handler;
1405 	struct tid_rb_node **entry_to_rb;
1406 	spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1407 	u32 tid_limit;
1408 	u32 tid_used;
1409 	u32 *invalid_tids;
1410 	u32 invalid_tid_idx;
1411 	/* protect invalid_tids array and invalid_tid_idx */
1412 	spinlock_t invalid_lock;
1413 	struct mm_struct *mm;
1414 };
1415 
1416 extern struct list_head hfi1_dev_list;
1417 extern spinlock_t hfi1_devs_lock;
1418 struct hfi1_devdata *hfi1_lookup(int unit);
1419 
1420 static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1421 {
1422 	return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1423 		HFI1_MAX_SHARED_CTXTS;
1424 }
1425 
1426 int hfi1_init(struct hfi1_devdata *dd, int reinit);
1427 int hfi1_count_active_units(void);
1428 
1429 int hfi1_diag_add(struct hfi1_devdata *dd);
1430 void hfi1_diag_remove(struct hfi1_devdata *dd);
1431 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1432 
1433 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1434 
1435 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1436 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1437 int hfi1_create_kctxts(struct hfi1_devdata *dd);
1438 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1439 			 struct hfi1_ctxtdata **rcd);
1440 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1441 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1442 			 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1443 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1444 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1445 void hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1446 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1447 						 u16 ctxt);
1448 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1449 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1450 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1451 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1452 void set_all_slowpath(struct hfi1_devdata *dd);
1453 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd);
1454 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1455 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1456 
1457 extern const struct pci_device_id hfi1_pci_tbl[];
1458 void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1459 			 struct hfi1_pkt_state *ps,
1460 			 struct rvt_swqe *wqe);
1461 
1462 void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1463 			  struct hfi1_pkt_state *ps,
1464 			  struct rvt_swqe *wqe);
1465 
1466 /* receive packet handler dispositions */
1467 #define RCV_PKT_OK      0x0 /* keep going */
1468 #define RCV_PKT_LIMIT   0x1 /* stop, hit limit, start thread */
1469 #define RCV_PKT_DONE    0x2 /* stop, no more packets detected */
1470 
1471 /* calculate the current RHF address */
1472 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1473 {
1474 	return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1475 }
1476 
1477 int hfi1_reset_device(int);
1478 
1479 void receive_interrupt_work(struct work_struct *work);
1480 
1481 /* extract service channel from header and rhf */
1482 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1483 {
1484 	return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1485 }
1486 
1487 #define HFI1_JKEY_WIDTH       16
1488 #define HFI1_JKEY_MASK        (BIT(16) - 1)
1489 #define HFI1_ADMIN_JKEY_RANGE 32
1490 
1491 /*
1492  * J_KEYs are split and allocated in the following groups:
1493  *   0 - 31    - users with administrator privileges
1494  *  32 - 63    - kernel protocols using KDETH packets
1495  *  64 - 65535 - all other users using KDETH packets
1496  */
1497 static inline u16 generate_jkey(kuid_t uid)
1498 {
1499 	u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1500 
1501 	if (capable(CAP_SYS_ADMIN))
1502 		jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1503 	else if (jkey < 64)
1504 		jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1505 
1506 	return jkey;
1507 }
1508 
1509 /*
1510  * active_egress_rate
1511  *
1512  * returns the active egress rate in units of [10^6 bits/sec]
1513  */
1514 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1515 {
1516 	u16 link_speed = ppd->link_speed_active;
1517 	u16 link_width = ppd->link_width_active;
1518 	u32 egress_rate;
1519 
1520 	if (link_speed == OPA_LINK_SPEED_25G)
1521 		egress_rate = 25000;
1522 	else /* assume OPA_LINK_SPEED_12_5G */
1523 		egress_rate = 12500;
1524 
1525 	switch (link_width) {
1526 	case OPA_LINK_WIDTH_4X:
1527 		egress_rate *= 4;
1528 		break;
1529 	case OPA_LINK_WIDTH_3X:
1530 		egress_rate *= 3;
1531 		break;
1532 	case OPA_LINK_WIDTH_2X:
1533 		egress_rate *= 2;
1534 		break;
1535 	default:
1536 		/* assume IB_WIDTH_1X */
1537 		break;
1538 	}
1539 
1540 	return egress_rate;
1541 }
1542 
1543 /*
1544  * egress_cycles
1545  *
1546  * Returns the number of 'fabric clock cycles' to egress a packet
1547  * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1548  * rate is (approximately) 805 MHz, the units of the returned value
1549  * are (1/805 MHz).
1550  */
1551 static inline u32 egress_cycles(u32 len, u32 rate)
1552 {
1553 	u32 cycles;
1554 
1555 	/*
1556 	 * cycles is:
1557 	 *
1558 	 *          (length) [bits] / (rate) [bits/sec]
1559 	 *  ---------------------------------------------------
1560 	 *  fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1561 	 */
1562 
1563 	cycles = len * 8; /* bits */
1564 	cycles *= 805;
1565 	cycles /= rate;
1566 
1567 	return cycles;
1568 }
1569 
1570 void set_link_ipg(struct hfi1_pportdata *ppd);
1571 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1572 		  u32 rqpn, u8 svc_type);
1573 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1574 		u16 pkey, u32 slid, u32 dlid, u8 sc5,
1575 		const struct ib_grh *old_grh);
1576 void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1577 		    u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1578 		    u8 sc5, const struct ib_grh *old_grh);
1579 typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1580 				u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1581 				u8 sc5, const struct ib_grh *old_grh);
1582 
1583 #define PKEY_CHECK_INVALID -1
1584 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1585 		      u8 sc5, int8_t s_pkey_index);
1586 
1587 #define PACKET_EGRESS_TIMEOUT 350
1588 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1589 {
1590 	/* Pause at least 1us, to ensure chip returns all credits */
1591 	u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1592 
1593 	udelay(usec ? usec : 1);
1594 }
1595 
1596 /**
1597  * sc_to_vlt() reverse lookup sc to vl
1598  * @dd - devdata
1599  * @sc5 - 5 bit sc
1600  */
1601 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1602 {
1603 	unsigned seq;
1604 	u8 rval;
1605 
1606 	if (sc5 >= OPA_MAX_SCS)
1607 		return (u8)(0xff);
1608 
1609 	do {
1610 		seq = read_seqbegin(&dd->sc2vl_lock);
1611 		rval = *(((u8 *)dd->sc2vl) + sc5);
1612 	} while (read_seqretry(&dd->sc2vl_lock, seq));
1613 
1614 	return rval;
1615 }
1616 
1617 #define PKEY_MEMBER_MASK 0x8000
1618 #define PKEY_LOW_15_MASK 0x7fff
1619 
1620 /*
1621  * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1622  * being an entry from the ingress partition key table), return 0
1623  * otherwise. Use the matching criteria for ingress partition keys
1624  * specified in the OPAv1 spec., section 9.10.14.
1625  */
1626 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1627 {
1628 	u16 mkey = pkey & PKEY_LOW_15_MASK;
1629 	u16 ment = ent & PKEY_LOW_15_MASK;
1630 
1631 	if (mkey == ment) {
1632 		/*
1633 		 * If pkey[15] is clear (limited partition member),
1634 		 * is bit 15 in the corresponding table element
1635 		 * clear (limited member)?
1636 		 */
1637 		if (!(pkey & PKEY_MEMBER_MASK))
1638 			return !!(ent & PKEY_MEMBER_MASK);
1639 		return 1;
1640 	}
1641 	return 0;
1642 }
1643 
1644 /*
1645  * ingress_pkey_table_search - search the entire pkey table for
1646  * an entry which matches 'pkey'. return 0 if a match is found,
1647  * and 1 otherwise.
1648  */
1649 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1650 {
1651 	int i;
1652 
1653 	for (i = 0; i < MAX_PKEY_VALUES; i++) {
1654 		if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1655 			return 0;
1656 	}
1657 	return 1;
1658 }
1659 
1660 /*
1661  * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1662  * i.e., increment port_rcv_constraint_errors for the port, and record
1663  * the 'error info' for this failure.
1664  */
1665 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1666 				    u32 slid)
1667 {
1668 	struct hfi1_devdata *dd = ppd->dd;
1669 
1670 	incr_cntr64(&ppd->port_rcv_constraint_errors);
1671 	if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1672 		dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1673 		dd->err_info_rcv_constraint.slid = slid;
1674 		dd->err_info_rcv_constraint.pkey = pkey;
1675 	}
1676 }
1677 
1678 /*
1679  * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1680  * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1681  * is a hint as to the best place in the partition key table to begin
1682  * searching. This function should not be called on the data path because
1683  * of performance reasons. On datapath pkey check is expected to be done
1684  * by HW and rcv_pkey_check function should be called instead.
1685  */
1686 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1687 				     u8 sc5, u8 idx, u32 slid, bool force)
1688 {
1689 	if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1690 		return 0;
1691 
1692 	/* If SC15, pkey[0:14] must be 0x7fff */
1693 	if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1694 		goto bad;
1695 
1696 	/* Is the pkey = 0x0, or 0x8000? */
1697 	if ((pkey & PKEY_LOW_15_MASK) == 0)
1698 		goto bad;
1699 
1700 	/* The most likely matching pkey has index 'idx' */
1701 	if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1702 		return 0;
1703 
1704 	/* no match - try the whole table */
1705 	if (!ingress_pkey_table_search(ppd, pkey))
1706 		return 0;
1707 
1708 bad:
1709 	ingress_pkey_table_fail(ppd, pkey, slid);
1710 	return 1;
1711 }
1712 
1713 /*
1714  * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1715  * otherwise. It only ensures pkey is vlid for QP0. This function
1716  * should be called on the data path instead of ingress_pkey_check
1717  * as on data path, pkey check is done by HW (except for QP0).
1718  */
1719 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1720 				 u8 sc5, u16 slid)
1721 {
1722 	if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1723 		return 0;
1724 
1725 	/* If SC15, pkey[0:14] must be 0x7fff */
1726 	if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1727 		goto bad;
1728 
1729 	return 0;
1730 bad:
1731 	ingress_pkey_table_fail(ppd, pkey, slid);
1732 	return 1;
1733 }
1734 
1735 /* MTU handling */
1736 
1737 /* MTU enumeration, 256-4k match IB */
1738 #define OPA_MTU_0     0
1739 #define OPA_MTU_256   1
1740 #define OPA_MTU_512   2
1741 #define OPA_MTU_1024  3
1742 #define OPA_MTU_2048  4
1743 #define OPA_MTU_4096  5
1744 
1745 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1746 int mtu_to_enum(u32 mtu, int default_if_bad);
1747 u16 enum_to_mtu(int mtu);
1748 static inline int valid_ib_mtu(unsigned int mtu)
1749 {
1750 	return mtu == 256 || mtu == 512 ||
1751 		mtu == 1024 || mtu == 2048 ||
1752 		mtu == 4096;
1753 }
1754 
1755 static inline int valid_opa_max_mtu(unsigned int mtu)
1756 {
1757 	return mtu >= 2048 &&
1758 		(valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1759 }
1760 
1761 int set_mtu(struct hfi1_pportdata *ppd);
1762 
1763 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1764 void hfi1_disable_after_error(struct hfi1_devdata *dd);
1765 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1766 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1767 
1768 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1769 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1770 
1771 void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1772 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1773 void reset_link_credits(struct hfi1_devdata *dd);
1774 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1775 
1776 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1777 
1778 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1779 {
1780 	return ppd->dd;
1781 }
1782 
1783 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1784 {
1785 	return container_of(dev, struct hfi1_devdata, verbs_dev);
1786 }
1787 
1788 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1789 {
1790 	return dd_from_dev(to_idev(ibdev));
1791 }
1792 
1793 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1794 {
1795 	return container_of(ibp, struct hfi1_pportdata, ibport_data);
1796 }
1797 
1798 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1799 {
1800 	return container_of(rdi, struct hfi1_ibdev, rdi);
1801 }
1802 
1803 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1804 {
1805 	struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1806 	unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1807 
1808 	WARN_ON(pidx >= dd->num_pports);
1809 	return &dd->pport[pidx].ibport_data;
1810 }
1811 
1812 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1813 {
1814 	return &rcd->ppd->ibport_data;
1815 }
1816 
1817 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1818 			       bool do_cnp);
1819 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt,
1820 			       bool do_cnp)
1821 {
1822 	bool becn;
1823 	bool fecn;
1824 
1825 	if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1826 		fecn = hfi1_16B_get_fecn(pkt->hdr);
1827 		becn = hfi1_16B_get_becn(pkt->hdr);
1828 	} else {
1829 		fecn = ib_bth_get_fecn(pkt->ohdr);
1830 		becn = ib_bth_get_becn(pkt->ohdr);
1831 	}
1832 	if (unlikely(fecn || becn)) {
1833 		hfi1_process_ecn_slowpath(qp, pkt, do_cnp);
1834 		return fecn;
1835 	}
1836 	return false;
1837 }
1838 
1839 /*
1840  * Return the indexed PKEY from the port PKEY table.
1841  */
1842 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1843 {
1844 	struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1845 	u16 ret;
1846 
1847 	if (index >= ARRAY_SIZE(ppd->pkeys))
1848 		ret = 0;
1849 	else
1850 		ret = ppd->pkeys[index];
1851 
1852 	return ret;
1853 }
1854 
1855 /*
1856  * Return the indexed GUID from the port GUIDs table.
1857  */
1858 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1859 {
1860 	struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1861 
1862 	WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1863 	return cpu_to_be64(ppd->guids[index]);
1864 }
1865 
1866 /*
1867  * Called by readers of cc_state only, must call under rcu_read_lock().
1868  */
1869 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1870 {
1871 	return rcu_dereference(ppd->cc_state);
1872 }
1873 
1874 /*
1875  * Called by writers of cc_state only,  must call under cc_state_lock.
1876  */
1877 static inline
1878 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1879 {
1880 	return rcu_dereference_protected(ppd->cc_state,
1881 					 lockdep_is_held(&ppd->cc_state_lock));
1882 }
1883 
1884 /*
1885  * values for dd->flags (_device_ related flags)
1886  */
1887 #define HFI1_INITTED           0x1    /* chip and driver up and initted */
1888 #define HFI1_PRESENT           0x2    /* chip accesses can be done */
1889 #define HFI1_FROZEN            0x4    /* chip in SPC freeze */
1890 #define HFI1_HAS_SDMA_TIMEOUT  0x8
1891 #define HFI1_HAS_SEND_DMA      0x10   /* Supports Send DMA */
1892 #define HFI1_FORCED_FREEZE     0x80   /* driver forced freeze mode */
1893 #define HFI1_SHUTDOWN          0x100  /* device is shutting down */
1894 
1895 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1896 #define HFI1_PBC_LENGTH_MASK                     ((1 << 11) - 1)
1897 
1898 /* ctxt_flag bit offsets */
1899 		/* base context has not finished initializing */
1900 #define HFI1_CTXT_BASE_UNINIT 1
1901 		/* base context initaliation failed */
1902 #define HFI1_CTXT_BASE_FAILED 2
1903 		/* waiting for a packet to arrive */
1904 #define HFI1_CTXT_WAITING_RCV 3
1905 		/* waiting for an urgent packet to arrive */
1906 #define HFI1_CTXT_WAITING_URG 4
1907 
1908 /* free up any allocated data at closes */
1909 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
1910 				  const struct pci_device_id *ent);
1911 void hfi1_free_devdata(struct hfi1_devdata *dd);
1912 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1913 
1914 /* LED beaconing functions */
1915 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1916 			     unsigned int timeoff);
1917 void shutdown_led_override(struct hfi1_pportdata *ppd);
1918 
1919 #define HFI1_CREDIT_RETURN_RATE (100)
1920 
1921 /*
1922  * The number of words for the KDETH protocol field.  If this is
1923  * larger then the actual field used, then part of the payload
1924  * will be in the header.
1925  *
1926  * Optimally, we want this sized so that a typical case will
1927  * use full cache lines.  The typical local KDETH header would
1928  * be:
1929  *
1930  *	Bytes	Field
1931  *	  8	LRH
1932  *	 12	BHT
1933  *	 ??	KDETH
1934  *	  8	RHF
1935  *	---
1936  *	 28 + KDETH
1937  *
1938  * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1939  */
1940 #define DEFAULT_RCVHDRSIZE 9
1941 
1942 /*
1943  * Maximal header byte count:
1944  *
1945  *	Bytes	Field
1946  *	  8	LRH
1947  *	 40	GRH (optional)
1948  *	 12	BTH
1949  *	 ??	KDETH
1950  *	  8	RHF
1951  *	---
1952  *	 68 + KDETH
1953  *
1954  * We also want to maintain a cache line alignment to assist DMA'ing
1955  * of the header bytes.  Round up to a good size.
1956  */
1957 #define DEFAULT_RCVHDR_ENTSIZE 32
1958 
1959 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1960 			u32 nlocked, u32 npages);
1961 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1962 			    size_t npages, bool writable, struct page **pages);
1963 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1964 			     size_t npages, bool dirty);
1965 
1966 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1967 {
1968 	*((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1969 }
1970 
1971 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1972 {
1973 	/*
1974 	 * volatile because it's a DMA target from the chip, routine is
1975 	 * inlined, and don't want register caching or reordering.
1976 	 */
1977 	return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1978 }
1979 
1980 /*
1981  * sysfs interface.
1982  */
1983 
1984 extern const char ib_hfi1_version[];
1985 
1986 int hfi1_device_create(struct hfi1_devdata *dd);
1987 void hfi1_device_remove(struct hfi1_devdata *dd);
1988 
1989 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1990 			   struct kobject *kobj);
1991 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
1992 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
1993 /* Hook for sysfs read of QSFP */
1994 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1995 
1996 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent);
1997 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd);
1998 void hfi1_pcie_cleanup(struct pci_dev *pdev);
1999 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
2000 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
2001 int pcie_speeds(struct hfi1_devdata *dd);
2002 int request_msix(struct hfi1_devdata *dd, u32 msireq);
2003 int restore_pci_variables(struct hfi1_devdata *dd);
2004 int save_pci_variables(struct hfi1_devdata *dd);
2005 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
2006 int parse_platform_config(struct hfi1_devdata *dd);
2007 int get_platform_config_field(struct hfi1_devdata *dd,
2008 			      enum platform_config_table_type_encoding
2009 			      table_type, int table_index, int field_index,
2010 			      u32 *data, u32 len);
2011 
2012 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
2013 
2014 /*
2015  * Flush write combining store buffers (if present) and perform a write
2016  * barrier.
2017  */
2018 static inline void flush_wc(void)
2019 {
2020 	asm volatile("sfence" : : : "memory");
2021 }
2022 
2023 void handle_eflags(struct hfi1_packet *packet);
2024 int process_receive_ib(struct hfi1_packet *packet);
2025 int process_receive_bypass(struct hfi1_packet *packet);
2026 int process_receive_error(struct hfi1_packet *packet);
2027 int kdeth_process_expected(struct hfi1_packet *packet);
2028 int kdeth_process_eager(struct hfi1_packet *packet);
2029 int process_receive_invalid(struct hfi1_packet *packet);
2030 void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
2031 
2032 /* global module parameter variables */
2033 extern unsigned int hfi1_max_mtu;
2034 extern unsigned int hfi1_cu;
2035 extern unsigned int user_credit_return_threshold;
2036 extern int num_user_contexts;
2037 extern unsigned long n_krcvqs;
2038 extern uint krcvqs[];
2039 extern int krcvqsset;
2040 extern uint kdeth_qp;
2041 extern uint loopback;
2042 extern uint quick_linkup;
2043 extern uint rcv_intr_timeout;
2044 extern uint rcv_intr_count;
2045 extern uint rcv_intr_dynamic;
2046 extern ushort link_crc_mask;
2047 
2048 extern struct mutex hfi1_mutex;
2049 
2050 /* Number of seconds before our card status check...  */
2051 #define STATUS_TIMEOUT 60
2052 
2053 #define DRIVER_NAME		"hfi1"
2054 #define HFI1_USER_MINOR_BASE     0
2055 #define HFI1_TRACE_MINOR         127
2056 #define HFI1_NMINORS             255
2057 
2058 #define PCI_VENDOR_ID_INTEL 0x8086
2059 #define PCI_DEVICE_ID_INTEL0 0x24f0
2060 #define PCI_DEVICE_ID_INTEL1 0x24f1
2061 
2062 #define HFI1_PKT_USER_SC_INTEGRITY					    \
2063 	(SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK	    \
2064 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK		\
2065 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK		    \
2066 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2067 
2068 #define HFI1_PKT_KERNEL_SC_INTEGRITY					    \
2069 	(SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2070 
2071 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2072 						  u16 ctxt_type)
2073 {
2074 	u64 base_sc_integrity;
2075 
2076 	/* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2077 	if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2078 		return 0;
2079 
2080 	base_sc_integrity =
2081 	SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2082 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2083 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2084 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2085 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2086 #ifndef CONFIG_FAULT_INJECTION
2087 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2088 #endif
2089 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2090 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2091 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2092 	| SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2093 	| SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2094 	| SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2095 	| SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2096 	| SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2097 	| SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2098 	| SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2099 
2100 	if (ctxt_type == SC_USER)
2101 		base_sc_integrity |=
2102 #ifndef CONFIG_FAULT_INJECTION
2103 			SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
2104 #endif
2105 			HFI1_PKT_USER_SC_INTEGRITY;
2106 	else
2107 		base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2108 
2109 	/* turn on send-side job key checks if !A0 */
2110 	if (!is_ax(dd))
2111 		base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2112 
2113 	return base_sc_integrity;
2114 }
2115 
2116 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2117 {
2118 	u64 base_sdma_integrity;
2119 
2120 	/* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2121 	if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2122 		return 0;
2123 
2124 	base_sdma_integrity =
2125 	SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2126 	| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2127 	| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2128 	| SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2129 	| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2130 	| SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2131 	| SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2132 	| SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2133 	| SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2134 	| SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2135 	| SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2136 	| SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2137 	| SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2138 	| SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2139 
2140 	if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2141 		base_sdma_integrity |=
2142 		SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2143 
2144 	/* turn on send-side job key checks if !A0 */
2145 	if (!is_ax(dd))
2146 		base_sdma_integrity |=
2147 			SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2148 
2149 	return base_sdma_integrity;
2150 }
2151 
2152 /*
2153  * hfi1_early_err is used (only!) to print early errors before devdata is
2154  * allocated, or when dd->pcidev may not be valid, and at the tail end of
2155  * cleanup when devdata may have been freed, etc.  hfi1_dev_porterr is
2156  * the same as dd_dev_err, but is used when the message really needs
2157  * the IB port# to be definitive as to what's happening..
2158  */
2159 #define hfi1_early_err(dev, fmt, ...) \
2160 	dev_err(dev, fmt, ##__VA_ARGS__)
2161 
2162 #define hfi1_early_info(dev, fmt, ...) \
2163 	dev_info(dev, fmt, ##__VA_ARGS__)
2164 
2165 #define dd_dev_emerg(dd, fmt, ...) \
2166 	dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2167 		  rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2168 
2169 #define dd_dev_err(dd, fmt, ...) \
2170 	dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2171 		rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2172 
2173 #define dd_dev_err_ratelimited(dd, fmt, ...) \
2174 	dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2175 			    rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2176 			    ##__VA_ARGS__)
2177 
2178 #define dd_dev_warn(dd, fmt, ...) \
2179 	dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2180 		 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2181 
2182 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
2183 	dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2184 			     rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2185 			     ##__VA_ARGS__)
2186 
2187 #define dd_dev_info(dd, fmt, ...) \
2188 	dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2189 		 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2190 
2191 #define dd_dev_info_ratelimited(dd, fmt, ...) \
2192 	dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2193 			     rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2194 			     ##__VA_ARGS__)
2195 
2196 #define dd_dev_dbg(dd, fmt, ...) \
2197 	dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2198 		rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2199 
2200 #define hfi1_dev_porterr(dd, port, fmt, ...) \
2201 	dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2202 		rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
2203 
2204 /*
2205  * this is used for formatting hw error messages...
2206  */
2207 struct hfi1_hwerror_msgs {
2208 	u64 mask;
2209 	const char *msg;
2210 	size_t sz;
2211 };
2212 
2213 /* in intr.c... */
2214 void hfi1_format_hwerrors(u64 hwerrs,
2215 			  const struct hfi1_hwerror_msgs *hwerrmsgs,
2216 			  size_t nhwerrmsgs, char *msg, size_t lmsg);
2217 
2218 #define USER_OPCODE_CHECK_VAL 0xC0
2219 #define USER_OPCODE_CHECK_MASK 0xC0
2220 #define OPCODE_CHECK_VAL_DISABLED 0x0
2221 #define OPCODE_CHECK_MASK_DISABLED 0x0
2222 
2223 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2224 {
2225 	struct hfi1_pportdata *ppd;
2226 	int i;
2227 
2228 	dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2229 	dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2230 	dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2231 
2232 	ppd = (struct hfi1_pportdata *)(dd + 1);
2233 	for (i = 0; i < dd->num_pports; i++, ppd++) {
2234 		ppd->ibport_data.rvp.z_rc_acks =
2235 			get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2236 		ppd->ibport_data.rvp.z_rc_qacks =
2237 			get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2238 	}
2239 }
2240 
2241 /* Control LED state */
2242 static inline void setextled(struct hfi1_devdata *dd, u32 on)
2243 {
2244 	if (on)
2245 		write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2246 	else
2247 		write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2248 }
2249 
2250 /* return the i2c resource given the target */
2251 static inline u32 i2c_target(u32 target)
2252 {
2253 	return target ? CR_I2C2 : CR_I2C1;
2254 }
2255 
2256 /* return the i2c chain chip resource that this HFI uses for QSFP */
2257 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2258 {
2259 	return i2c_target(dd->hfi1_id);
2260 }
2261 
2262 /* Is this device integrated or discrete? */
2263 static inline bool is_integrated(struct hfi1_devdata *dd)
2264 {
2265 	return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2266 }
2267 
2268 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2269 
2270 #define DD_DEV_ENTRY(dd)       __string(dev, dev_name(&(dd)->pcidev->dev))
2271 #define DD_DEV_ASSIGN(dd)      __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2272 
2273 static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2274 				       struct rdma_ah_attr *attr)
2275 {
2276 	struct hfi1_pportdata *ppd;
2277 	struct hfi1_ibport *ibp;
2278 	u32 dlid = rdma_ah_get_dlid(attr);
2279 
2280 	/*
2281 	 * Kernel clients may not have setup GRH information
2282 	 * Set that here.
2283 	 */
2284 	ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2285 	ppd = ppd_from_ibp(ibp);
2286 	if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2287 	      (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2288 	    (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2289 	    (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2290 	    (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2291 	    (rdma_ah_get_make_grd(attr))) {
2292 		rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2293 		rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2294 		rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2295 	}
2296 }
2297 
2298 /*
2299  * hfi1_check_mcast- Check if the given lid is
2300  * in the OPA multicast range.
2301  *
2302  * The LID might either reside in ah.dlid or might be
2303  * in the GRH of the address handle as DGID if extended
2304  * addresses are in use.
2305  */
2306 static inline bool hfi1_check_mcast(u32 lid)
2307 {
2308 	return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2309 		(lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2310 }
2311 
2312 #define opa_get_lid(lid, format)	\
2313 	__opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2314 
2315 /* Convert a lid to a specific lid space */
2316 static inline u32 __opa_get_lid(u32 lid, u8 format)
2317 {
2318 	bool is_mcast = hfi1_check_mcast(lid);
2319 
2320 	switch (format) {
2321 	case OPA_PORT_PACKET_FORMAT_8B:
2322 	case OPA_PORT_PACKET_FORMAT_10B:
2323 		if (is_mcast)
2324 			return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2325 				0xF0000);
2326 		return lid & 0xFFFFF;
2327 	case OPA_PORT_PACKET_FORMAT_16B:
2328 		if (is_mcast)
2329 			return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2330 				0xF00000);
2331 		return lid & 0xFFFFFF;
2332 	case OPA_PORT_PACKET_FORMAT_9B:
2333 		if (is_mcast)
2334 			return (lid -
2335 				opa_get_mcast_base(OPA_MCAST_NR) +
2336 				be16_to_cpu(IB_MULTICAST_LID_BASE));
2337 		else
2338 			return lid & 0xFFFF;
2339 	default:
2340 		return lid;
2341 	}
2342 }
2343 
2344 /* Return true if the given lid is the OPA 16B multicast range */
2345 static inline bool hfi1_is_16B_mcast(u32 lid)
2346 {
2347 	return ((lid >=
2348 		opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2349 		(lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2350 }
2351 
2352 static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2353 {
2354 	const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2355 	u32 dlid = rdma_ah_get_dlid(attr);
2356 
2357 	/* Modify ah_attr.dlid to be in the 32 bit LID space.
2358 	 * This is how the address will be laid out:
2359 	 * Assuming MCAST_NR to be 4,
2360 	 * 32 bit permissive LID = 0xFFFFFFFF
2361 	 * Multicast LID range = 0xFFFFFFFE to 0xF0000000
2362 	 * Unicast LID range = 0xEFFFFFFF to 1
2363 	 * Invalid LID = 0
2364 	 */
2365 	if (ib_is_opa_gid(&grh->dgid))
2366 		dlid = opa_get_lid_from_gid(&grh->dgid);
2367 	else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2368 		 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2369 		 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2370 		dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2371 			opa_get_mcast_base(OPA_MCAST_NR);
2372 	else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2373 		dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2374 
2375 	rdma_ah_set_dlid(attr, dlid);
2376 }
2377 
2378 static inline u8 hfi1_get_packet_type(u32 lid)
2379 {
2380 	/* 9B if lid > 0xF0000000 */
2381 	if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2382 		return HFI1_PKT_TYPE_9B;
2383 
2384 	/* 16B if lid > 0xC000 */
2385 	if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2386 		return HFI1_PKT_TYPE_16B;
2387 
2388 	return HFI1_PKT_TYPE_9B;
2389 }
2390 
2391 static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2392 {
2393 	/*
2394 	 * If there was an incoming 16B packet with permissive
2395 	 * LIDs, OPA GIDs would have been programmed when those
2396 	 * packets were received. A 16B packet will have to
2397 	 * be sent in response to that packet. Return a 16B
2398 	 * header type if that's the case.
2399 	 */
2400 	if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2401 		return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2402 			HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2403 
2404 	/*
2405 	 * Return a 16B header type if either the the destination
2406 	 * or source lid is extended.
2407 	 */
2408 	if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2409 		return HFI1_PKT_TYPE_16B;
2410 
2411 	return hfi1_get_packet_type(lid);
2412 }
2413 
2414 static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2415 				     struct ib_grh *grh, u32 slid,
2416 				     u32 dlid)
2417 {
2418 	struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2419 	struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2420 
2421 	if (!ibp)
2422 		return;
2423 
2424 	grh->hop_limit = 1;
2425 	grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2426 	if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2427 		grh->sgid.global.interface_id =
2428 			OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2429 	else
2430 		grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2431 
2432 	/*
2433 	 * Upper layers (like mad) may compare the dgid in the
2434 	 * wc that is obtained here with the sgid_index in
2435 	 * the wr. Since sgid_index in wr is always 0 for
2436 	 * extended lids, set the dgid here to the default
2437 	 * IB gid.
2438 	 */
2439 	grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2440 	grh->dgid.global.interface_id =
2441 		cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2442 }
2443 
2444 static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2445 {
2446 	return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2447 		     SIZE_OF_LT) & 0x7;
2448 }
2449 
2450 static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2451 				    u16 lrh0, u16 len,
2452 				    u16 dlid, u16 slid)
2453 {
2454 	hdr->lrh[0] = cpu_to_be16(lrh0);
2455 	hdr->lrh[1] = cpu_to_be16(dlid);
2456 	hdr->lrh[2] = cpu_to_be16(len);
2457 	hdr->lrh[3] = cpu_to_be16(slid);
2458 }
2459 
2460 static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2461 				     u32 slid, u32 dlid,
2462 				     u16 len, u16 pkey,
2463 				     bool becn, bool fecn, u8 l4,
2464 				     u8 sc)
2465 {
2466 	u32 lrh0 = 0;
2467 	u32 lrh1 = 0x40000000;
2468 	u32 lrh2 = 0;
2469 	u32 lrh3 = 0;
2470 
2471 	lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2472 	lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2473 	lrh0 = (lrh0 & ~OPA_16B_LID_MASK)  | (slid & OPA_16B_LID_MASK);
2474 	lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2475 	lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2476 	lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2477 	lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2478 		((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2479 	lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2480 		((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2481 	lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
2482 	lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2483 
2484 	hdr->lrh[0] = lrh0;
2485 	hdr->lrh[1] = lrh1;
2486 	hdr->lrh[2] = lrh2;
2487 	hdr->lrh[3] = lrh3;
2488 }
2489 #endif                          /* _HFI1_KERNEL_H */
2490