1 #ifndef _HFI1_KERNEL_H 2 #define _HFI1_KERNEL_H 3 /* 4 * Copyright(c) 2015, 2016 Intel Corporation. 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * - Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * - Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * - Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 * 48 */ 49 50 #include <linux/interrupt.h> 51 #include <linux/pci.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/mutex.h> 54 #include <linux/list.h> 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/io.h> 58 #include <linux/fs.h> 59 #include <linux/completion.h> 60 #include <linux/kref.h> 61 #include <linux/sched.h> 62 #include <linux/cdev.h> 63 #include <linux/delay.h> 64 #include <linux/kthread.h> 65 #include <rdma/rdma_vt.h> 66 67 #include "chip_registers.h" 68 #include "common.h" 69 #include "verbs.h" 70 #include "pio.h" 71 #include "chip.h" 72 #include "mad.h" 73 #include "qsfp.h" 74 #include "platform.h" 75 #include "affinity.h" 76 77 /* bumped 1 from s/w major version of TrueScale */ 78 #define HFI1_CHIP_VERS_MAJ 3U 79 80 /* don't care about this except printing */ 81 #define HFI1_CHIP_VERS_MIN 0U 82 83 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 84 #define HFI1_OUI 0x001175 85 #define HFI1_OUI_LSB 40 86 87 #define DROP_PACKET_OFF 0 88 #define DROP_PACKET_ON 1 89 90 extern unsigned long hfi1_cap_mask; 91 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) 92 #define HFI1_CAP_UGET_MASK(mask, cap) \ 93 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) 94 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap)) 95 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap)) 96 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap)) 97 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap)) 98 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \ 99 HFI1_CAP_MISC_MASK) 100 /* Offline Disabled Reason is 4-bits */ 101 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON) 102 103 /* 104 * Control context is always 0 and handles the error packets. 105 * It also handles the VL15 and multicast packets. 106 */ 107 #define HFI1_CTRL_CTXT 0 108 109 /* 110 * Driver context will store software counters for each of the events 111 * associated with these status registers 112 */ 113 #define NUM_CCE_ERR_STATUS_COUNTERS 41 114 #define NUM_RCV_ERR_STATUS_COUNTERS 64 115 #define NUM_MISC_ERR_STATUS_COUNTERS 13 116 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36 117 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4 118 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64 119 #define NUM_SEND_ERR_STATUS_COUNTERS 3 120 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5 121 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24 122 123 /* 124 * per driver stats, either not device nor port-specific, or 125 * summed over all of the devices and ports. 126 * They are described by name via ipathfs filesystem, so layout 127 * and number of elements can change without breaking compatibility. 128 * If members are added or deleted hfi1_statnames[] in debugfs.c must 129 * change to match. 130 */ 131 struct hfi1_ib_stats { 132 __u64 sps_ints; /* number of interrupts handled */ 133 __u64 sps_errints; /* number of error interrupts */ 134 __u64 sps_txerrs; /* tx-related packet errors */ 135 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 136 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 137 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 138 __u64 sps_ctxts; /* number of contexts currently open */ 139 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 140 __u64 sps_buffull; 141 __u64 sps_hdrfull; 142 }; 143 144 extern struct hfi1_ib_stats hfi1_stats; 145 extern const struct pci_error_handlers hfi1_pci_err_handler; 146 147 /* 148 * First-cut criterion for "device is active" is 149 * two thousand dwords combined Tx, Rx traffic per 150 * 5-second interval. SMA packets are 64 dwords, 151 * and occur "a few per second", presumably each way. 152 */ 153 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000) 154 155 /* 156 * Below contains all data related to a single context (formerly called port). 157 */ 158 159 #ifdef CONFIG_DEBUG_FS 160 struct hfi1_opcode_stats_perctx; 161 #endif 162 163 struct ctxt_eager_bufs { 164 ssize_t size; /* total size of eager buffers */ 165 u32 count; /* size of buffers array */ 166 u32 numbufs; /* number of buffers allocated */ 167 u32 alloced; /* number of rcvarray entries used */ 168 u32 rcvtid_size; /* size of each eager rcv tid */ 169 u32 threshold; /* head update threshold */ 170 struct eager_buffer { 171 void *addr; 172 dma_addr_t phys; 173 ssize_t len; 174 } *buffers; 175 struct { 176 void *addr; 177 dma_addr_t phys; 178 } *rcvtids; 179 }; 180 181 struct exp_tid_set { 182 struct list_head list; 183 u32 count; 184 }; 185 186 struct hfi1_ctxtdata { 187 /* shadow the ctxt's RcvCtrl register */ 188 u64 rcvctrl; 189 /* rcvhdrq base, needs mmap before useful */ 190 void *rcvhdrq; 191 /* kernel virtual address where hdrqtail is updated */ 192 volatile __le64 *rcvhdrtail_kvaddr; 193 /* 194 * Shared page for kernel to signal user processes that send buffers 195 * need disarming. The process should call HFI1_CMD_DISARM_BUFS 196 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 197 */ 198 unsigned long *user_event_mask; 199 /* when waiting for rcv or pioavail */ 200 wait_queue_head_t wait; 201 /* rcvhdrq size (for freeing) */ 202 size_t rcvhdrq_size; 203 /* number of rcvhdrq entries */ 204 u16 rcvhdrq_cnt; 205 /* size of each of the rcvhdrq entries */ 206 u16 rcvhdrqentsize; 207 /* mmap of hdrq, must fit in 44 bits */ 208 dma_addr_t rcvhdrq_phys; 209 dma_addr_t rcvhdrqtailaddr_phys; 210 struct ctxt_eager_bufs egrbufs; 211 /* this receive context's assigned PIO ACK send context */ 212 struct send_context *sc; 213 214 /* dynamic receive available interrupt timeout */ 215 u32 rcvavail_timeout; 216 /* 217 * number of opens (including slave sub-contexts) on this instance 218 * (ignoring forks, dup, etc. for now) 219 */ 220 int cnt; 221 /* 222 * how much space to leave at start of eager TID entries for 223 * protocol use, on each TID 224 */ 225 /* instead of calculating it */ 226 unsigned ctxt; 227 /* non-zero if ctxt is being shared. */ 228 u16 subctxt_cnt; 229 /* non-zero if ctxt is being shared. */ 230 u16 subctxt_id; 231 u8 uuid[16]; 232 /* job key */ 233 u16 jkey; 234 /* number of RcvArray groups for this context. */ 235 u32 rcv_array_groups; 236 /* index of first eager TID entry. */ 237 u32 eager_base; 238 /* number of expected TID entries */ 239 u32 expected_count; 240 /* index of first expected TID entry. */ 241 u32 expected_base; 242 243 struct exp_tid_set tid_group_list; 244 struct exp_tid_set tid_used_list; 245 struct exp_tid_set tid_full_list; 246 247 /* lock protecting all Expected TID data */ 248 struct mutex exp_lock; 249 /* number of pio bufs for this ctxt (all procs, if shared) */ 250 u32 piocnt; 251 /* first pio buffer for this ctxt */ 252 u32 pio_base; 253 /* chip offset of PIO buffers for this ctxt */ 254 u32 piobufs; 255 /* per-context configuration flags */ 256 u32 flags; 257 /* per-context event flags for fileops/intr communication */ 258 unsigned long event_flags; 259 /* WAIT_RCV that timed out, no interrupt */ 260 u32 rcvwait_to; 261 /* WAIT_PIO that timed out, no interrupt */ 262 u32 piowait_to; 263 /* WAIT_RCV already happened, no wait */ 264 u32 rcvnowait; 265 /* WAIT_PIO already happened, no wait */ 266 u32 pionowait; 267 /* total number of polled urgent packets */ 268 u32 urgent; 269 /* saved total number of polled urgent packets for poll edge trigger */ 270 u32 urgent_poll; 271 /* pid of process using this ctxt */ 272 pid_t pid; 273 pid_t subpid[HFI1_MAX_SHARED_CTXTS]; 274 /* same size as task_struct .comm[], command that opened context */ 275 char comm[TASK_COMM_LEN]; 276 /* so file ops can get at unit */ 277 struct hfi1_devdata *dd; 278 /* so functions that need physical port can get it easily */ 279 struct hfi1_pportdata *ppd; 280 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 281 void *subctxt_uregbase; 282 /* An array of pages for the eager receive buffers * N */ 283 void *subctxt_rcvegrbuf; 284 /* An array of pages for the eager header queue entries * N */ 285 void *subctxt_rcvhdr_base; 286 /* The version of the library which opened this ctxt */ 287 u32 userversion; 288 /* Bitmask of active slaves */ 289 u32 active_slaves; 290 /* Type of packets or conditions we want to poll for */ 291 u16 poll_type; 292 /* receive packet sequence counter */ 293 u8 seq_cnt; 294 u8 redirect_seq_cnt; 295 /* ctxt rcvhdrq head offset */ 296 u32 head; 297 u32 pkt_count; 298 /* QPs waiting for context processing */ 299 struct list_head qp_wait_list; 300 /* interrupt handling */ 301 u64 imask; /* clear interrupt mask */ 302 int ireg; /* clear interrupt register */ 303 unsigned numa_id; /* numa node of this context */ 304 /* verbs stats per CTX */ 305 struct hfi1_opcode_stats_perctx *opstats; 306 /* 307 * This is the kernel thread that will keep making 308 * progress on the user sdma requests behind the scenes. 309 * There is one per context (shared contexts use the master's). 310 */ 311 struct task_struct *progress; 312 struct list_head sdma_queues; 313 /* protect sdma queues */ 314 spinlock_t sdma_qlock; 315 316 /* Is ASPM interrupt supported for this context */ 317 bool aspm_intr_supported; 318 /* ASPM state (enabled/disabled) for this context */ 319 bool aspm_enabled; 320 /* Timer for re-enabling ASPM if interrupt activity quietens down */ 321 struct timer_list aspm_timer; 322 /* Lock to serialize between intr, timer intr and user threads */ 323 spinlock_t aspm_lock; 324 /* Is ASPM processing enabled for this context (in intr context) */ 325 bool aspm_intr_enable; 326 /* Last interrupt timestamp */ 327 ktime_t aspm_ts_last_intr; 328 /* Last timestamp at which we scheduled a timer for this context */ 329 ktime_t aspm_ts_timer_sched; 330 331 /* 332 * The interrupt handler for a particular receive context can vary 333 * throughout it's lifetime. This is not a lock protected data member so 334 * it must be updated atomically and the prev and new value must always 335 * be valid. Worst case is we process an extra interrupt and up to 64 336 * packets with the wrong interrupt handler. 337 */ 338 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded); 339 }; 340 341 /* 342 * Represents a single packet at a high level. Put commonly computed things in 343 * here so we do not have to keep doing them over and over. The rule of thumb is 344 * if something is used one time to derive some value, store that something in 345 * here. If it is used multiple times, then store the result of that derivation 346 * in here. 347 */ 348 struct hfi1_packet { 349 void *ebuf; 350 void *hdr; 351 struct hfi1_ctxtdata *rcd; 352 __le32 *rhf_addr; 353 struct rvt_qp *qp; 354 struct hfi1_other_headers *ohdr; 355 u64 rhf; 356 u32 maxcnt; 357 u32 rhqoff; 358 u32 hdrqtail; 359 int numpkt; 360 u16 tlen; 361 u16 hlen; 362 s16 etail; 363 u16 rsize; 364 u8 updegr; 365 u8 rcv_flags; 366 u8 etype; 367 }; 368 369 static inline bool has_sc4_bit(struct hfi1_packet *p) 370 { 371 return !!rhf_dc_info(p->rhf); 372 } 373 374 /* 375 * Private data for snoop/capture support. 376 */ 377 struct hfi1_snoop_data { 378 int mode_flag; 379 struct cdev cdev; 380 struct device *class_dev; 381 /* protect snoop data */ 382 spinlock_t snoop_lock; 383 struct list_head queue; 384 wait_queue_head_t waitq; 385 void *filter_value; 386 int (*filter_callback)(void *hdr, void *data, void *value); 387 u64 dcc_cfg; /* saved value of DCC Cfg register */ 388 }; 389 390 /* snoop mode_flag values */ 391 #define HFI1_PORT_SNOOP_MODE 1U 392 #define HFI1_PORT_CAPTURE_MODE 2U 393 394 struct rvt_sge_state; 395 396 /* 397 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 398 * Mostly for MADs that set or query link parameters, also ipath 399 * config interfaces 400 */ 401 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 402 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */ 403 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 404 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */ 405 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 406 #define HFI1_IB_CFG_SPD 5 /* current Link spd */ 407 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 408 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 409 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 410 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 411 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */ 412 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 413 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 414 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 415 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 416 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 417 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */ 418 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */ 419 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19 420 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 421 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */ 422 423 /* 424 * HFI or Host Link States 425 * 426 * These describe the states the driver thinks the logical and physical 427 * states are in. Used as an argument to set_link_state(). Implemented 428 * as bits for easy multi-state checking. The actual state can only be 429 * one. 430 */ 431 #define __HLS_UP_INIT_BP 0 432 #define __HLS_UP_ARMED_BP 1 433 #define __HLS_UP_ACTIVE_BP 2 434 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */ 435 #define __HLS_DN_POLL_BP 4 436 #define __HLS_DN_DISABLE_BP 5 437 #define __HLS_DN_OFFLINE_BP 6 438 #define __HLS_VERIFY_CAP_BP 7 439 #define __HLS_GOING_UP_BP 8 440 #define __HLS_GOING_OFFLINE_BP 9 441 #define __HLS_LINK_COOLDOWN_BP 10 442 443 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) 444 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) 445 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) 446 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ 447 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) 448 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) 449 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) 450 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) 451 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) 452 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) 453 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) 454 455 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) 456 #define HLS_DOWN ~(HLS_UP) 457 458 /* use this MTU size if none other is given */ 459 #define HFI1_DEFAULT_ACTIVE_MTU 10240 460 /* use this MTU size as the default maximum */ 461 #define HFI1_DEFAULT_MAX_MTU 10240 462 /* default partition key */ 463 #define DEFAULT_PKEY 0xffff 464 465 /* 466 * Possible fabric manager config parameters for fm_{get,set}_table() 467 */ 468 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */ 469 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */ 470 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */ 471 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */ 472 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */ 473 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */ 474 475 /* 476 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 477 * these are bits so they can be combined, e.g. 478 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB 479 */ 480 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01 481 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02 482 #define HFI1_RCVCTRL_CTXT_ENB 0x04 483 #define HFI1_RCVCTRL_CTXT_DIS 0x08 484 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10 485 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20 486 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 487 #define HFI1_RCVCTRL_PKEY_DIS 0x80 488 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400 489 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800 490 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000 491 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000 492 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000 493 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000 494 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000 495 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000 496 497 /* partition enforcement flags */ 498 #define HFI1_PART_ENFORCE_IN 0x1 499 #define HFI1_PART_ENFORCE_OUT 0x2 500 501 /* how often we check for synthetic counter wrap around */ 502 #define SYNTH_CNT_TIME 2 503 504 /* Counter flags */ 505 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */ 506 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */ 507 #define CNTR_DISABLED 0x2 /* Disable this counter */ 508 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */ 509 #define CNTR_VL 0x8 /* Per VL counter */ 510 #define CNTR_SDMA 0x10 511 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */ 512 #define CNTR_MODE_W 0x0 513 #define CNTR_MODE_R 0x1 514 515 /* VLs Supported/Operational */ 516 #define HFI1_MIN_VLS_SUPPORTED 1 517 #define HFI1_MAX_VLS_SUPPORTED 8 518 519 static inline void incr_cntr64(u64 *cntr) 520 { 521 if (*cntr < (u64)-1LL) 522 (*cntr)++; 523 } 524 525 static inline void incr_cntr32(u32 *cntr) 526 { 527 if (*cntr < (u32)-1LL) 528 (*cntr)++; 529 } 530 531 #define MAX_NAME_SIZE 64 532 struct hfi1_msix_entry { 533 enum irq_type type; 534 struct msix_entry msix; 535 void *arg; 536 char name[MAX_NAME_SIZE]; 537 cpumask_t mask; 538 }; 539 540 /* per-SL CCA information */ 541 struct cca_timer { 542 struct hrtimer hrtimer; 543 struct hfi1_pportdata *ppd; /* read-only */ 544 int sl; /* read-only */ 545 u16 ccti; /* read/write - current value of CCTI */ 546 }; 547 548 struct link_down_reason { 549 /* 550 * SMA-facing value. Should be set from .latest when 551 * HLS_UP_* -> HLS_DN_* transition actually occurs. 552 */ 553 u8 sma; 554 u8 latest; 555 }; 556 557 enum { 558 LO_PRIO_TABLE, 559 HI_PRIO_TABLE, 560 MAX_PRIO_TABLE 561 }; 562 563 struct vl_arb_cache { 564 /* protect vl arb cache */ 565 spinlock_t lock; 566 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE]; 567 }; 568 569 /* 570 * The structure below encapsulates data relevant to a physical IB Port. 571 * Current chips support only one such port, but the separation 572 * clarifies things a bit. Note that to conform to IB conventions, 573 * port-numbers are one-based. The first or only port is port1. 574 */ 575 struct hfi1_pportdata { 576 struct hfi1_ibport ibport_data; 577 578 struct hfi1_devdata *dd; 579 struct kobject pport_cc_kobj; 580 struct kobject sc2vl_kobj; 581 struct kobject sl2sc_kobj; 582 struct kobject vl2mtu_kobj; 583 584 /* PHY support */ 585 u32 port_type; 586 struct qsfp_data qsfp_info; 587 588 /* GUID for this interface, in host order */ 589 u64 guid; 590 /* GUID for peer interface, in host order */ 591 u64 neighbor_guid; 592 593 /* up or down physical link state */ 594 u32 linkup; 595 596 /* 597 * this address is mapped read-only into user processes so they can 598 * get status cheaply, whenever they want. One qword of status per port 599 */ 600 u64 *statusp; 601 602 /* SendDMA related entries */ 603 604 struct workqueue_struct *hfi1_wq; 605 606 /* move out of interrupt context */ 607 struct work_struct link_vc_work; 608 struct work_struct link_up_work; 609 struct work_struct link_down_work; 610 struct work_struct sma_message_work; 611 struct work_struct freeze_work; 612 struct work_struct link_downgrade_work; 613 struct work_struct link_bounce_work; 614 /* host link state variables */ 615 struct mutex hls_lock; 616 u32 host_link_state; 617 618 spinlock_t sdma_alllock ____cacheline_aligned_in_smp; 619 620 u32 lstate; /* logical link state */ 621 622 /* these are the "32 bit" regs */ 623 624 u32 ibmtu; /* The MTU programmed for this unit */ 625 /* 626 * Current max size IB packet (in bytes) including IB headers, that 627 * we can send. Changes when ibmtu changes. 628 */ 629 u32 ibmaxlen; 630 u32 current_egress_rate; /* units [10^6 bits/sec] */ 631 /* LID programmed for this instance */ 632 u16 lid; 633 /* list of pkeys programmed; 0 if not set */ 634 u16 pkeys[MAX_PKEY_VALUES]; 635 u16 link_width_supported; 636 u16 link_width_downgrade_supported; 637 u16 link_speed_supported; 638 u16 link_width_enabled; 639 u16 link_width_downgrade_enabled; 640 u16 link_speed_enabled; 641 u16 link_width_active; 642 u16 link_width_downgrade_tx_active; 643 u16 link_width_downgrade_rx_active; 644 u16 link_speed_active; 645 u8 vls_supported; 646 u8 vls_operational; 647 u8 actual_vls_operational; 648 /* LID mask control */ 649 u8 lmc; 650 /* Rx Polarity inversion (compensate for ~tx on partner) */ 651 u8 rx_pol_inv; 652 653 u8 hw_pidx; /* physical port index */ 654 u8 port; /* IB port number and index into dd->pports - 1 */ 655 /* type of neighbor node */ 656 u8 neighbor_type; 657 u8 neighbor_normal; 658 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */ 659 u8 neighbor_port_number; 660 u8 is_sm_config_started; 661 u8 offline_disabled_reason; 662 u8 is_active_optimize_enabled; 663 u8 driver_link_ready; /* driver ready for active link */ 664 u8 link_enabled; /* link enabled? */ 665 u8 linkinit_reason; 666 u8 local_tx_rate; /* rate given to 8051 firmware */ 667 u8 last_pstate; /* info only */ 668 669 /* placeholders for IB MAD packet settings */ 670 u8 overrun_threshold; 671 u8 phy_error_threshold; 672 673 /* Used to override LED behavior for things like maintenance beaconing*/ 674 /* 675 * Alternates per phase of blink 676 * [0] holds LED off duration, [1] holds LED on duration 677 */ 678 unsigned long led_override_vals[2]; 679 u8 led_override_phase; /* LSB picks from vals[] */ 680 atomic_t led_override_timer_active; 681 /* Used to flash LEDs in override mode */ 682 struct timer_list led_override_timer; 683 684 u32 sm_trap_qp; 685 u32 sa_qp; 686 687 /* 688 * cca_timer_lock protects access to the per-SL cca_timer 689 * structures (specifically the ccti member). 690 */ 691 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp; 692 struct cca_timer cca_timer[OPA_MAX_SLS]; 693 694 /* List of congestion control table entries */ 695 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX]; 696 697 /* congestion entries, each entry corresponding to a SL */ 698 struct opa_congestion_setting_entry_shadow 699 congestion_entries[OPA_MAX_SLS]; 700 701 /* 702 * cc_state_lock protects (write) access to the per-port 703 * struct cc_state. 704 */ 705 spinlock_t cc_state_lock ____cacheline_aligned_in_smp; 706 707 struct cc_state __rcu *cc_state; 708 709 /* Total number of congestion control table entries */ 710 u16 total_cct_entry; 711 712 /* Bit map identifying service level */ 713 u32 cc_sl_control_map; 714 715 /* CA's max number of 64 entry units in the congestion control table */ 716 u8 cc_max_table_entries; 717 718 /* 719 * begin congestion log related entries 720 * cc_log_lock protects all congestion log related data 721 */ 722 spinlock_t cc_log_lock ____cacheline_aligned_in_smp; 723 u8 threshold_cong_event_map[OPA_MAX_SLS / 8]; 724 u16 threshold_event_counter; 725 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS]; 726 int cc_log_idx; /* index for logging events */ 727 int cc_mad_idx; /* index for reporting events */ 728 /* end congestion log related entries */ 729 730 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE]; 731 732 /* port relative counter buffer */ 733 u64 *cntrs; 734 /* port relative synthetic counter buffer */ 735 u64 *scntrs; 736 /* port_xmit_discards are synthesized from different egress errors */ 737 u64 port_xmit_discards; 738 u64 port_xmit_discards_vl[C_VL_COUNT]; 739 u64 port_xmit_constraint_errors; 740 u64 port_rcv_constraint_errors; 741 /* count of 'link_err' interrupts from DC */ 742 u64 link_downed; 743 /* number of times link retrained successfully */ 744 u64 link_up; 745 /* number of times a link unknown frame was reported */ 746 u64 unknown_frame_count; 747 /* port_ltp_crc_mode is returned in 'portinfo' MADs */ 748 u16 port_ltp_crc_mode; 749 /* port_crc_mode_enabled is the crc we support */ 750 u8 port_crc_mode_enabled; 751 /* mgmt_allowed is also returned in 'portinfo' MADs */ 752 u8 mgmt_allowed; 753 u8 part_enforce; /* partition enforcement flags */ 754 struct link_down_reason local_link_down_reason; 755 struct link_down_reason neigh_link_down_reason; 756 /* Value to be sent to link peer on LinkDown .*/ 757 u8 remote_link_down_reason; 758 /* Error events that will cause a port bounce. */ 759 u32 port_error_action; 760 struct work_struct linkstate_active_work; 761 /* Does this port need to prescan for FECNs */ 762 bool cc_prescan; 763 }; 764 765 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet); 766 767 typedef void (*opcode_handler)(struct hfi1_packet *packet); 768 769 /* return values for the RHF receive functions */ 770 #define RHF_RCV_CONTINUE 0 /* keep going */ 771 #define RHF_RCV_DONE 1 /* stop, this packet processed */ 772 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */ 773 774 struct rcv_array_data { 775 u8 group_size; 776 u16 ngroups; 777 u16 nctxt_extra; 778 }; 779 780 struct per_vl_data { 781 u16 mtu; 782 struct send_context *sc; 783 }; 784 785 /* 16 to directly index */ 786 #define PER_VL_SEND_CONTEXTS 16 787 788 struct err_info_rcvport { 789 u8 status_and_code; 790 u64 packet_flit1; 791 u64 packet_flit2; 792 }; 793 794 struct err_info_constraint { 795 u8 status; 796 u16 pkey; 797 u32 slid; 798 }; 799 800 struct hfi1_temp { 801 unsigned int curr; /* current temperature */ 802 unsigned int lo_lim; /* low temperature limit */ 803 unsigned int hi_lim; /* high temperature limit */ 804 unsigned int crit_lim; /* critical temperature limit */ 805 u8 triggers; /* temperature triggers */ 806 }; 807 808 /* common data between shared ASIC HFIs */ 809 struct hfi1_asic_data { 810 struct hfi1_devdata *dds[2]; /* back pointers */ 811 struct mutex asic_resource_mutex; 812 }; 813 814 /* device data struct now contains only "general per-device" info. 815 * fields related to a physical IB port are in a hfi1_pportdata struct. 816 */ 817 struct sdma_engine; 818 struct sdma_vl_map; 819 820 #define BOARD_VERS_MAX 96 /* how long the version string can be */ 821 #define SERIAL_MAX 16 /* length of the serial number */ 822 823 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64); 824 struct hfi1_devdata { 825 struct hfi1_ibdev verbs_dev; /* must be first */ 826 struct list_head list; 827 /* pointers to related structs for this device */ 828 /* pci access data structure */ 829 struct pci_dev *pcidev; 830 struct cdev user_cdev; 831 struct cdev diag_cdev; 832 struct cdev ui_cdev; 833 struct device *user_device; 834 struct device *diag_device; 835 struct device *ui_device; 836 837 /* mem-mapped pointer to base of chip regs */ 838 u8 __iomem *kregbase; 839 /* end of mem-mapped chip space excluding sendbuf and user regs */ 840 u8 __iomem *kregend; 841 /* physical address of chip for io_remap, etc. */ 842 resource_size_t physaddr; 843 /* receive context data */ 844 struct hfi1_ctxtdata **rcd; 845 /* send context data */ 846 struct send_context_info *send_contexts; 847 /* map hardware send contexts to software index */ 848 u8 *hw_to_sw; 849 /* spinlock for allocating and releasing send context resources */ 850 spinlock_t sc_lock; 851 /* Per VL data. Enough for all VLs but not all elements are set/used. */ 852 struct per_vl_data vld[PER_VL_SEND_CONTEXTS]; 853 /* lock for pio_map */ 854 spinlock_t pio_map_lock; 855 /* array of kernel send contexts */ 856 struct send_context **kernel_send_context; 857 /* array of vl maps */ 858 struct pio_vl_map __rcu *pio_map; 859 /* seqlock for sc2vl */ 860 seqlock_t sc2vl_lock; 861 u64 sc2vl[4]; 862 /* Send Context initialization lock. */ 863 spinlock_t sc_init_lock; 864 865 /* fields common to all SDMA engines */ 866 867 /* default flags to last descriptor */ 868 u64 default_desc1; 869 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ 870 dma_addr_t sdma_heads_phys; 871 void *sdma_pad_dma; /* DMA'ed by chip */ 872 dma_addr_t sdma_pad_phys; 873 /* for deallocation */ 874 size_t sdma_heads_size; 875 /* number from the chip */ 876 u32 chip_sdma_engines; 877 /* num used */ 878 u32 num_sdma; 879 /* lock for sdma_map */ 880 spinlock_t sde_map_lock; 881 /* array of engines sized by num_sdma */ 882 struct sdma_engine *per_sdma; 883 /* array of vl maps */ 884 struct sdma_vl_map __rcu *sdma_map; 885 /* SPC freeze waitqueue and variable */ 886 wait_queue_head_t sdma_unfreeze_wq; 887 atomic_t sdma_unfreeze_count; 888 889 /* common data between shared ASIC HFIs in this OS */ 890 struct hfi1_asic_data *asic_data; 891 892 /* hfi1_pportdata, points to array of (physical) port-specific 893 * data structs, indexed by pidx (0..n-1) 894 */ 895 struct hfi1_pportdata *pport; 896 897 /* mem-mapped pointer to base of PIO buffers */ 898 void __iomem *piobase; 899 /* 900 * write-combining mem-mapped pointer to base of RcvArray 901 * memory. 902 */ 903 void __iomem *rcvarray_wc; 904 /* 905 * credit return base - a per-NUMA range of DMA address that 906 * the chip will use to update the per-context free counter 907 */ 908 struct credit_return_base *cr_base; 909 910 /* send context numbers and sizes for each type */ 911 struct sc_config_sizes sc_sizes[SC_MAX]; 912 913 u32 lcb_access_count; /* count of LCB users */ 914 915 char *boardname; /* human readable board info */ 916 917 /* device (not port) flags, basically device capabilities */ 918 u32 flags; 919 920 /* reset value */ 921 u64 z_int_counter; 922 u64 z_rcv_limit; 923 u64 z_send_schedule; 924 /* percpu int_counter */ 925 u64 __percpu *int_counter; 926 u64 __percpu *rcv_limit; 927 u64 __percpu *send_schedule; 928 /* number of receive contexts in use by the driver */ 929 u32 num_rcv_contexts; 930 /* number of pio send contexts in use by the driver */ 931 u32 num_send_contexts; 932 /* 933 * number of ctxts available for PSM open 934 */ 935 u32 freectxts; 936 /* total number of available user/PSM contexts */ 937 u32 num_user_contexts; 938 /* base receive interrupt timeout, in CSR units */ 939 u32 rcv_intr_timeout_csr; 940 941 u64 __iomem *egrtidbase; 942 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ 943 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ 944 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 945 spinlock_t uctxt_lock; /* rcd and user context changes */ 946 /* exclusive access to 8051 */ 947 spinlock_t dc8051_lock; 948 /* exclusive access to 8051 memory */ 949 spinlock_t dc8051_memlock; 950 int dc8051_timed_out; /* remember if the 8051 timed out */ 951 /* 952 * A page that will hold event notification bitmaps for all 953 * contexts. This page will be mapped into all processes. 954 */ 955 unsigned long *events; 956 /* 957 * per unit status, see also portdata statusp 958 * mapped read-only into user processes so they can get unit and 959 * IB link status cheaply 960 */ 961 struct hfi1_status *status; 962 u32 freezelen; /* max length of freezemsg */ 963 964 /* revision register shadow */ 965 u64 revision; 966 /* Base GUID for device (network order) */ 967 u64 base_guid; 968 969 /* these are the "32 bit" regs */ 970 971 /* value we put in kr_rcvhdrsize */ 972 u32 rcvhdrsize; 973 /* number of receive contexts the chip supports */ 974 u32 chip_rcv_contexts; 975 /* number of receive array entries */ 976 u32 chip_rcv_array_count; 977 /* number of PIO send contexts the chip supports */ 978 u32 chip_send_contexts; 979 /* number of bytes in the PIO memory buffer */ 980 u32 chip_pio_mem_size; 981 /* number of bytes in the SDMA memory buffer */ 982 u32 chip_sdma_mem_size; 983 984 /* size of each rcvegrbuffer */ 985 u32 rcvegrbufsize; 986 /* log2 of above */ 987 u16 rcvegrbufsize_shift; 988 /* both sides of the PCIe link are gen3 capable */ 989 u8 link_gen3_capable; 990 /* localbus width (1, 2,4,8,16,32) from config space */ 991 u32 lbus_width; 992 /* localbus speed in MHz */ 993 u32 lbus_speed; 994 int unit; /* unit # of this chip */ 995 int node; /* home node of this chip */ 996 997 /* save these PCI fields to restore after a reset */ 998 u32 pcibar0; 999 u32 pcibar1; 1000 u32 pci_rom; 1001 u16 pci_command; 1002 u16 pcie_devctl; 1003 u16 pcie_lnkctl; 1004 u16 pcie_devctl2; 1005 u32 pci_msix0; 1006 u32 pci_lnkctl3; 1007 u32 pci_tph2; 1008 1009 /* 1010 * ASCII serial number, from flash, large enough for original 1011 * all digit strings, and longer serial number format 1012 */ 1013 u8 serial[SERIAL_MAX]; 1014 /* human readable board version */ 1015 u8 boardversion[BOARD_VERS_MAX]; 1016 u8 lbus_info[32]; /* human readable localbus info */ 1017 /* chip major rev, from CceRevision */ 1018 u8 majrev; 1019 /* chip minor rev, from CceRevision */ 1020 u8 minrev; 1021 /* hardware ID */ 1022 u8 hfi1_id; 1023 /* implementation code */ 1024 u8 icode; 1025 /* default link down value (poll/sleep) */ 1026 u8 link_default; 1027 /* vAU of this device */ 1028 u8 vau; 1029 /* vCU of this device */ 1030 u8 vcu; 1031 /* link credits of this device */ 1032 u16 link_credits; 1033 /* initial vl15 credits to use */ 1034 u16 vl15_init; 1035 1036 /* Misc small ints */ 1037 /* Number of physical ports available */ 1038 u8 num_pports; 1039 /* Lowest context number which can be used by user processes */ 1040 u8 first_user_ctxt; 1041 u8 n_krcv_queues; 1042 u8 qos_shift; 1043 u8 qpn_mask; 1044 1045 u16 rhf_offset; /* offset of RHF within receive header entry */ 1046 u16 irev; /* implementation revision */ 1047 u16 dc8051_ver; /* 8051 firmware version */ 1048 1049 struct platform_config platform_config; 1050 struct platform_config_cache pcfg_cache; 1051 1052 struct diag_client *diag_client; 1053 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */ 1054 1055 u8 psxmitwait_supported; 1056 /* cycle length of PS* counters in HW (in picoseconds) */ 1057 u16 psxmitwait_check_rate; 1058 /* high volume overflow errors deferred to tasklet */ 1059 struct tasklet_struct error_tasklet; 1060 1061 /* MSI-X information */ 1062 struct hfi1_msix_entry *msix_entries; 1063 u32 num_msix_entries; 1064 1065 /* INTx information */ 1066 u32 requested_intx_irq; /* did we request one? */ 1067 char intx_name[MAX_NAME_SIZE]; /* INTx name */ 1068 1069 /* general interrupt: mask of handled interrupts */ 1070 u64 gi_mask[CCE_NUM_INT_CSRS]; 1071 1072 struct rcv_array_data rcv_entries; 1073 1074 /* 1075 * 64 bit synthetic counters 1076 */ 1077 struct timer_list synth_stats_timer; 1078 1079 /* 1080 * device counters 1081 */ 1082 char *cntrnames; 1083 size_t cntrnameslen; 1084 size_t ndevcntrs; 1085 u64 *cntrs; 1086 u64 *scntrs; 1087 1088 /* 1089 * remembered values for synthetic counters 1090 */ 1091 u64 last_tx; 1092 u64 last_rx; 1093 1094 /* 1095 * per-port counters 1096 */ 1097 size_t nportcntrs; 1098 char *portcntrnames; 1099 size_t portcntrnameslen; 1100 1101 struct hfi1_snoop_data hfi1_snoop; 1102 1103 struct err_info_rcvport err_info_rcvport; 1104 struct err_info_constraint err_info_rcv_constraint; 1105 struct err_info_constraint err_info_xmit_constraint; 1106 u8 err_info_uncorrectable; 1107 u8 err_info_fmconfig; 1108 1109 atomic_t drop_packet; 1110 u8 do_drop; 1111 1112 /* 1113 * Software counters for the status bits defined by the 1114 * associated error status registers 1115 */ 1116 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS]; 1117 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS]; 1118 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS]; 1119 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS]; 1120 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS]; 1121 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS]; 1122 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS]; 1123 1124 /* Software counter that spans all contexts */ 1125 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS]; 1126 /* Software counter that spans all DMA engines */ 1127 u64 sw_send_dma_eng_err_status_cnt[ 1128 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS]; 1129 /* Software counter that aggregates all cce_err_status errors */ 1130 u64 sw_cce_err_status_aggregate; 1131 1132 /* receive interrupt functions */ 1133 rhf_rcv_function_ptr *rhf_rcv_function_map; 1134 rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; 1135 1136 /* 1137 * Handlers for outgoing data so that snoop/capture does not 1138 * have to have its hooks in the send path 1139 */ 1140 send_routine process_pio_send; 1141 send_routine process_dma_send; 1142 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1143 u64 pbc, const void *from, size_t count); 1144 1145 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ 1146 u8 oui1; 1147 u8 oui2; 1148 u8 oui3; 1149 /* Timer and counter used to detect RcvBufOvflCnt changes */ 1150 struct timer_list rcverr_timer; 1151 u32 rcv_ovfl_cnt; 1152 1153 wait_queue_head_t event_queue; 1154 1155 /* Save the enabled LCB error bits */ 1156 u64 lcb_err_en; 1157 u8 dc_shutdown; 1158 1159 /* receive context tail dummy address */ 1160 __le64 *rcvhdrtail_dummy_kvaddr; 1161 dma_addr_t rcvhdrtail_dummy_physaddr; 1162 1163 bool eprom_available; /* true if EPROM is available for this device */ 1164 bool aspm_supported; /* Does HW support ASPM */ 1165 bool aspm_enabled; /* ASPM state: enabled/disabled */ 1166 /* Serialize ASPM enable/disable between multiple verbs contexts */ 1167 spinlock_t aspm_lock; 1168 /* Number of verbs contexts which have disabled ASPM */ 1169 atomic_t aspm_disabled_cnt; 1170 1171 struct hfi1_affinity *affinity; 1172 struct kobject kobj; 1173 }; 1174 1175 /* 8051 firmware version helper */ 1176 #define dc8051_ver(a, b) ((a) << 8 | (b)) 1177 1178 /* f_put_tid types */ 1179 #define PT_EXPECTED 0 1180 #define PT_EAGER 1 1181 #define PT_INVALID 2 1182 1183 struct tid_rb_node; 1184 struct mmu_rb_node; 1185 1186 /* Private data for file operations */ 1187 struct hfi1_filedata { 1188 struct hfi1_ctxtdata *uctxt; 1189 unsigned subctxt; 1190 struct hfi1_user_sdma_comp_q *cq; 1191 struct hfi1_user_sdma_pkt_q *pq; 1192 /* for cpu affinity; -1 if none */ 1193 int rec_cpu_num; 1194 u32 tid_n_pinned; 1195 struct rb_root tid_rb_root; 1196 struct tid_rb_node **entry_to_rb; 1197 spinlock_t tid_lock; /* protect tid_[limit,used] counters */ 1198 u32 tid_limit; 1199 u32 tid_used; 1200 u32 *invalid_tids; 1201 u32 invalid_tid_idx; 1202 /* protect invalid_tids array and invalid_tid_idx */ 1203 spinlock_t invalid_lock; 1204 }; 1205 1206 extern struct list_head hfi1_dev_list; 1207 extern spinlock_t hfi1_devs_lock; 1208 struct hfi1_devdata *hfi1_lookup(int unit); 1209 extern u32 hfi1_cpulist_count; 1210 extern unsigned long *hfi1_cpulist; 1211 1212 extern unsigned int snoop_drop_send; 1213 extern unsigned int snoop_force_capture; 1214 int hfi1_init(struct hfi1_devdata *, int); 1215 int hfi1_count_units(int *npresentp, int *nupp); 1216 int hfi1_count_active_units(void); 1217 1218 int hfi1_diag_add(struct hfi1_devdata *); 1219 void hfi1_diag_remove(struct hfi1_devdata *); 1220 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup); 1221 1222 void handle_user_interrupt(struct hfi1_ctxtdata *rcd); 1223 1224 int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *); 1225 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *); 1226 int hfi1_create_ctxts(struct hfi1_devdata *dd); 1227 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32, int); 1228 void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *, 1229 struct hfi1_devdata *, u8, u8); 1230 void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *); 1231 1232 int handle_receive_interrupt(struct hfi1_ctxtdata *, int); 1233 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int); 1234 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int); 1235 void set_all_slowpath(struct hfi1_devdata *dd); 1236 1237 /* receive packet handler dispositions */ 1238 #define RCV_PKT_OK 0x0 /* keep going */ 1239 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */ 1240 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */ 1241 1242 /* calculate the current RHF address */ 1243 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd) 1244 { 1245 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset; 1246 } 1247 1248 int hfi1_reset_device(int); 1249 1250 /* return the driver's idea of the logical OPA port state */ 1251 static inline u32 driver_lstate(struct hfi1_pportdata *ppd) 1252 { 1253 return ppd->lstate; /* use the cached value */ 1254 } 1255 1256 void receive_interrupt_work(struct work_struct *work); 1257 1258 /* extract service channel from header and rhf */ 1259 static inline int hdr2sc(struct hfi1_message_header *hdr, u64 rhf) 1260 { 1261 return ((be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf) | 1262 ((!!(rhf & RHF_DC_INFO_SMASK)) << 4); 1263 } 1264 1265 static inline u16 generate_jkey(kuid_t uid) 1266 { 1267 return from_kuid(current_user_ns(), uid) & 0xffff; 1268 } 1269 1270 /* 1271 * active_egress_rate 1272 * 1273 * returns the active egress rate in units of [10^6 bits/sec] 1274 */ 1275 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd) 1276 { 1277 u16 link_speed = ppd->link_speed_active; 1278 u16 link_width = ppd->link_width_active; 1279 u32 egress_rate; 1280 1281 if (link_speed == OPA_LINK_SPEED_25G) 1282 egress_rate = 25000; 1283 else /* assume OPA_LINK_SPEED_12_5G */ 1284 egress_rate = 12500; 1285 1286 switch (link_width) { 1287 case OPA_LINK_WIDTH_4X: 1288 egress_rate *= 4; 1289 break; 1290 case OPA_LINK_WIDTH_3X: 1291 egress_rate *= 3; 1292 break; 1293 case OPA_LINK_WIDTH_2X: 1294 egress_rate *= 2; 1295 break; 1296 default: 1297 /* assume IB_WIDTH_1X */ 1298 break; 1299 } 1300 1301 return egress_rate; 1302 } 1303 1304 /* 1305 * egress_cycles 1306 * 1307 * Returns the number of 'fabric clock cycles' to egress a packet 1308 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock 1309 * rate is (approximately) 805 MHz, the units of the returned value 1310 * are (1/805 MHz). 1311 */ 1312 static inline u32 egress_cycles(u32 len, u32 rate) 1313 { 1314 u32 cycles; 1315 1316 /* 1317 * cycles is: 1318 * 1319 * (length) [bits] / (rate) [bits/sec] 1320 * --------------------------------------------------- 1321 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec] 1322 */ 1323 1324 cycles = len * 8; /* bits */ 1325 cycles *= 805; 1326 cycles /= rate; 1327 1328 return cycles; 1329 } 1330 1331 void set_link_ipg(struct hfi1_pportdata *ppd); 1332 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn, 1333 u32 rqpn, u8 svc_type); 1334 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn, 1335 u32 pkey, u32 slid, u32 dlid, u8 sc5, 1336 const struct ib_grh *old_grh); 1337 #define PKEY_CHECK_INVALID -1 1338 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth, 1339 u8 sc5, int8_t s_pkey_index); 1340 1341 #define PACKET_EGRESS_TIMEOUT 350 1342 static inline void pause_for_credit_return(struct hfi1_devdata *dd) 1343 { 1344 /* Pause at least 1us, to ensure chip returns all credits */ 1345 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000; 1346 1347 udelay(usec ? usec : 1); 1348 } 1349 1350 /** 1351 * sc_to_vlt() reverse lookup sc to vl 1352 * @dd - devdata 1353 * @sc5 - 5 bit sc 1354 */ 1355 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5) 1356 { 1357 unsigned seq; 1358 u8 rval; 1359 1360 if (sc5 >= OPA_MAX_SCS) 1361 return (u8)(0xff); 1362 1363 do { 1364 seq = read_seqbegin(&dd->sc2vl_lock); 1365 rval = *(((u8 *)dd->sc2vl) + sc5); 1366 } while (read_seqretry(&dd->sc2vl_lock, seq)); 1367 1368 return rval; 1369 } 1370 1371 #define PKEY_MEMBER_MASK 0x8000 1372 #define PKEY_LOW_15_MASK 0x7fff 1373 1374 /* 1375 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent 1376 * being an entry from the ingress partition key table), return 0 1377 * otherwise. Use the matching criteria for ingress partition keys 1378 * specified in the OPAv1 spec., section 9.10.14. 1379 */ 1380 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent) 1381 { 1382 u16 mkey = pkey & PKEY_LOW_15_MASK; 1383 u16 ment = ent & PKEY_LOW_15_MASK; 1384 1385 if (mkey == ment) { 1386 /* 1387 * If pkey[15] is clear (limited partition member), 1388 * is bit 15 in the corresponding table element 1389 * clear (limited member)? 1390 */ 1391 if (!(pkey & PKEY_MEMBER_MASK)) 1392 return !!(ent & PKEY_MEMBER_MASK); 1393 return 1; 1394 } 1395 return 0; 1396 } 1397 1398 /* 1399 * ingress_pkey_table_search - search the entire pkey table for 1400 * an entry which matches 'pkey'. return 0 if a match is found, 1401 * and 1 otherwise. 1402 */ 1403 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey) 1404 { 1405 int i; 1406 1407 for (i = 0; i < MAX_PKEY_VALUES; i++) { 1408 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i])) 1409 return 0; 1410 } 1411 return 1; 1412 } 1413 1414 /* 1415 * ingress_pkey_table_fail - record a failure of ingress pkey validation, 1416 * i.e., increment port_rcv_constraint_errors for the port, and record 1417 * the 'error info' for this failure. 1418 */ 1419 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey, 1420 u16 slid) 1421 { 1422 struct hfi1_devdata *dd = ppd->dd; 1423 1424 incr_cntr64(&ppd->port_rcv_constraint_errors); 1425 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) { 1426 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK; 1427 dd->err_info_rcv_constraint.slid = slid; 1428 dd->err_info_rcv_constraint.pkey = pkey; 1429 } 1430 } 1431 1432 /* 1433 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1 1434 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx 1435 * is a hint as to the best place in the partition key table to begin 1436 * searching. This function should not be called on the data path because 1437 * of performance reasons. On datapath pkey check is expected to be done 1438 * by HW and rcv_pkey_check function should be called instead. 1439 */ 1440 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1441 u8 sc5, u8 idx, u16 slid) 1442 { 1443 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1444 return 0; 1445 1446 /* If SC15, pkey[0:14] must be 0x7fff */ 1447 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1448 goto bad; 1449 1450 /* Is the pkey = 0x0, or 0x8000? */ 1451 if ((pkey & PKEY_LOW_15_MASK) == 0) 1452 goto bad; 1453 1454 /* The most likely matching pkey has index 'idx' */ 1455 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx])) 1456 return 0; 1457 1458 /* no match - try the whole table */ 1459 if (!ingress_pkey_table_search(ppd, pkey)) 1460 return 0; 1461 1462 bad: 1463 ingress_pkey_table_fail(ppd, pkey, slid); 1464 return 1; 1465 } 1466 1467 /* 1468 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1 1469 * otherwise. It only ensures pkey is vlid for QP0. This function 1470 * should be called on the data path instead of ingress_pkey_check 1471 * as on data path, pkey check is done by HW (except for QP0). 1472 */ 1473 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey, 1474 u8 sc5, u16 slid) 1475 { 1476 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN)) 1477 return 0; 1478 1479 /* If SC15, pkey[0:14] must be 0x7fff */ 1480 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK)) 1481 goto bad; 1482 1483 return 0; 1484 bad: 1485 ingress_pkey_table_fail(ppd, pkey, slid); 1486 return 1; 1487 } 1488 1489 /* MTU handling */ 1490 1491 /* MTU enumeration, 256-4k match IB */ 1492 #define OPA_MTU_0 0 1493 #define OPA_MTU_256 1 1494 #define OPA_MTU_512 2 1495 #define OPA_MTU_1024 3 1496 #define OPA_MTU_2048 4 1497 #define OPA_MTU_4096 5 1498 1499 u32 lrh_max_header_bytes(struct hfi1_devdata *dd); 1500 int mtu_to_enum(u32 mtu, int default_if_bad); 1501 u16 enum_to_mtu(int); 1502 static inline int valid_ib_mtu(unsigned int mtu) 1503 { 1504 return mtu == 256 || mtu == 512 || 1505 mtu == 1024 || mtu == 2048 || 1506 mtu == 4096; 1507 } 1508 1509 static inline int valid_opa_max_mtu(unsigned int mtu) 1510 { 1511 return mtu >= 2048 && 1512 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240); 1513 } 1514 1515 int set_mtu(struct hfi1_pportdata *); 1516 1517 int hfi1_set_lid(struct hfi1_pportdata *, u32, u8); 1518 void hfi1_disable_after_error(struct hfi1_devdata *); 1519 int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int); 1520 int hfi1_rcvbuf_validate(u32, u8, u16 *); 1521 1522 int fm_get_table(struct hfi1_pportdata *, int, void *); 1523 int fm_set_table(struct hfi1_pportdata *, int, void *); 1524 1525 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf); 1526 void reset_link_credits(struct hfi1_devdata *dd); 1527 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); 1528 1529 int snoop_recv_handler(struct hfi1_packet *packet); 1530 int snoop_send_dma_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 1531 u64 pbc); 1532 int snoop_send_pio_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, 1533 u64 pbc); 1534 void snoop_inline_pio_send(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1535 u64 pbc, const void *from, size_t count); 1536 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); 1537 1538 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) 1539 { 1540 return ppd->dd; 1541 } 1542 1543 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev) 1544 { 1545 return container_of(dev, struct hfi1_devdata, verbs_dev); 1546 } 1547 1548 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev) 1549 { 1550 return dd_from_dev(to_idev(ibdev)); 1551 } 1552 1553 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp) 1554 { 1555 return container_of(ibp, struct hfi1_pportdata, ibport_data); 1556 } 1557 1558 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi) 1559 { 1560 return container_of(rdi, struct hfi1_ibdev, rdi); 1561 } 1562 1563 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port) 1564 { 1565 struct hfi1_devdata *dd = dd_from_ibdev(ibdev); 1566 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1567 1568 WARN_ON(pidx >= dd->num_pports); 1569 return &dd->pport[pidx].ibport_data; 1570 } 1571 1572 /* 1573 * Return the indexed PKEY from the port PKEY table. 1574 */ 1575 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index) 1576 { 1577 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1578 u16 ret; 1579 1580 if (index >= ARRAY_SIZE(ppd->pkeys)) 1581 ret = 0; 1582 else 1583 ret = ppd->pkeys[index]; 1584 1585 return ret; 1586 } 1587 1588 /* 1589 * Readers of cc_state must call get_cc_state() under rcu_read_lock(). 1590 * Writers of cc_state must call get_cc_state() under cc_state_lock. 1591 */ 1592 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) 1593 { 1594 return rcu_dereference(ppd->cc_state); 1595 } 1596 1597 /* 1598 * values for dd->flags (_device_ related flags) 1599 */ 1600 #define HFI1_INITTED 0x1 /* chip and driver up and initted */ 1601 #define HFI1_PRESENT 0x2 /* chip accesses can be done */ 1602 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */ 1603 #define HFI1_HAS_SDMA_TIMEOUT 0x8 1604 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */ 1605 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */ 1606 1607 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1608 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1) 1609 1610 /* ctxt_flag bit offsets */ 1611 /* context has been setup */ 1612 #define HFI1_CTXT_SETUP_DONE 1 1613 /* waiting for a packet to arrive */ 1614 #define HFI1_CTXT_WAITING_RCV 2 1615 /* master has not finished initializing */ 1616 #define HFI1_CTXT_MASTER_UNINIT 4 1617 /* waiting for an urgent packet to arrive */ 1618 #define HFI1_CTXT_WAITING_URG 5 1619 1620 /* free up any allocated data at closes */ 1621 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *, 1622 const struct pci_device_id *); 1623 void hfi1_free_devdata(struct hfi1_devdata *); 1624 void cc_state_reclaim(struct rcu_head *rcu); 1625 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra); 1626 1627 /* LED beaconing functions */ 1628 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon, 1629 unsigned int timeoff); 1630 void shutdown_led_override(struct hfi1_pportdata *ppd); 1631 1632 #define HFI1_CREDIT_RETURN_RATE (100) 1633 1634 /* 1635 * The number of words for the KDETH protocol field. If this is 1636 * larger then the actual field used, then part of the payload 1637 * will be in the header. 1638 * 1639 * Optimally, we want this sized so that a typical case will 1640 * use full cache lines. The typical local KDETH header would 1641 * be: 1642 * 1643 * Bytes Field 1644 * 8 LRH 1645 * 12 BHT 1646 * ?? KDETH 1647 * 8 RHF 1648 * --- 1649 * 28 + KDETH 1650 * 1651 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS 1652 */ 1653 #define DEFAULT_RCVHDRSIZE 9 1654 1655 /* 1656 * Maximal header byte count: 1657 * 1658 * Bytes Field 1659 * 8 LRH 1660 * 40 GRH (optional) 1661 * 12 BTH 1662 * ?? KDETH 1663 * 8 RHF 1664 * --- 1665 * 68 + KDETH 1666 * 1667 * We also want to maintain a cache line alignment to assist DMA'ing 1668 * of the header bytes. Round up to a good size. 1669 */ 1670 #define DEFAULT_RCVHDR_ENTSIZE 32 1671 1672 bool hfi1_can_pin_pages(struct hfi1_devdata *, u32, u32); 1673 int hfi1_acquire_user_pages(unsigned long, size_t, bool, struct page **); 1674 void hfi1_release_user_pages(struct mm_struct *, struct page **, size_t, bool); 1675 1676 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1677 { 1678 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL; 1679 } 1680 1681 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd) 1682 { 1683 /* 1684 * volatile because it's a DMA target from the chip, routine is 1685 * inlined, and don't want register caching or reordering. 1686 */ 1687 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr); 1688 } 1689 1690 /* 1691 * sysfs interface. 1692 */ 1693 1694 extern const char ib_hfi1_version[]; 1695 1696 int hfi1_device_create(struct hfi1_devdata *); 1697 void hfi1_device_remove(struct hfi1_devdata *); 1698 1699 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, 1700 struct kobject *kobj); 1701 int hfi1_verbs_register_sysfs(struct hfi1_devdata *); 1702 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *); 1703 /* Hook for sysfs read of QSFP */ 1704 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); 1705 1706 int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *); 1707 void hfi1_pcie_cleanup(struct pci_dev *); 1708 int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *, 1709 const struct pci_device_id *); 1710 void hfi1_pcie_ddcleanup(struct hfi1_devdata *); 1711 void hfi1_pcie_flr(struct hfi1_devdata *); 1712 int pcie_speeds(struct hfi1_devdata *); 1713 void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *); 1714 void hfi1_enable_intx(struct pci_dev *); 1715 void restore_pci_variables(struct hfi1_devdata *dd); 1716 int do_pcie_gen3_transition(struct hfi1_devdata *dd); 1717 int parse_platform_config(struct hfi1_devdata *dd); 1718 int get_platform_config_field(struct hfi1_devdata *dd, 1719 enum platform_config_table_type_encoding 1720 table_type, int table_index, int field_index, 1721 u32 *data, u32 len); 1722 1723 const char *get_unit_name(int unit); 1724 const char *get_card_name(struct rvt_dev_info *rdi); 1725 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi); 1726 1727 /* 1728 * Flush write combining store buffers (if present) and perform a write 1729 * barrier. 1730 */ 1731 static inline void flush_wc(void) 1732 { 1733 asm volatile("sfence" : : : "memory"); 1734 } 1735 1736 void handle_eflags(struct hfi1_packet *packet); 1737 int process_receive_ib(struct hfi1_packet *packet); 1738 int process_receive_bypass(struct hfi1_packet *packet); 1739 int process_receive_error(struct hfi1_packet *packet); 1740 int kdeth_process_expected(struct hfi1_packet *packet); 1741 int kdeth_process_eager(struct hfi1_packet *packet); 1742 int process_receive_invalid(struct hfi1_packet *packet); 1743 1744 extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8]; 1745 1746 void update_sge(struct rvt_sge_state *ss, u32 length); 1747 1748 /* global module parameter variables */ 1749 extern unsigned int hfi1_max_mtu; 1750 extern unsigned int hfi1_cu; 1751 extern unsigned int user_credit_return_threshold; 1752 extern int num_user_contexts; 1753 extern unsigned n_krcvqs; 1754 extern uint krcvqs[]; 1755 extern int krcvqsset; 1756 extern uint kdeth_qp; 1757 extern uint loopback; 1758 extern uint quick_linkup; 1759 extern uint rcv_intr_timeout; 1760 extern uint rcv_intr_count; 1761 extern uint rcv_intr_dynamic; 1762 extern ushort link_crc_mask; 1763 1764 extern struct mutex hfi1_mutex; 1765 1766 /* Number of seconds before our card status check... */ 1767 #define STATUS_TIMEOUT 60 1768 1769 #define DRIVER_NAME "hfi1" 1770 #define HFI1_USER_MINOR_BASE 0 1771 #define HFI1_TRACE_MINOR 127 1772 #define HFI1_DIAGPKT_MINOR 128 1773 #define HFI1_DIAG_MINOR_BASE 129 1774 #define HFI1_SNOOP_CAPTURE_BASE 200 1775 #define HFI1_NMINORS 255 1776 1777 #define PCI_VENDOR_ID_INTEL 0x8086 1778 #define PCI_DEVICE_ID_INTEL0 0x24f0 1779 #define PCI_DEVICE_ID_INTEL1 0x24f1 1780 1781 #define HFI1_PKT_USER_SC_INTEGRITY \ 1782 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \ 1783 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \ 1784 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \ 1785 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK) 1786 1787 #define HFI1_PKT_KERNEL_SC_INTEGRITY \ 1788 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK) 1789 1790 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, 1791 u16 ctxt_type) 1792 { 1793 u64 base_sc_integrity = 1794 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1795 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK 1796 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1797 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1798 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1799 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 1800 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1801 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1802 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1803 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 1804 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1805 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1806 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 1807 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 1808 | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 1809 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 1810 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1811 1812 if (ctxt_type == SC_USER) 1813 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY; 1814 else 1815 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; 1816 1817 if (is_ax(dd)) 1818 /* turn off send-side job key checks - A0 */ 1819 return base_sc_integrity & 1820 ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1821 return base_sc_integrity; 1822 } 1823 1824 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) 1825 { 1826 u64 base_sdma_integrity = 1827 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 1828 | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK 1829 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK 1830 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 1831 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 1832 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK 1833 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 1834 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 1835 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 1836 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 1837 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 1838 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 1839 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 1840 | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 1841 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 1842 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; 1843 1844 if (is_ax(dd)) 1845 /* turn off send-side job key checks - A0 */ 1846 return base_sdma_integrity & 1847 ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; 1848 return base_sdma_integrity; 1849 } 1850 1851 /* 1852 * hfi1_early_err is used (only!) to print early errors before devdata is 1853 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1854 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is 1855 * the same as dd_dev_err, but is used when the message really needs 1856 * the IB port# to be definitive as to what's happening.. 1857 */ 1858 #define hfi1_early_err(dev, fmt, ...) \ 1859 dev_err(dev, fmt, ##__VA_ARGS__) 1860 1861 #define hfi1_early_info(dev, fmt, ...) \ 1862 dev_info(dev, fmt, ##__VA_ARGS__) 1863 1864 #define dd_dev_emerg(dd, fmt, ...) \ 1865 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \ 1866 get_unit_name((dd)->unit), ##__VA_ARGS__) 1867 #define dd_dev_err(dd, fmt, ...) \ 1868 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1869 get_unit_name((dd)->unit), ##__VA_ARGS__) 1870 #define dd_dev_warn(dd, fmt, ...) \ 1871 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 1872 get_unit_name((dd)->unit), ##__VA_ARGS__) 1873 1874 #define dd_dev_warn_ratelimited(dd, fmt, ...) \ 1875 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \ 1876 get_unit_name((dd)->unit), ##__VA_ARGS__) 1877 1878 #define dd_dev_info(dd, fmt, ...) \ 1879 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \ 1880 get_unit_name((dd)->unit), ##__VA_ARGS__) 1881 1882 #define dd_dev_dbg(dd, fmt, ...) \ 1883 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \ 1884 get_unit_name((dd)->unit), ##__VA_ARGS__) 1885 1886 #define hfi1_dev_porterr(dd, port, fmt, ...) \ 1887 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \ 1888 get_unit_name((dd)->unit), (port), ##__VA_ARGS__) 1889 1890 /* 1891 * this is used for formatting hw error messages... 1892 */ 1893 struct hfi1_hwerror_msgs { 1894 u64 mask; 1895 const char *msg; 1896 size_t sz; 1897 }; 1898 1899 /* in intr.c... */ 1900 void hfi1_format_hwerrors(u64 hwerrs, 1901 const struct hfi1_hwerror_msgs *hwerrmsgs, 1902 size_t nhwerrmsgs, char *msg, size_t lmsg); 1903 1904 #define USER_OPCODE_CHECK_VAL 0xC0 1905 #define USER_OPCODE_CHECK_MASK 0xC0 1906 #define OPCODE_CHECK_VAL_DISABLED 0x0 1907 #define OPCODE_CHECK_MASK_DISABLED 0x0 1908 1909 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd) 1910 { 1911 struct hfi1_pportdata *ppd; 1912 int i; 1913 1914 dd->z_int_counter = get_all_cpu_total(dd->int_counter); 1915 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit); 1916 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule); 1917 1918 ppd = (struct hfi1_pportdata *)(dd + 1); 1919 for (i = 0; i < dd->num_pports; i++, ppd++) { 1920 ppd->ibport_data.rvp.z_rc_acks = 1921 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks); 1922 ppd->ibport_data.rvp.z_rc_qacks = 1923 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks); 1924 } 1925 } 1926 1927 /* Control LED state */ 1928 static inline void setextled(struct hfi1_devdata *dd, u32 on) 1929 { 1930 if (on) 1931 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); 1932 else 1933 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); 1934 } 1935 1936 /* return the i2c resource given the target */ 1937 static inline u32 i2c_target(u32 target) 1938 { 1939 return target ? CR_I2C2 : CR_I2C1; 1940 } 1941 1942 /* return the i2c chain chip resource that this HFI uses for QSFP */ 1943 static inline u32 qsfp_resource(struct hfi1_devdata *dd) 1944 { 1945 return i2c_target(dd->hfi1_id); 1946 } 1947 1948 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); 1949 1950 #endif /* _HFI1_KERNEL_H */ 1951