1 /* 2 * Copyright(c) 2015 - 2017 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/firmware.h> 49 #include <linux/mutex.h> 50 #include <linux/module.h> 51 #include <linux/delay.h> 52 #include <linux/crc32.h> 53 54 #include "hfi.h" 55 #include "trace.h" 56 57 /* 58 * Make it easy to toggle firmware file name and if it gets loaded by 59 * editing the following. This may be something we do while in development 60 * but not necessarily something a user would ever need to use. 61 */ 62 #define DEFAULT_FW_8051_NAME_FPGA "hfi_dc8051.bin" 63 #define DEFAULT_FW_8051_NAME_ASIC "hfi1_dc8051.fw" 64 #define DEFAULT_FW_FABRIC_NAME "hfi1_fabric.fw" 65 #define DEFAULT_FW_SBUS_NAME "hfi1_sbus.fw" 66 #define DEFAULT_FW_PCIE_NAME "hfi1_pcie.fw" 67 #define DEFAULT_PLATFORM_CONFIG_NAME "hfi1_platform.dat" 68 #define ALT_FW_8051_NAME_ASIC "hfi1_dc8051_d.fw" 69 #define ALT_FW_FABRIC_NAME "hfi1_fabric_d.fw" 70 #define ALT_FW_SBUS_NAME "hfi1_sbus_d.fw" 71 #define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw" 72 73 static uint fw_8051_load = 1; 74 static uint fw_fabric_serdes_load = 1; 75 static uint fw_pcie_serdes_load = 1; 76 static uint fw_sbus_load = 1; 77 78 /* 79 * Access required in platform.c 80 * Maintains state of whether the platform config was fetched via the 81 * fallback option 82 */ 83 uint platform_config_load; 84 85 /* Firmware file names get set in hfi1_firmware_init() based on the above */ 86 static char *fw_8051_name; 87 static char *fw_fabric_serdes_name; 88 static char *fw_sbus_name; 89 static char *fw_pcie_serdes_name; 90 static char *platform_config_name; 91 92 #define SBUS_MAX_POLL_COUNT 100 93 #define SBUS_COUNTER(reg, name) \ 94 (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \ 95 ASIC_STS_SBUS_COUNTERS_##name##_CNT_MASK) 96 97 /* 98 * Firmware security header. 99 */ 100 struct css_header { 101 u32 module_type; 102 u32 header_len; 103 u32 header_version; 104 u32 module_id; 105 u32 module_vendor; 106 u32 date; /* BCD yyyymmdd */ 107 u32 size; /* in DWORDs */ 108 u32 key_size; /* in DWORDs */ 109 u32 modulus_size; /* in DWORDs */ 110 u32 exponent_size; /* in DWORDs */ 111 u32 reserved[22]; 112 }; 113 114 /* expected field values */ 115 #define CSS_MODULE_TYPE 0x00000006 116 #define CSS_HEADER_LEN 0x000000a1 117 #define CSS_HEADER_VERSION 0x00010000 118 #define CSS_MODULE_VENDOR 0x00008086 119 120 #define KEY_SIZE 256 121 #define MU_SIZE 8 122 #define EXPONENT_SIZE 4 123 124 /* the file itself */ 125 struct firmware_file { 126 struct css_header css_header; 127 u8 modulus[KEY_SIZE]; 128 u8 exponent[EXPONENT_SIZE]; 129 u8 signature[KEY_SIZE]; 130 u8 firmware[]; 131 }; 132 133 struct augmented_firmware_file { 134 struct css_header css_header; 135 u8 modulus[KEY_SIZE]; 136 u8 exponent[EXPONENT_SIZE]; 137 u8 signature[KEY_SIZE]; 138 u8 r2[KEY_SIZE]; 139 u8 mu[MU_SIZE]; 140 u8 firmware[]; 141 }; 142 143 /* augmented file size difference */ 144 #define AUGMENT_SIZE (sizeof(struct augmented_firmware_file) - \ 145 sizeof(struct firmware_file)) 146 147 struct firmware_details { 148 /* Linux core piece */ 149 const struct firmware *fw; 150 151 struct css_header *css_header; 152 u8 *firmware_ptr; /* pointer to binary data */ 153 u32 firmware_len; /* length in bytes */ 154 u8 *modulus; /* pointer to the modulus */ 155 u8 *exponent; /* pointer to the exponent */ 156 u8 *signature; /* pointer to the signature */ 157 u8 *r2; /* pointer to r2 */ 158 u8 *mu; /* pointer to mu */ 159 struct augmented_firmware_file dummy_header; 160 }; 161 162 /* 163 * The mutex protects fw_state, fw_err, and all of the firmware_details 164 * variables. 165 */ 166 static DEFINE_MUTEX(fw_mutex); 167 enum fw_state { 168 FW_EMPTY, 169 FW_TRY, 170 FW_FINAL, 171 FW_ERR 172 }; 173 174 static enum fw_state fw_state = FW_EMPTY; 175 static int fw_err; 176 static struct firmware_details fw_8051; 177 static struct firmware_details fw_fabric; 178 static struct firmware_details fw_pcie; 179 static struct firmware_details fw_sbus; 180 static const struct firmware *platform_config; 181 182 /* flags for turn_off_spicos() */ 183 #define SPICO_SBUS 0x1 184 #define SPICO_FABRIC 0x2 185 #define ENABLE_SPICO_SMASK 0x1 186 187 /* security block commands */ 188 #define RSA_CMD_INIT 0x1 189 #define RSA_CMD_START 0x2 190 191 /* security block status */ 192 #define RSA_STATUS_IDLE 0x0 193 #define RSA_STATUS_ACTIVE 0x1 194 #define RSA_STATUS_DONE 0x2 195 #define RSA_STATUS_FAILED 0x3 196 197 /* RSA engine timeout, in ms */ 198 #define RSA_ENGINE_TIMEOUT 100 /* ms */ 199 200 /* hardware mutex timeout, in ms */ 201 #define HM_TIMEOUT 10 /* ms */ 202 203 /* 8051 memory access timeout, in us */ 204 #define DC8051_ACCESS_TIMEOUT 100 /* us */ 205 206 /* the number of fabric SerDes on the SBus */ 207 #define NUM_FABRIC_SERDES 4 208 209 /* ASIC_STS_SBUS_RESULT.RESULT_CODE value */ 210 #define SBUS_READ_COMPLETE 0x4 211 212 /* SBus fabric SerDes addresses, one set per HFI */ 213 static const u8 fabric_serdes_addrs[2][NUM_FABRIC_SERDES] = { 214 { 0x01, 0x02, 0x03, 0x04 }, 215 { 0x28, 0x29, 0x2a, 0x2b } 216 }; 217 218 /* SBus PCIe SerDes addresses, one set per HFI */ 219 static const u8 pcie_serdes_addrs[2][NUM_PCIE_SERDES] = { 220 { 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 221 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26 }, 222 { 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d, 223 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d } 224 }; 225 226 /* SBus PCIe PCS addresses, one set per HFI */ 227 const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES] = { 228 { 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17, 229 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23, 0x25, 0x27 }, 230 { 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 231 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e } 232 }; 233 234 /* SBus fabric SerDes broadcast addresses, one per HFI */ 235 static const u8 fabric_serdes_broadcast[2] = { 0xe4, 0xe5 }; 236 static const u8 all_fabric_serdes_broadcast = 0xe1; 237 238 /* SBus PCIe SerDes broadcast addresses, one per HFI */ 239 const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 }; 240 static const u8 all_pcie_serdes_broadcast = 0xe0; 241 242 static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = { 243 0, 244 SYSTEM_TABLE_MAX, 245 PORT_TABLE_MAX, 246 RX_PRESET_TABLE_MAX, 247 TX_PRESET_TABLE_MAX, 248 QSFP_ATTEN_TABLE_MAX, 249 VARIABLE_SETTINGS_TABLE_MAX 250 }; 251 252 /* forwards */ 253 static void dispose_one_firmware(struct firmware_details *fdet); 254 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd, 255 struct firmware_details *fdet); 256 static void dump_fw_version(struct hfi1_devdata *dd); 257 258 /* 259 * Read a single 64-bit value from 8051 data memory. 260 * 261 * Expects: 262 * o caller to have already set up data read, no auto increment 263 * o caller to turn off read enable when finished 264 * 265 * The address argument is a byte offset. Bits 0:2 in the address are 266 * ignored - i.e. the hardware will always do aligned 8-byte reads as if 267 * the lower bits are zero. 268 * 269 * Return 0 on success, -ENXIO on a read error (timeout). 270 */ 271 static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result) 272 { 273 u64 reg; 274 int count; 275 276 /* step 1: set the address, clear enable */ 277 reg = (addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK) 278 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT; 279 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); 280 /* step 2: enable */ 281 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 282 reg | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK); 283 284 /* wait until ACCESS_COMPLETED is set */ 285 count = 0; 286 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) 287 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK) 288 == 0) { 289 count++; 290 if (count > DC8051_ACCESS_TIMEOUT) { 291 dd_dev_err(dd, "timeout reading 8051 data\n"); 292 return -ENXIO; 293 } 294 ndelay(10); 295 } 296 297 /* gather the data */ 298 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); 299 300 return 0; 301 } 302 303 /* 304 * Read 8051 data starting at addr, for len bytes. Will read in 8-byte chunks. 305 * Return 0 on success, -errno on error. 306 */ 307 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result) 308 { 309 unsigned long flags; 310 u32 done; 311 int ret = 0; 312 313 spin_lock_irqsave(&dd->dc8051_memlock, flags); 314 315 /* data read set-up, no auto-increment */ 316 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); 317 318 for (done = 0; done < len; addr += 8, done += 8, result++) { 319 ret = __read_8051_data(dd, addr, result); 320 if (ret) 321 break; 322 } 323 324 /* turn off read enable */ 325 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); 326 327 spin_unlock_irqrestore(&dd->dc8051_memlock, flags); 328 329 return ret; 330 } 331 332 /* 333 * Write data or code to the 8051 code or data RAM. 334 */ 335 static int write_8051(struct hfi1_devdata *dd, int code, u32 start, 336 const u8 *data, u32 len) 337 { 338 u64 reg; 339 u32 offset; 340 int aligned, count; 341 342 /* check alignment */ 343 aligned = ((unsigned long)data & 0x7) == 0; 344 345 /* write set-up */ 346 reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull) 347 | DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK; 348 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg); 349 350 reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK) 351 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT) 352 | DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK; 353 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); 354 355 /* write */ 356 for (offset = 0; offset < len; offset += 8) { 357 int bytes = len - offset; 358 359 if (bytes < 8) { 360 reg = 0; 361 memcpy(®, &data[offset], bytes); 362 } else if (aligned) { 363 reg = *(u64 *)&data[offset]; 364 } else { 365 memcpy(®, &data[offset], 8); 366 } 367 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg); 368 369 /* wait until ACCESS_COMPLETED is set */ 370 count = 0; 371 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) 372 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK) 373 == 0) { 374 count++; 375 if (count > DC8051_ACCESS_TIMEOUT) { 376 dd_dev_err(dd, "timeout writing 8051 data\n"); 377 return -ENXIO; 378 } 379 udelay(1); 380 } 381 } 382 383 /* turn off write access, auto increment (also sets to data access) */ 384 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); 385 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); 386 387 return 0; 388 } 389 390 /* return 0 if values match, non-zero and complain otherwise */ 391 static int invalid_header(struct hfi1_devdata *dd, const char *what, 392 u32 actual, u32 expected) 393 { 394 if (actual == expected) 395 return 0; 396 397 dd_dev_err(dd, 398 "invalid firmware header field %s: expected 0x%x, actual 0x%x\n", 399 what, expected, actual); 400 return 1; 401 } 402 403 /* 404 * Verify that the static fields in the CSS header match. 405 */ 406 static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css) 407 { 408 /* verify CSS header fields (most sizes are in DW, so add /4) */ 409 if (invalid_header(dd, "module_type", css->module_type, 410 CSS_MODULE_TYPE) || 411 invalid_header(dd, "header_len", css->header_len, 412 (sizeof(struct firmware_file) / 4)) || 413 invalid_header(dd, "header_version", css->header_version, 414 CSS_HEADER_VERSION) || 415 invalid_header(dd, "module_vendor", css->module_vendor, 416 CSS_MODULE_VENDOR) || 417 invalid_header(dd, "key_size", css->key_size, KEY_SIZE / 4) || 418 invalid_header(dd, "modulus_size", css->modulus_size, 419 KEY_SIZE / 4) || 420 invalid_header(dd, "exponent_size", css->exponent_size, 421 EXPONENT_SIZE / 4)) { 422 return -EINVAL; 423 } 424 return 0; 425 } 426 427 /* 428 * Make sure there are at least some bytes after the prefix. 429 */ 430 static int payload_check(struct hfi1_devdata *dd, const char *name, 431 long file_size, long prefix_size) 432 { 433 /* make sure we have some payload */ 434 if (prefix_size >= file_size) { 435 dd_dev_err(dd, 436 "firmware \"%s\", size %ld, must be larger than %ld bytes\n", 437 name, file_size, prefix_size); 438 return -EINVAL; 439 } 440 441 return 0; 442 } 443 444 /* 445 * Request the firmware from the system. Extract the pieces and fill in 446 * fdet. If successful, the caller will need to call dispose_one_firmware(). 447 * Returns 0 on success, -ERRNO on error. 448 */ 449 static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name, 450 struct firmware_details *fdet) 451 { 452 struct css_header *css; 453 int ret; 454 455 memset(fdet, 0, sizeof(*fdet)); 456 457 ret = request_firmware(&fdet->fw, name, &dd->pcidev->dev); 458 if (ret) { 459 dd_dev_warn(dd, "cannot find firmware \"%s\", err %d\n", 460 name, ret); 461 return ret; 462 } 463 464 /* verify the firmware */ 465 if (fdet->fw->size < sizeof(struct css_header)) { 466 dd_dev_err(dd, "firmware \"%s\" is too small\n", name); 467 ret = -EINVAL; 468 goto done; 469 } 470 css = (struct css_header *)fdet->fw->data; 471 472 hfi1_cdbg(FIRMWARE, "Firmware %s details:", name); 473 hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size); 474 hfi1_cdbg(FIRMWARE, "CSS structure:"); 475 hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type); 476 hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)", 477 css->header_len, 4 * css->header_len); 478 hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version); 479 hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id); 480 hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor); 481 hfi1_cdbg(FIRMWARE, " date 0x%x", css->date); 482 hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)", 483 css->size, 4 * css->size); 484 hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)", 485 css->key_size, 4 * css->key_size); 486 hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)", 487 css->modulus_size, 4 * css->modulus_size); 488 hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)", 489 css->exponent_size, 4 * css->exponent_size); 490 hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes", 491 fdet->fw->size - sizeof(struct firmware_file)); 492 493 /* 494 * If the file does not have a valid CSS header, fail. 495 * Otherwise, check the CSS size field for an expected size. 496 * The augmented file has r2 and mu inserted after the header 497 * was generated, so there will be a known difference between 498 * the CSS header size and the actual file size. Use this 499 * difference to identify an augmented file. 500 * 501 * Note: css->size is in DWORDs, multiply by 4 to get bytes. 502 */ 503 ret = verify_css_header(dd, css); 504 if (ret) { 505 dd_dev_info(dd, "Invalid CSS header for \"%s\"\n", name); 506 } else if ((css->size * 4) == fdet->fw->size) { 507 /* non-augmented firmware file */ 508 struct firmware_file *ff = (struct firmware_file *) 509 fdet->fw->data; 510 511 /* make sure there are bytes in the payload */ 512 ret = payload_check(dd, name, fdet->fw->size, 513 sizeof(struct firmware_file)); 514 if (ret == 0) { 515 fdet->css_header = css; 516 fdet->modulus = ff->modulus; 517 fdet->exponent = ff->exponent; 518 fdet->signature = ff->signature; 519 fdet->r2 = fdet->dummy_header.r2; /* use dummy space */ 520 fdet->mu = fdet->dummy_header.mu; /* use dummy space */ 521 fdet->firmware_ptr = ff->firmware; 522 fdet->firmware_len = fdet->fw->size - 523 sizeof(struct firmware_file); 524 /* 525 * Header does not include r2 and mu - generate here. 526 * For now, fail. 527 */ 528 dd_dev_err(dd, "driver is unable to validate firmware without r2 and mu (not in firmware file)\n"); 529 ret = -EINVAL; 530 } 531 } else if ((css->size * 4) + AUGMENT_SIZE == fdet->fw->size) { 532 /* augmented firmware file */ 533 struct augmented_firmware_file *aff = 534 (struct augmented_firmware_file *)fdet->fw->data; 535 536 /* make sure there are bytes in the payload */ 537 ret = payload_check(dd, name, fdet->fw->size, 538 sizeof(struct augmented_firmware_file)); 539 if (ret == 0) { 540 fdet->css_header = css; 541 fdet->modulus = aff->modulus; 542 fdet->exponent = aff->exponent; 543 fdet->signature = aff->signature; 544 fdet->r2 = aff->r2; 545 fdet->mu = aff->mu; 546 fdet->firmware_ptr = aff->firmware; 547 fdet->firmware_len = fdet->fw->size - 548 sizeof(struct augmented_firmware_file); 549 } 550 } else { 551 /* css->size check failed */ 552 dd_dev_err(dd, 553 "invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n", 554 fdet->fw->size / 4, 555 (fdet->fw->size - AUGMENT_SIZE) / 4, 556 css->size); 557 558 ret = -EINVAL; 559 } 560 561 done: 562 /* if returning an error, clean up after ourselves */ 563 if (ret) 564 dispose_one_firmware(fdet); 565 return ret; 566 } 567 568 static void dispose_one_firmware(struct firmware_details *fdet) 569 { 570 release_firmware(fdet->fw); 571 /* erase all previous information */ 572 memset(fdet, 0, sizeof(*fdet)); 573 } 574 575 /* 576 * Obtain the 4 firmwares from the OS. All must be obtained at once or not 577 * at all. If called with the firmware state in FW_TRY, use alternate names. 578 * On exit, this routine will have set the firmware state to one of FW_TRY, 579 * FW_FINAL, or FW_ERR. 580 * 581 * Must be holding fw_mutex. 582 */ 583 static void __obtain_firmware(struct hfi1_devdata *dd) 584 { 585 int err = 0; 586 587 if (fw_state == FW_FINAL) /* nothing more to obtain */ 588 return; 589 if (fw_state == FW_ERR) /* already in error */ 590 return; 591 592 /* fw_state is FW_EMPTY or FW_TRY */ 593 retry: 594 if (fw_state == FW_TRY) { 595 /* 596 * We tried the original and it failed. Move to the 597 * alternate. 598 */ 599 dd_dev_warn(dd, "using alternate firmware names\n"); 600 /* 601 * Let others run. Some systems, when missing firmware, does 602 * something that holds for 30 seconds. If we do that twice 603 * in a row it triggers task blocked warning. 604 */ 605 cond_resched(); 606 if (fw_8051_load) 607 dispose_one_firmware(&fw_8051); 608 if (fw_fabric_serdes_load) 609 dispose_one_firmware(&fw_fabric); 610 if (fw_sbus_load) 611 dispose_one_firmware(&fw_sbus); 612 if (fw_pcie_serdes_load) 613 dispose_one_firmware(&fw_pcie); 614 fw_8051_name = ALT_FW_8051_NAME_ASIC; 615 fw_fabric_serdes_name = ALT_FW_FABRIC_NAME; 616 fw_sbus_name = ALT_FW_SBUS_NAME; 617 fw_pcie_serdes_name = ALT_FW_PCIE_NAME; 618 } 619 620 if (fw_sbus_load) { 621 err = obtain_one_firmware(dd, fw_sbus_name, &fw_sbus); 622 if (err) 623 goto done; 624 } 625 626 if (fw_pcie_serdes_load) { 627 err = obtain_one_firmware(dd, fw_pcie_serdes_name, &fw_pcie); 628 if (err) 629 goto done; 630 } 631 632 if (fw_fabric_serdes_load) { 633 err = obtain_one_firmware(dd, fw_fabric_serdes_name, 634 &fw_fabric); 635 if (err) 636 goto done; 637 } 638 639 if (fw_8051_load) { 640 err = obtain_one_firmware(dd, fw_8051_name, &fw_8051); 641 if (err) 642 goto done; 643 } 644 645 done: 646 if (err) { 647 /* oops, had problems obtaining a firmware */ 648 if (fw_state == FW_EMPTY && dd->icode == ICODE_RTL_SILICON) { 649 /* retry with alternate (RTL only) */ 650 fw_state = FW_TRY; 651 goto retry; 652 } 653 dd_dev_err(dd, "unable to obtain working firmware\n"); 654 fw_state = FW_ERR; 655 fw_err = -ENOENT; 656 } else { 657 /* success */ 658 if (fw_state == FW_EMPTY && 659 dd->icode != ICODE_FUNCTIONAL_SIMULATOR) 660 fw_state = FW_TRY; /* may retry later */ 661 else 662 fw_state = FW_FINAL; /* cannot try again */ 663 } 664 } 665 666 /* 667 * Called by all HFIs when loading their firmware - i.e. device probe time. 668 * The first one will do the actual firmware load. Use a mutex to resolve 669 * any possible race condition. 670 * 671 * The call to this routine cannot be moved to driver load because the kernel 672 * call request_firmware() requires a device which is only available after 673 * the first device probe. 674 */ 675 static int obtain_firmware(struct hfi1_devdata *dd) 676 { 677 unsigned long timeout; 678 int err = 0; 679 680 mutex_lock(&fw_mutex); 681 682 /* 40s delay due to long delay on missing firmware on some systems */ 683 timeout = jiffies + msecs_to_jiffies(40000); 684 while (fw_state == FW_TRY) { 685 /* 686 * Another device is trying the firmware. Wait until it 687 * decides what works (or not). 688 */ 689 if (time_after(jiffies, timeout)) { 690 /* waited too long */ 691 dd_dev_err(dd, "Timeout waiting for firmware try"); 692 fw_state = FW_ERR; 693 fw_err = -ETIMEDOUT; 694 break; 695 } 696 mutex_unlock(&fw_mutex); 697 msleep(20); /* arbitrary delay */ 698 mutex_lock(&fw_mutex); 699 } 700 /* not in FW_TRY state */ 701 702 if (fw_state == FW_FINAL) { 703 if (platform_config) { 704 dd->platform_config.data = platform_config->data; 705 dd->platform_config.size = platform_config->size; 706 } 707 goto done; /* already acquired */ 708 } else if (fw_state == FW_ERR) { 709 goto done; /* already tried and failed */ 710 } 711 /* fw_state is FW_EMPTY */ 712 713 /* set fw_state to FW_TRY, FW_FINAL, or FW_ERR, and fw_err */ 714 __obtain_firmware(dd); 715 716 if (platform_config_load) { 717 platform_config = NULL; 718 err = request_firmware(&platform_config, platform_config_name, 719 &dd->pcidev->dev); 720 if (err) { 721 platform_config = NULL; 722 dd_dev_err(dd, 723 "%s: No default platform config file found\n", 724 __func__); 725 goto done; 726 } 727 dd->platform_config.data = platform_config->data; 728 dd->platform_config.size = platform_config->size; 729 } 730 731 done: 732 mutex_unlock(&fw_mutex); 733 734 return fw_err; 735 } 736 737 /* 738 * Called when the driver unloads. The timing is asymmetric with its 739 * counterpart, obtain_firmware(). If called at device remove time, 740 * then it is conceivable that another device could probe while the 741 * firmware is being disposed. The mutexes can be moved to do that 742 * safely, but then the firmware would be requested from the OS multiple 743 * times. 744 * 745 * No mutex is needed as the driver is unloading and there cannot be any 746 * other callers. 747 */ 748 void dispose_firmware(void) 749 { 750 dispose_one_firmware(&fw_8051); 751 dispose_one_firmware(&fw_fabric); 752 dispose_one_firmware(&fw_pcie); 753 dispose_one_firmware(&fw_sbus); 754 755 release_firmware(platform_config); 756 platform_config = NULL; 757 758 /* retain the error state, otherwise revert to empty */ 759 if (fw_state != FW_ERR) 760 fw_state = FW_EMPTY; 761 } 762 763 /* 764 * Called with the result of a firmware download. 765 * 766 * Return 1 to retry loading the firmware, 0 to stop. 767 */ 768 static int retry_firmware(struct hfi1_devdata *dd, int load_result) 769 { 770 int retry; 771 772 mutex_lock(&fw_mutex); 773 774 if (load_result == 0) { 775 /* 776 * The load succeeded, so expect all others to do the same. 777 * Do not retry again. 778 */ 779 if (fw_state == FW_TRY) 780 fw_state = FW_FINAL; 781 retry = 0; /* do NOT retry */ 782 } else if (fw_state == FW_TRY) { 783 /* load failed, obtain alternate firmware */ 784 __obtain_firmware(dd); 785 retry = (fw_state == FW_FINAL); 786 } else { 787 /* else in FW_FINAL or FW_ERR, no retry in either case */ 788 retry = 0; 789 } 790 791 mutex_unlock(&fw_mutex); 792 return retry; 793 } 794 795 /* 796 * Write a block of data to a given array CSR. All calls will be in 797 * multiples of 8 bytes. 798 */ 799 static void write_rsa_data(struct hfi1_devdata *dd, int what, 800 const u8 *data, int nbytes) 801 { 802 int qw_size = nbytes / 8; 803 int i; 804 805 if (((unsigned long)data & 0x7) == 0) { 806 /* aligned */ 807 u64 *ptr = (u64 *)data; 808 809 for (i = 0; i < qw_size; i++, ptr++) 810 write_csr(dd, what + (8 * i), *ptr); 811 } else { 812 /* not aligned */ 813 for (i = 0; i < qw_size; i++, data += 8) { 814 u64 value; 815 816 memcpy(&value, data, 8); 817 write_csr(dd, what + (8 * i), value); 818 } 819 } 820 } 821 822 /* 823 * Write a block of data to a given CSR as a stream of writes. All calls will 824 * be in multiples of 8 bytes. 825 */ 826 static void write_streamed_rsa_data(struct hfi1_devdata *dd, int what, 827 const u8 *data, int nbytes) 828 { 829 u64 *ptr = (u64 *)data; 830 int qw_size = nbytes / 8; 831 832 for (; qw_size > 0; qw_size--, ptr++) 833 write_csr(dd, what, *ptr); 834 } 835 836 /* 837 * Download the signature and start the RSA mechanism. Wait for 838 * RSA_ENGINE_TIMEOUT before giving up. 839 */ 840 static int run_rsa(struct hfi1_devdata *dd, const char *who, 841 const u8 *signature) 842 { 843 unsigned long timeout; 844 u64 reg; 845 u32 status; 846 int ret = 0; 847 848 /* write the signature */ 849 write_rsa_data(dd, MISC_CFG_RSA_SIGNATURE, signature, KEY_SIZE); 850 851 /* initialize RSA */ 852 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT); 853 854 /* 855 * Make sure the engine is idle and insert a delay between the two 856 * writes to MISC_CFG_RSA_CMD. 857 */ 858 status = (read_csr(dd, MISC_CFG_FW_CTRL) 859 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK) 860 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT; 861 if (status != RSA_STATUS_IDLE) { 862 dd_dev_err(dd, "%s security engine not idle - giving up\n", 863 who); 864 return -EBUSY; 865 } 866 867 /* start RSA */ 868 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START); 869 870 /* 871 * Look for the result. 872 * 873 * The RSA engine is hooked up to two MISC errors. The driver 874 * masks these errors as they do not respond to the standard 875 * error "clear down" mechanism. Look for these errors here and 876 * clear them when possible. This routine will exit with the 877 * errors of the current run still set. 878 * 879 * MISC_FW_AUTH_FAILED_ERR 880 * Firmware authorization failed. This can be cleared by 881 * re-initializing the RSA engine, then clearing the status bit. 882 * Do not re-init the RSA angine immediately after a successful 883 * run - this will reset the current authorization. 884 * 885 * MISC_KEY_MISMATCH_ERR 886 * Key does not match. The only way to clear this is to load 887 * a matching key then clear the status bit. If this error 888 * is raised, it will persist outside of this routine until a 889 * matching key is loaded. 890 */ 891 timeout = msecs_to_jiffies(RSA_ENGINE_TIMEOUT) + jiffies; 892 while (1) { 893 status = (read_csr(dd, MISC_CFG_FW_CTRL) 894 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK) 895 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT; 896 897 if (status == RSA_STATUS_IDLE) { 898 /* should not happen */ 899 dd_dev_err(dd, "%s firmware security bad idle state\n", 900 who); 901 ret = -EINVAL; 902 break; 903 } else if (status == RSA_STATUS_DONE) { 904 /* finished successfully */ 905 break; 906 } else if (status == RSA_STATUS_FAILED) { 907 /* finished unsuccessfully */ 908 ret = -EINVAL; 909 break; 910 } 911 /* else still active */ 912 913 if (time_after(jiffies, timeout)) { 914 /* 915 * Timed out while active. We can't reset the engine 916 * if it is stuck active, but run through the 917 * error code to see what error bits are set. 918 */ 919 dd_dev_err(dd, "%s firmware security time out\n", who); 920 ret = -ETIMEDOUT; 921 break; 922 } 923 924 msleep(20); 925 } 926 927 /* 928 * Arrive here on success or failure. Clear all RSA engine 929 * errors. All current errors will stick - the RSA logic is keeping 930 * error high. All previous errors will clear - the RSA logic 931 * is not keeping the error high. 932 */ 933 write_csr(dd, MISC_ERR_CLEAR, 934 MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK | 935 MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK); 936 /* 937 * All that is left are the current errors. Print warnings on 938 * authorization failure details, if any. Firmware authorization 939 * can be retried, so these are only warnings. 940 */ 941 reg = read_csr(dd, MISC_ERR_STATUS); 942 if (ret) { 943 if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK) 944 dd_dev_warn(dd, "%s firmware authorization failed\n", 945 who); 946 if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK) 947 dd_dev_warn(dd, "%s firmware key mismatch\n", who); 948 } 949 950 return ret; 951 } 952 953 static void load_security_variables(struct hfi1_devdata *dd, 954 struct firmware_details *fdet) 955 { 956 /* Security variables a. Write the modulus */ 957 write_rsa_data(dd, MISC_CFG_RSA_MODULUS, fdet->modulus, KEY_SIZE); 958 /* Security variables b. Write the r2 */ 959 write_rsa_data(dd, MISC_CFG_RSA_R2, fdet->r2, KEY_SIZE); 960 /* Security variables c. Write the mu */ 961 write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE); 962 /* Security variables d. Write the header */ 963 write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD, 964 (u8 *)fdet->css_header, 965 sizeof(struct css_header)); 966 } 967 968 /* return the 8051 firmware state */ 969 static inline u32 get_firmware_state(struct hfi1_devdata *dd) 970 { 971 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); 972 973 return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT) 974 & DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK; 975 } 976 977 /* 978 * Wait until the firmware is up and ready to take host requests. 979 * Return 0 on success, -ETIMEDOUT on timeout. 980 */ 981 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout) 982 { 983 unsigned long timeout; 984 985 /* in the simulator, the fake 8051 is always ready */ 986 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 987 return 0; 988 989 timeout = msecs_to_jiffies(mstimeout) + jiffies; 990 while (1) { 991 if (get_firmware_state(dd) == 0xa0) /* ready */ 992 return 0; 993 if (time_after(jiffies, timeout)) /* timed out */ 994 return -ETIMEDOUT; 995 usleep_range(1950, 2050); /* sleep 2ms-ish */ 996 } 997 } 998 999 /* 1000 * Load the 8051 firmware. 1001 */ 1002 static int load_8051_firmware(struct hfi1_devdata *dd, 1003 struct firmware_details *fdet) 1004 { 1005 u64 reg; 1006 int ret; 1007 u8 ver_major; 1008 u8 ver_minor; 1009 u8 ver_patch; 1010 1011 /* 1012 * DC Reset sequence 1013 * Load DC 8051 firmware 1014 */ 1015 /* 1016 * DC reset step 1: Reset DC8051 1017 */ 1018 reg = DC_DC8051_CFG_RST_M8051W_SMASK 1019 | DC_DC8051_CFG_RST_CRAM_SMASK 1020 | DC_DC8051_CFG_RST_DRAM_SMASK 1021 | DC_DC8051_CFG_RST_IRAM_SMASK 1022 | DC_DC8051_CFG_RST_SFR_SMASK; 1023 write_csr(dd, DC_DC8051_CFG_RST, reg); 1024 1025 /* 1026 * DC reset step 2 (optional): Load 8051 data memory with link 1027 * configuration 1028 */ 1029 1030 /* 1031 * DC reset step 3: Load DC8051 firmware 1032 */ 1033 /* release all but the core reset */ 1034 reg = DC_DC8051_CFG_RST_M8051W_SMASK; 1035 write_csr(dd, DC_DC8051_CFG_RST, reg); 1036 1037 /* Firmware load step 1 */ 1038 load_security_variables(dd, fdet); 1039 1040 /* 1041 * Firmware load step 2. Clear MISC_CFG_FW_CTRL.FW_8051_LOADED 1042 */ 1043 write_csr(dd, MISC_CFG_FW_CTRL, 0); 1044 1045 /* Firmware load steps 3-5 */ 1046 ret = write_8051(dd, 1/*code*/, 0, fdet->firmware_ptr, 1047 fdet->firmware_len); 1048 if (ret) 1049 return ret; 1050 1051 /* 1052 * DC reset step 4. Host starts the DC8051 firmware 1053 */ 1054 /* 1055 * Firmware load step 6. Set MISC_CFG_FW_CTRL.FW_8051_LOADED 1056 */ 1057 write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK); 1058 1059 /* Firmware load steps 7-10 */ 1060 ret = run_rsa(dd, "8051", fdet->signature); 1061 if (ret) 1062 return ret; 1063 1064 /* clear all reset bits, releasing the 8051 */ 1065 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 1066 1067 /* 1068 * DC reset step 5. Wait for firmware to be ready to accept host 1069 * requests. 1070 */ 1071 ret = wait_fm_ready(dd, TIMEOUT_8051_START); 1072 if (ret) { /* timed out */ 1073 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n", 1074 get_firmware_state(dd)); 1075 return -ETIMEDOUT; 1076 } 1077 1078 read_misc_status(dd, &ver_major, &ver_minor, &ver_patch); 1079 dd_dev_info(dd, "8051 firmware version %d.%d.%d\n", 1080 (int)ver_major, (int)ver_minor, (int)ver_patch); 1081 dd->dc8051_ver = dc8051_ver(ver_major, ver_minor, ver_patch); 1082 1083 return 0; 1084 } 1085 1086 /* 1087 * Write the SBus request register 1088 * 1089 * No need for masking - the arguments are sized exactly. 1090 */ 1091 void sbus_request(struct hfi1_devdata *dd, 1092 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in) 1093 { 1094 write_csr(dd, ASIC_CFG_SBUS_REQUEST, 1095 ((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT) | 1096 ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT) | 1097 ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT) | 1098 ((u64)receiver_addr << 1099 ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT)); 1100 } 1101 1102 /* 1103 * Read a value from the SBus. 1104 * 1105 * Requires the caller to be in fast mode 1106 */ 1107 static u32 sbus_read(struct hfi1_devdata *dd, u8 receiver_addr, u8 data_addr, 1108 u32 data_in) 1109 { 1110 u64 reg; 1111 int retries; 1112 int success = 0; 1113 u32 result = 0; 1114 u32 result_code = 0; 1115 1116 sbus_request(dd, receiver_addr, data_addr, READ_SBUS_RECEIVER, data_in); 1117 1118 for (retries = 0; retries < 100; retries++) { 1119 usleep_range(1000, 1200); /* arbitrary */ 1120 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1121 result_code = (reg >> ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT) 1122 & ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK; 1123 if (result_code != SBUS_READ_COMPLETE) 1124 continue; 1125 1126 success = 1; 1127 result = (reg >> ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT) 1128 & ASIC_STS_SBUS_RESULT_DATA_OUT_MASK; 1129 break; 1130 } 1131 1132 if (!success) { 1133 dd_dev_err(dd, "%s: read failed, result code 0x%x\n", __func__, 1134 result_code); 1135 } 1136 1137 return result; 1138 } 1139 1140 /* 1141 * Turn off the SBus and fabric serdes spicos. 1142 * 1143 * + Must be called with Sbus fast mode turned on. 1144 * + Must be called after fabric serdes broadcast is set up. 1145 * + Must be called before the 8051 is loaded - assumes 8051 is not loaded 1146 * when using MISC_CFG_FW_CTRL. 1147 */ 1148 static void turn_off_spicos(struct hfi1_devdata *dd, int flags) 1149 { 1150 /* only needed on A0 */ 1151 if (!is_ax(dd)) 1152 return; 1153 1154 dd_dev_info(dd, "Turning off spicos:%s%s\n", 1155 flags & SPICO_SBUS ? " SBus" : "", 1156 flags & SPICO_FABRIC ? " fabric" : ""); 1157 1158 write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK); 1159 /* disable SBus spico */ 1160 if (flags & SPICO_SBUS) 1161 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01, 1162 WRITE_SBUS_RECEIVER, 0x00000040); 1163 1164 /* disable the fabric serdes spicos */ 1165 if (flags & SPICO_FABRIC) 1166 sbus_request(dd, fabric_serdes_broadcast[dd->hfi1_id], 1167 0x07, WRITE_SBUS_RECEIVER, 0x00000000); 1168 write_csr(dd, MISC_CFG_FW_CTRL, 0); 1169 } 1170 1171 /* 1172 * Reset all of the fabric serdes for this HFI in preparation to take the 1173 * link to Polling. 1174 * 1175 * To do a reset, we need to write to to the serdes registers. Unfortunately, 1176 * the fabric serdes download to the other HFI on the ASIC will have turned 1177 * off the firmware validation on this HFI. This means we can't write to the 1178 * registers to reset the serdes. Work around this by performing a complete 1179 * re-download and validation of the fabric serdes firmware. This, as a 1180 * by-product, will reset the serdes. NOTE: the re-download requires that 1181 * the 8051 be in the Offline state. I.e. not actively trying to use the 1182 * serdes. This routine is called at the point where the link is Offline and 1183 * is getting ready to go to Polling. 1184 */ 1185 void fabric_serdes_reset(struct hfi1_devdata *dd) 1186 { 1187 int ret; 1188 1189 if (!fw_fabric_serdes_load) 1190 return; 1191 1192 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1193 if (ret) { 1194 dd_dev_err(dd, 1195 "Cannot acquire SBus resource to reset fabric SerDes - perhaps you should reboot\n"); 1196 return; 1197 } 1198 set_sbus_fast_mode(dd); 1199 1200 if (is_ax(dd)) { 1201 /* A0 serdes do not work with a re-download */ 1202 u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; 1203 1204 /* place SerDes in reset and disable SPICO */ 1205 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011); 1206 /* wait 100 refclk cycles @ 156.25MHz => 640ns */ 1207 udelay(1); 1208 /* remove SerDes reset */ 1209 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010); 1210 /* turn SPICO enable on */ 1211 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002); 1212 } else { 1213 turn_off_spicos(dd, SPICO_FABRIC); 1214 /* 1215 * No need for firmware retry - what to download has already 1216 * been decided. 1217 * No need to pay attention to the load return - the only 1218 * failure is a validation failure, which has already been 1219 * checked by the initial download. 1220 */ 1221 (void)load_fabric_serdes_firmware(dd, &fw_fabric); 1222 } 1223 1224 clear_sbus_fast_mode(dd); 1225 release_chip_resource(dd, CR_SBUS); 1226 } 1227 1228 /* Access to the SBus in this routine should probably be serialized */ 1229 int sbus_request_slow(struct hfi1_devdata *dd, 1230 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in) 1231 { 1232 u64 reg, count = 0; 1233 1234 /* make sure fast mode is clear */ 1235 clear_sbus_fast_mode(dd); 1236 1237 sbus_request(dd, receiver_addr, data_addr, command, data_in); 1238 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 1239 ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK); 1240 /* Wait for both DONE and RCV_DATA_VALID to go high */ 1241 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1242 while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) && 1243 (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) { 1244 if (count++ >= SBUS_MAX_POLL_COUNT) { 1245 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); 1246 /* 1247 * If the loop has timed out, we are OK if DONE bit 1248 * is set and RCV_DATA_VALID and EXECUTE counters 1249 * are the same. If not, we cannot proceed. 1250 */ 1251 if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) && 1252 (SBUS_COUNTER(counts, RCV_DATA_VALID) == 1253 SBUS_COUNTER(counts, EXECUTE))) 1254 break; 1255 return -ETIMEDOUT; 1256 } 1257 udelay(1); 1258 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1259 } 1260 count = 0; 1261 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0); 1262 /* Wait for DONE to clear after EXECUTE is cleared */ 1263 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1264 while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) { 1265 if (count++ >= SBUS_MAX_POLL_COUNT) 1266 return -ETIME; 1267 udelay(1); 1268 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1269 } 1270 return 0; 1271 } 1272 1273 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd, 1274 struct firmware_details *fdet) 1275 { 1276 int i, err; 1277 const u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; /* receiver addr */ 1278 1279 dd_dev_info(dd, "Downloading fabric firmware\n"); 1280 1281 /* step 1: load security variables */ 1282 load_security_variables(dd, fdet); 1283 /* step 2: place SerDes in reset and disable SPICO */ 1284 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011); 1285 /* wait 100 refclk cycles @ 156.25MHz => 640ns */ 1286 udelay(1); 1287 /* step 3: remove SerDes reset */ 1288 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010); 1289 /* step 4: assert IMEM override */ 1290 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x40000000); 1291 /* step 5: download SerDes machine code */ 1292 for (i = 0; i < fdet->firmware_len; i += 4) { 1293 sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER, 1294 *(u32 *)&fdet->firmware_ptr[i]); 1295 } 1296 /* step 6: IMEM override off */ 1297 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000); 1298 /* step 7: turn ECC on */ 1299 sbus_request(dd, ra, 0x0b, WRITE_SBUS_RECEIVER, 0x000c0000); 1300 1301 /* steps 8-11: run the RSA engine */ 1302 err = run_rsa(dd, "fabric serdes", fdet->signature); 1303 if (err) 1304 return err; 1305 1306 /* step 12: turn SPICO enable on */ 1307 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002); 1308 /* step 13: enable core hardware interrupts */ 1309 sbus_request(dd, ra, 0x08, WRITE_SBUS_RECEIVER, 0x00000000); 1310 1311 return 0; 1312 } 1313 1314 static int load_sbus_firmware(struct hfi1_devdata *dd, 1315 struct firmware_details *fdet) 1316 { 1317 int i, err; 1318 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */ 1319 1320 dd_dev_info(dd, "Downloading SBus firmware\n"); 1321 1322 /* step 1: load security variables */ 1323 load_security_variables(dd, fdet); 1324 /* step 2: place SPICO into reset and enable off */ 1325 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x000000c0); 1326 /* step 3: remove reset, enable off, IMEM_CNTRL_EN on */ 1327 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000240); 1328 /* step 4: set starting IMEM address for burst download */ 1329 sbus_request(dd, ra, 0x03, WRITE_SBUS_RECEIVER, 0x80000000); 1330 /* step 5: download the SBus Master machine code */ 1331 for (i = 0; i < fdet->firmware_len; i += 4) { 1332 sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER, 1333 *(u32 *)&fdet->firmware_ptr[i]); 1334 } 1335 /* step 6: set IMEM_CNTL_EN off */ 1336 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040); 1337 /* step 7: turn ECC on */ 1338 sbus_request(dd, ra, 0x16, WRITE_SBUS_RECEIVER, 0x000c0000); 1339 1340 /* steps 8-11: run the RSA engine */ 1341 err = run_rsa(dd, "SBus", fdet->signature); 1342 if (err) 1343 return err; 1344 1345 /* step 12: set SPICO_ENABLE on */ 1346 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140); 1347 1348 return 0; 1349 } 1350 1351 static int load_pcie_serdes_firmware(struct hfi1_devdata *dd, 1352 struct firmware_details *fdet) 1353 { 1354 int i; 1355 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */ 1356 1357 dd_dev_info(dd, "Downloading PCIe firmware\n"); 1358 1359 /* step 1: load security variables */ 1360 load_security_variables(dd, fdet); 1361 /* step 2: assert single step (halts the SBus Master spico) */ 1362 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000001); 1363 /* step 3: enable XDMEM access */ 1364 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40); 1365 /* step 4: load firmware into SBus Master XDMEM */ 1366 /* 1367 * NOTE: the dmem address, write_en, and wdata are all pre-packed, 1368 * we only need to pick up the bytes and write them 1369 */ 1370 for (i = 0; i < fdet->firmware_len; i += 4) { 1371 sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER, 1372 *(u32 *)&fdet->firmware_ptr[i]); 1373 } 1374 /* step 5: disable XDMEM access */ 1375 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140); 1376 /* step 6: allow SBus Spico to run */ 1377 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000); 1378 1379 /* 1380 * steps 7-11: run RSA, if it succeeds, firmware is available to 1381 * be swapped 1382 */ 1383 return run_rsa(dd, "PCIe serdes", fdet->signature); 1384 } 1385 1386 /* 1387 * Set the given broadcast values on the given list of devices. 1388 */ 1389 static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2, 1390 const u8 *addrs, int count) 1391 { 1392 while (--count >= 0) { 1393 /* 1394 * Set BROADCAST_GROUP_1 and BROADCAST_GROUP_2, leave 1395 * defaults for everything else. Do not read-modify-write, 1396 * per instruction from the manufacturer. 1397 * 1398 * Register 0xfd: 1399 * bits what 1400 * ----- --------------------------------- 1401 * 0 IGNORE_BROADCAST (default 0) 1402 * 11:4 BROADCAST_GROUP_1 (default 0xff) 1403 * 23:16 BROADCAST_GROUP_2 (default 0xff) 1404 */ 1405 sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER, 1406 (u32)bg1 << 4 | (u32)bg2 << 16); 1407 } 1408 } 1409 1410 int acquire_hw_mutex(struct hfi1_devdata *dd) 1411 { 1412 unsigned long timeout; 1413 int try = 0; 1414 u8 mask = 1 << dd->hfi1_id; 1415 u8 user; 1416 1417 retry: 1418 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies; 1419 while (1) { 1420 write_csr(dd, ASIC_CFG_MUTEX, mask); 1421 user = (u8)read_csr(dd, ASIC_CFG_MUTEX); 1422 if (user == mask) 1423 return 0; /* success */ 1424 if (time_after(jiffies, timeout)) 1425 break; /* timed out */ 1426 msleep(20); 1427 } 1428 1429 /* timed out */ 1430 dd_dev_err(dd, 1431 "Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n", 1432 (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up"); 1433 1434 if (try == 0) { 1435 /* break mutex and retry */ 1436 write_csr(dd, ASIC_CFG_MUTEX, 0); 1437 try++; 1438 goto retry; 1439 } 1440 1441 return -EBUSY; 1442 } 1443 1444 void release_hw_mutex(struct hfi1_devdata *dd) 1445 { 1446 write_csr(dd, ASIC_CFG_MUTEX, 0); 1447 } 1448 1449 /* return the given resource bit(s) as a mask for the given HFI */ 1450 static inline u64 resource_mask(u32 hfi1_id, u32 resource) 1451 { 1452 return ((u64)resource) << (hfi1_id ? CR_DYN_SHIFT : 0); 1453 } 1454 1455 static void fail_mutex_acquire_message(struct hfi1_devdata *dd, 1456 const char *func) 1457 { 1458 dd_dev_err(dd, 1459 "%s: hardware mutex stuck - suggest rebooting the machine\n", 1460 func); 1461 } 1462 1463 /* 1464 * Acquire access to a chip resource. 1465 * 1466 * Return 0 on success, -EBUSY if resource busy, -EIO if mutex acquire failed. 1467 */ 1468 static int __acquire_chip_resource(struct hfi1_devdata *dd, u32 resource) 1469 { 1470 u64 scratch0, all_bits, my_bit; 1471 int ret; 1472 1473 if (resource & CR_DYN_MASK) { 1474 /* a dynamic resource is in use if either HFI has set the bit */ 1475 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0 && 1476 (resource & (CR_I2C1 | CR_I2C2))) { 1477 /* discrete devices must serialize across both chains */ 1478 all_bits = resource_mask(0, CR_I2C1 | CR_I2C2) | 1479 resource_mask(1, CR_I2C1 | CR_I2C2); 1480 } else { 1481 all_bits = resource_mask(0, resource) | 1482 resource_mask(1, resource); 1483 } 1484 my_bit = resource_mask(dd->hfi1_id, resource); 1485 } else { 1486 /* non-dynamic resources are not split between HFIs */ 1487 all_bits = resource; 1488 my_bit = resource; 1489 } 1490 1491 /* lock against other callers within the driver wanting a resource */ 1492 mutex_lock(&dd->asic_data->asic_resource_mutex); 1493 1494 ret = acquire_hw_mutex(dd); 1495 if (ret) { 1496 fail_mutex_acquire_message(dd, __func__); 1497 ret = -EIO; 1498 goto done; 1499 } 1500 1501 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1502 if (scratch0 & all_bits) { 1503 ret = -EBUSY; 1504 } else { 1505 write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit); 1506 /* force write to be visible to other HFI on another OS */ 1507 (void)read_csr(dd, ASIC_CFG_SCRATCH); 1508 } 1509 1510 release_hw_mutex(dd); 1511 1512 done: 1513 mutex_unlock(&dd->asic_data->asic_resource_mutex); 1514 return ret; 1515 } 1516 1517 /* 1518 * Acquire access to a chip resource, wait up to mswait milliseconds for 1519 * the resource to become available. 1520 * 1521 * Return 0 on success, -EBUSY if busy (even after wait), -EIO if mutex 1522 * acquire failed. 1523 */ 1524 int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait) 1525 { 1526 unsigned long timeout; 1527 int ret; 1528 1529 timeout = jiffies + msecs_to_jiffies(mswait); 1530 while (1) { 1531 ret = __acquire_chip_resource(dd, resource); 1532 if (ret != -EBUSY) 1533 return ret; 1534 /* resource is busy, check our timeout */ 1535 if (time_after_eq(jiffies, timeout)) 1536 return -EBUSY; 1537 usleep_range(80, 120); /* arbitrary delay */ 1538 } 1539 } 1540 1541 /* 1542 * Release access to a chip resource 1543 */ 1544 void release_chip_resource(struct hfi1_devdata *dd, u32 resource) 1545 { 1546 u64 scratch0, bit; 1547 1548 /* only dynamic resources should ever be cleared */ 1549 if (!(resource & CR_DYN_MASK)) { 1550 dd_dev_err(dd, "%s: invalid resource 0x%x\n", __func__, 1551 resource); 1552 return; 1553 } 1554 bit = resource_mask(dd->hfi1_id, resource); 1555 1556 /* lock against other callers within the driver wanting a resource */ 1557 mutex_lock(&dd->asic_data->asic_resource_mutex); 1558 1559 if (acquire_hw_mutex(dd)) { 1560 fail_mutex_acquire_message(dd, __func__); 1561 goto done; 1562 } 1563 1564 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1565 if ((scratch0 & bit) != 0) { 1566 scratch0 &= ~bit; 1567 write_csr(dd, ASIC_CFG_SCRATCH, scratch0); 1568 /* force write to be visible to other HFI on another OS */ 1569 (void)read_csr(dd, ASIC_CFG_SCRATCH); 1570 } else { 1571 dd_dev_warn(dd, "%s: id %d, resource 0x%x: bit not set\n", 1572 __func__, dd->hfi1_id, resource); 1573 } 1574 1575 release_hw_mutex(dd); 1576 1577 done: 1578 mutex_unlock(&dd->asic_data->asic_resource_mutex); 1579 } 1580 1581 /* 1582 * Return true if resource is set, false otherwise. Print a warning 1583 * if not set and a function is supplied. 1584 */ 1585 bool check_chip_resource(struct hfi1_devdata *dd, u32 resource, 1586 const char *func) 1587 { 1588 u64 scratch0, bit; 1589 1590 if (resource & CR_DYN_MASK) 1591 bit = resource_mask(dd->hfi1_id, resource); 1592 else 1593 bit = resource; 1594 1595 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1596 if ((scratch0 & bit) == 0) { 1597 if (func) 1598 dd_dev_warn(dd, 1599 "%s: id %d, resource 0x%x, not acquired!\n", 1600 func, dd->hfi1_id, resource); 1601 return false; 1602 } 1603 return true; 1604 } 1605 1606 static void clear_chip_resources(struct hfi1_devdata *dd, const char *func) 1607 { 1608 u64 scratch0; 1609 1610 /* lock against other callers within the driver wanting a resource */ 1611 mutex_lock(&dd->asic_data->asic_resource_mutex); 1612 1613 if (acquire_hw_mutex(dd)) { 1614 fail_mutex_acquire_message(dd, func); 1615 goto done; 1616 } 1617 1618 /* clear all dynamic access bits for this HFI */ 1619 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1620 scratch0 &= ~resource_mask(dd->hfi1_id, CR_DYN_MASK); 1621 write_csr(dd, ASIC_CFG_SCRATCH, scratch0); 1622 /* force write to be visible to other HFI on another OS */ 1623 (void)read_csr(dd, ASIC_CFG_SCRATCH); 1624 1625 release_hw_mutex(dd); 1626 1627 done: 1628 mutex_unlock(&dd->asic_data->asic_resource_mutex); 1629 } 1630 1631 void init_chip_resources(struct hfi1_devdata *dd) 1632 { 1633 /* clear any holds left by us */ 1634 clear_chip_resources(dd, __func__); 1635 } 1636 1637 void finish_chip_resources(struct hfi1_devdata *dd) 1638 { 1639 /* clear any holds left by us */ 1640 clear_chip_resources(dd, __func__); 1641 } 1642 1643 void set_sbus_fast_mode(struct hfi1_devdata *dd) 1644 { 1645 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 1646 ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK); 1647 } 1648 1649 void clear_sbus_fast_mode(struct hfi1_devdata *dd) 1650 { 1651 u64 reg, count = 0; 1652 1653 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); 1654 while (SBUS_COUNTER(reg, EXECUTE) != 1655 SBUS_COUNTER(reg, RCV_DATA_VALID)) { 1656 if (count++ >= SBUS_MAX_POLL_COUNT) 1657 break; 1658 udelay(1); 1659 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); 1660 } 1661 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0); 1662 } 1663 1664 int load_firmware(struct hfi1_devdata *dd) 1665 { 1666 int ret; 1667 1668 if (fw_fabric_serdes_load) { 1669 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1670 if (ret) 1671 return ret; 1672 1673 set_sbus_fast_mode(dd); 1674 1675 set_serdes_broadcast(dd, all_fabric_serdes_broadcast, 1676 fabric_serdes_broadcast[dd->hfi1_id], 1677 fabric_serdes_addrs[dd->hfi1_id], 1678 NUM_FABRIC_SERDES); 1679 turn_off_spicos(dd, SPICO_FABRIC); 1680 do { 1681 ret = load_fabric_serdes_firmware(dd, &fw_fabric); 1682 } while (retry_firmware(dd, ret)); 1683 1684 clear_sbus_fast_mode(dd); 1685 release_chip_resource(dd, CR_SBUS); 1686 if (ret) 1687 return ret; 1688 } 1689 1690 if (fw_8051_load) { 1691 do { 1692 ret = load_8051_firmware(dd, &fw_8051); 1693 } while (retry_firmware(dd, ret)); 1694 if (ret) 1695 return ret; 1696 } 1697 1698 dump_fw_version(dd); 1699 return 0; 1700 } 1701 1702 int hfi1_firmware_init(struct hfi1_devdata *dd) 1703 { 1704 /* only RTL can use these */ 1705 if (dd->icode != ICODE_RTL_SILICON) { 1706 fw_fabric_serdes_load = 0; 1707 fw_pcie_serdes_load = 0; 1708 fw_sbus_load = 0; 1709 } 1710 1711 /* no 8051 or QSFP on simulator */ 1712 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 1713 fw_8051_load = 0; 1714 platform_config_load = 0; 1715 } 1716 1717 if (!fw_8051_name) { 1718 if (dd->icode == ICODE_RTL_SILICON) 1719 fw_8051_name = DEFAULT_FW_8051_NAME_ASIC; 1720 else 1721 fw_8051_name = DEFAULT_FW_8051_NAME_FPGA; 1722 } 1723 if (!fw_fabric_serdes_name) 1724 fw_fabric_serdes_name = DEFAULT_FW_FABRIC_NAME; 1725 if (!fw_sbus_name) 1726 fw_sbus_name = DEFAULT_FW_SBUS_NAME; 1727 if (!fw_pcie_serdes_name) 1728 fw_pcie_serdes_name = DEFAULT_FW_PCIE_NAME; 1729 if (!platform_config_name) 1730 platform_config_name = DEFAULT_PLATFORM_CONFIG_NAME; 1731 1732 return obtain_firmware(dd); 1733 } 1734 1735 /* 1736 * This function is a helper function for parse_platform_config(...) and 1737 * does not check for validity of the platform configuration cache 1738 * (because we know it is invalid as we are building up the cache). 1739 * As such, this should not be called from anywhere other than 1740 * parse_platform_config 1741 */ 1742 static int check_meta_version(struct hfi1_devdata *dd, u32 *system_table) 1743 { 1744 u32 meta_ver, meta_ver_meta, ver_start, ver_len, mask; 1745 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 1746 1747 if (!system_table) 1748 return -EINVAL; 1749 1750 meta_ver_meta = 1751 *(pcfgcache->config_tables[PLATFORM_CONFIG_SYSTEM_TABLE].table_metadata 1752 + SYSTEM_TABLE_META_VERSION); 1753 1754 mask = ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1); 1755 ver_start = meta_ver_meta & mask; 1756 1757 meta_ver_meta >>= METADATA_TABLE_FIELD_LEN_SHIFT; 1758 1759 mask = ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1); 1760 ver_len = meta_ver_meta & mask; 1761 1762 ver_start /= 8; 1763 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1); 1764 1765 if (meta_ver < 5) { 1766 dd_dev_info( 1767 dd, "%s:Please update platform config\n", __func__); 1768 return -EINVAL; 1769 } 1770 return 0; 1771 } 1772 1773 int parse_platform_config(struct hfi1_devdata *dd) 1774 { 1775 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 1776 u32 *ptr = NULL; 1777 u32 header1 = 0, header2 = 0, magic_num = 0, crc = 0, file_length = 0; 1778 u32 record_idx = 0, table_type = 0, table_length_dwords = 0; 1779 int ret = -EINVAL; /* assume failure */ 1780 1781 /* 1782 * For integrated devices that did not fall back to the default file, 1783 * the SI tuning information for active channels is acquired from the 1784 * scratch register bitmap, thus there is no platform config to parse. 1785 * Skip parsing in these situations. 1786 */ 1787 if (is_integrated(dd) && !platform_config_load) 1788 return 0; 1789 1790 if (!dd->platform_config.data) { 1791 dd_dev_err(dd, "%s: Missing config file\n", __func__); 1792 goto bail; 1793 } 1794 ptr = (u32 *)dd->platform_config.data; 1795 1796 magic_num = *ptr; 1797 ptr++; 1798 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) { 1799 dd_dev_err(dd, "%s: Bad config file\n", __func__); 1800 goto bail; 1801 } 1802 1803 /* Field is file size in DWORDs */ 1804 file_length = (*ptr) * 4; 1805 ptr++; 1806 1807 if (file_length > dd->platform_config.size) { 1808 dd_dev_info(dd, "%s:File claims to be larger than read size\n", 1809 __func__); 1810 goto bail; 1811 } else if (file_length < dd->platform_config.size) { 1812 dd_dev_info(dd, 1813 "%s:File claims to be smaller than read size, continuing\n", 1814 __func__); 1815 } 1816 /* exactly equal, perfection */ 1817 1818 /* 1819 * In both cases where we proceed, using the self-reported file length 1820 * is the safer option 1821 */ 1822 while (ptr < (u32 *)(dd->platform_config.data + file_length)) { 1823 header1 = *ptr; 1824 header2 = *(ptr + 1); 1825 if (header1 != ~header2) { 1826 dd_dev_err(dd, "%s: Failed validation at offset %ld\n", 1827 __func__, (ptr - (u32 *) 1828 dd->platform_config.data)); 1829 goto bail; 1830 } 1831 1832 record_idx = *ptr & 1833 ((1 << PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS) - 1); 1834 1835 table_length_dwords = (*ptr >> 1836 PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT) & 1837 ((1 << PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS) - 1); 1838 1839 table_type = (*ptr >> PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT) & 1840 ((1 << PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS) - 1); 1841 1842 /* Done with this set of headers */ 1843 ptr += 2; 1844 1845 if (record_idx) { 1846 /* data table */ 1847 switch (table_type) { 1848 case PLATFORM_CONFIG_SYSTEM_TABLE: 1849 pcfgcache->config_tables[table_type].num_table = 1850 1; 1851 ret = check_meta_version(dd, ptr); 1852 if (ret) 1853 goto bail; 1854 break; 1855 case PLATFORM_CONFIG_PORT_TABLE: 1856 pcfgcache->config_tables[table_type].num_table = 1857 2; 1858 break; 1859 case PLATFORM_CONFIG_RX_PRESET_TABLE: 1860 /* fall through */ 1861 case PLATFORM_CONFIG_TX_PRESET_TABLE: 1862 /* fall through */ 1863 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 1864 /* fall through */ 1865 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 1866 pcfgcache->config_tables[table_type].num_table = 1867 table_length_dwords; 1868 break; 1869 default: 1870 dd_dev_err(dd, 1871 "%s: Unknown data table %d, offset %ld\n", 1872 __func__, table_type, 1873 (ptr - (u32 *) 1874 dd->platform_config.data)); 1875 goto bail; /* We don't trust this file now */ 1876 } 1877 pcfgcache->config_tables[table_type].table = ptr; 1878 } else { 1879 /* metadata table */ 1880 switch (table_type) { 1881 case PLATFORM_CONFIG_SYSTEM_TABLE: 1882 /* fall through */ 1883 case PLATFORM_CONFIG_PORT_TABLE: 1884 /* fall through */ 1885 case PLATFORM_CONFIG_RX_PRESET_TABLE: 1886 /* fall through */ 1887 case PLATFORM_CONFIG_TX_PRESET_TABLE: 1888 /* fall through */ 1889 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 1890 /* fall through */ 1891 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 1892 break; 1893 default: 1894 dd_dev_err(dd, 1895 "%s: Unknown meta table %d, offset %ld\n", 1896 __func__, table_type, 1897 (ptr - 1898 (u32 *)dd->platform_config.data)); 1899 goto bail; /* We don't trust this file now */ 1900 } 1901 pcfgcache->config_tables[table_type].table_metadata = 1902 ptr; 1903 } 1904 1905 /* Calculate and check table crc */ 1906 crc = crc32_le(~(u32)0, (unsigned char const *)ptr, 1907 (table_length_dwords * 4)); 1908 crc ^= ~(u32)0; 1909 1910 /* Jump the table */ 1911 ptr += table_length_dwords; 1912 if (crc != *ptr) { 1913 dd_dev_err(dd, "%s: Failed CRC check at offset %ld\n", 1914 __func__, (ptr - 1915 (u32 *)dd->platform_config.data)); 1916 goto bail; 1917 } 1918 /* Jump the CRC DWORD */ 1919 ptr++; 1920 } 1921 1922 pcfgcache->cache_valid = 1; 1923 return 0; 1924 bail: 1925 memset(pcfgcache, 0, sizeof(struct platform_config_cache)); 1926 return ret; 1927 } 1928 1929 static void get_integrated_platform_config_field( 1930 struct hfi1_devdata *dd, 1931 enum platform_config_table_type_encoding table_type, 1932 int field_index, u32 *data) 1933 { 1934 struct hfi1_pportdata *ppd = dd->pport; 1935 u8 *cache = ppd->qsfp_info.cache; 1936 u32 tx_preset = 0; 1937 1938 switch (table_type) { 1939 case PLATFORM_CONFIG_SYSTEM_TABLE: 1940 if (field_index == SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) 1941 *data = ppd->max_power_class; 1942 else if (field_index == SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G) 1943 *data = ppd->default_atten; 1944 break; 1945 case PLATFORM_CONFIG_PORT_TABLE: 1946 if (field_index == PORT_TABLE_PORT_TYPE) 1947 *data = ppd->port_type; 1948 else if (field_index == PORT_TABLE_LOCAL_ATTEN_25G) 1949 *data = ppd->local_atten; 1950 else if (field_index == PORT_TABLE_REMOTE_ATTEN_25G) 1951 *data = ppd->remote_atten; 1952 break; 1953 case PLATFORM_CONFIG_RX_PRESET_TABLE: 1954 if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR_APPLY) 1955 *data = (ppd->rx_preset & QSFP_RX_CDR_APPLY_SMASK) >> 1956 QSFP_RX_CDR_APPLY_SHIFT; 1957 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP_APPLY) 1958 *data = (ppd->rx_preset & QSFP_RX_EMP_APPLY_SMASK) >> 1959 QSFP_RX_EMP_APPLY_SHIFT; 1960 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP_APPLY) 1961 *data = (ppd->rx_preset & QSFP_RX_AMP_APPLY_SMASK) >> 1962 QSFP_RX_AMP_APPLY_SHIFT; 1963 else if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR) 1964 *data = (ppd->rx_preset & QSFP_RX_CDR_SMASK) >> 1965 QSFP_RX_CDR_SHIFT; 1966 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP) 1967 *data = (ppd->rx_preset & QSFP_RX_EMP_SMASK) >> 1968 QSFP_RX_EMP_SHIFT; 1969 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP) 1970 *data = (ppd->rx_preset & QSFP_RX_AMP_SMASK) >> 1971 QSFP_RX_AMP_SHIFT; 1972 break; 1973 case PLATFORM_CONFIG_TX_PRESET_TABLE: 1974 if (cache[QSFP_EQ_INFO_OFFS] & 0x4) 1975 tx_preset = ppd->tx_preset_eq; 1976 else 1977 tx_preset = ppd->tx_preset_noeq; 1978 if (field_index == TX_PRESET_TABLE_PRECUR) 1979 *data = (tx_preset & TX_PRECUR_SMASK) >> 1980 TX_PRECUR_SHIFT; 1981 else if (field_index == TX_PRESET_TABLE_ATTN) 1982 *data = (tx_preset & TX_ATTN_SMASK) >> 1983 TX_ATTN_SHIFT; 1984 else if (field_index == TX_PRESET_TABLE_POSTCUR) 1985 *data = (tx_preset & TX_POSTCUR_SMASK) >> 1986 TX_POSTCUR_SHIFT; 1987 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR_APPLY) 1988 *data = (tx_preset & QSFP_TX_CDR_APPLY_SMASK) >> 1989 QSFP_TX_CDR_APPLY_SHIFT; 1990 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ_APPLY) 1991 *data = (tx_preset & QSFP_TX_EQ_APPLY_SMASK) >> 1992 QSFP_TX_EQ_APPLY_SHIFT; 1993 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR) 1994 *data = (tx_preset & QSFP_TX_CDR_SMASK) >> 1995 QSFP_TX_CDR_SHIFT; 1996 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ) 1997 *data = (tx_preset & QSFP_TX_EQ_SMASK) >> 1998 QSFP_TX_EQ_SHIFT; 1999 break; 2000 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 2001 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 2002 default: 2003 break; 2004 } 2005 } 2006 2007 static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table, 2008 int field, u32 *field_len_bits, 2009 u32 *field_start_bits) 2010 { 2011 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 2012 u32 *src_ptr = NULL; 2013 2014 if (!pcfgcache->cache_valid) 2015 return -EINVAL; 2016 2017 switch (table) { 2018 case PLATFORM_CONFIG_SYSTEM_TABLE: 2019 /* fall through */ 2020 case PLATFORM_CONFIG_PORT_TABLE: 2021 /* fall through */ 2022 case PLATFORM_CONFIG_RX_PRESET_TABLE: 2023 /* fall through */ 2024 case PLATFORM_CONFIG_TX_PRESET_TABLE: 2025 /* fall through */ 2026 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 2027 /* fall through */ 2028 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 2029 if (field && field < platform_config_table_limits[table]) 2030 src_ptr = 2031 pcfgcache->config_tables[table].table_metadata + field; 2032 break; 2033 default: 2034 dd_dev_info(dd, "%s: Unknown table\n", __func__); 2035 break; 2036 } 2037 2038 if (!src_ptr) 2039 return -EINVAL; 2040 2041 if (field_start_bits) 2042 *field_start_bits = *src_ptr & 2043 ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1); 2044 2045 if (field_len_bits) 2046 *field_len_bits = (*src_ptr >> METADATA_TABLE_FIELD_LEN_SHIFT) 2047 & ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1); 2048 2049 return 0; 2050 } 2051 2052 /* This is the central interface to getting data out of the platform config 2053 * file. It depends on parse_platform_config() having populated the 2054 * platform_config_cache in hfi1_devdata, and checks the cache_valid member to 2055 * validate the sanity of the cache. 2056 * 2057 * The non-obvious parameters: 2058 * @table_index: Acts as a look up key into which instance of the tables the 2059 * relevant field is fetched from. 2060 * 2061 * This applies to the data tables that have multiple instances. The port table 2062 * is an exception to this rule as each HFI only has one port and thus the 2063 * relevant table can be distinguished by hfi_id. 2064 * 2065 * @data: pointer to memory that will be populated with the field requested. 2066 * @len: length of memory pointed by @data in bytes. 2067 */ 2068 int get_platform_config_field(struct hfi1_devdata *dd, 2069 enum platform_config_table_type_encoding 2070 table_type, int table_index, int field_index, 2071 u32 *data, u32 len) 2072 { 2073 int ret = 0, wlen = 0, seek = 0; 2074 u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL; 2075 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 2076 2077 if (data) 2078 memset(data, 0, len); 2079 else 2080 return -EINVAL; 2081 2082 if (is_integrated(dd) && !platform_config_load) { 2083 /* 2084 * Use saved configuration from ppd for integrated platforms 2085 */ 2086 get_integrated_platform_config_field(dd, table_type, 2087 field_index, data); 2088 return 0; 2089 } 2090 2091 ret = get_platform_fw_field_metadata(dd, table_type, field_index, 2092 &field_len_bits, 2093 &field_start_bits); 2094 if (ret) 2095 return -EINVAL; 2096 2097 /* Convert length to bits */ 2098 len *= 8; 2099 2100 /* Our metadata function checked cache_valid and field_index for us */ 2101 switch (table_type) { 2102 case PLATFORM_CONFIG_SYSTEM_TABLE: 2103 src_ptr = pcfgcache->config_tables[table_type].table; 2104 2105 if (field_index != SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) { 2106 if (len < field_len_bits) 2107 return -EINVAL; 2108 2109 seek = field_start_bits / 8; 2110 wlen = field_len_bits / 8; 2111 2112 src_ptr = (u32 *)((u8 *)src_ptr + seek); 2113 2114 /* 2115 * We expect the field to be byte aligned and whole byte 2116 * lengths if we are here 2117 */ 2118 memcpy(data, src_ptr, wlen); 2119 return 0; 2120 } 2121 break; 2122 case PLATFORM_CONFIG_PORT_TABLE: 2123 /* Port table is 4 DWORDS */ 2124 src_ptr = dd->hfi1_id ? 2125 pcfgcache->config_tables[table_type].table + 4 : 2126 pcfgcache->config_tables[table_type].table; 2127 break; 2128 case PLATFORM_CONFIG_RX_PRESET_TABLE: 2129 /* fall through */ 2130 case PLATFORM_CONFIG_TX_PRESET_TABLE: 2131 /* fall through */ 2132 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 2133 /* fall through */ 2134 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 2135 src_ptr = pcfgcache->config_tables[table_type].table; 2136 2137 if (table_index < 2138 pcfgcache->config_tables[table_type].num_table) 2139 src_ptr += table_index; 2140 else 2141 src_ptr = NULL; 2142 break; 2143 default: 2144 dd_dev_info(dd, "%s: Unknown table\n", __func__); 2145 break; 2146 } 2147 2148 if (!src_ptr || len < field_len_bits) 2149 return -EINVAL; 2150 2151 src_ptr += (field_start_bits / 32); 2152 *data = (*src_ptr >> (field_start_bits % 32)) & 2153 ((1 << field_len_bits) - 1); 2154 2155 return 0; 2156 } 2157 2158 /* 2159 * Download the firmware needed for the Gen3 PCIe SerDes. An update 2160 * to the SBus firmware is needed before updating the PCIe firmware. 2161 * 2162 * Note: caller must be holding the SBus resource. 2163 */ 2164 int load_pcie_firmware(struct hfi1_devdata *dd) 2165 { 2166 int ret = 0; 2167 2168 /* both firmware loads below use the SBus */ 2169 set_sbus_fast_mode(dd); 2170 2171 if (fw_sbus_load) { 2172 turn_off_spicos(dd, SPICO_SBUS); 2173 do { 2174 ret = load_sbus_firmware(dd, &fw_sbus); 2175 } while (retry_firmware(dd, ret)); 2176 if (ret) 2177 goto done; 2178 } 2179 2180 if (fw_pcie_serdes_load) { 2181 dd_dev_info(dd, "Setting PCIe SerDes broadcast\n"); 2182 set_serdes_broadcast(dd, all_pcie_serdes_broadcast, 2183 pcie_serdes_broadcast[dd->hfi1_id], 2184 pcie_serdes_addrs[dd->hfi1_id], 2185 NUM_PCIE_SERDES); 2186 do { 2187 ret = load_pcie_serdes_firmware(dd, &fw_pcie); 2188 } while (retry_firmware(dd, ret)); 2189 if (ret) 2190 goto done; 2191 } 2192 2193 done: 2194 clear_sbus_fast_mode(dd); 2195 2196 return ret; 2197 } 2198 2199 /* 2200 * Read the GUID from the hardware, store it in dd. 2201 */ 2202 void read_guid(struct hfi1_devdata *dd) 2203 { 2204 /* Take the DC out of reset to get a valid GUID value */ 2205 write_csr(dd, CCE_DC_CTRL, 0); 2206 (void)read_csr(dd, CCE_DC_CTRL); 2207 2208 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID); 2209 dd_dev_info(dd, "GUID %llx", 2210 (unsigned long long)dd->base_guid); 2211 } 2212 2213 /* read and display firmware version info */ 2214 static void dump_fw_version(struct hfi1_devdata *dd) 2215 { 2216 u32 pcie_vers[NUM_PCIE_SERDES]; 2217 u32 fabric_vers[NUM_FABRIC_SERDES]; 2218 u32 sbus_vers; 2219 int i; 2220 int all_same; 2221 int ret; 2222 u8 rcv_addr; 2223 2224 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 2225 if (ret) { 2226 dd_dev_err(dd, "Unable to acquire SBus to read firmware versions\n"); 2227 return; 2228 } 2229 2230 /* set fast mode */ 2231 set_sbus_fast_mode(dd); 2232 2233 /* read version for SBus Master */ 2234 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x02, WRITE_SBUS_RECEIVER, 0); 2235 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x07, WRITE_SBUS_RECEIVER, 0x1); 2236 /* wait for interrupt to be processed */ 2237 usleep_range(10000, 11000); 2238 sbus_vers = sbus_read(dd, SBUS_MASTER_BROADCAST, 0x08, 0x1); 2239 dd_dev_info(dd, "SBus Master firmware version 0x%08x\n", sbus_vers); 2240 2241 /* read version for PCIe SerDes */ 2242 all_same = 1; 2243 pcie_vers[0] = 0; 2244 for (i = 0; i < NUM_PCIE_SERDES; i++) { 2245 rcv_addr = pcie_serdes_addrs[dd->hfi1_id][i]; 2246 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0); 2247 /* wait for interrupt to be processed */ 2248 usleep_range(10000, 11000); 2249 pcie_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0); 2250 if (i > 0 && pcie_vers[0] != pcie_vers[i]) 2251 all_same = 0; 2252 } 2253 2254 if (all_same) { 2255 dd_dev_info(dd, "PCIe SerDes firmware version 0x%x\n", 2256 pcie_vers[0]); 2257 } else { 2258 dd_dev_warn(dd, "PCIe SerDes do not have the same firmware version\n"); 2259 for (i = 0; i < NUM_PCIE_SERDES; i++) { 2260 dd_dev_info(dd, 2261 "PCIe SerDes lane %d firmware version 0x%x\n", 2262 i, pcie_vers[i]); 2263 } 2264 } 2265 2266 /* read version for fabric SerDes */ 2267 all_same = 1; 2268 fabric_vers[0] = 0; 2269 for (i = 0; i < NUM_FABRIC_SERDES; i++) { 2270 rcv_addr = fabric_serdes_addrs[dd->hfi1_id][i]; 2271 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0); 2272 /* wait for interrupt to be processed */ 2273 usleep_range(10000, 11000); 2274 fabric_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0); 2275 if (i > 0 && fabric_vers[0] != fabric_vers[i]) 2276 all_same = 0; 2277 } 2278 2279 if (all_same) { 2280 dd_dev_info(dd, "Fabric SerDes firmware version 0x%x\n", 2281 fabric_vers[0]); 2282 } else { 2283 dd_dev_warn(dd, "Fabric SerDes do not have the same firmware version\n"); 2284 for (i = 0; i < NUM_FABRIC_SERDES; i++) { 2285 dd_dev_info(dd, 2286 "Fabric SerDes lane %d firmware version 0x%x\n", 2287 i, fabric_vers[i]); 2288 } 2289 } 2290 2291 clear_sbus_fast_mode(dd); 2292 release_chip_resource(dd, CR_SBUS); 2293 } 2294