1 /* 2 * Copyright(c) 2015, 2016 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 48 #include <linux/firmware.h> 49 #include <linux/mutex.h> 50 #include <linux/module.h> 51 #include <linux/delay.h> 52 #include <linux/crc32.h> 53 54 #include "hfi.h" 55 #include "trace.h" 56 57 /* 58 * Make it easy to toggle firmware file name and if it gets loaded by 59 * editing the following. This may be something we do while in development 60 * but not necessarily something a user would ever need to use. 61 */ 62 #define DEFAULT_FW_8051_NAME_FPGA "hfi_dc8051.bin" 63 #define DEFAULT_FW_8051_NAME_ASIC "hfi1_dc8051.fw" 64 #define DEFAULT_FW_FABRIC_NAME "hfi1_fabric.fw" 65 #define DEFAULT_FW_SBUS_NAME "hfi1_sbus.fw" 66 #define DEFAULT_FW_PCIE_NAME "hfi1_pcie.fw" 67 #define DEFAULT_PLATFORM_CONFIG_NAME "hfi1_platform.dat" 68 #define ALT_FW_8051_NAME_ASIC "hfi1_dc8051_d.fw" 69 #define ALT_FW_FABRIC_NAME "hfi1_fabric_d.fw" 70 #define ALT_FW_SBUS_NAME "hfi1_sbus_d.fw" 71 #define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw" 72 73 static uint fw_8051_load = 1; 74 static uint fw_fabric_serdes_load = 1; 75 static uint fw_pcie_serdes_load = 1; 76 static uint fw_sbus_load = 1; 77 78 /* 79 * Access required in platform.c 80 * Maintains state of whether the platform config was fetched via the 81 * fallback option 82 */ 83 uint platform_config_load; 84 85 /* Firmware file names get set in hfi1_firmware_init() based on the above */ 86 static char *fw_8051_name; 87 static char *fw_fabric_serdes_name; 88 static char *fw_sbus_name; 89 static char *fw_pcie_serdes_name; 90 static char *platform_config_name; 91 92 #define SBUS_MAX_POLL_COUNT 100 93 #define SBUS_COUNTER(reg, name) \ 94 (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \ 95 ASIC_STS_SBUS_COUNTERS_##name##_CNT_MASK) 96 97 /* 98 * Firmware security header. 99 */ 100 struct css_header { 101 u32 module_type; 102 u32 header_len; 103 u32 header_version; 104 u32 module_id; 105 u32 module_vendor; 106 u32 date; /* BCD yyyymmdd */ 107 u32 size; /* in DWORDs */ 108 u32 key_size; /* in DWORDs */ 109 u32 modulus_size; /* in DWORDs */ 110 u32 exponent_size; /* in DWORDs */ 111 u32 reserved[22]; 112 }; 113 114 /* expected field values */ 115 #define CSS_MODULE_TYPE 0x00000006 116 #define CSS_HEADER_LEN 0x000000a1 117 #define CSS_HEADER_VERSION 0x00010000 118 #define CSS_MODULE_VENDOR 0x00008086 119 120 #define KEY_SIZE 256 121 #define MU_SIZE 8 122 #define EXPONENT_SIZE 4 123 124 /* the file itself */ 125 struct firmware_file { 126 struct css_header css_header; 127 u8 modulus[KEY_SIZE]; 128 u8 exponent[EXPONENT_SIZE]; 129 u8 signature[KEY_SIZE]; 130 u8 firmware[]; 131 }; 132 133 struct augmented_firmware_file { 134 struct css_header css_header; 135 u8 modulus[KEY_SIZE]; 136 u8 exponent[EXPONENT_SIZE]; 137 u8 signature[KEY_SIZE]; 138 u8 r2[KEY_SIZE]; 139 u8 mu[MU_SIZE]; 140 u8 firmware[]; 141 }; 142 143 /* augmented file size difference */ 144 #define AUGMENT_SIZE (sizeof(struct augmented_firmware_file) - \ 145 sizeof(struct firmware_file)) 146 147 struct firmware_details { 148 /* Linux core piece */ 149 const struct firmware *fw; 150 151 struct css_header *css_header; 152 u8 *firmware_ptr; /* pointer to binary data */ 153 u32 firmware_len; /* length in bytes */ 154 u8 *modulus; /* pointer to the modulus */ 155 u8 *exponent; /* pointer to the exponent */ 156 u8 *signature; /* pointer to the signature */ 157 u8 *r2; /* pointer to r2 */ 158 u8 *mu; /* pointer to mu */ 159 struct augmented_firmware_file dummy_header; 160 }; 161 162 /* 163 * The mutex protects fw_state, fw_err, and all of the firmware_details 164 * variables. 165 */ 166 static DEFINE_MUTEX(fw_mutex); 167 enum fw_state { 168 FW_EMPTY, 169 FW_TRY, 170 FW_FINAL, 171 FW_ERR 172 }; 173 174 static enum fw_state fw_state = FW_EMPTY; 175 static int fw_err; 176 static struct firmware_details fw_8051; 177 static struct firmware_details fw_fabric; 178 static struct firmware_details fw_pcie; 179 static struct firmware_details fw_sbus; 180 static const struct firmware *platform_config; 181 182 /* flags for turn_off_spicos() */ 183 #define SPICO_SBUS 0x1 184 #define SPICO_FABRIC 0x2 185 #define ENABLE_SPICO_SMASK 0x1 186 187 /* security block commands */ 188 #define RSA_CMD_INIT 0x1 189 #define RSA_CMD_START 0x2 190 191 /* security block status */ 192 #define RSA_STATUS_IDLE 0x0 193 #define RSA_STATUS_ACTIVE 0x1 194 #define RSA_STATUS_DONE 0x2 195 #define RSA_STATUS_FAILED 0x3 196 197 /* RSA engine timeout, in ms */ 198 #define RSA_ENGINE_TIMEOUT 100 /* ms */ 199 200 /* hardware mutex timeout, in ms */ 201 #define HM_TIMEOUT 10 /* ms */ 202 203 /* 8051 memory access timeout, in us */ 204 #define DC8051_ACCESS_TIMEOUT 100 /* us */ 205 206 /* the number of fabric SerDes on the SBus */ 207 #define NUM_FABRIC_SERDES 4 208 209 /* ASIC_STS_SBUS_RESULT.RESULT_CODE value */ 210 #define SBUS_READ_COMPLETE 0x4 211 212 /* SBus fabric SerDes addresses, one set per HFI */ 213 static const u8 fabric_serdes_addrs[2][NUM_FABRIC_SERDES] = { 214 { 0x01, 0x02, 0x03, 0x04 }, 215 { 0x28, 0x29, 0x2a, 0x2b } 216 }; 217 218 /* SBus PCIe SerDes addresses, one set per HFI */ 219 static const u8 pcie_serdes_addrs[2][NUM_PCIE_SERDES] = { 220 { 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 221 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26 }, 222 { 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d, 223 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d } 224 }; 225 226 /* SBus PCIe PCS addresses, one set per HFI */ 227 const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES] = { 228 { 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17, 229 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23, 0x25, 0x27 }, 230 { 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 231 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e } 232 }; 233 234 /* SBus fabric SerDes broadcast addresses, one per HFI */ 235 static const u8 fabric_serdes_broadcast[2] = { 0xe4, 0xe5 }; 236 static const u8 all_fabric_serdes_broadcast = 0xe1; 237 238 /* SBus PCIe SerDes broadcast addresses, one per HFI */ 239 const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 }; 240 static const u8 all_pcie_serdes_broadcast = 0xe0; 241 242 /* forwards */ 243 static void dispose_one_firmware(struct firmware_details *fdet); 244 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd, 245 struct firmware_details *fdet); 246 static void dump_fw_version(struct hfi1_devdata *dd); 247 248 /* 249 * Read a single 64-bit value from 8051 data memory. 250 * 251 * Expects: 252 * o caller to have already set up data read, no auto increment 253 * o caller to turn off read enable when finished 254 * 255 * The address argument is a byte offset. Bits 0:2 in the address are 256 * ignored - i.e. the hardware will always do aligned 8-byte reads as if 257 * the lower bits are zero. 258 * 259 * Return 0 on success, -ENXIO on a read error (timeout). 260 */ 261 static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result) 262 { 263 u64 reg; 264 int count; 265 266 /* start the read at the given address */ 267 reg = ((addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK) 268 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT) 269 | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK; 270 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); 271 272 /* wait until ACCESS_COMPLETED is set */ 273 count = 0; 274 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) 275 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK) 276 == 0) { 277 count++; 278 if (count > DC8051_ACCESS_TIMEOUT) { 279 dd_dev_err(dd, "timeout reading 8051 data\n"); 280 return -ENXIO; 281 } 282 ndelay(10); 283 } 284 285 /* gather the data */ 286 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); 287 288 return 0; 289 } 290 291 /* 292 * Read 8051 data starting at addr, for len bytes. Will read in 8-byte chunks. 293 * Return 0 on success, -errno on error. 294 */ 295 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result) 296 { 297 unsigned long flags; 298 u32 done; 299 int ret = 0; 300 301 spin_lock_irqsave(&dd->dc8051_memlock, flags); 302 303 /* data read set-up, no auto-increment */ 304 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); 305 306 for (done = 0; done < len; addr += 8, done += 8, result++) { 307 ret = __read_8051_data(dd, addr, result); 308 if (ret) 309 break; 310 } 311 312 /* turn off read enable */ 313 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); 314 315 spin_unlock_irqrestore(&dd->dc8051_memlock, flags); 316 317 return ret; 318 } 319 320 /* 321 * Write data or code to the 8051 code or data RAM. 322 */ 323 static int write_8051(struct hfi1_devdata *dd, int code, u32 start, 324 const u8 *data, u32 len) 325 { 326 u64 reg; 327 u32 offset; 328 int aligned, count; 329 330 /* check alignment */ 331 aligned = ((unsigned long)data & 0x7) == 0; 332 333 /* write set-up */ 334 reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull) 335 | DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK; 336 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg); 337 338 reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK) 339 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT) 340 | DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK; 341 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); 342 343 /* write */ 344 for (offset = 0; offset < len; offset += 8) { 345 int bytes = len - offset; 346 347 if (bytes < 8) { 348 reg = 0; 349 memcpy(®, &data[offset], bytes); 350 } else if (aligned) { 351 reg = *(u64 *)&data[offset]; 352 } else { 353 memcpy(®, &data[offset], 8); 354 } 355 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg); 356 357 /* wait until ACCESS_COMPLETED is set */ 358 count = 0; 359 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) 360 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK) 361 == 0) { 362 count++; 363 if (count > DC8051_ACCESS_TIMEOUT) { 364 dd_dev_err(dd, "timeout writing 8051 data\n"); 365 return -ENXIO; 366 } 367 udelay(1); 368 } 369 } 370 371 /* turn off write access, auto increment (also sets to data access) */ 372 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); 373 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); 374 375 return 0; 376 } 377 378 /* return 0 if values match, non-zero and complain otherwise */ 379 static int invalid_header(struct hfi1_devdata *dd, const char *what, 380 u32 actual, u32 expected) 381 { 382 if (actual == expected) 383 return 0; 384 385 dd_dev_err(dd, 386 "invalid firmware header field %s: expected 0x%x, actual 0x%x\n", 387 what, expected, actual); 388 return 1; 389 } 390 391 /* 392 * Verify that the static fields in the CSS header match. 393 */ 394 static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css) 395 { 396 /* verify CSS header fields (most sizes are in DW, so add /4) */ 397 if (invalid_header(dd, "module_type", css->module_type, 398 CSS_MODULE_TYPE) || 399 invalid_header(dd, "header_len", css->header_len, 400 (sizeof(struct firmware_file) / 4)) || 401 invalid_header(dd, "header_version", css->header_version, 402 CSS_HEADER_VERSION) || 403 invalid_header(dd, "module_vendor", css->module_vendor, 404 CSS_MODULE_VENDOR) || 405 invalid_header(dd, "key_size", css->key_size, KEY_SIZE / 4) || 406 invalid_header(dd, "modulus_size", css->modulus_size, 407 KEY_SIZE / 4) || 408 invalid_header(dd, "exponent_size", css->exponent_size, 409 EXPONENT_SIZE / 4)) { 410 return -EINVAL; 411 } 412 return 0; 413 } 414 415 /* 416 * Make sure there are at least some bytes after the prefix. 417 */ 418 static int payload_check(struct hfi1_devdata *dd, const char *name, 419 long file_size, long prefix_size) 420 { 421 /* make sure we have some payload */ 422 if (prefix_size >= file_size) { 423 dd_dev_err(dd, 424 "firmware \"%s\", size %ld, must be larger than %ld bytes\n", 425 name, file_size, prefix_size); 426 return -EINVAL; 427 } 428 429 return 0; 430 } 431 432 /* 433 * Request the firmware from the system. Extract the pieces and fill in 434 * fdet. If successful, the caller will need to call dispose_one_firmware(). 435 * Returns 0 on success, -ERRNO on error. 436 */ 437 static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name, 438 struct firmware_details *fdet) 439 { 440 struct css_header *css; 441 int ret; 442 443 memset(fdet, 0, sizeof(*fdet)); 444 445 ret = request_firmware(&fdet->fw, name, &dd->pcidev->dev); 446 if (ret) { 447 dd_dev_warn(dd, "cannot find firmware \"%s\", err %d\n", 448 name, ret); 449 return ret; 450 } 451 452 /* verify the firmware */ 453 if (fdet->fw->size < sizeof(struct css_header)) { 454 dd_dev_err(dd, "firmware \"%s\" is too small\n", name); 455 ret = -EINVAL; 456 goto done; 457 } 458 css = (struct css_header *)fdet->fw->data; 459 460 hfi1_cdbg(FIRMWARE, "Firmware %s details:", name); 461 hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size); 462 hfi1_cdbg(FIRMWARE, "CSS structure:"); 463 hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type); 464 hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)", 465 css->header_len, 4 * css->header_len); 466 hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version); 467 hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id); 468 hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor); 469 hfi1_cdbg(FIRMWARE, " date 0x%x", css->date); 470 hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)", 471 css->size, 4 * css->size); 472 hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)", 473 css->key_size, 4 * css->key_size); 474 hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)", 475 css->modulus_size, 4 * css->modulus_size); 476 hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)", 477 css->exponent_size, 4 * css->exponent_size); 478 hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes", 479 fdet->fw->size - sizeof(struct firmware_file)); 480 481 /* 482 * If the file does not have a valid CSS header, fail. 483 * Otherwise, check the CSS size field for an expected size. 484 * The augmented file has r2 and mu inserted after the header 485 * was generated, so there will be a known difference between 486 * the CSS header size and the actual file size. Use this 487 * difference to identify an augmented file. 488 * 489 * Note: css->size is in DWORDs, multiply by 4 to get bytes. 490 */ 491 ret = verify_css_header(dd, css); 492 if (ret) { 493 dd_dev_info(dd, "Invalid CSS header for \"%s\"\n", name); 494 } else if ((css->size * 4) == fdet->fw->size) { 495 /* non-augmented firmware file */ 496 struct firmware_file *ff = (struct firmware_file *) 497 fdet->fw->data; 498 499 /* make sure there are bytes in the payload */ 500 ret = payload_check(dd, name, fdet->fw->size, 501 sizeof(struct firmware_file)); 502 if (ret == 0) { 503 fdet->css_header = css; 504 fdet->modulus = ff->modulus; 505 fdet->exponent = ff->exponent; 506 fdet->signature = ff->signature; 507 fdet->r2 = fdet->dummy_header.r2; /* use dummy space */ 508 fdet->mu = fdet->dummy_header.mu; /* use dummy space */ 509 fdet->firmware_ptr = ff->firmware; 510 fdet->firmware_len = fdet->fw->size - 511 sizeof(struct firmware_file); 512 /* 513 * Header does not include r2 and mu - generate here. 514 * For now, fail. 515 */ 516 dd_dev_err(dd, "driver is unable to validate firmware without r2 and mu (not in firmware file)\n"); 517 ret = -EINVAL; 518 } 519 } else if ((css->size * 4) + AUGMENT_SIZE == fdet->fw->size) { 520 /* augmented firmware file */ 521 struct augmented_firmware_file *aff = 522 (struct augmented_firmware_file *)fdet->fw->data; 523 524 /* make sure there are bytes in the payload */ 525 ret = payload_check(dd, name, fdet->fw->size, 526 sizeof(struct augmented_firmware_file)); 527 if (ret == 0) { 528 fdet->css_header = css; 529 fdet->modulus = aff->modulus; 530 fdet->exponent = aff->exponent; 531 fdet->signature = aff->signature; 532 fdet->r2 = aff->r2; 533 fdet->mu = aff->mu; 534 fdet->firmware_ptr = aff->firmware; 535 fdet->firmware_len = fdet->fw->size - 536 sizeof(struct augmented_firmware_file); 537 } 538 } else { 539 /* css->size check failed */ 540 dd_dev_err(dd, 541 "invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n", 542 fdet->fw->size / 4, 543 (fdet->fw->size - AUGMENT_SIZE) / 4, 544 css->size); 545 546 ret = -EINVAL; 547 } 548 549 done: 550 /* if returning an error, clean up after ourselves */ 551 if (ret) 552 dispose_one_firmware(fdet); 553 return ret; 554 } 555 556 static void dispose_one_firmware(struct firmware_details *fdet) 557 { 558 release_firmware(fdet->fw); 559 /* erase all previous information */ 560 memset(fdet, 0, sizeof(*fdet)); 561 } 562 563 /* 564 * Obtain the 4 firmwares from the OS. All must be obtained at once or not 565 * at all. If called with the firmware state in FW_TRY, use alternate names. 566 * On exit, this routine will have set the firmware state to one of FW_TRY, 567 * FW_FINAL, or FW_ERR. 568 * 569 * Must be holding fw_mutex. 570 */ 571 static void __obtain_firmware(struct hfi1_devdata *dd) 572 { 573 int err = 0; 574 575 if (fw_state == FW_FINAL) /* nothing more to obtain */ 576 return; 577 if (fw_state == FW_ERR) /* already in error */ 578 return; 579 580 /* fw_state is FW_EMPTY or FW_TRY */ 581 retry: 582 if (fw_state == FW_TRY) { 583 /* 584 * We tried the original and it failed. Move to the 585 * alternate. 586 */ 587 dd_dev_warn(dd, "using alternate firmware names\n"); 588 /* 589 * Let others run. Some systems, when missing firmware, does 590 * something that holds for 30 seconds. If we do that twice 591 * in a row it triggers task blocked warning. 592 */ 593 cond_resched(); 594 if (fw_8051_load) 595 dispose_one_firmware(&fw_8051); 596 if (fw_fabric_serdes_load) 597 dispose_one_firmware(&fw_fabric); 598 if (fw_sbus_load) 599 dispose_one_firmware(&fw_sbus); 600 if (fw_pcie_serdes_load) 601 dispose_one_firmware(&fw_pcie); 602 fw_8051_name = ALT_FW_8051_NAME_ASIC; 603 fw_fabric_serdes_name = ALT_FW_FABRIC_NAME; 604 fw_sbus_name = ALT_FW_SBUS_NAME; 605 fw_pcie_serdes_name = ALT_FW_PCIE_NAME; 606 } 607 608 if (fw_sbus_load) { 609 err = obtain_one_firmware(dd, fw_sbus_name, &fw_sbus); 610 if (err) 611 goto done; 612 } 613 614 if (fw_pcie_serdes_load) { 615 err = obtain_one_firmware(dd, fw_pcie_serdes_name, &fw_pcie); 616 if (err) 617 goto done; 618 } 619 620 if (fw_fabric_serdes_load) { 621 err = obtain_one_firmware(dd, fw_fabric_serdes_name, 622 &fw_fabric); 623 if (err) 624 goto done; 625 } 626 627 if (fw_8051_load) { 628 err = obtain_one_firmware(dd, fw_8051_name, &fw_8051); 629 if (err) 630 goto done; 631 } 632 633 done: 634 if (err) { 635 /* oops, had problems obtaining a firmware */ 636 if (fw_state == FW_EMPTY && dd->icode == ICODE_RTL_SILICON) { 637 /* retry with alternate (RTL only) */ 638 fw_state = FW_TRY; 639 goto retry; 640 } 641 dd_dev_err(dd, "unable to obtain working firmware\n"); 642 fw_state = FW_ERR; 643 fw_err = -ENOENT; 644 } else { 645 /* success */ 646 if (fw_state == FW_EMPTY && 647 dd->icode != ICODE_FUNCTIONAL_SIMULATOR) 648 fw_state = FW_TRY; /* may retry later */ 649 else 650 fw_state = FW_FINAL; /* cannot try again */ 651 } 652 } 653 654 /* 655 * Called by all HFIs when loading their firmware - i.e. device probe time. 656 * The first one will do the actual firmware load. Use a mutex to resolve 657 * any possible race condition. 658 * 659 * The call to this routine cannot be moved to driver load because the kernel 660 * call request_firmware() requires a device which is only available after 661 * the first device probe. 662 */ 663 static int obtain_firmware(struct hfi1_devdata *dd) 664 { 665 unsigned long timeout; 666 int err = 0; 667 668 mutex_lock(&fw_mutex); 669 670 /* 40s delay due to long delay on missing firmware on some systems */ 671 timeout = jiffies + msecs_to_jiffies(40000); 672 while (fw_state == FW_TRY) { 673 /* 674 * Another device is trying the firmware. Wait until it 675 * decides what works (or not). 676 */ 677 if (time_after(jiffies, timeout)) { 678 /* waited too long */ 679 dd_dev_err(dd, "Timeout waiting for firmware try"); 680 fw_state = FW_ERR; 681 fw_err = -ETIMEDOUT; 682 break; 683 } 684 mutex_unlock(&fw_mutex); 685 msleep(20); /* arbitrary delay */ 686 mutex_lock(&fw_mutex); 687 } 688 /* not in FW_TRY state */ 689 690 if (fw_state == FW_FINAL) { 691 if (platform_config) { 692 dd->platform_config.data = platform_config->data; 693 dd->platform_config.size = platform_config->size; 694 } 695 goto done; /* already acquired */ 696 } else if (fw_state == FW_ERR) { 697 goto done; /* already tried and failed */ 698 } 699 /* fw_state is FW_EMPTY */ 700 701 /* set fw_state to FW_TRY, FW_FINAL, or FW_ERR, and fw_err */ 702 __obtain_firmware(dd); 703 704 if (platform_config_load) { 705 platform_config = NULL; 706 err = request_firmware(&platform_config, platform_config_name, 707 &dd->pcidev->dev); 708 if (err) { 709 platform_config = NULL; 710 goto done; 711 } 712 dd->platform_config.data = platform_config->data; 713 dd->platform_config.size = platform_config->size; 714 } 715 716 done: 717 mutex_unlock(&fw_mutex); 718 719 return fw_err; 720 } 721 722 /* 723 * Called when the driver unloads. The timing is asymmetric with its 724 * counterpart, obtain_firmware(). If called at device remove time, 725 * then it is conceivable that another device could probe while the 726 * firmware is being disposed. The mutexes can be moved to do that 727 * safely, but then the firmware would be requested from the OS multiple 728 * times. 729 * 730 * No mutex is needed as the driver is unloading and there cannot be any 731 * other callers. 732 */ 733 void dispose_firmware(void) 734 { 735 dispose_one_firmware(&fw_8051); 736 dispose_one_firmware(&fw_fabric); 737 dispose_one_firmware(&fw_pcie); 738 dispose_one_firmware(&fw_sbus); 739 740 release_firmware(platform_config); 741 platform_config = NULL; 742 743 /* retain the error state, otherwise revert to empty */ 744 if (fw_state != FW_ERR) 745 fw_state = FW_EMPTY; 746 } 747 748 /* 749 * Called with the result of a firmware download. 750 * 751 * Return 1 to retry loading the firmware, 0 to stop. 752 */ 753 static int retry_firmware(struct hfi1_devdata *dd, int load_result) 754 { 755 int retry; 756 757 mutex_lock(&fw_mutex); 758 759 if (load_result == 0) { 760 /* 761 * The load succeeded, so expect all others to do the same. 762 * Do not retry again. 763 */ 764 if (fw_state == FW_TRY) 765 fw_state = FW_FINAL; 766 retry = 0; /* do NOT retry */ 767 } else if (fw_state == FW_TRY) { 768 /* load failed, obtain alternate firmware */ 769 __obtain_firmware(dd); 770 retry = (fw_state == FW_FINAL); 771 } else { 772 /* else in FW_FINAL or FW_ERR, no retry in either case */ 773 retry = 0; 774 } 775 776 mutex_unlock(&fw_mutex); 777 return retry; 778 } 779 780 /* 781 * Write a block of data to a given array CSR. All calls will be in 782 * multiples of 8 bytes. 783 */ 784 static void write_rsa_data(struct hfi1_devdata *dd, int what, 785 const u8 *data, int nbytes) 786 { 787 int qw_size = nbytes / 8; 788 int i; 789 790 if (((unsigned long)data & 0x7) == 0) { 791 /* aligned */ 792 u64 *ptr = (u64 *)data; 793 794 for (i = 0; i < qw_size; i++, ptr++) 795 write_csr(dd, what + (8 * i), *ptr); 796 } else { 797 /* not aligned */ 798 for (i = 0; i < qw_size; i++, data += 8) { 799 u64 value; 800 801 memcpy(&value, data, 8); 802 write_csr(dd, what + (8 * i), value); 803 } 804 } 805 } 806 807 /* 808 * Write a block of data to a given CSR as a stream of writes. All calls will 809 * be in multiples of 8 bytes. 810 */ 811 static void write_streamed_rsa_data(struct hfi1_devdata *dd, int what, 812 const u8 *data, int nbytes) 813 { 814 u64 *ptr = (u64 *)data; 815 int qw_size = nbytes / 8; 816 817 for (; qw_size > 0; qw_size--, ptr++) 818 write_csr(dd, what, *ptr); 819 } 820 821 /* 822 * Download the signature and start the RSA mechanism. Wait for 823 * RSA_ENGINE_TIMEOUT before giving up. 824 */ 825 static int run_rsa(struct hfi1_devdata *dd, const char *who, 826 const u8 *signature) 827 { 828 unsigned long timeout; 829 u64 reg; 830 u32 status; 831 int ret = 0; 832 833 /* write the signature */ 834 write_rsa_data(dd, MISC_CFG_RSA_SIGNATURE, signature, KEY_SIZE); 835 836 /* initialize RSA */ 837 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT); 838 839 /* 840 * Make sure the engine is idle and insert a delay between the two 841 * writes to MISC_CFG_RSA_CMD. 842 */ 843 status = (read_csr(dd, MISC_CFG_FW_CTRL) 844 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK) 845 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT; 846 if (status != RSA_STATUS_IDLE) { 847 dd_dev_err(dd, "%s security engine not idle - giving up\n", 848 who); 849 return -EBUSY; 850 } 851 852 /* start RSA */ 853 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START); 854 855 /* 856 * Look for the result. 857 * 858 * The RSA engine is hooked up to two MISC errors. The driver 859 * masks these errors as they do not respond to the standard 860 * error "clear down" mechanism. Look for these errors here and 861 * clear them when possible. This routine will exit with the 862 * errors of the current run still set. 863 * 864 * MISC_FW_AUTH_FAILED_ERR 865 * Firmware authorization failed. This can be cleared by 866 * re-initializing the RSA engine, then clearing the status bit. 867 * Do not re-init the RSA angine immediately after a successful 868 * run - this will reset the current authorization. 869 * 870 * MISC_KEY_MISMATCH_ERR 871 * Key does not match. The only way to clear this is to load 872 * a matching key then clear the status bit. If this error 873 * is raised, it will persist outside of this routine until a 874 * matching key is loaded. 875 */ 876 timeout = msecs_to_jiffies(RSA_ENGINE_TIMEOUT) + jiffies; 877 while (1) { 878 status = (read_csr(dd, MISC_CFG_FW_CTRL) 879 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK) 880 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT; 881 882 if (status == RSA_STATUS_IDLE) { 883 /* should not happen */ 884 dd_dev_err(dd, "%s firmware security bad idle state\n", 885 who); 886 ret = -EINVAL; 887 break; 888 } else if (status == RSA_STATUS_DONE) { 889 /* finished successfully */ 890 break; 891 } else if (status == RSA_STATUS_FAILED) { 892 /* finished unsuccessfully */ 893 ret = -EINVAL; 894 break; 895 } 896 /* else still active */ 897 898 if (time_after(jiffies, timeout)) { 899 /* 900 * Timed out while active. We can't reset the engine 901 * if it is stuck active, but run through the 902 * error code to see what error bits are set. 903 */ 904 dd_dev_err(dd, "%s firmware security time out\n", who); 905 ret = -ETIMEDOUT; 906 break; 907 } 908 909 msleep(20); 910 } 911 912 /* 913 * Arrive here on success or failure. Clear all RSA engine 914 * errors. All current errors will stick - the RSA logic is keeping 915 * error high. All previous errors will clear - the RSA logic 916 * is not keeping the error high. 917 */ 918 write_csr(dd, MISC_ERR_CLEAR, 919 MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK | 920 MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK); 921 /* 922 * All that is left are the current errors. Print warnings on 923 * authorization failure details, if any. Firmware authorization 924 * can be retried, so these are only warnings. 925 */ 926 reg = read_csr(dd, MISC_ERR_STATUS); 927 if (ret) { 928 if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK) 929 dd_dev_warn(dd, "%s firmware authorization failed\n", 930 who); 931 if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK) 932 dd_dev_warn(dd, "%s firmware key mismatch\n", who); 933 } 934 935 return ret; 936 } 937 938 static void load_security_variables(struct hfi1_devdata *dd, 939 struct firmware_details *fdet) 940 { 941 /* Security variables a. Write the modulus */ 942 write_rsa_data(dd, MISC_CFG_RSA_MODULUS, fdet->modulus, KEY_SIZE); 943 /* Security variables b. Write the r2 */ 944 write_rsa_data(dd, MISC_CFG_RSA_R2, fdet->r2, KEY_SIZE); 945 /* Security variables c. Write the mu */ 946 write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE); 947 /* Security variables d. Write the header */ 948 write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD, 949 (u8 *)fdet->css_header, 950 sizeof(struct css_header)); 951 } 952 953 /* return the 8051 firmware state */ 954 static inline u32 get_firmware_state(struct hfi1_devdata *dd) 955 { 956 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); 957 958 return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT) 959 & DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK; 960 } 961 962 /* 963 * Wait until the firmware is up and ready to take host requests. 964 * Return 0 on success, -ETIMEDOUT on timeout. 965 */ 966 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout) 967 { 968 unsigned long timeout; 969 970 /* in the simulator, the fake 8051 is always ready */ 971 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) 972 return 0; 973 974 timeout = msecs_to_jiffies(mstimeout) + jiffies; 975 while (1) { 976 if (get_firmware_state(dd) == 0xa0) /* ready */ 977 return 0; 978 if (time_after(jiffies, timeout)) /* timed out */ 979 return -ETIMEDOUT; 980 usleep_range(1950, 2050); /* sleep 2ms-ish */ 981 } 982 } 983 984 /* 985 * Load the 8051 firmware. 986 */ 987 static int load_8051_firmware(struct hfi1_devdata *dd, 988 struct firmware_details *fdet) 989 { 990 u64 reg; 991 int ret; 992 u8 ver_a, ver_b; 993 994 /* 995 * DC Reset sequence 996 * Load DC 8051 firmware 997 */ 998 /* 999 * DC reset step 1: Reset DC8051 1000 */ 1001 reg = DC_DC8051_CFG_RST_M8051W_SMASK 1002 | DC_DC8051_CFG_RST_CRAM_SMASK 1003 | DC_DC8051_CFG_RST_DRAM_SMASK 1004 | DC_DC8051_CFG_RST_IRAM_SMASK 1005 | DC_DC8051_CFG_RST_SFR_SMASK; 1006 write_csr(dd, DC_DC8051_CFG_RST, reg); 1007 1008 /* 1009 * DC reset step 2 (optional): Load 8051 data memory with link 1010 * configuration 1011 */ 1012 1013 /* 1014 * DC reset step 3: Load DC8051 firmware 1015 */ 1016 /* release all but the core reset */ 1017 reg = DC_DC8051_CFG_RST_M8051W_SMASK; 1018 write_csr(dd, DC_DC8051_CFG_RST, reg); 1019 1020 /* Firmware load step 1 */ 1021 load_security_variables(dd, fdet); 1022 1023 /* 1024 * Firmware load step 2. Clear MISC_CFG_FW_CTRL.FW_8051_LOADED 1025 */ 1026 write_csr(dd, MISC_CFG_FW_CTRL, 0); 1027 1028 /* Firmware load steps 3-5 */ 1029 ret = write_8051(dd, 1/*code*/, 0, fdet->firmware_ptr, 1030 fdet->firmware_len); 1031 if (ret) 1032 return ret; 1033 1034 /* 1035 * DC reset step 4. Host starts the DC8051 firmware 1036 */ 1037 /* 1038 * Firmware load step 6. Set MISC_CFG_FW_CTRL.FW_8051_LOADED 1039 */ 1040 write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK); 1041 1042 /* Firmware load steps 7-10 */ 1043 ret = run_rsa(dd, "8051", fdet->signature); 1044 if (ret) 1045 return ret; 1046 1047 /* clear all reset bits, releasing the 8051 */ 1048 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 1049 1050 /* 1051 * DC reset step 5. Wait for firmware to be ready to accept host 1052 * requests. 1053 */ 1054 ret = wait_fm_ready(dd, TIMEOUT_8051_START); 1055 if (ret) { /* timed out */ 1056 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n", 1057 get_firmware_state(dd)); 1058 return -ETIMEDOUT; 1059 } 1060 1061 read_misc_status(dd, &ver_a, &ver_b); 1062 dd_dev_info(dd, "8051 firmware version %d.%d\n", 1063 (int)ver_b, (int)ver_a); 1064 dd->dc8051_ver = dc8051_ver(ver_b, ver_a); 1065 1066 return 0; 1067 } 1068 1069 /* 1070 * Write the SBus request register 1071 * 1072 * No need for masking - the arguments are sized exactly. 1073 */ 1074 void sbus_request(struct hfi1_devdata *dd, 1075 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in) 1076 { 1077 write_csr(dd, ASIC_CFG_SBUS_REQUEST, 1078 ((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT) | 1079 ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT) | 1080 ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT) | 1081 ((u64)receiver_addr << 1082 ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT)); 1083 } 1084 1085 /* 1086 * Read a value from the SBus. 1087 * 1088 * Requires the caller to be in fast mode 1089 */ 1090 static u32 sbus_read(struct hfi1_devdata *dd, u8 receiver_addr, u8 data_addr, 1091 u32 data_in) 1092 { 1093 u64 reg; 1094 int retries; 1095 int success = 0; 1096 u32 result = 0; 1097 u32 result_code = 0; 1098 1099 sbus_request(dd, receiver_addr, data_addr, READ_SBUS_RECEIVER, data_in); 1100 1101 for (retries = 0; retries < 100; retries++) { 1102 usleep_range(1000, 1200); /* arbitrary */ 1103 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1104 result_code = (reg >> ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT) 1105 & ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK; 1106 if (result_code != SBUS_READ_COMPLETE) 1107 continue; 1108 1109 success = 1; 1110 result = (reg >> ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT) 1111 & ASIC_STS_SBUS_RESULT_DATA_OUT_MASK; 1112 break; 1113 } 1114 1115 if (!success) { 1116 dd_dev_err(dd, "%s: read failed, result code 0x%x\n", __func__, 1117 result_code); 1118 } 1119 1120 return result; 1121 } 1122 1123 /* 1124 * Turn off the SBus and fabric serdes spicos. 1125 * 1126 * + Must be called with Sbus fast mode turned on. 1127 * + Must be called after fabric serdes broadcast is set up. 1128 * + Must be called before the 8051 is loaded - assumes 8051 is not loaded 1129 * when using MISC_CFG_FW_CTRL. 1130 */ 1131 static void turn_off_spicos(struct hfi1_devdata *dd, int flags) 1132 { 1133 /* only needed on A0 */ 1134 if (!is_ax(dd)) 1135 return; 1136 1137 dd_dev_info(dd, "Turning off spicos:%s%s\n", 1138 flags & SPICO_SBUS ? " SBus" : "", 1139 flags & SPICO_FABRIC ? " fabric" : ""); 1140 1141 write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK); 1142 /* disable SBus spico */ 1143 if (flags & SPICO_SBUS) 1144 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01, 1145 WRITE_SBUS_RECEIVER, 0x00000040); 1146 1147 /* disable the fabric serdes spicos */ 1148 if (flags & SPICO_FABRIC) 1149 sbus_request(dd, fabric_serdes_broadcast[dd->hfi1_id], 1150 0x07, WRITE_SBUS_RECEIVER, 0x00000000); 1151 write_csr(dd, MISC_CFG_FW_CTRL, 0); 1152 } 1153 1154 /* 1155 * Reset all of the fabric serdes for this HFI in preparation to take the 1156 * link to Polling. 1157 * 1158 * To do a reset, we need to write to to the serdes registers. Unfortunately, 1159 * the fabric serdes download to the other HFI on the ASIC will have turned 1160 * off the firmware validation on this HFI. This means we can't write to the 1161 * registers to reset the serdes. Work around this by performing a complete 1162 * re-download and validation of the fabric serdes firmware. This, as a 1163 * by-product, will reset the serdes. NOTE: the re-download requires that 1164 * the 8051 be in the Offline state. I.e. not actively trying to use the 1165 * serdes. This routine is called at the point where the link is Offline and 1166 * is getting ready to go to Polling. 1167 */ 1168 void fabric_serdes_reset(struct hfi1_devdata *dd) 1169 { 1170 int ret; 1171 1172 if (!fw_fabric_serdes_load) 1173 return; 1174 1175 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1176 if (ret) { 1177 dd_dev_err(dd, 1178 "Cannot acquire SBus resource to reset fabric SerDes - perhaps you should reboot\n"); 1179 return; 1180 } 1181 set_sbus_fast_mode(dd); 1182 1183 if (is_ax(dd)) { 1184 /* A0 serdes do not work with a re-download */ 1185 u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; 1186 1187 /* place SerDes in reset and disable SPICO */ 1188 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011); 1189 /* wait 100 refclk cycles @ 156.25MHz => 640ns */ 1190 udelay(1); 1191 /* remove SerDes reset */ 1192 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010); 1193 /* turn SPICO enable on */ 1194 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002); 1195 } else { 1196 turn_off_spicos(dd, SPICO_FABRIC); 1197 /* 1198 * No need for firmware retry - what to download has already 1199 * been decided. 1200 * No need to pay attention to the load return - the only 1201 * failure is a validation failure, which has already been 1202 * checked by the initial download. 1203 */ 1204 (void)load_fabric_serdes_firmware(dd, &fw_fabric); 1205 } 1206 1207 clear_sbus_fast_mode(dd); 1208 release_chip_resource(dd, CR_SBUS); 1209 } 1210 1211 /* Access to the SBus in this routine should probably be serialized */ 1212 int sbus_request_slow(struct hfi1_devdata *dd, 1213 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in) 1214 { 1215 u64 reg, count = 0; 1216 1217 /* make sure fast mode is clear */ 1218 clear_sbus_fast_mode(dd); 1219 1220 sbus_request(dd, receiver_addr, data_addr, command, data_in); 1221 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 1222 ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK); 1223 /* Wait for both DONE and RCV_DATA_VALID to go high */ 1224 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1225 while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) && 1226 (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) { 1227 if (count++ >= SBUS_MAX_POLL_COUNT) { 1228 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); 1229 /* 1230 * If the loop has timed out, we are OK if DONE bit 1231 * is set and RCV_DATA_VALID and EXECUTE counters 1232 * are the same. If not, we cannot proceed. 1233 */ 1234 if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) && 1235 (SBUS_COUNTER(counts, RCV_DATA_VALID) == 1236 SBUS_COUNTER(counts, EXECUTE))) 1237 break; 1238 return -ETIMEDOUT; 1239 } 1240 udelay(1); 1241 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1242 } 1243 count = 0; 1244 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0); 1245 /* Wait for DONE to clear after EXECUTE is cleared */ 1246 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1247 while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) { 1248 if (count++ >= SBUS_MAX_POLL_COUNT) 1249 return -ETIME; 1250 udelay(1); 1251 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); 1252 } 1253 return 0; 1254 } 1255 1256 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd, 1257 struct firmware_details *fdet) 1258 { 1259 int i, err; 1260 const u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; /* receiver addr */ 1261 1262 dd_dev_info(dd, "Downloading fabric firmware\n"); 1263 1264 /* step 1: load security variables */ 1265 load_security_variables(dd, fdet); 1266 /* step 2: place SerDes in reset and disable SPICO */ 1267 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011); 1268 /* wait 100 refclk cycles @ 156.25MHz => 640ns */ 1269 udelay(1); 1270 /* step 3: remove SerDes reset */ 1271 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010); 1272 /* step 4: assert IMEM override */ 1273 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x40000000); 1274 /* step 5: download SerDes machine code */ 1275 for (i = 0; i < fdet->firmware_len; i += 4) { 1276 sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER, 1277 *(u32 *)&fdet->firmware_ptr[i]); 1278 } 1279 /* step 6: IMEM override off */ 1280 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000); 1281 /* step 7: turn ECC on */ 1282 sbus_request(dd, ra, 0x0b, WRITE_SBUS_RECEIVER, 0x000c0000); 1283 1284 /* steps 8-11: run the RSA engine */ 1285 err = run_rsa(dd, "fabric serdes", fdet->signature); 1286 if (err) 1287 return err; 1288 1289 /* step 12: turn SPICO enable on */ 1290 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002); 1291 /* step 13: enable core hardware interrupts */ 1292 sbus_request(dd, ra, 0x08, WRITE_SBUS_RECEIVER, 0x00000000); 1293 1294 return 0; 1295 } 1296 1297 static int load_sbus_firmware(struct hfi1_devdata *dd, 1298 struct firmware_details *fdet) 1299 { 1300 int i, err; 1301 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */ 1302 1303 dd_dev_info(dd, "Downloading SBus firmware\n"); 1304 1305 /* step 1: load security variables */ 1306 load_security_variables(dd, fdet); 1307 /* step 2: place SPICO into reset and enable off */ 1308 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x000000c0); 1309 /* step 3: remove reset, enable off, IMEM_CNTRL_EN on */ 1310 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000240); 1311 /* step 4: set starting IMEM address for burst download */ 1312 sbus_request(dd, ra, 0x03, WRITE_SBUS_RECEIVER, 0x80000000); 1313 /* step 5: download the SBus Master machine code */ 1314 for (i = 0; i < fdet->firmware_len; i += 4) { 1315 sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER, 1316 *(u32 *)&fdet->firmware_ptr[i]); 1317 } 1318 /* step 6: set IMEM_CNTL_EN off */ 1319 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040); 1320 /* step 7: turn ECC on */ 1321 sbus_request(dd, ra, 0x16, WRITE_SBUS_RECEIVER, 0x000c0000); 1322 1323 /* steps 8-11: run the RSA engine */ 1324 err = run_rsa(dd, "SBus", fdet->signature); 1325 if (err) 1326 return err; 1327 1328 /* step 12: set SPICO_ENABLE on */ 1329 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140); 1330 1331 return 0; 1332 } 1333 1334 static int load_pcie_serdes_firmware(struct hfi1_devdata *dd, 1335 struct firmware_details *fdet) 1336 { 1337 int i; 1338 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */ 1339 1340 dd_dev_info(dd, "Downloading PCIe firmware\n"); 1341 1342 /* step 1: load security variables */ 1343 load_security_variables(dd, fdet); 1344 /* step 2: assert single step (halts the SBus Master spico) */ 1345 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000001); 1346 /* step 3: enable XDMEM access */ 1347 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40); 1348 /* step 4: load firmware into SBus Master XDMEM */ 1349 /* 1350 * NOTE: the dmem address, write_en, and wdata are all pre-packed, 1351 * we only need to pick up the bytes and write them 1352 */ 1353 for (i = 0; i < fdet->firmware_len; i += 4) { 1354 sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER, 1355 *(u32 *)&fdet->firmware_ptr[i]); 1356 } 1357 /* step 5: disable XDMEM access */ 1358 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140); 1359 /* step 6: allow SBus Spico to run */ 1360 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000); 1361 1362 /* 1363 * steps 7-11: run RSA, if it succeeds, firmware is available to 1364 * be swapped 1365 */ 1366 return run_rsa(dd, "PCIe serdes", fdet->signature); 1367 } 1368 1369 /* 1370 * Set the given broadcast values on the given list of devices. 1371 */ 1372 static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2, 1373 const u8 *addrs, int count) 1374 { 1375 while (--count >= 0) { 1376 /* 1377 * Set BROADCAST_GROUP_1 and BROADCAST_GROUP_2, leave 1378 * defaults for everything else. Do not read-modify-write, 1379 * per instruction from the manufacturer. 1380 * 1381 * Register 0xfd: 1382 * bits what 1383 * ----- --------------------------------- 1384 * 0 IGNORE_BROADCAST (default 0) 1385 * 11:4 BROADCAST_GROUP_1 (default 0xff) 1386 * 23:16 BROADCAST_GROUP_2 (default 0xff) 1387 */ 1388 sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER, 1389 (u32)bg1 << 4 | (u32)bg2 << 16); 1390 } 1391 } 1392 1393 int acquire_hw_mutex(struct hfi1_devdata *dd) 1394 { 1395 unsigned long timeout; 1396 int try = 0; 1397 u8 mask = 1 << dd->hfi1_id; 1398 u8 user; 1399 1400 retry: 1401 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies; 1402 while (1) { 1403 write_csr(dd, ASIC_CFG_MUTEX, mask); 1404 user = (u8)read_csr(dd, ASIC_CFG_MUTEX); 1405 if (user == mask) 1406 return 0; /* success */ 1407 if (time_after(jiffies, timeout)) 1408 break; /* timed out */ 1409 msleep(20); 1410 } 1411 1412 /* timed out */ 1413 dd_dev_err(dd, 1414 "Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n", 1415 (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up"); 1416 1417 if (try == 0) { 1418 /* break mutex and retry */ 1419 write_csr(dd, ASIC_CFG_MUTEX, 0); 1420 try++; 1421 goto retry; 1422 } 1423 1424 return -EBUSY; 1425 } 1426 1427 void release_hw_mutex(struct hfi1_devdata *dd) 1428 { 1429 write_csr(dd, ASIC_CFG_MUTEX, 0); 1430 } 1431 1432 /* return the given resource bit(s) as a mask for the given HFI */ 1433 static inline u64 resource_mask(u32 hfi1_id, u32 resource) 1434 { 1435 return ((u64)resource) << (hfi1_id ? CR_DYN_SHIFT : 0); 1436 } 1437 1438 static void fail_mutex_acquire_message(struct hfi1_devdata *dd, 1439 const char *func) 1440 { 1441 dd_dev_err(dd, 1442 "%s: hardware mutex stuck - suggest rebooting the machine\n", 1443 func); 1444 } 1445 1446 /* 1447 * Acquire access to a chip resource. 1448 * 1449 * Return 0 on success, -EBUSY if resource busy, -EIO if mutex acquire failed. 1450 */ 1451 static int __acquire_chip_resource(struct hfi1_devdata *dd, u32 resource) 1452 { 1453 u64 scratch0, all_bits, my_bit; 1454 int ret; 1455 1456 if (resource & CR_DYN_MASK) { 1457 /* a dynamic resource is in use if either HFI has set the bit */ 1458 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0 && 1459 (resource & (CR_I2C1 | CR_I2C2))) { 1460 /* discrete devices must serialize across both chains */ 1461 all_bits = resource_mask(0, CR_I2C1 | CR_I2C2) | 1462 resource_mask(1, CR_I2C1 | CR_I2C2); 1463 } else { 1464 all_bits = resource_mask(0, resource) | 1465 resource_mask(1, resource); 1466 } 1467 my_bit = resource_mask(dd->hfi1_id, resource); 1468 } else { 1469 /* non-dynamic resources are not split between HFIs */ 1470 all_bits = resource; 1471 my_bit = resource; 1472 } 1473 1474 /* lock against other callers within the driver wanting a resource */ 1475 mutex_lock(&dd->asic_data->asic_resource_mutex); 1476 1477 ret = acquire_hw_mutex(dd); 1478 if (ret) { 1479 fail_mutex_acquire_message(dd, __func__); 1480 ret = -EIO; 1481 goto done; 1482 } 1483 1484 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1485 if (scratch0 & all_bits) { 1486 ret = -EBUSY; 1487 } else { 1488 write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit); 1489 /* force write to be visible to other HFI on another OS */ 1490 (void)read_csr(dd, ASIC_CFG_SCRATCH); 1491 } 1492 1493 release_hw_mutex(dd); 1494 1495 done: 1496 mutex_unlock(&dd->asic_data->asic_resource_mutex); 1497 return ret; 1498 } 1499 1500 /* 1501 * Acquire access to a chip resource, wait up to mswait milliseconds for 1502 * the resource to become available. 1503 * 1504 * Return 0 on success, -EBUSY if busy (even after wait), -EIO if mutex 1505 * acquire failed. 1506 */ 1507 int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait) 1508 { 1509 unsigned long timeout; 1510 int ret; 1511 1512 timeout = jiffies + msecs_to_jiffies(mswait); 1513 while (1) { 1514 ret = __acquire_chip_resource(dd, resource); 1515 if (ret != -EBUSY) 1516 return ret; 1517 /* resource is busy, check our timeout */ 1518 if (time_after_eq(jiffies, timeout)) 1519 return -EBUSY; 1520 usleep_range(80, 120); /* arbitrary delay */ 1521 } 1522 } 1523 1524 /* 1525 * Release access to a chip resource 1526 */ 1527 void release_chip_resource(struct hfi1_devdata *dd, u32 resource) 1528 { 1529 u64 scratch0, bit; 1530 1531 /* only dynamic resources should ever be cleared */ 1532 if (!(resource & CR_DYN_MASK)) { 1533 dd_dev_err(dd, "%s: invalid resource 0x%x\n", __func__, 1534 resource); 1535 return; 1536 } 1537 bit = resource_mask(dd->hfi1_id, resource); 1538 1539 /* lock against other callers within the driver wanting a resource */ 1540 mutex_lock(&dd->asic_data->asic_resource_mutex); 1541 1542 if (acquire_hw_mutex(dd)) { 1543 fail_mutex_acquire_message(dd, __func__); 1544 goto done; 1545 } 1546 1547 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1548 if ((scratch0 & bit) != 0) { 1549 scratch0 &= ~bit; 1550 write_csr(dd, ASIC_CFG_SCRATCH, scratch0); 1551 /* force write to be visible to other HFI on another OS */ 1552 (void)read_csr(dd, ASIC_CFG_SCRATCH); 1553 } else { 1554 dd_dev_warn(dd, "%s: id %d, resource 0x%x: bit not set\n", 1555 __func__, dd->hfi1_id, resource); 1556 } 1557 1558 release_hw_mutex(dd); 1559 1560 done: 1561 mutex_unlock(&dd->asic_data->asic_resource_mutex); 1562 } 1563 1564 /* 1565 * Return true if resource is set, false otherwise. Print a warning 1566 * if not set and a function is supplied. 1567 */ 1568 bool check_chip_resource(struct hfi1_devdata *dd, u32 resource, 1569 const char *func) 1570 { 1571 u64 scratch0, bit; 1572 1573 if (resource & CR_DYN_MASK) 1574 bit = resource_mask(dd->hfi1_id, resource); 1575 else 1576 bit = resource; 1577 1578 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1579 if ((scratch0 & bit) == 0) { 1580 if (func) 1581 dd_dev_warn(dd, 1582 "%s: id %d, resource 0x%x, not acquired!\n", 1583 func, dd->hfi1_id, resource); 1584 return false; 1585 } 1586 return true; 1587 } 1588 1589 static void clear_chip_resources(struct hfi1_devdata *dd, const char *func) 1590 { 1591 u64 scratch0; 1592 1593 /* lock against other callers within the driver wanting a resource */ 1594 mutex_lock(&dd->asic_data->asic_resource_mutex); 1595 1596 if (acquire_hw_mutex(dd)) { 1597 fail_mutex_acquire_message(dd, func); 1598 goto done; 1599 } 1600 1601 /* clear all dynamic access bits for this HFI */ 1602 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); 1603 scratch0 &= ~resource_mask(dd->hfi1_id, CR_DYN_MASK); 1604 write_csr(dd, ASIC_CFG_SCRATCH, scratch0); 1605 /* force write to be visible to other HFI on another OS */ 1606 (void)read_csr(dd, ASIC_CFG_SCRATCH); 1607 1608 release_hw_mutex(dd); 1609 1610 done: 1611 mutex_unlock(&dd->asic_data->asic_resource_mutex); 1612 } 1613 1614 void init_chip_resources(struct hfi1_devdata *dd) 1615 { 1616 /* clear any holds left by us */ 1617 clear_chip_resources(dd, __func__); 1618 } 1619 1620 void finish_chip_resources(struct hfi1_devdata *dd) 1621 { 1622 /* clear any holds left by us */ 1623 clear_chip_resources(dd, __func__); 1624 } 1625 1626 void set_sbus_fast_mode(struct hfi1_devdata *dd) 1627 { 1628 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 1629 ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK); 1630 } 1631 1632 void clear_sbus_fast_mode(struct hfi1_devdata *dd) 1633 { 1634 u64 reg, count = 0; 1635 1636 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); 1637 while (SBUS_COUNTER(reg, EXECUTE) != 1638 SBUS_COUNTER(reg, RCV_DATA_VALID)) { 1639 if (count++ >= SBUS_MAX_POLL_COUNT) 1640 break; 1641 udelay(1); 1642 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); 1643 } 1644 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0); 1645 } 1646 1647 int load_firmware(struct hfi1_devdata *dd) 1648 { 1649 int ret; 1650 1651 if (fw_fabric_serdes_load) { 1652 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 1653 if (ret) 1654 return ret; 1655 1656 set_sbus_fast_mode(dd); 1657 1658 set_serdes_broadcast(dd, all_fabric_serdes_broadcast, 1659 fabric_serdes_broadcast[dd->hfi1_id], 1660 fabric_serdes_addrs[dd->hfi1_id], 1661 NUM_FABRIC_SERDES); 1662 turn_off_spicos(dd, SPICO_FABRIC); 1663 do { 1664 ret = load_fabric_serdes_firmware(dd, &fw_fabric); 1665 } while (retry_firmware(dd, ret)); 1666 1667 clear_sbus_fast_mode(dd); 1668 release_chip_resource(dd, CR_SBUS); 1669 if (ret) 1670 return ret; 1671 } 1672 1673 if (fw_8051_load) { 1674 do { 1675 ret = load_8051_firmware(dd, &fw_8051); 1676 } while (retry_firmware(dd, ret)); 1677 if (ret) 1678 return ret; 1679 } 1680 1681 dump_fw_version(dd); 1682 return 0; 1683 } 1684 1685 int hfi1_firmware_init(struct hfi1_devdata *dd) 1686 { 1687 /* only RTL can use these */ 1688 if (dd->icode != ICODE_RTL_SILICON) { 1689 fw_fabric_serdes_load = 0; 1690 fw_pcie_serdes_load = 0; 1691 fw_sbus_load = 0; 1692 } 1693 1694 /* no 8051 or QSFP on simulator */ 1695 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) { 1696 fw_8051_load = 0; 1697 platform_config_load = 0; 1698 } 1699 1700 if (!fw_8051_name) { 1701 if (dd->icode == ICODE_RTL_SILICON) 1702 fw_8051_name = DEFAULT_FW_8051_NAME_ASIC; 1703 else 1704 fw_8051_name = DEFAULT_FW_8051_NAME_FPGA; 1705 } 1706 if (!fw_fabric_serdes_name) 1707 fw_fabric_serdes_name = DEFAULT_FW_FABRIC_NAME; 1708 if (!fw_sbus_name) 1709 fw_sbus_name = DEFAULT_FW_SBUS_NAME; 1710 if (!fw_pcie_serdes_name) 1711 fw_pcie_serdes_name = DEFAULT_FW_PCIE_NAME; 1712 if (!platform_config_name) 1713 platform_config_name = DEFAULT_PLATFORM_CONFIG_NAME; 1714 1715 return obtain_firmware(dd); 1716 } 1717 1718 /* 1719 * This function is a helper function for parse_platform_config(...) and 1720 * does not check for validity of the platform configuration cache 1721 * (because we know it is invalid as we are building up the cache). 1722 * As such, this should not be called from anywhere other than 1723 * parse_platform_config 1724 */ 1725 static int check_meta_version(struct hfi1_devdata *dd, u32 *system_table) 1726 { 1727 u32 meta_ver, meta_ver_meta, ver_start, ver_len, mask; 1728 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 1729 1730 if (!system_table) 1731 return -EINVAL; 1732 1733 meta_ver_meta = 1734 *(pcfgcache->config_tables[PLATFORM_CONFIG_SYSTEM_TABLE].table_metadata 1735 + SYSTEM_TABLE_META_VERSION); 1736 1737 mask = ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1); 1738 ver_start = meta_ver_meta & mask; 1739 1740 meta_ver_meta >>= METADATA_TABLE_FIELD_LEN_SHIFT; 1741 1742 mask = ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1); 1743 ver_len = meta_ver_meta & mask; 1744 1745 ver_start /= 8; 1746 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1); 1747 1748 if (meta_ver < 5) { 1749 dd_dev_info( 1750 dd, "%s:Please update platform config\n", __func__); 1751 return -EINVAL; 1752 } 1753 return 0; 1754 } 1755 1756 int parse_platform_config(struct hfi1_devdata *dd) 1757 { 1758 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 1759 u32 *ptr = NULL; 1760 u32 header1 = 0, header2 = 0, magic_num = 0, crc = 0, file_length = 0; 1761 u32 record_idx = 0, table_type = 0, table_length_dwords = 0; 1762 int ret = -EINVAL; /* assume failure */ 1763 1764 if (!dd->platform_config.data) { 1765 dd_dev_info(dd, "%s: Missing config file\n", __func__); 1766 goto bail; 1767 } 1768 ptr = (u32 *)dd->platform_config.data; 1769 1770 magic_num = *ptr; 1771 ptr++; 1772 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) { 1773 dd_dev_info(dd, "%s: Bad config file\n", __func__); 1774 goto bail; 1775 } 1776 1777 /* Field is file size in DWORDs */ 1778 file_length = (*ptr) * 4; 1779 ptr++; 1780 1781 if (file_length > dd->platform_config.size) { 1782 dd_dev_info(dd, "%s:File claims to be larger than read size\n", 1783 __func__); 1784 goto bail; 1785 } else if (file_length < dd->platform_config.size) { 1786 dd_dev_info(dd, 1787 "%s:File claims to be smaller than read size, continuing\n", 1788 __func__); 1789 } 1790 /* exactly equal, perfection */ 1791 1792 /* 1793 * In both cases where we proceed, using the self-reported file length 1794 * is the safer option 1795 */ 1796 while (ptr < (u32 *)(dd->platform_config.data + file_length)) { 1797 header1 = *ptr; 1798 header2 = *(ptr + 1); 1799 if (header1 != ~header2) { 1800 dd_dev_info(dd, "%s: Failed validation at offset %ld\n", 1801 __func__, (ptr - (u32 *) 1802 dd->platform_config.data)); 1803 goto bail; 1804 } 1805 1806 record_idx = *ptr & 1807 ((1 << PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS) - 1); 1808 1809 table_length_dwords = (*ptr >> 1810 PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT) & 1811 ((1 << PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS) - 1); 1812 1813 table_type = (*ptr >> PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT) & 1814 ((1 << PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS) - 1); 1815 1816 /* Done with this set of headers */ 1817 ptr += 2; 1818 1819 if (record_idx) { 1820 /* data table */ 1821 switch (table_type) { 1822 case PLATFORM_CONFIG_SYSTEM_TABLE: 1823 pcfgcache->config_tables[table_type].num_table = 1824 1; 1825 ret = check_meta_version(dd, ptr); 1826 if (ret) 1827 goto bail; 1828 break; 1829 case PLATFORM_CONFIG_PORT_TABLE: 1830 pcfgcache->config_tables[table_type].num_table = 1831 2; 1832 break; 1833 case PLATFORM_CONFIG_RX_PRESET_TABLE: 1834 /* fall through */ 1835 case PLATFORM_CONFIG_TX_PRESET_TABLE: 1836 /* fall through */ 1837 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 1838 /* fall through */ 1839 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 1840 pcfgcache->config_tables[table_type].num_table = 1841 table_length_dwords; 1842 break; 1843 default: 1844 dd_dev_info(dd, 1845 "%s: Unknown data table %d, offset %ld\n", 1846 __func__, table_type, 1847 (ptr - (u32 *) 1848 dd->platform_config.data)); 1849 goto bail; /* We don't trust this file now */ 1850 } 1851 pcfgcache->config_tables[table_type].table = ptr; 1852 } else { 1853 /* metadata table */ 1854 switch (table_type) { 1855 case PLATFORM_CONFIG_SYSTEM_TABLE: 1856 /* fall through */ 1857 case PLATFORM_CONFIG_PORT_TABLE: 1858 /* fall through */ 1859 case PLATFORM_CONFIG_RX_PRESET_TABLE: 1860 /* fall through */ 1861 case PLATFORM_CONFIG_TX_PRESET_TABLE: 1862 /* fall through */ 1863 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 1864 /* fall through */ 1865 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 1866 break; 1867 default: 1868 dd_dev_info(dd, 1869 "%s: Unknown meta table %d, offset %ld\n", 1870 __func__, table_type, 1871 (ptr - 1872 (u32 *)dd->platform_config.data)); 1873 goto bail; /* We don't trust this file now */ 1874 } 1875 pcfgcache->config_tables[table_type].table_metadata = 1876 ptr; 1877 } 1878 1879 /* Calculate and check table crc */ 1880 crc = crc32_le(~(u32)0, (unsigned char const *)ptr, 1881 (table_length_dwords * 4)); 1882 crc ^= ~(u32)0; 1883 1884 /* Jump the table */ 1885 ptr += table_length_dwords; 1886 if (crc != *ptr) { 1887 dd_dev_info(dd, "%s: Failed CRC check at offset %ld\n", 1888 __func__, (ptr - 1889 (u32 *) 1890 dd->platform_config.data)); 1891 goto bail; 1892 } 1893 /* Jump the CRC DWORD */ 1894 ptr++; 1895 } 1896 1897 pcfgcache->cache_valid = 1; 1898 return 0; 1899 bail: 1900 memset(pcfgcache, 0, sizeof(struct platform_config_cache)); 1901 return ret; 1902 } 1903 1904 static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table, 1905 int field, u32 *field_len_bits, 1906 u32 *field_start_bits) 1907 { 1908 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 1909 u32 *src_ptr = NULL; 1910 1911 if (!pcfgcache->cache_valid) 1912 return -EINVAL; 1913 1914 switch (table) { 1915 case PLATFORM_CONFIG_SYSTEM_TABLE: 1916 /* fall through */ 1917 case PLATFORM_CONFIG_PORT_TABLE: 1918 /* fall through */ 1919 case PLATFORM_CONFIG_RX_PRESET_TABLE: 1920 /* fall through */ 1921 case PLATFORM_CONFIG_TX_PRESET_TABLE: 1922 /* fall through */ 1923 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 1924 /* fall through */ 1925 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 1926 if (field && field < platform_config_table_limits[table]) 1927 src_ptr = 1928 pcfgcache->config_tables[table].table_metadata + field; 1929 break; 1930 default: 1931 dd_dev_info(dd, "%s: Unknown table\n", __func__); 1932 break; 1933 } 1934 1935 if (!src_ptr) 1936 return -EINVAL; 1937 1938 if (field_start_bits) 1939 *field_start_bits = *src_ptr & 1940 ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1); 1941 1942 if (field_len_bits) 1943 *field_len_bits = (*src_ptr >> METADATA_TABLE_FIELD_LEN_SHIFT) 1944 & ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1); 1945 1946 return 0; 1947 } 1948 1949 /* This is the central interface to getting data out of the platform config 1950 * file. It depends on parse_platform_config() having populated the 1951 * platform_config_cache in hfi1_devdata, and checks the cache_valid member to 1952 * validate the sanity of the cache. 1953 * 1954 * The non-obvious parameters: 1955 * @table_index: Acts as a look up key into which instance of the tables the 1956 * relevant field is fetched from. 1957 * 1958 * This applies to the data tables that have multiple instances. The port table 1959 * is an exception to this rule as each HFI only has one port and thus the 1960 * relevant table can be distinguished by hfi_id. 1961 * 1962 * @data: pointer to memory that will be populated with the field requested. 1963 * @len: length of memory pointed by @data in bytes. 1964 */ 1965 int get_platform_config_field(struct hfi1_devdata *dd, 1966 enum platform_config_table_type_encoding 1967 table_type, int table_index, int field_index, 1968 u32 *data, u32 len) 1969 { 1970 int ret = 0, wlen = 0, seek = 0; 1971 u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL; 1972 struct platform_config_cache *pcfgcache = &dd->pcfg_cache; 1973 1974 if (data) 1975 memset(data, 0, len); 1976 else 1977 return -EINVAL; 1978 1979 ret = get_platform_fw_field_metadata(dd, table_type, field_index, 1980 &field_len_bits, 1981 &field_start_bits); 1982 if (ret) 1983 return -EINVAL; 1984 1985 /* Convert length to bits */ 1986 len *= 8; 1987 1988 /* Our metadata function checked cache_valid and field_index for us */ 1989 switch (table_type) { 1990 case PLATFORM_CONFIG_SYSTEM_TABLE: 1991 src_ptr = pcfgcache->config_tables[table_type].table; 1992 1993 if (field_index != SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) { 1994 if (len < field_len_bits) 1995 return -EINVAL; 1996 1997 seek = field_start_bits / 8; 1998 wlen = field_len_bits / 8; 1999 2000 src_ptr = (u32 *)((u8 *)src_ptr + seek); 2001 2002 /* 2003 * We expect the field to be byte aligned and whole byte 2004 * lengths if we are here 2005 */ 2006 memcpy(data, src_ptr, wlen); 2007 return 0; 2008 } 2009 break; 2010 case PLATFORM_CONFIG_PORT_TABLE: 2011 /* Port table is 4 DWORDS */ 2012 src_ptr = dd->hfi1_id ? 2013 pcfgcache->config_tables[table_type].table + 4 : 2014 pcfgcache->config_tables[table_type].table; 2015 break; 2016 case PLATFORM_CONFIG_RX_PRESET_TABLE: 2017 /* fall through */ 2018 case PLATFORM_CONFIG_TX_PRESET_TABLE: 2019 /* fall through */ 2020 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE: 2021 /* fall through */ 2022 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 2023 src_ptr = pcfgcache->config_tables[table_type].table; 2024 2025 if (table_index < 2026 pcfgcache->config_tables[table_type].num_table) 2027 src_ptr += table_index; 2028 else 2029 src_ptr = NULL; 2030 break; 2031 default: 2032 dd_dev_info(dd, "%s: Unknown table\n", __func__); 2033 break; 2034 } 2035 2036 if (!src_ptr || len < field_len_bits) 2037 return -EINVAL; 2038 2039 src_ptr += (field_start_bits / 32); 2040 *data = (*src_ptr >> (field_start_bits % 32)) & 2041 ((1 << field_len_bits) - 1); 2042 2043 return 0; 2044 } 2045 2046 /* 2047 * Download the firmware needed for the Gen3 PCIe SerDes. An update 2048 * to the SBus firmware is needed before updating the PCIe firmware. 2049 * 2050 * Note: caller must be holding the SBus resource. 2051 */ 2052 int load_pcie_firmware(struct hfi1_devdata *dd) 2053 { 2054 int ret = 0; 2055 2056 /* both firmware loads below use the SBus */ 2057 set_sbus_fast_mode(dd); 2058 2059 if (fw_sbus_load) { 2060 turn_off_spicos(dd, SPICO_SBUS); 2061 do { 2062 ret = load_sbus_firmware(dd, &fw_sbus); 2063 } while (retry_firmware(dd, ret)); 2064 if (ret) 2065 goto done; 2066 } 2067 2068 if (fw_pcie_serdes_load) { 2069 dd_dev_info(dd, "Setting PCIe SerDes broadcast\n"); 2070 set_serdes_broadcast(dd, all_pcie_serdes_broadcast, 2071 pcie_serdes_broadcast[dd->hfi1_id], 2072 pcie_serdes_addrs[dd->hfi1_id], 2073 NUM_PCIE_SERDES); 2074 do { 2075 ret = load_pcie_serdes_firmware(dd, &fw_pcie); 2076 } while (retry_firmware(dd, ret)); 2077 if (ret) 2078 goto done; 2079 } 2080 2081 done: 2082 clear_sbus_fast_mode(dd); 2083 2084 return ret; 2085 } 2086 2087 /* 2088 * Read the GUID from the hardware, store it in dd. 2089 */ 2090 void read_guid(struct hfi1_devdata *dd) 2091 { 2092 /* Take the DC out of reset to get a valid GUID value */ 2093 write_csr(dd, CCE_DC_CTRL, 0); 2094 (void)read_csr(dd, CCE_DC_CTRL); 2095 2096 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID); 2097 dd_dev_info(dd, "GUID %llx", 2098 (unsigned long long)dd->base_guid); 2099 } 2100 2101 /* read and display firmware version info */ 2102 static void dump_fw_version(struct hfi1_devdata *dd) 2103 { 2104 u32 pcie_vers[NUM_PCIE_SERDES]; 2105 u32 fabric_vers[NUM_FABRIC_SERDES]; 2106 u32 sbus_vers; 2107 int i; 2108 int all_same; 2109 int ret; 2110 u8 rcv_addr; 2111 2112 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); 2113 if (ret) { 2114 dd_dev_err(dd, "Unable to acquire SBus to read firmware versions\n"); 2115 return; 2116 } 2117 2118 /* set fast mode */ 2119 set_sbus_fast_mode(dd); 2120 2121 /* read version for SBus Master */ 2122 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x02, WRITE_SBUS_RECEIVER, 0); 2123 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x07, WRITE_SBUS_RECEIVER, 0x1); 2124 /* wait for interrupt to be processed */ 2125 usleep_range(10000, 11000); 2126 sbus_vers = sbus_read(dd, SBUS_MASTER_BROADCAST, 0x08, 0x1); 2127 dd_dev_info(dd, "SBus Master firmware version 0x%08x\n", sbus_vers); 2128 2129 /* read version for PCIe SerDes */ 2130 all_same = 1; 2131 pcie_vers[0] = 0; 2132 for (i = 0; i < NUM_PCIE_SERDES; i++) { 2133 rcv_addr = pcie_serdes_addrs[dd->hfi1_id][i]; 2134 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0); 2135 /* wait for interrupt to be processed */ 2136 usleep_range(10000, 11000); 2137 pcie_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0); 2138 if (i > 0 && pcie_vers[0] != pcie_vers[i]) 2139 all_same = 0; 2140 } 2141 2142 if (all_same) { 2143 dd_dev_info(dd, "PCIe SerDes firmware version 0x%x\n", 2144 pcie_vers[0]); 2145 } else { 2146 dd_dev_warn(dd, "PCIe SerDes do not have the same firmware version\n"); 2147 for (i = 0; i < NUM_PCIE_SERDES; i++) { 2148 dd_dev_info(dd, 2149 "PCIe SerDes lane %d firmware version 0x%x\n", 2150 i, pcie_vers[i]); 2151 } 2152 } 2153 2154 /* read version for fabric SerDes */ 2155 all_same = 1; 2156 fabric_vers[0] = 0; 2157 for (i = 0; i < NUM_FABRIC_SERDES; i++) { 2158 rcv_addr = fabric_serdes_addrs[dd->hfi1_id][i]; 2159 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0); 2160 /* wait for interrupt to be processed */ 2161 usleep_range(10000, 11000); 2162 fabric_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0); 2163 if (i > 0 && fabric_vers[0] != fabric_vers[i]) 2164 all_same = 0; 2165 } 2166 2167 if (all_same) { 2168 dd_dev_info(dd, "Fabric SerDes firmware version 0x%x\n", 2169 fabric_vers[0]); 2170 } else { 2171 dd_dev_warn(dd, "Fabric SerDes do not have the same firmware version\n"); 2172 for (i = 0; i < NUM_FABRIC_SERDES; i++) { 2173 dd_dev_info(dd, 2174 "Fabric SerDes lane %d firmware version 0x%x\n", 2175 i, fabric_vers[i]); 2176 } 2177 } 2178 2179 clear_sbus_fast_mode(dd); 2180 release_chip_resource(dd, CR_SBUS); 2181 } 2182