1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2026 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_COM_H_ 7 #define _EFA_COM_H_ 8 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/semaphore.h> 13 #include <linux/sched.h> 14 15 #include <rdma/ib_verbs.h> 16 17 #include "efa_ah_cache.h" 18 #include "efa_common_defs.h" 19 #include "efa_admin_defs.h" 20 #include "efa_admin_cmds_defs.h" 21 #include "efa_regs_defs.h" 22 23 #define EFA_MAX_HANDLERS 256 24 25 #define EFA_ADMIN_V1_PROTO_VER 0 26 #define EFA_ADMIN_V2_PROTO_VER 1 27 28 struct efa_com_admin_cq { 29 struct efa_admin_acq_entry *entries; 30 dma_addr_t dma_addr; 31 spinlock_t lock; /* Protects ACQ */ 32 bool validate_checksum; 33 34 u16 cc; /* consumer counter */ 35 u8 phase; 36 }; 37 38 struct efa_com_admin_sq { 39 u8 *buffer; 40 u16 entry_size; 41 u16 payload_offset; 42 u16 max_payload_size; 43 dma_addr_t dma_addr; 44 spinlock_t lock; /* Protects ASQ */ 45 u8 proto_ver; 46 47 u32 __iomem *db_addr; 48 49 u16 cc; /* consumer counter */ 50 u16 pc; /* producer counter */ 51 u8 phase; 52 53 }; 54 55 /* Don't use anything other than atomic64 */ 56 struct efa_com_stats_admin { 57 atomic64_t submitted_cmd; 58 atomic64_t completed_cmd; 59 atomic64_t cmd_err; 60 atomic64_t no_completion; 61 }; 62 63 enum { 64 EFA_AQ_STATE_RUNNING_BIT = 0, 65 EFA_AQ_STATE_POLLING_BIT = 1, 66 }; 67 68 struct efa_com_admin_queue { 69 void *dmadev; 70 void *efa_dev; 71 struct efa_comp_ctx *comp_ctx; 72 u32 completion_timeout; /* usecs */ 73 u16 poll_interval; /* msecs */ 74 u16 depth; 75 struct efa_com_admin_cq cq; 76 struct efa_com_admin_sq sq; 77 u32 msix_vector_idx; 78 79 unsigned long state; 80 81 /* Count the number of available admin commands */ 82 struct semaphore avail_cmds; 83 84 struct efa_com_stats_admin stats; 85 86 spinlock_t comp_ctx_lock; /* Protects completion context pool */ 87 u32 *comp_ctx_pool; 88 u16 comp_ctx_pool_next; 89 }; 90 91 struct efa_aenq_handlers; 92 struct efa_com_eq; 93 typedef void (*efa_eqe_handler)(struct efa_com_eq *eeq, 94 struct efa_admin_eqe *eqe); 95 96 struct efa_com_aenq { 97 struct efa_admin_aenq_entry *entries; 98 struct efa_aenq_handlers *aenq_handlers; 99 dma_addr_t dma_addr; 100 u32 cc; /* consumer counter */ 101 u32 msix_vector_idx; 102 u16 depth; 103 u8 phase; 104 }; 105 106 struct efa_com_mmio_read { 107 struct efa_admin_mmio_req_read_less_resp *read_resp; 108 dma_addr_t read_resp_dma_addr; 109 u16 seq_num; 110 u16 mmio_read_timeout; /* usecs */ 111 /* serializes mmio reads */ 112 spinlock_t lock; 113 }; 114 115 struct efa_com_dev { 116 struct efa_com_admin_queue aq; 117 struct efa_com_aenq aenq; 118 u8 __iomem *reg_bar; 119 void *dmadev; 120 void *efa_dev; 121 u32 supported_features; 122 u32 dma_addr_bits; 123 124 struct efa_ah_cache ah_cache; 125 126 u32 dev_api_ver; 127 struct efa_com_mmio_read mmio_read; 128 }; 129 130 struct efa_com_eq { 131 struct efa_com_dev *edev; 132 struct efa_admin_eqe *eqes; 133 dma_addr_t dma_addr; 134 u32 cc; /* Consumer counter */ 135 u16 eqn; 136 u16 depth; 137 u8 phase; 138 efa_eqe_handler cb; 139 }; 140 141 struct efa_com_create_eq_params { 142 dma_addr_t dma_addr; 143 u32 event_bitmask; 144 u16 depth; 145 u8 entry_size_in_bytes; 146 u8 msix_vec; 147 }; 148 149 struct efa_com_create_eq_result { 150 u16 eqn; 151 }; 152 153 struct efa_com_destroy_eq_params { 154 u16 eqn; 155 }; 156 157 typedef void (*efa_aenq_handler)(void *data, 158 struct efa_admin_aenq_entry *aenq_e); 159 160 /* Holds aenq handlers. Indexed by AENQ event group */ 161 struct efa_aenq_handlers { 162 efa_aenq_handler handlers[EFA_MAX_HANDLERS]; 163 efa_aenq_handler unimplemented_handler; 164 }; 165 166 void efa_com_set_dma_addr(dma_addr_t addr, u32 *addr_high, u32 *addr_low); 167 int efa_com_admin_init(struct efa_com_dev *edev, 168 struct efa_aenq_handlers *aenq_handlers); 169 void efa_com_admin_destroy(struct efa_com_dev *edev); 170 int efa_com_eq_init(struct efa_com_dev *edev, struct efa_com_eq *eeq, 171 efa_eqe_handler cb, u16 depth, u8 msix_vec); 172 void efa_com_eq_destroy(struct efa_com_dev *edev, struct efa_com_eq *eeq); 173 int efa_com_dev_reset(struct efa_com_dev *edev, 174 enum efa_regs_reset_reason_types reset_reason); 175 void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling); 176 void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev); 177 int efa_com_mmio_reg_read_init(struct efa_com_dev *edev); 178 void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev); 179 180 int efa_com_validate_version(struct efa_com_dev *edev); 181 int efa_com_get_dma_width(struct efa_com_dev *edev); 182 183 int efa_com_cmd_exec(struct efa_com_admin_queue *aq, 184 u8 opcode, u8 flags, 185 void *payload, size_t payload_size, 186 struct efa_admin_acq_entry *comp, size_t comp_size); 187 void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data); 188 void efa_com_eq_comp_intr_handler(struct efa_com_dev *edev, 189 struct efa_com_eq *eeq); 190 191 #endif /* _EFA_COM_H_ */ 192