1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 /* 3 * Copyright 2018-2025 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #include <linux/log2.h> 7 8 #include "efa_com.h" 9 #include "efa_regs_defs.h" 10 11 #define ADMIN_CMD_TIMEOUT_US 30000000 /* usecs */ 12 13 #define EFA_REG_READ_TIMEOUT_US 50000 /* usecs */ 14 #define EFA_MMIO_READ_INVALID 0xffffffff 15 16 #define EFA_POLL_INTERVAL_MS 100 /* msecs */ 17 18 #define EFA_ASYNC_QUEUE_DEPTH 16 19 #define EFA_ADMIN_QUEUE_DEPTH 32 20 21 #define EFA_CTRL_MAJOR 0 22 #define EFA_CTRL_MINOR 0 23 #define EFA_CTRL_SUB_MINOR 1 24 25 enum efa_cmd_status { 26 EFA_CMD_UNUSED, 27 EFA_CMD_ALLOCATED, 28 EFA_CMD_SUBMITTED, 29 EFA_CMD_COMPLETED, 30 }; 31 32 struct efa_comp_ctx { 33 struct completion wait_event; 34 struct efa_admin_acq_entry *user_cqe; 35 u32 comp_size; 36 enum efa_cmd_status status; 37 u16 cmd_id; 38 u8 cmd_opcode; 39 }; 40 41 static const char *efa_com_cmd_str(u8 cmd) 42 { 43 #define EFA_CMD_STR_CASE(_cmd) case EFA_ADMIN_##_cmd: return #_cmd 44 45 switch (cmd) { 46 EFA_CMD_STR_CASE(CREATE_QP); 47 EFA_CMD_STR_CASE(MODIFY_QP); 48 EFA_CMD_STR_CASE(QUERY_QP); 49 EFA_CMD_STR_CASE(DESTROY_QP); 50 EFA_CMD_STR_CASE(CREATE_AH); 51 EFA_CMD_STR_CASE(DESTROY_AH); 52 EFA_CMD_STR_CASE(REG_MR); 53 EFA_CMD_STR_CASE(DEREG_MR); 54 EFA_CMD_STR_CASE(CREATE_CQ); 55 EFA_CMD_STR_CASE(DESTROY_CQ); 56 EFA_CMD_STR_CASE(GET_FEATURE); 57 EFA_CMD_STR_CASE(SET_FEATURE); 58 EFA_CMD_STR_CASE(GET_STATS); 59 EFA_CMD_STR_CASE(ALLOC_PD); 60 EFA_CMD_STR_CASE(DEALLOC_PD); 61 EFA_CMD_STR_CASE(ALLOC_UAR); 62 EFA_CMD_STR_CASE(DEALLOC_UAR); 63 EFA_CMD_STR_CASE(CREATE_EQ); 64 EFA_CMD_STR_CASE(DESTROY_EQ); 65 default: return "unknown command opcode"; 66 } 67 #undef EFA_CMD_STR_CASE 68 } 69 70 void efa_com_set_dma_addr(dma_addr_t addr, u32 *addr_high, u32 *addr_low) 71 { 72 *addr_low = lower_32_bits(addr); 73 *addr_high = upper_32_bits(addr); 74 } 75 76 static u32 efa_com_reg_read32(struct efa_com_dev *edev, u16 offset) 77 { 78 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 79 struct efa_admin_mmio_req_read_less_resp *read_resp; 80 unsigned long exp_time; 81 u32 mmio_read_reg = 0; 82 u32 err; 83 84 read_resp = mmio_read->read_resp; 85 86 spin_lock(&mmio_read->lock); 87 mmio_read->seq_num++; 88 89 /* trash DMA req_id to identify when hardware is done */ 90 read_resp->req_id = mmio_read->seq_num + 0x9aL; 91 EFA_SET(&mmio_read_reg, EFA_REGS_MMIO_REG_READ_REG_OFF, offset); 92 EFA_SET(&mmio_read_reg, EFA_REGS_MMIO_REG_READ_REQ_ID, 93 mmio_read->seq_num); 94 95 writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF); 96 97 exp_time = jiffies + usecs_to_jiffies(mmio_read->mmio_read_timeout); 98 do { 99 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num) 100 break; 101 udelay(1); 102 } while (time_is_after_jiffies(exp_time)); 103 104 if (read_resp->req_id != mmio_read->seq_num) { 105 ibdev_err_ratelimited( 106 edev->efa_dev, 107 "Reading register timed out. expected: req id[%u] offset[%#x] actual: req id[%u] offset[%#x]\n", 108 mmio_read->seq_num, offset, read_resp->req_id, 109 read_resp->reg_off); 110 err = EFA_MMIO_READ_INVALID; 111 goto out; 112 } 113 114 if (read_resp->reg_off != offset) { 115 ibdev_err_ratelimited( 116 edev->efa_dev, 117 "Reading register failed: wrong offset provided\n"); 118 err = EFA_MMIO_READ_INVALID; 119 goto out; 120 } 121 122 err = read_resp->reg_val; 123 out: 124 spin_unlock(&mmio_read->lock); 125 return err; 126 } 127 128 static int efa_com_admin_init_sq(struct efa_com_dev *edev) 129 { 130 struct efa_com_admin_queue *aq = &edev->aq; 131 struct efa_com_admin_sq *sq = &aq->sq; 132 u16 size = aq->depth * sizeof(*sq->entries); 133 u32 aq_caps = 0; 134 u32 addr_high; 135 u32 addr_low; 136 137 sq->entries = 138 dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL); 139 if (!sq->entries) 140 return -ENOMEM; 141 142 spin_lock_init(&sq->lock); 143 144 sq->cc = 0; 145 sq->pc = 0; 146 sq->phase = 1; 147 148 sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF); 149 150 addr_high = upper_32_bits(sq->dma_addr); 151 addr_low = lower_32_bits(sq->dma_addr); 152 153 writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF); 154 writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF); 155 156 EFA_SET(&aq_caps, EFA_REGS_AQ_CAPS_AQ_DEPTH, aq->depth); 157 EFA_SET(&aq_caps, EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE, 158 sizeof(struct efa_admin_aq_entry)); 159 160 writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF); 161 162 return 0; 163 } 164 165 static int efa_com_admin_init_cq(struct efa_com_dev *edev) 166 { 167 struct efa_com_admin_queue *aq = &edev->aq; 168 struct efa_com_admin_cq *cq = &aq->cq; 169 u16 size = aq->depth * sizeof(*cq->entries); 170 u32 acq_caps = 0; 171 u32 addr_high; 172 u32 addr_low; 173 174 cq->entries = 175 dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL); 176 if (!cq->entries) 177 return -ENOMEM; 178 179 spin_lock_init(&cq->lock); 180 181 cq->cc = 0; 182 cq->phase = 1; 183 184 addr_high = upper_32_bits(cq->dma_addr); 185 addr_low = lower_32_bits(cq->dma_addr); 186 187 writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF); 188 writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF); 189 190 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_DEPTH, aq->depth); 191 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE, 192 sizeof(struct efa_admin_acq_entry)); 193 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR, 194 aq->msix_vector_idx); 195 196 writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF); 197 198 return 0; 199 } 200 201 static int efa_com_admin_init_aenq(struct efa_com_dev *edev, 202 struct efa_aenq_handlers *aenq_handlers) 203 { 204 struct efa_com_aenq *aenq = &edev->aenq; 205 u32 addr_low, addr_high; 206 u32 aenq_caps = 0; 207 u16 size; 208 209 if (!aenq_handlers) { 210 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n"); 211 return -EINVAL; 212 } 213 214 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries); 215 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr, 216 GFP_KERNEL); 217 if (!aenq->entries) 218 return -ENOMEM; 219 220 aenq->aenq_handlers = aenq_handlers; 221 aenq->depth = EFA_ASYNC_QUEUE_DEPTH; 222 aenq->cc = 0; 223 aenq->phase = 1; 224 225 addr_low = lower_32_bits(aenq->dma_addr); 226 addr_high = upper_32_bits(aenq->dma_addr); 227 228 writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF); 229 writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF); 230 231 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_DEPTH, aenq->depth); 232 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE, 233 sizeof(struct efa_admin_aenq_entry)); 234 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR, 235 aenq->msix_vector_idx); 236 writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF); 237 238 /* 239 * Init cons_db to mark that all entries in the queue 240 * are initially available 241 */ 242 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); 243 244 return 0; 245 } 246 247 static u16 efa_com_alloc_ctx_id(struct efa_com_admin_queue *aq) 248 { 249 u16 ctx_id; 250 251 spin_lock(&aq->comp_ctx_lock); 252 ctx_id = aq->comp_ctx_pool[aq->comp_ctx_pool_next]; 253 aq->comp_ctx_pool_next++; 254 spin_unlock(&aq->comp_ctx_lock); 255 256 return ctx_id; 257 } 258 259 static void efa_com_dealloc_ctx_id(struct efa_com_admin_queue *aq, 260 u16 ctx_id) 261 { 262 spin_lock(&aq->comp_ctx_lock); 263 aq->comp_ctx_pool_next--; 264 aq->comp_ctx_pool[aq->comp_ctx_pool_next] = ctx_id; 265 spin_unlock(&aq->comp_ctx_lock); 266 } 267 268 static struct efa_comp_ctx *efa_com_alloc_comp_ctx(struct efa_com_admin_queue *aq) 269 { 270 struct efa_comp_ctx *comp_ctx; 271 u16 ctx_id; 272 273 ctx_id = efa_com_alloc_ctx_id(aq); 274 275 comp_ctx = &aq->comp_ctx[ctx_id]; 276 if (comp_ctx->status != EFA_CMD_UNUSED) { 277 efa_com_dealloc_ctx_id(aq, ctx_id); 278 ibdev_err_ratelimited(aq->efa_dev, 279 "Completion context[%u] is used[%u]\n", 280 ctx_id, comp_ctx->status); 281 return NULL; 282 } 283 284 comp_ctx->status = EFA_CMD_ALLOCATED; 285 ibdev_dbg(aq->efa_dev, "Take completion context[%u]\n", ctx_id); 286 return comp_ctx; 287 } 288 289 static inline u16 efa_com_get_comp_ctx_id(struct efa_com_admin_queue *aq, 290 struct efa_comp_ctx *comp_ctx) 291 { 292 return comp_ctx - aq->comp_ctx; 293 } 294 295 static inline void efa_com_dealloc_comp_ctx(struct efa_com_admin_queue *aq, 296 struct efa_comp_ctx *comp_ctx) 297 { 298 u16 ctx_id = efa_com_get_comp_ctx_id(aq, comp_ctx); 299 300 ibdev_dbg(aq->efa_dev, "Put completion context[%u]\n", ctx_id); 301 comp_ctx->status = EFA_CMD_UNUSED; 302 efa_com_dealloc_ctx_id(aq, ctx_id); 303 } 304 305 static inline struct efa_comp_ctx *efa_com_get_comp_ctx_by_cmd_id(struct efa_com_admin_queue *aq, 306 u16 cmd_id) 307 { 308 u16 ctx_id = cmd_id & (aq->depth - 1); 309 310 return &aq->comp_ctx[ctx_id]; 311 } 312 313 static struct efa_comp_ctx *__efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 314 struct efa_admin_aq_entry *cmd, 315 size_t cmd_size_in_bytes, 316 struct efa_admin_acq_entry *comp, 317 size_t comp_size_in_bytes) 318 { 319 struct efa_admin_aq_entry *aqe; 320 struct efa_comp_ctx *comp_ctx; 321 u16 queue_size_mask; 322 u16 cmd_id; 323 u16 ctx_id; 324 u16 pi; 325 326 comp_ctx = efa_com_alloc_comp_ctx(aq); 327 if (!comp_ctx) 328 return ERR_PTR(-EINVAL); 329 330 queue_size_mask = aq->depth - 1; 331 pi = aq->sq.pc & queue_size_mask; 332 ctx_id = efa_com_get_comp_ctx_id(aq, comp_ctx); 333 334 /* cmd_id LSBs are the ctx_id and MSBs are entropy bits from pc */ 335 cmd_id = ctx_id & queue_size_mask; 336 cmd_id |= aq->sq.pc << ilog2(aq->depth); 337 cmd_id &= EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 338 339 cmd->aq_common_descriptor.command_id = cmd_id; 340 EFA_SET(&cmd->aq_common_descriptor.flags, 341 EFA_ADMIN_AQ_COMMON_DESC_PHASE, aq->sq.phase); 342 343 comp_ctx->status = EFA_CMD_SUBMITTED; 344 comp_ctx->comp_size = comp_size_in_bytes; 345 comp_ctx->user_cqe = comp; 346 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 347 comp_ctx->cmd_id = cmd_id; 348 349 reinit_completion(&comp_ctx->wait_event); 350 351 aqe = &aq->sq.entries[pi]; 352 memset(aqe, 0, sizeof(*aqe)); 353 memcpy(aqe, cmd, cmd_size_in_bytes); 354 355 aq->sq.pc++; 356 atomic64_inc(&aq->stats.submitted_cmd); 357 358 if ((aq->sq.pc & queue_size_mask) == 0) 359 aq->sq.phase = !aq->sq.phase; 360 361 /* barrier not needed in case of writel */ 362 writel(aq->sq.pc, aq->sq.db_addr); 363 364 return comp_ctx; 365 } 366 367 static inline int efa_com_init_comp_ctxt(struct efa_com_admin_queue *aq) 368 { 369 size_t pool_size = aq->depth * sizeof(*aq->comp_ctx_pool); 370 size_t size = aq->depth * sizeof(struct efa_comp_ctx); 371 struct efa_comp_ctx *comp_ctx; 372 u16 i; 373 374 aq->comp_ctx = devm_kzalloc(aq->dmadev, size, GFP_KERNEL); 375 aq->comp_ctx_pool = devm_kzalloc(aq->dmadev, pool_size, GFP_KERNEL); 376 if (!aq->comp_ctx || !aq->comp_ctx_pool) { 377 devm_kfree(aq->dmadev, aq->comp_ctx_pool); 378 devm_kfree(aq->dmadev, aq->comp_ctx); 379 return -ENOMEM; 380 } 381 382 for (i = 0; i < aq->depth; i++) { 383 comp_ctx = &aq->comp_ctx[i]; 384 comp_ctx->status = EFA_CMD_UNUSED; 385 init_completion(&comp_ctx->wait_event); 386 387 aq->comp_ctx_pool[i] = i; 388 } 389 390 spin_lock_init(&aq->comp_ctx_lock); 391 392 aq->comp_ctx_pool_next = 0; 393 394 return 0; 395 } 396 397 static struct efa_comp_ctx *efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 398 struct efa_admin_aq_entry *cmd, 399 size_t cmd_size_in_bytes, 400 struct efa_admin_acq_entry *comp, 401 size_t comp_size_in_bytes) 402 { 403 struct efa_comp_ctx *comp_ctx; 404 405 spin_lock(&aq->sq.lock); 406 if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) { 407 ibdev_err_ratelimited(aq->efa_dev, "Admin queue is closed\n"); 408 spin_unlock(&aq->sq.lock); 409 return ERR_PTR(-ENODEV); 410 } 411 412 comp_ctx = __efa_com_submit_admin_cmd(aq, cmd, cmd_size_in_bytes, comp, 413 comp_size_in_bytes); 414 spin_unlock(&aq->sq.lock); 415 if (IS_ERR(comp_ctx)) 416 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 417 418 return comp_ctx; 419 } 420 421 static int efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq, 422 struct efa_admin_acq_entry *cqe) 423 { 424 struct efa_comp_ctx *comp_ctx; 425 u16 cmd_id; 426 427 cmd_id = EFA_GET(&cqe->acq_common_descriptor.command, 428 EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID); 429 430 comp_ctx = efa_com_get_comp_ctx_by_cmd_id(aq, cmd_id); 431 if (comp_ctx->status != EFA_CMD_SUBMITTED || comp_ctx->cmd_id != cmd_id) { 432 ibdev_err(aq->efa_dev, 433 "Received completion with unexpected command id[%x], status[%d] sq producer[%d], sq consumer[%d], cq consumer[%d]\n", 434 cmd_id, comp_ctx->status, aq->sq.pc, aq->sq.cc, 435 aq->cq.cc); 436 return -EINVAL; 437 } 438 439 comp_ctx->status = EFA_CMD_COMPLETED; 440 memcpy(comp_ctx->user_cqe, cqe, comp_ctx->comp_size); 441 442 if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) 443 complete(&comp_ctx->wait_event); 444 445 return 0; 446 } 447 448 static void efa_com_handle_admin_completion(struct efa_com_admin_queue *aq) 449 { 450 struct efa_admin_acq_entry *cqe; 451 u16 queue_size_mask; 452 u16 comp_cmds = 0; 453 u8 phase; 454 int err; 455 u16 ci; 456 457 queue_size_mask = aq->depth - 1; 458 459 ci = aq->cq.cc & queue_size_mask; 460 phase = aq->cq.phase; 461 462 cqe = &aq->cq.entries[ci]; 463 464 /* Go over all the completions */ 465 while ((READ_ONCE(cqe->acq_common_descriptor.flags) & 466 EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 467 /* 468 * Do not read the rest of the completion entry before the 469 * phase bit was validated 470 */ 471 dma_rmb(); 472 err = efa_com_handle_single_admin_completion(aq, cqe); 473 if (!err) 474 comp_cmds++; 475 476 aq->cq.cc++; 477 ci++; 478 if (ci == aq->depth) { 479 ci = 0; 480 phase = !phase; 481 } 482 483 cqe = &aq->cq.entries[ci]; 484 } 485 486 aq->cq.phase = phase; 487 aq->sq.cc += comp_cmds; 488 atomic64_add(comp_cmds, &aq->stats.completed_cmd); 489 } 490 491 static int efa_com_comp_status_to_errno(u8 comp_status) 492 { 493 switch (comp_status) { 494 case EFA_ADMIN_SUCCESS: 495 return 0; 496 case EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 497 return -ENOMEM; 498 case EFA_ADMIN_UNSUPPORTED_OPCODE: 499 return -EOPNOTSUPP; 500 case EFA_ADMIN_BAD_OPCODE: 501 case EFA_ADMIN_MALFORMED_REQUEST: 502 case EFA_ADMIN_ILLEGAL_PARAMETER: 503 case EFA_ADMIN_UNKNOWN_ERROR: 504 return -EINVAL; 505 default: 506 return -EINVAL; 507 } 508 } 509 510 static int efa_com_wait_and_process_admin_cq_polling(struct efa_comp_ctx *comp_ctx, 511 struct efa_com_admin_queue *aq) 512 { 513 unsigned long timeout; 514 unsigned long flags; 515 int err; 516 517 timeout = jiffies + usecs_to_jiffies(aq->completion_timeout); 518 519 while (1) { 520 spin_lock_irqsave(&aq->cq.lock, flags); 521 efa_com_handle_admin_completion(aq); 522 spin_unlock_irqrestore(&aq->cq.lock, flags); 523 524 if (comp_ctx->status != EFA_CMD_SUBMITTED) 525 break; 526 527 if (time_is_before_jiffies(timeout)) { 528 ibdev_err_ratelimited( 529 aq->efa_dev, 530 "Wait for completion (polling) timeout\n"); 531 /* EFA didn't have any completion */ 532 atomic64_inc(&aq->stats.no_completion); 533 534 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 535 err = -ETIME; 536 goto out; 537 } 538 539 msleep(aq->poll_interval); 540 } 541 542 err = efa_com_comp_status_to_errno(comp_ctx->user_cqe->acq_common_descriptor.status); 543 out: 544 efa_com_dealloc_comp_ctx(aq, comp_ctx); 545 return err; 546 } 547 548 static int efa_com_wait_and_process_admin_cq_interrupts(struct efa_comp_ctx *comp_ctx, 549 struct efa_com_admin_queue *aq) 550 { 551 unsigned long flags; 552 int err; 553 554 wait_for_completion_timeout(&comp_ctx->wait_event, 555 usecs_to_jiffies(aq->completion_timeout)); 556 557 /* 558 * In case the command wasn't completed find out the root cause. 559 * There might be 2 kinds of errors 560 * 1) No completion (timeout reached) 561 * 2) There is completion but the device didn't get any msi-x interrupt. 562 */ 563 if (comp_ctx->status == EFA_CMD_SUBMITTED) { 564 spin_lock_irqsave(&aq->cq.lock, flags); 565 efa_com_handle_admin_completion(aq); 566 spin_unlock_irqrestore(&aq->cq.lock, flags); 567 568 atomic64_inc(&aq->stats.no_completion); 569 570 if (comp_ctx->status == EFA_CMD_COMPLETED) 571 ibdev_err_ratelimited( 572 aq->efa_dev, 573 "The device sent a completion but the driver didn't receive any MSI-X interrupt for admin cmd %s(%d) status %d (id: %d, sq producer: %d, sq consumer: %d, cq consumer: %d)\n", 574 efa_com_cmd_str(comp_ctx->cmd_opcode), 575 comp_ctx->cmd_opcode, comp_ctx->status, 576 comp_ctx->cmd_id, aq->sq.pc, aq->sq.cc, 577 aq->cq.cc); 578 else 579 ibdev_err_ratelimited( 580 aq->efa_dev, 581 "The device didn't send any completion for admin cmd %s(%d) status %d (id: %d, sq producer: %d, sq consumer: %d, cq consumer: %d)\n", 582 efa_com_cmd_str(comp_ctx->cmd_opcode), 583 comp_ctx->cmd_opcode, comp_ctx->status, 584 comp_ctx->cmd_id, aq->sq.pc, aq->sq.cc, 585 aq->cq.cc); 586 587 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 588 err = -ETIME; 589 goto out; 590 } 591 592 err = efa_com_comp_status_to_errno(comp_ctx->user_cqe->acq_common_descriptor.status); 593 out: 594 efa_com_dealloc_comp_ctx(aq, comp_ctx); 595 return err; 596 } 597 598 /* 599 * There are two types to wait for completion. 600 * Polling mode - wait until the completion is available. 601 * Async mode - wait on wait queue until the completion is ready 602 * (or the timeout expired). 603 * It is expected that the IRQ called efa_com_handle_admin_completion 604 * to mark the completions. 605 */ 606 static int efa_com_wait_and_process_admin_cq(struct efa_comp_ctx *comp_ctx, 607 struct efa_com_admin_queue *aq) 608 { 609 if (test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) 610 return efa_com_wait_and_process_admin_cq_polling(comp_ctx, aq); 611 612 return efa_com_wait_and_process_admin_cq_interrupts(comp_ctx, aq); 613 } 614 615 /** 616 * efa_com_cmd_exec - Execute admin command 617 * @aq: admin queue. 618 * @cmd: the admin command to execute. 619 * @cmd_size: the command size. 620 * @comp: command completion return entry. 621 * @comp_size: command completion size. 622 * Submit an admin command and then wait until the device will return a 623 * completion. 624 * The completion will be copied into comp. 625 * 626 * @return - 0 on success, negative value on failure. 627 */ 628 int efa_com_cmd_exec(struct efa_com_admin_queue *aq, 629 struct efa_admin_aq_entry *cmd, 630 size_t cmd_size, 631 struct efa_admin_acq_entry *comp, 632 size_t comp_size) 633 { 634 struct efa_comp_ctx *comp_ctx; 635 int err; 636 637 might_sleep(); 638 639 /* In case of queue FULL */ 640 down(&aq->avail_cmds); 641 642 ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n", 643 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 644 cmd->aq_common_descriptor.opcode); 645 comp_ctx = efa_com_submit_admin_cmd(aq, cmd, cmd_size, comp, comp_size); 646 if (IS_ERR(comp_ctx)) { 647 ibdev_err_ratelimited( 648 aq->efa_dev, 649 "Failed to submit command %s (opcode %u) err %pe\n", 650 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 651 cmd->aq_common_descriptor.opcode, comp_ctx); 652 653 up(&aq->avail_cmds); 654 atomic64_inc(&aq->stats.cmd_err); 655 return PTR_ERR(comp_ctx); 656 } 657 658 err = efa_com_wait_and_process_admin_cq(comp_ctx, aq); 659 if (err) { 660 ibdev_err_ratelimited( 661 aq->efa_dev, 662 "Failed to process command %s (opcode %u) comp_status %d err %d\n", 663 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 664 cmd->aq_common_descriptor.opcode, 665 comp_ctx->user_cqe->acq_common_descriptor.status, err); 666 atomic64_inc(&aq->stats.cmd_err); 667 } 668 669 up(&aq->avail_cmds); 670 671 return err; 672 } 673 674 /** 675 * efa_com_admin_destroy - Destroy the admin and the async events queues. 676 * @edev: EFA communication layer struct 677 */ 678 void efa_com_admin_destroy(struct efa_com_dev *edev) 679 { 680 struct efa_com_admin_queue *aq = &edev->aq; 681 struct efa_com_aenq *aenq = &edev->aenq; 682 struct efa_com_admin_cq *cq = &aq->cq; 683 struct efa_com_admin_sq *sq = &aq->sq; 684 u16 size; 685 686 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 687 688 devm_kfree(edev->dmadev, aq->comp_ctx_pool); 689 devm_kfree(edev->dmadev, aq->comp_ctx); 690 691 size = aq->depth * sizeof(*sq->entries); 692 dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr); 693 694 size = aq->depth * sizeof(*cq->entries); 695 dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr); 696 697 size = aenq->depth * sizeof(*aenq->entries); 698 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr); 699 } 700 701 /** 702 * efa_com_set_admin_polling_mode - Set the admin completion queue polling mode 703 * @edev: EFA communication layer struct 704 * @polling: Enable/Disable polling mode 705 * 706 * Set the admin completion mode. 707 */ 708 void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling) 709 { 710 u32 mask_value = 0; 711 712 if (polling) 713 EFA_SET(&mask_value, EFA_REGS_INTR_MASK_EN, 1); 714 715 writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF); 716 if (polling) 717 set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); 718 else 719 clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); 720 } 721 722 static void efa_com_stats_init(struct efa_com_dev *edev) 723 { 724 atomic64_t *s = (atomic64_t *)&edev->aq.stats; 725 int i; 726 727 for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++) 728 atomic64_set(s, 0); 729 } 730 731 /** 732 * efa_com_admin_init - Init the admin and the async queues 733 * @edev: EFA communication layer struct 734 * @aenq_handlers: Those handlers to be called upon event. 735 * 736 * Initialize the admin submission and completion queues. 737 * Initialize the asynchronous events notification queues. 738 * 739 * @return - 0 on success, negative value on failure. 740 */ 741 int efa_com_admin_init(struct efa_com_dev *edev, 742 struct efa_aenq_handlers *aenq_handlers) 743 { 744 struct efa_com_admin_queue *aq = &edev->aq; 745 u32 timeout; 746 u32 dev_sts; 747 u32 cap; 748 int err; 749 750 dev_sts = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF); 751 if (!EFA_GET(&dev_sts, EFA_REGS_DEV_STS_READY)) { 752 ibdev_err(edev->efa_dev, 753 "Device isn't ready, abort com init %#x\n", dev_sts); 754 return -ENODEV; 755 } 756 757 aq->depth = EFA_ADMIN_QUEUE_DEPTH; 758 759 aq->dmadev = edev->dmadev; 760 aq->efa_dev = edev->efa_dev; 761 set_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state); 762 763 sema_init(&aq->avail_cmds, aq->depth); 764 765 efa_com_stats_init(edev); 766 767 err = efa_com_init_comp_ctxt(aq); 768 if (err) 769 return err; 770 771 err = efa_com_admin_init_sq(edev); 772 if (err) 773 goto err_destroy_comp_ctxt; 774 775 err = efa_com_admin_init_cq(edev); 776 if (err) 777 goto err_destroy_sq; 778 779 efa_com_set_admin_polling_mode(edev, false); 780 781 err = efa_com_admin_init_aenq(edev, aenq_handlers); 782 if (err) 783 goto err_destroy_cq; 784 785 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF); 786 timeout = EFA_GET(&cap, EFA_REGS_CAPS_ADMIN_CMD_TO); 787 if (timeout) 788 /* the resolution of timeout reg is 100ms */ 789 aq->completion_timeout = timeout * 100000; 790 else 791 aq->completion_timeout = ADMIN_CMD_TIMEOUT_US; 792 793 aq->poll_interval = EFA_POLL_INTERVAL_MS; 794 795 set_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 796 797 return 0; 798 799 err_destroy_cq: 800 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries), 801 aq->cq.entries, aq->cq.dma_addr); 802 err_destroy_sq: 803 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries), 804 aq->sq.entries, aq->sq.dma_addr); 805 err_destroy_comp_ctxt: 806 devm_kfree(edev->dmadev, aq->comp_ctx); 807 808 return err; 809 } 810 811 /** 812 * efa_com_admin_q_comp_intr_handler - admin queue interrupt handler 813 * @edev: EFA communication layer struct 814 * 815 * This method goes over the admin completion queue and wakes up 816 * all the pending threads that wait on the commands wait event. 817 * 818 * Note: Should be called after MSI-X interrupt. 819 */ 820 void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev) 821 { 822 unsigned long flags; 823 824 spin_lock_irqsave(&edev->aq.cq.lock, flags); 825 efa_com_handle_admin_completion(&edev->aq); 826 spin_unlock_irqrestore(&edev->aq.cq.lock, flags); 827 } 828 829 /* 830 * efa_handle_specific_aenq_event: 831 * return the handler that is relevant to the specific event group 832 */ 833 static efa_aenq_handler efa_com_get_specific_aenq_cb(struct efa_com_dev *edev, 834 u16 group) 835 { 836 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers; 837 838 if (group < EFA_MAX_HANDLERS && aenq_handlers->handlers[group]) 839 return aenq_handlers->handlers[group]; 840 841 return aenq_handlers->unimplemented_handler; 842 } 843 844 /** 845 * efa_com_aenq_intr_handler - AENQ interrupt handler 846 * @edev: EFA communication layer struct 847 * @data: Data of interrupt handler. 848 * 849 * Go over the async event notification queue and call the proper aenq handler. 850 */ 851 void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data) 852 { 853 struct efa_admin_aenq_common_desc *aenq_common; 854 struct efa_com_aenq *aenq = &edev->aenq; 855 struct efa_admin_aenq_entry *aenq_e; 856 efa_aenq_handler handler_cb; 857 u32 processed = 0; 858 u8 phase; 859 u32 ci; 860 861 ci = aenq->cc & (aenq->depth - 1); 862 phase = aenq->phase; 863 aenq_e = &aenq->entries[ci]; /* Get first entry */ 864 aenq_common = &aenq_e->aenq_common_desc; 865 866 /* Go over all the events */ 867 while ((READ_ONCE(aenq_common->flags) & 868 EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { 869 /* 870 * Do not read the rest of the completion entry before the 871 * phase bit was validated 872 */ 873 dma_rmb(); 874 875 /* Handle specific event*/ 876 handler_cb = efa_com_get_specific_aenq_cb(edev, 877 aenq_common->group); 878 handler_cb(data, aenq_e); /* call the actual event handler*/ 879 880 /* Get next event entry */ 881 ci++; 882 processed++; 883 884 if (ci == aenq->depth) { 885 ci = 0; 886 phase = !phase; 887 } 888 aenq_e = &aenq->entries[ci]; 889 aenq_common = &aenq_e->aenq_common_desc; 890 } 891 892 aenq->cc += processed; 893 aenq->phase = phase; 894 895 /* Don't update aenq doorbell if there weren't any processed events */ 896 if (!processed) 897 return; 898 899 /* barrier not needed in case of writel */ 900 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); 901 } 902 903 static void efa_com_mmio_reg_read_resp_addr_init(struct efa_com_dev *edev) 904 { 905 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 906 u32 addr_high; 907 u32 addr_low; 908 909 /* dma_addr_bits is unknown at this point */ 910 addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0); 911 addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0); 912 913 writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF); 914 writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF); 915 } 916 917 int efa_com_mmio_reg_read_init(struct efa_com_dev *edev) 918 { 919 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 920 921 spin_lock_init(&mmio_read->lock); 922 mmio_read->read_resp = 923 dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), 924 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 925 if (!mmio_read->read_resp) 926 return -ENOMEM; 927 928 efa_com_mmio_reg_read_resp_addr_init(edev); 929 930 mmio_read->read_resp->req_id = 0; 931 mmio_read->seq_num = 0; 932 mmio_read->mmio_read_timeout = EFA_REG_READ_TIMEOUT_US; 933 934 return 0; 935 } 936 937 void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev) 938 { 939 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 940 941 dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), 942 mmio_read->read_resp, mmio_read->read_resp_dma_addr); 943 } 944 945 int efa_com_validate_version(struct efa_com_dev *edev) 946 { 947 u32 min_ctrl_ver = 0; 948 u32 ctrl_ver_masked; 949 u32 min_ver = 0; 950 u32 ctrl_ver; 951 u32 ver; 952 953 /* 954 * Make sure the EFA version and the controller version are at least 955 * as the driver expects 956 */ 957 ver = efa_com_reg_read32(edev, EFA_REGS_VERSION_OFF); 958 ctrl_ver = efa_com_reg_read32(edev, 959 EFA_REGS_CONTROLLER_VERSION_OFF); 960 961 ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n", 962 EFA_GET(&ver, EFA_REGS_VERSION_MAJOR_VERSION), 963 EFA_GET(&ver, EFA_REGS_VERSION_MINOR_VERSION)); 964 965 EFA_SET(&min_ver, EFA_REGS_VERSION_MAJOR_VERSION, 966 EFA_ADMIN_API_VERSION_MAJOR); 967 EFA_SET(&min_ver, EFA_REGS_VERSION_MINOR_VERSION, 968 EFA_ADMIN_API_VERSION_MINOR); 969 if (ver < min_ver) { 970 ibdev_err(edev->efa_dev, 971 "EFA version is lower than the minimal version the driver supports\n"); 972 return -EOPNOTSUPP; 973 } 974 975 ibdev_dbg( 976 edev->efa_dev, 977 "efa controller version: %d.%d.%d implementation version %d\n", 978 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION), 979 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION), 980 EFA_GET(&ctrl_ver, 981 EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION), 982 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_IMPL_ID)); 983 984 ctrl_ver_masked = 985 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION) | 986 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION) | 987 EFA_GET(&ctrl_ver, 988 EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION); 989 990 EFA_SET(&min_ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION, 991 EFA_CTRL_MAJOR); 992 EFA_SET(&min_ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION, 993 EFA_CTRL_MINOR); 994 EFA_SET(&min_ctrl_ver, EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION, 995 EFA_CTRL_SUB_MINOR); 996 /* Validate the ctrl version without the implementation ID */ 997 if (ctrl_ver_masked < min_ctrl_ver) { 998 ibdev_err(edev->efa_dev, 999 "EFA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1000 return -EOPNOTSUPP; 1001 } 1002 1003 return 0; 1004 } 1005 1006 /** 1007 * efa_com_get_dma_width - Retrieve physical dma address width the device 1008 * supports. 1009 * @edev: EFA communication layer struct 1010 * 1011 * Retrieve the maximum physical address bits the device can handle. 1012 * 1013 * @return: > 0 on Success and negative value otherwise. 1014 */ 1015 int efa_com_get_dma_width(struct efa_com_dev *edev) 1016 { 1017 u32 caps = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF); 1018 int width; 1019 1020 width = EFA_GET(&caps, EFA_REGS_CAPS_DMA_ADDR_WIDTH); 1021 1022 ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width); 1023 1024 if (width < 32 || width > 64) { 1025 ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width); 1026 return -EINVAL; 1027 } 1028 1029 edev->dma_addr_bits = width; 1030 1031 return width; 1032 } 1033 1034 static int wait_for_reset_state(struct efa_com_dev *edev, u32 timeout, int on) 1035 { 1036 u32 val, i; 1037 1038 for (i = 0; i < timeout; i++) { 1039 val = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF); 1040 1041 if (EFA_GET(&val, EFA_REGS_DEV_STS_RESET_IN_PROGRESS) == on) 1042 return 0; 1043 1044 ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val); 1045 msleep(EFA_POLL_INTERVAL_MS); 1046 } 1047 1048 return -ETIME; 1049 } 1050 1051 /** 1052 * efa_com_dev_reset - Perform device FLR to the device. 1053 * @edev: EFA communication layer struct 1054 * @reset_reason: Specify what is the trigger for the reset in case of an error. 1055 * 1056 * @return - 0 on success, negative value on failure. 1057 */ 1058 int efa_com_dev_reset(struct efa_com_dev *edev, 1059 enum efa_regs_reset_reason_types reset_reason) 1060 { 1061 u32 stat, timeout, cap; 1062 u32 reset_val = 0; 1063 int err; 1064 1065 stat = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF); 1066 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF); 1067 1068 if (!EFA_GET(&stat, EFA_REGS_DEV_STS_READY)) { 1069 ibdev_err(edev->efa_dev, 1070 "Device isn't ready, can't reset device\n"); 1071 return -EINVAL; 1072 } 1073 1074 timeout = EFA_GET(&cap, EFA_REGS_CAPS_RESET_TIMEOUT); 1075 if (!timeout) { 1076 ibdev_err(edev->efa_dev, "Invalid timeout value\n"); 1077 return -EINVAL; 1078 } 1079 1080 /* start reset */ 1081 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_DEV_RESET, 1); 1082 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_RESET_REASON, reset_reason); 1083 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); 1084 1085 /* reset clears the mmio readless address, restore it */ 1086 efa_com_mmio_reg_read_resp_addr_init(edev); 1087 1088 err = wait_for_reset_state(edev, timeout, 1); 1089 if (err) { 1090 ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n"); 1091 return err; 1092 } 1093 1094 /* reset done */ 1095 writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); 1096 err = wait_for_reset_state(edev, timeout, 0); 1097 if (err) { 1098 ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n"); 1099 return err; 1100 } 1101 1102 timeout = EFA_GET(&cap, EFA_REGS_CAPS_ADMIN_CMD_TO); 1103 if (timeout) 1104 /* the resolution of timeout reg is 100ms */ 1105 edev->aq.completion_timeout = timeout * 100000; 1106 else 1107 edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US; 1108 1109 return 0; 1110 } 1111 1112 static int efa_com_create_eq(struct efa_com_dev *edev, 1113 struct efa_com_create_eq_params *params, 1114 struct efa_com_create_eq_result *result) 1115 { 1116 struct efa_com_admin_queue *aq = &edev->aq; 1117 struct efa_admin_create_eq_resp resp = {}; 1118 struct efa_admin_create_eq_cmd cmd = {}; 1119 int err; 1120 1121 cmd.aq_common_descriptor.opcode = EFA_ADMIN_CREATE_EQ; 1122 EFA_SET(&cmd.caps, EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS, 1123 params->entry_size_in_bytes / 4); 1124 cmd.depth = params->depth; 1125 cmd.event_bitmask = params->event_bitmask; 1126 cmd.msix_vec = params->msix_vec; 1127 1128 efa_com_set_dma_addr(params->dma_addr, &cmd.ba.mem_addr_high, 1129 &cmd.ba.mem_addr_low); 1130 1131 err = efa_com_cmd_exec(aq, 1132 (struct efa_admin_aq_entry *)&cmd, 1133 sizeof(cmd), 1134 (struct efa_admin_acq_entry *)&resp, 1135 sizeof(resp)); 1136 if (err) { 1137 ibdev_err_ratelimited(edev->efa_dev, 1138 "Failed to create eq[%d]\n", err); 1139 return err; 1140 } 1141 1142 result->eqn = resp.eqn; 1143 1144 return 0; 1145 } 1146 1147 static void efa_com_destroy_eq(struct efa_com_dev *edev, 1148 struct efa_com_destroy_eq_params *params) 1149 { 1150 struct efa_com_admin_queue *aq = &edev->aq; 1151 struct efa_admin_destroy_eq_resp resp = {}; 1152 struct efa_admin_destroy_eq_cmd cmd = {}; 1153 int err; 1154 1155 cmd.aq_common_descriptor.opcode = EFA_ADMIN_DESTROY_EQ; 1156 cmd.eqn = params->eqn; 1157 1158 err = efa_com_cmd_exec(aq, 1159 (struct efa_admin_aq_entry *)&cmd, 1160 sizeof(cmd), 1161 (struct efa_admin_acq_entry *)&resp, 1162 sizeof(resp)); 1163 if (err) 1164 ibdev_err_ratelimited(edev->efa_dev, 1165 "Failed to destroy EQ-%u [%d]\n", cmd.eqn, 1166 err); 1167 } 1168 1169 static void efa_com_arm_eq(struct efa_com_dev *edev, struct efa_com_eq *eeq) 1170 { 1171 u32 val = 0; 1172 1173 EFA_SET(&val, EFA_REGS_EQ_DB_EQN, eeq->eqn); 1174 EFA_SET(&val, EFA_REGS_EQ_DB_ARM, 1); 1175 1176 writel(val, edev->reg_bar + EFA_REGS_EQ_DB_OFF); 1177 } 1178 1179 void efa_com_eq_comp_intr_handler(struct efa_com_dev *edev, 1180 struct efa_com_eq *eeq) 1181 { 1182 struct efa_admin_eqe *eqe; 1183 u32 processed = 0; 1184 u8 phase; 1185 u32 ci; 1186 1187 ci = eeq->cc & (eeq->depth - 1); 1188 phase = eeq->phase; 1189 eqe = &eeq->eqes[ci]; 1190 1191 /* Go over all the events */ 1192 while ((READ_ONCE(eqe->common) & EFA_ADMIN_EQE_PHASE_MASK) == phase) { 1193 /* 1194 * Do not read the rest of the completion entry before the 1195 * phase bit was validated 1196 */ 1197 dma_rmb(); 1198 1199 eeq->cb(eeq, eqe); 1200 1201 /* Get next event entry */ 1202 ci++; 1203 processed++; 1204 1205 if (ci == eeq->depth) { 1206 ci = 0; 1207 phase = !phase; 1208 } 1209 1210 eqe = &eeq->eqes[ci]; 1211 } 1212 1213 eeq->cc += processed; 1214 eeq->phase = phase; 1215 efa_com_arm_eq(eeq->edev, eeq); 1216 } 1217 1218 void efa_com_eq_destroy(struct efa_com_dev *edev, struct efa_com_eq *eeq) 1219 { 1220 struct efa_com_destroy_eq_params params = { 1221 .eqn = eeq->eqn, 1222 }; 1223 1224 efa_com_destroy_eq(edev, ¶ms); 1225 dma_free_coherent(edev->dmadev, eeq->depth * sizeof(*eeq->eqes), 1226 eeq->eqes, eeq->dma_addr); 1227 } 1228 1229 int efa_com_eq_init(struct efa_com_dev *edev, struct efa_com_eq *eeq, 1230 efa_eqe_handler cb, u16 depth, u8 msix_vec) 1231 { 1232 struct efa_com_create_eq_params params = {}; 1233 struct efa_com_create_eq_result result = {}; 1234 int err; 1235 1236 params.depth = depth; 1237 params.entry_size_in_bytes = sizeof(*eeq->eqes); 1238 EFA_SET(¶ms.event_bitmask, 1239 EFA_ADMIN_CREATE_EQ_CMD_COMPLETION_EVENTS, 1); 1240 params.msix_vec = msix_vec; 1241 1242 eeq->eqes = dma_alloc_coherent(edev->dmadev, 1243 params.depth * sizeof(*eeq->eqes), 1244 ¶ms.dma_addr, GFP_KERNEL); 1245 if (!eeq->eqes) 1246 return -ENOMEM; 1247 1248 err = efa_com_create_eq(edev, ¶ms, &result); 1249 if (err) 1250 goto err_free_coherent; 1251 1252 eeq->eqn = result.eqn; 1253 eeq->edev = edev; 1254 eeq->dma_addr = params.dma_addr; 1255 eeq->phase = 1; 1256 eeq->depth = params.depth; 1257 eeq->cb = cb; 1258 efa_com_arm_eq(edev, eeq); 1259 1260 return 0; 1261 1262 err_free_coherent: 1263 dma_free_coherent(edev->dmadev, params.depth * sizeof(*eeq->eqes), 1264 eeq->eqes, params.dma_addr); 1265 return err; 1266 } 1267