1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2026 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_ADMIN_H_ 7 #define _EFA_ADMIN_H_ 8 9 #define EFA_ADMIN_API_VERSION_MAJOR 0 10 #define EFA_ADMIN_API_VERSION_MINOR 2 11 12 enum efa_admin_aq_completion_status { 13 EFA_ADMIN_SUCCESS = 0, 14 EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 15 EFA_ADMIN_BAD_OPCODE = 2, 16 EFA_ADMIN_UNSUPPORTED_OPCODE = 3, 17 EFA_ADMIN_MALFORMED_REQUEST = 4, 18 EFA_ADMIN_ILLEGAL_PARAMETER = 5, 19 EFA_ADMIN_UNKNOWN_ERROR = 6, 20 EFA_ADMIN_RESOURCE_BUSY = 7, 21 }; 22 23 struct efa_admin_aq_common_desc { 24 /* 25 * 11:0 : command_id 26 * 15:12 : reserved12 27 */ 28 u16 command_id; 29 30 /* as appears in efa_admin_aq_opcode */ 31 u8 opcode; 32 33 /* 34 * 0 : phase 35 * 1 : ctrl_data - control buffer address valid 36 * 2 : ctrl_data_indirect - control buffer address 37 * points to list of pages with addresses of control 38 * buffers 39 * 7:3 : reserved3 40 */ 41 u8 flags; 42 }; 43 44 /* 45 * used in efa_admin_aq_entry. Can point directly to control data, or to a 46 * page list chunk. Used also at the end of indirect mode page list chunks, 47 * for chaining. 48 */ 49 struct efa_admin_ctrl_buff_info { 50 u32 length; 51 52 struct efa_common_mem_addr address; 53 }; 54 55 struct efa_admin_aq_entry { 56 struct efa_admin_aq_common_desc aq_common_descriptor; 57 58 union { 59 u32 inline_data_w1[3]; 60 61 struct efa_admin_ctrl_buff_info control_buffer; 62 } u; 63 64 u32 inline_data_w4[12]; 65 }; 66 67 struct efa_admin_acq_common_desc { 68 /* 69 * command identifier to associate it with the aq descriptor 70 * 11:0 : command_id 71 * 15:12 : reserved12 72 */ 73 u16 command; 74 75 u8 status; 76 77 /* 78 * 0 : phase 79 * 7:1 : reserved1 80 */ 81 u8 flags; 82 83 /* Poly 0x8005 CRC16 with initial value 0xFFFF and final XOR of 0xFFFF */ 84 u16 checksum; 85 86 u16 reserved; 87 }; 88 89 struct efa_admin_acq_entry { 90 struct efa_admin_acq_common_desc acq_common_descriptor; 91 92 u32 response_specific_data[14]; 93 }; 94 95 struct efa_admin_aenq_common_desc { 96 u16 group; 97 98 u16 syndrome; 99 100 /* 101 * 0 : phase 102 * 7:1 : reserved - MBZ 103 */ 104 u8 flags; 105 106 u8 reserved1[3]; 107 108 u32 timestamp_low; 109 110 u32 timestamp_high; 111 }; 112 113 struct efa_admin_aenq_entry { 114 struct efa_admin_aenq_common_desc aenq_common_desc; 115 116 /* command specific inline data */ 117 u32 inline_data_w4[12]; 118 }; 119 120 enum efa_admin_eqe_event_type { 121 EFA_ADMIN_EQE_EVENT_TYPE_COMPLETION = 0, 122 }; 123 124 /* Completion event */ 125 struct efa_admin_comp_event { 126 /* CQ number */ 127 u16 cqn; 128 129 /* MBZ */ 130 u16 reserved; 131 132 /* MBZ */ 133 u32 reserved2; 134 }; 135 136 /* Event Queue Element */ 137 struct efa_admin_eqe { 138 /* 139 * 0 : phase 140 * 8:1 : event_type - Event type 141 * 31:9 : reserved - MBZ 142 */ 143 u32 common; 144 145 /* MBZ */ 146 u32 reserved; 147 148 union { 149 /* Event data */ 150 u32 event_data[2]; 151 152 /* Completion Event */ 153 struct efa_admin_comp_event comp_event; 154 } u; 155 }; 156 157 /* aq_common_desc */ 158 #define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 159 #define EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 160 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 161 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 162 163 /* acq_common_desc */ 164 #define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 165 #define EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 166 167 /* aenq_common_desc */ 168 #define EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 169 170 /* eqe */ 171 #define EFA_ADMIN_EQE_PHASE_MASK BIT(0) 172 #define EFA_ADMIN_EQE_EVENT_TYPE_MASK GENMASK(8, 1) 173 174 #endif /* _EFA_ADMIN_H_ */ 175