1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2026 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_ADMIN_H_ 7 #define _EFA_ADMIN_H_ 8 9 #define EFA_ADMIN_API_VERSION_MAJOR 0 10 #define EFA_ADMIN_API_VERSION_MINOR 3 11 12 enum efa_admin_aq_completion_status { 13 EFA_ADMIN_SUCCESS = 0, 14 EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 15 EFA_ADMIN_BAD_OPCODE = 2, 16 EFA_ADMIN_UNSUPPORTED_OPCODE = 3, 17 EFA_ADMIN_MALFORMED_REQUEST = 4, 18 EFA_ADMIN_ILLEGAL_PARAMETER = 5, 19 EFA_ADMIN_UNKNOWN_ERROR = 6, 20 EFA_ADMIN_RESOURCE_BUSY = 7, 21 }; 22 23 struct efa_admin_aq_common_desc { 24 /* 25 * 11:0 : command_id 26 * 15:12 : reserved12 27 */ 28 u16 command_id; 29 30 /* as appears in efa_admin_aq_opcode */ 31 u8 opcode; 32 33 /* 34 * 0 : phase 35 * 1 : ctrl_data - control buffer address valid 36 * 2 : ctrl_data_indirect - control buffer address 37 * points to list of pages with addresses of control 38 * buffers 39 * 7:3 : reserved3 40 */ 41 u8 flags; 42 }; 43 44 struct efa_admin_aq_common_desc_v2 { 45 struct efa_admin_aq_common_desc common; 46 47 /* 48 * Poly 0x8005 CRC16 with initial value 0xFFFF and final XOR of 49 * 0xFFFF. The checksum covers the entire admin command entry 50 * including the zeroed checksum field. 51 */ 52 u16 checksum; 53 54 u8 payload_ver; 55 56 u8 reserved[5]; 57 }; 58 59 /* 60 * used in efa_admin_aq_entry. Can point directly to control data, or to a 61 * page list chunk. Used also at the end of indirect mode page list chunks, 62 * for chaining. 63 */ 64 struct efa_admin_ctrl_buff_info { 65 u32 length; 66 67 struct efa_common_mem_addr address; 68 }; 69 70 struct efa_admin_aq_entry { 71 struct efa_admin_aq_common_desc aq_common_descriptor; 72 73 u32 request_payload[15]; 74 }; 75 76 struct efa_admin_aq_entry_v2 { 77 struct efa_admin_aq_common_desc_v2 aq_common_descriptor; 78 79 u32 request_payload[29]; 80 }; 81 82 struct efa_admin_acq_common_desc { 83 /* 84 * command identifier to associate it with the aq descriptor 85 * 11:0 : command_id 86 * 15:12 : reserved12 87 */ 88 u16 command; 89 90 u8 status; 91 92 /* 93 * 0 : phase 94 * 7:1 : reserved1 95 */ 96 u8 flags; 97 98 /* 99 * Poly 0x8005 CRC16 with initial value 0xFFFF and final XOR of 0xFFFF. 100 * The checksum covers the entire admin completion entry including the 101 * zeroed checksum field. 102 */ 103 u16 checksum; 104 105 u16 reserved; 106 }; 107 108 struct efa_admin_acq_entry { 109 struct efa_admin_acq_common_desc acq_common_descriptor; 110 111 u32 response_specific_data[14]; 112 }; 113 114 struct efa_admin_aenq_common_desc { 115 u16 group; 116 117 u16 syndrome; 118 119 /* 120 * 0 : phase 121 * 7:1 : reserved - MBZ 122 */ 123 u8 flags; 124 125 u8 reserved1[3]; 126 127 u32 timestamp_low; 128 129 u32 timestamp_high; 130 }; 131 132 struct efa_admin_aenq_entry { 133 struct efa_admin_aenq_common_desc aenq_common_desc; 134 135 /* command specific inline data */ 136 u32 inline_data_w4[12]; 137 }; 138 139 enum efa_admin_eqe_event_type { 140 EFA_ADMIN_EQE_EVENT_TYPE_COMPLETION = 0, 141 }; 142 143 /* Completion event */ 144 struct efa_admin_comp_event { 145 /* CQ number */ 146 u16 cqn; 147 148 /* MBZ */ 149 u16 reserved; 150 151 /* MBZ */ 152 u32 reserved2; 153 }; 154 155 /* Event Queue Element */ 156 struct efa_admin_eqe { 157 /* 158 * 0 : phase 159 * 8:1 : event_type - Event type 160 * 31:9 : reserved - MBZ 161 */ 162 u32 common; 163 164 /* MBZ */ 165 u32 reserved; 166 167 union { 168 /* Event data */ 169 u32 event_data[2]; 170 171 /* Completion Event */ 172 struct efa_admin_comp_event comp_event; 173 } u; 174 }; 175 176 /* aq_common_desc */ 177 #define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 178 #define EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 179 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 180 #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 181 182 /* acq_common_desc */ 183 #define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 184 #define EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 185 186 /* aenq_common_desc */ 187 #define EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 188 189 /* eqe */ 190 #define EFA_ADMIN_EQE_PHASE_MASK BIT(0) 191 #define EFA_ADMIN_EQE_EVENT_TYPE_MASK GENMASK(8, 1) 192 193 #endif /* _EFA_ADMIN_H_ */ 194