1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2026 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_ADMIN_CMDS_H_ 7 #define _EFA_ADMIN_CMDS_H_ 8 9 /* EFA admin queue opcodes */ 10 enum efa_admin_aq_opcode { 11 EFA_ADMIN_CREATE_QP = 1, 12 EFA_ADMIN_MODIFY_QP = 2, 13 EFA_ADMIN_QUERY_QP = 3, 14 EFA_ADMIN_DESTROY_QP = 4, 15 EFA_ADMIN_CREATE_AH = 5, 16 EFA_ADMIN_DESTROY_AH = 6, 17 EFA_ADMIN_REG_MR = 7, 18 EFA_ADMIN_DEREG_MR = 8, 19 EFA_ADMIN_CREATE_CQ = 9, 20 EFA_ADMIN_DESTROY_CQ = 10, 21 EFA_ADMIN_GET_FEATURE = 11, 22 EFA_ADMIN_SET_FEATURE = 12, 23 EFA_ADMIN_GET_STATS = 13, 24 EFA_ADMIN_ALLOC_PD = 14, 25 EFA_ADMIN_DEALLOC_PD = 15, 26 EFA_ADMIN_ALLOC_UAR = 16, 27 EFA_ADMIN_DEALLOC_UAR = 17, 28 EFA_ADMIN_CREATE_EQ = 18, 29 EFA_ADMIN_DESTROY_EQ = 19, 30 EFA_ADMIN_ALLOC_MR = 20, 31 EFA_ADMIN_MAX_OPCODE = 20, 32 }; 33 34 enum efa_admin_aq_feature_id { 35 EFA_ADMIN_DEVICE_ATTR = 1, 36 EFA_ADMIN_AENQ_CONFIG = 2, 37 EFA_ADMIN_NETWORK_ATTR = 3, 38 EFA_ADMIN_QUEUE_ATTR_1 = 4, 39 EFA_ADMIN_HW_HINTS = 5, 40 EFA_ADMIN_HOST_INFO = 6, 41 EFA_ADMIN_EVENT_QUEUE_ATTR = 7, 42 EFA_ADMIN_QUEUE_ATTR_2 = 9, 43 }; 44 45 /* QP transport type */ 46 enum efa_admin_qp_type { 47 /* Unreliable Datagram */ 48 EFA_ADMIN_QP_TYPE_UD = 1, 49 /* Scalable Reliable Datagram */ 50 EFA_ADMIN_QP_TYPE_SRD = 2, 51 }; 52 53 /* QP state */ 54 enum efa_admin_qp_state { 55 EFA_ADMIN_QP_STATE_RESET = 0, 56 EFA_ADMIN_QP_STATE_INIT = 1, 57 EFA_ADMIN_QP_STATE_RTR = 2, 58 EFA_ADMIN_QP_STATE_RTS = 3, 59 EFA_ADMIN_QP_STATE_SQD = 4, 60 EFA_ADMIN_QP_STATE_SQE = 5, 61 EFA_ADMIN_QP_STATE_ERR = 6, 62 }; 63 64 enum efa_admin_get_stats_type { 65 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0, 66 EFA_ADMIN_GET_STATS_TYPE_MESSAGES = 1, 67 EFA_ADMIN_GET_STATS_TYPE_RDMA_READ = 2, 68 EFA_ADMIN_GET_STATS_TYPE_RDMA_WRITE = 3, 69 EFA_ADMIN_GET_STATS_TYPE_NETWORK = 4, 70 }; 71 72 enum efa_admin_get_stats_scope { 73 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0, 74 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1, 75 }; 76 77 /* 78 * QP allocation sizes, converted by fabric QueuePair (QP) create command 79 * from QP capabilities. 80 */ 81 struct efa_admin_qp_alloc_size { 82 /* Send descriptor ring size in bytes */ 83 u32 send_queue_ring_size; 84 85 /* Max number of WQEs that can be outstanding on send queue. */ 86 u32 send_queue_depth; 87 88 /* 89 * Recv descriptor ring size in bytes, sufficient for user-provided 90 * number of WQEs 91 */ 92 u32 recv_queue_ring_size; 93 94 /* Max number of WQEs that can be outstanding on recv queue */ 95 u32 recv_queue_depth; 96 }; 97 98 struct efa_admin_create_qp_cmd { 99 /* Common Admin Queue descriptor */ 100 struct efa_admin_aq_common_desc aq_common_desc; 101 102 /* Protection Domain associated with this QP */ 103 u16 pd; 104 105 /* QP type */ 106 u8 qp_type; 107 108 /* 109 * 0 : sq_virt - If set, SQ ring base address is 110 * virtual (IOVA returned by MR registration) 111 * 1 : rq_virt - If set, RQ ring base address is 112 * virtual (IOVA returned by MR registration) 113 * 2 : unsolicited_write_recv - If set, work requests 114 * will not be consumed for incoming RDMA write with 115 * immediate 116 * 7:3 : reserved - MBZ 117 */ 118 u8 flags; 119 120 /* 121 * Send queue (SQ) ring base physical address. This field is not 122 * used if this is a Low Latency Queue(LLQ). 123 */ 124 u64 sq_base_addr; 125 126 /* Receive queue (RQ) ring base address. */ 127 u64 rq_base_addr; 128 129 /* Index of CQ to be associated with Send Queue completions */ 130 u32 send_cq_idx; 131 132 /* Index of CQ to be associated with Recv Queue completions */ 133 u32 recv_cq_idx; 134 135 /* 136 * Memory registration key for the SQ ring, used only when not in 137 * LLQ mode and base address is virtual 138 */ 139 u32 sq_l_key; 140 141 /* 142 * Memory registration key for the RQ ring, used only when base 143 * address is virtual 144 */ 145 u32 rq_l_key; 146 147 /* Requested QP allocation sizes */ 148 struct efa_admin_qp_alloc_size qp_alloc_size; 149 150 /* UAR number */ 151 u16 uar; 152 153 /* Requested service level for the QP, 0 is the default SL */ 154 u8 sl; 155 156 /* MBZ */ 157 u8 reserved; 158 159 /* MBZ */ 160 u32 reserved2; 161 }; 162 163 struct efa_admin_create_qp_resp { 164 /* Common Admin Queue completion descriptor */ 165 struct efa_admin_acq_common_desc acq_common_desc; 166 167 /* 168 * Opaque handle to be used for consequent admin operations on the 169 * QP 170 */ 171 u32 qp_handle; 172 173 /* 174 * QP number in the given EFA virtual device. Least-significant bits (as 175 * needed according to max_qp) carry unique QP ID 176 */ 177 u16 qp_num; 178 179 /* MBZ */ 180 u16 reserved; 181 182 /* Index of sub-CQ for Send Queue completions */ 183 u16 send_sub_cq_idx; 184 185 /* Index of sub-CQ for Receive Queue completions */ 186 u16 recv_sub_cq_idx; 187 188 /* SQ doorbell address, as offset to PCIe DB BAR */ 189 u32 sq_db_offset; 190 191 /* RQ doorbell address, as offset to PCIe DB BAR */ 192 u32 rq_db_offset; 193 194 /* 195 * low latency send queue ring base address as an offset to PCIe 196 * MMIO LLQ_MEM BAR 197 */ 198 u32 llq_descriptors_offset; 199 }; 200 201 struct efa_admin_modify_qp_cmd { 202 /* Common Admin Queue descriptor */ 203 struct efa_admin_aq_common_desc aq_common_desc; 204 205 /* 206 * Mask indicating which fields should be updated 207 * 0 : qp_state 208 * 1 : cur_qp_state 209 * 2 : qkey 210 * 3 : sq_psn 211 * 4 : sq_drained_async_notify 212 * 5 : rnr_retry 213 * 31:6 : reserved 214 */ 215 u32 modify_mask; 216 217 /* QP handle returned by create_qp command */ 218 u32 qp_handle; 219 220 /* QP state */ 221 u32 qp_state; 222 223 /* Override current QP state (before applying the transition) */ 224 u32 cur_qp_state; 225 226 /* QKey */ 227 u32 qkey; 228 229 /* SQ PSN */ 230 u32 sq_psn; 231 232 /* Enable async notification when SQ is drained */ 233 u8 sq_drained_async_notify; 234 235 /* Number of RNR retries (valid only for SRD QPs) */ 236 u8 rnr_retry; 237 238 /* MBZ */ 239 u16 reserved2; 240 }; 241 242 struct efa_admin_modify_qp_resp { 243 /* Common Admin Queue completion descriptor */ 244 struct efa_admin_acq_common_desc acq_common_desc; 245 }; 246 247 struct efa_admin_query_qp_cmd { 248 /* Common Admin Queue descriptor */ 249 struct efa_admin_aq_common_desc aq_common_desc; 250 251 /* QP handle returned by create_qp command */ 252 u32 qp_handle; 253 }; 254 255 struct efa_admin_query_qp_resp { 256 /* Common Admin Queue completion descriptor */ 257 struct efa_admin_acq_common_desc acq_common_desc; 258 259 /* QP state */ 260 u32 qp_state; 261 262 /* QKey */ 263 u32 qkey; 264 265 /* SQ PSN */ 266 u32 sq_psn; 267 268 /* Indicates that draining is in progress */ 269 u8 sq_draining; 270 271 /* Number of RNR retries (valid only for SRD QPs) */ 272 u8 rnr_retry; 273 274 /* MBZ */ 275 u16 reserved2; 276 }; 277 278 struct efa_admin_destroy_qp_cmd { 279 /* Common Admin Queue descriptor */ 280 struct efa_admin_aq_common_desc aq_common_desc; 281 282 /* QP handle returned by create_qp command */ 283 u32 qp_handle; 284 }; 285 286 struct efa_admin_destroy_qp_resp { 287 /* Common Admin Queue completion descriptor */ 288 struct efa_admin_acq_common_desc acq_common_desc; 289 }; 290 291 /* 292 * Create Address Handle command parameters. Must not be called more than 293 * once for the same destination 294 */ 295 struct efa_admin_create_ah_cmd { 296 /* Common Admin Queue descriptor */ 297 struct efa_admin_aq_common_desc aq_common_desc; 298 299 /* Destination address in network byte order */ 300 u8 dest_addr[16]; 301 302 /* PD number */ 303 u16 pd; 304 305 /* MBZ */ 306 u16 reserved; 307 }; 308 309 struct efa_admin_create_ah_resp { 310 /* Common Admin Queue completion descriptor */ 311 struct efa_admin_acq_common_desc acq_common_desc; 312 313 /* Target interface address handle (opaque) */ 314 u16 ah; 315 316 /* MBZ */ 317 u16 reserved; 318 }; 319 320 struct efa_admin_destroy_ah_cmd { 321 /* Common Admin Queue descriptor */ 322 struct efa_admin_aq_common_desc aq_common_desc; 323 324 /* Target interface address handle (opaque) */ 325 u16 ah; 326 327 /* PD number */ 328 u16 pd; 329 }; 330 331 struct efa_admin_destroy_ah_resp { 332 /* Common Admin Queue completion descriptor */ 333 struct efa_admin_acq_common_desc acq_common_desc; 334 }; 335 336 /* 337 * Registration of MemoryRegion, required for QP working with Virtual 338 * Addresses. In standard verbs semantics, region length is limited to 2GB 339 * space, but EFA offers larger MR support for large memory space, to ease 340 * on users working with very large datasets (i.e. full GPU memory mapping). 341 */ 342 struct efa_admin_reg_mr_cmd { 343 /* Common Admin Queue descriptor */ 344 struct efa_admin_aq_common_desc aq_common_desc; 345 346 /* Protection Domain */ 347 u16 pd; 348 349 /* MBZ */ 350 u16 reserved16_w1; 351 352 /* Physical Buffer List, each element is page-aligned. */ 353 union { 354 /* 355 * Inline array of guest-physical page addresses of user 356 * memory pages (optimization for short region 357 * registrations) 358 */ 359 u64 inline_pbl_array[4]; 360 361 /* points to PBL (direct or indirect, chained if needed) */ 362 struct efa_admin_ctrl_buff_info pbl; 363 } pbl; 364 365 /* Memory region length, in bytes. */ 366 u64 mr_length; 367 368 /* 369 * flags and page size 370 * 4:0 : phys_page_size_shift - page size is (1 << 371 * phys_page_size_shift). Page size is used for 372 * building the Virtual to Physical address mapping 373 * 6:5 : reserved - MBZ 374 * 7 : mem_addr_phy_mode_en - Enable bit for physical 375 * memory registration (no translation), can be used 376 * only by privileged clients. If set, PBL must 377 * contain a single entry. 378 */ 379 u8 flags; 380 381 /* 382 * permissions 383 * 0 : local_write_enable - Local write permissions: 384 * must be set for RQ buffers and buffers posted for 385 * RDMA Read requests 386 * 1 : remote_write_enable - Remote write 387 * permissions: must be set to enable RDMA write to 388 * the region 389 * 2 : remote_read_enable - Remote read permissions: 390 * must be set to enable RDMA read from the region 391 * 7:3 : reserved2 - MBZ 392 */ 393 u8 permissions; 394 395 /* MBZ */ 396 u16 reserved16_w5; 397 398 /* number of pages in PBL (redundant, could be calculated) */ 399 u32 page_num; 400 401 /* 402 * IO Virtual Address associated with this MR. If 403 * mem_addr_phy_mode_en is set, contains the physical address of 404 * the region. 405 */ 406 u64 iova; 407 }; 408 409 struct efa_admin_reg_mr_resp { 410 /* Common Admin Queue completion descriptor */ 411 struct efa_admin_acq_common_desc acq_common_desc; 412 413 /* 414 * L_Key, to be used in conjunction with local buffer references in 415 * SQ and RQ WQE, or with virtual RQ/CQ rings 416 */ 417 u32 l_key; 418 419 /* 420 * R_Key, to be used in RDMA messages to refer to remotely accessed 421 * memory region 422 */ 423 u32 r_key; 424 425 /* 426 * Mask indicating which fields have valid values 427 * 0 : recv_ic_id 428 * 1 : rdma_read_ic_id 429 * 2 : rdma_recv_ic_id 430 */ 431 u8 validity; 432 433 /* 434 * Physical interconnect used by the device to reach the MR for receive 435 * operation 436 */ 437 u8 recv_ic_id; 438 439 /* 440 * Physical interconnect used by the device to reach the MR for RDMA 441 * read operation 442 */ 443 u8 rdma_read_ic_id; 444 445 /* 446 * Physical interconnect used by the device to reach the MR for RDMA 447 * write receive 448 */ 449 u8 rdma_recv_ic_id; 450 }; 451 452 struct efa_admin_dereg_mr_cmd { 453 /* Common Admin Queue descriptor */ 454 struct efa_admin_aq_common_desc aq_common_desc; 455 456 /* L_Key, memory region's l_key */ 457 u32 l_key; 458 }; 459 460 struct efa_admin_dereg_mr_resp { 461 /* Common Admin Queue completion descriptor */ 462 struct efa_admin_acq_common_desc acq_common_desc; 463 }; 464 465 /* 466 * Allocation of MemoryRegion, required for QP working with Virtual 467 * Addresses in kernel verbs semantics, ready for fast registration use. 468 */ 469 struct efa_admin_alloc_mr_cmd { 470 /* Common Admin Queue descriptor */ 471 struct efa_admin_aq_common_desc aq_common_desc; 472 473 /* Protection Domain */ 474 u16 pd; 475 476 /* MBZ */ 477 u16 reserved1; 478 479 /* Maximum number of pages this MR supports. */ 480 u32 max_pages; 481 }; 482 483 struct efa_admin_alloc_mr_resp { 484 /* Common Admin Queue completion descriptor */ 485 struct efa_admin_acq_common_desc acq_common_desc; 486 487 /* 488 * L_Key, to be used in conjunction with local buffer references in 489 * SQ and RQ WQE, or with virtual RQ/CQ rings 490 */ 491 u32 l_key; 492 493 /* 494 * R_Key, to be used in RDMA messages to refer to remotely accessed 495 * memory region 496 */ 497 u32 r_key; 498 }; 499 500 struct efa_admin_create_cq_cmd { 501 struct efa_admin_aq_common_desc aq_common_desc; 502 503 /* 504 * 4:0 : reserved5 - MBZ 505 * 5 : interrupt_mode_enabled - if set, cq operates 506 * in interrupt mode (i.e. CQ events and EQ elements 507 * are generated), otherwise - polling 508 * 6 : virt - If set, ring base address is virtual 509 * (IOVA returned by MR registration) 510 * 7 : reserved6 - MBZ 511 */ 512 u8 cq_caps_1; 513 514 /* 515 * 4:0 : cq_entry_size_words - size of CQ entry in 516 * 32-bit words, valid values: 4, 8. 517 * 5 : set_src_addr - If set, source address will be 518 * filled on RX completions from unknown senders. 519 * Requires 8 words CQ entry size. 520 * 7:6 : reserved7 - MBZ 521 */ 522 u8 cq_caps_2; 523 524 /* Sub completion queue depth in # of entries. must be power of 2 */ 525 u16 sub_cq_depth; 526 527 /* EQ number assigned to this cq */ 528 u16 eqn; 529 530 /* MBZ */ 531 u16 reserved; 532 533 /* 534 * CQ ring base address, virtual or physical depending on 'virt' 535 * flag 536 */ 537 struct efa_common_mem_addr cq_ba; 538 539 /* 540 * Memory registration key for the ring, used only when base 541 * address is virtual 542 */ 543 u32 l_key; 544 545 /* 546 * number of sub cqs - must be equal to sub_cqs_per_cq of queue 547 * attributes. 548 */ 549 u16 num_sub_cqs; 550 551 /* UAR number */ 552 u16 uar; 553 }; 554 555 struct efa_admin_create_cq_resp { 556 struct efa_admin_acq_common_desc acq_common_desc; 557 558 u16 cq_idx; 559 560 /* actual sub cq depth in number of entries */ 561 u16 sub_cq_actual_depth; 562 563 /* CQ doorbell address, as offset to PCIe DB BAR */ 564 u32 db_offset; 565 566 /* 567 * 0 : db_valid - If set, doorbell offset is valid. 568 * Always set when interrupts are requested. 569 */ 570 u32 flags; 571 }; 572 573 struct efa_admin_destroy_cq_cmd { 574 struct efa_admin_aq_common_desc aq_common_desc; 575 576 u16 cq_idx; 577 578 /* MBZ */ 579 u16 reserved1; 580 }; 581 582 struct efa_admin_destroy_cq_resp { 583 struct efa_admin_acq_common_desc acq_common_desc; 584 }; 585 586 /* 587 * EFA AQ Get Statistics command. Extended statistics are placed in control 588 * buffer pointed by AQ entry 589 */ 590 struct efa_admin_aq_get_stats_cmd { 591 struct efa_admin_aq_common_desc aq_common_descriptor; 592 593 union { 594 /* command specific inline data */ 595 u32 inline_data_w1[3]; 596 597 struct efa_admin_ctrl_buff_info control_buffer; 598 } u; 599 600 /* stats type as defined in enum efa_admin_get_stats_type */ 601 u8 type; 602 603 /* stats scope defined in enum efa_admin_get_stats_scope */ 604 u8 scope; 605 606 u16 scope_modifier; 607 }; 608 609 struct efa_admin_basic_stats { 610 u64 tx_bytes; 611 612 u64 tx_pkts; 613 614 u64 rx_bytes; 615 616 u64 rx_pkts; 617 618 u64 rx_drops; 619 620 u64 qkey_viol; 621 }; 622 623 struct efa_admin_messages_stats { 624 u64 send_bytes; 625 626 u64 send_wrs; 627 628 u64 recv_bytes; 629 630 u64 recv_wrs; 631 }; 632 633 struct efa_admin_rdma_read_stats { 634 u64 read_wrs; 635 636 u64 read_bytes; 637 638 u64 read_wr_err; 639 640 u64 read_resp_bytes; 641 }; 642 643 struct efa_admin_rdma_write_stats { 644 u64 write_wrs; 645 646 u64 write_bytes; 647 648 u64 write_wr_err; 649 650 u64 write_recv_bytes; 651 }; 652 653 struct efa_admin_network_stats { 654 u64 retrans_bytes; 655 656 u64 retrans_pkts; 657 658 u64 retrans_timeout_events; 659 660 u64 unresponsive_remote_events; 661 662 u64 impaired_remote_conn_events; 663 }; 664 665 struct efa_admin_acq_get_stats_resp { 666 struct efa_admin_acq_common_desc acq_common_desc; 667 668 union { 669 struct efa_admin_basic_stats basic_stats; 670 671 struct efa_admin_messages_stats messages_stats; 672 673 struct efa_admin_rdma_read_stats rdma_read_stats; 674 675 struct efa_admin_rdma_write_stats rdma_write_stats; 676 677 struct efa_admin_network_stats network_stats; 678 } u; 679 }; 680 681 struct efa_admin_get_set_feature_common_desc { 682 /* MBZ */ 683 u8 reserved0; 684 685 /* as appears in efa_admin_aq_feature_id */ 686 u8 feature_id; 687 688 /* MBZ */ 689 u16 reserved16; 690 }; 691 692 struct efa_admin_feature_device_attr_desc { 693 /* Bitmap of efa_admin_aq_feature_id */ 694 u64 supported_features; 695 696 /* Bitmap of supported page sizes in MR registrations */ 697 u64 page_size_cap; 698 699 u32 fw_version; 700 701 u32 admin_api_version; 702 703 u32 device_version; 704 705 /* Bar used for SQ and RQ doorbells */ 706 u16 db_bar; 707 708 /* Indicates how many bits are used on physical address access */ 709 u8 phys_addr_width; 710 711 /* Indicates how many bits are used on virtual address access */ 712 u8 virt_addr_width; 713 714 /* 715 * 0 : rdma_read - If set, RDMA Read is supported on 716 * TX queues 717 * 1 : rnr_retry - If set, RNR retry is supported on 718 * modify QP command 719 * 2 : data_polling_128 - If set, 128 bytes data 720 * polling is supported 721 * 3 : rdma_write - If set, RDMA Write is supported 722 * on TX queues 723 * 4 : unsolicited_write_recv - If set, unsolicited 724 * write with imm. receive is supported 725 * 31:5 : reserved - MBZ 726 */ 727 u32 device_caps; 728 729 /* Max RDMA transfer size in bytes */ 730 u32 max_rdma_size; 731 732 /* Unique global ID for an EFA device */ 733 u64 guid; 734 735 /* The device maximum link speed in Gbit/sec */ 736 u16 max_link_speed_gbps; 737 738 /* MBZ */ 739 u16 reserved0; 740 741 /* MBZ */ 742 u32 reserved1; 743 }; 744 745 struct efa_admin_feature_queue_attr_desc_1 { 746 /* The maximum number of queue pairs supported */ 747 u32 max_qp; 748 749 /* Maximum number of WQEs per Send Queue */ 750 u32 max_sq_depth; 751 752 /* 753 * Maximum size of data that can be sent inline in a Send WQE 754 * (deprecated by 755 * efa_admin_feature_queue_attr_desc_2::inline_buf_size_ex on 756 * supporting devices) 757 */ 758 u32 inline_buf_size; 759 760 /* Maximum number of buffer descriptors per Recv Queue */ 761 u32 max_rq_depth; 762 763 /* The maximum number of completion queues supported per VF */ 764 u32 max_cq; 765 766 /* Maximum number of CQEs per Completion Queue */ 767 u32 max_cq_depth; 768 769 /* Number of sub-CQs to be created for each CQ */ 770 u16 sub_cqs_per_cq; 771 772 /* Minimum number of WQEs per SQ */ 773 u16 min_sq_depth; 774 775 /* Maximum number of SGEs (buffers) allowed for a single send WQE */ 776 u16 max_wr_send_sges; 777 778 /* Maximum number of SGEs allowed for a single recv WQE */ 779 u16 max_wr_recv_sges; 780 781 /* The maximum number of memory regions supported */ 782 u32 max_mr; 783 784 /* The maximum number of pages can be registered */ 785 u32 max_mr_pages; 786 787 /* The maximum number of protection domains supported */ 788 u32 max_pd; 789 790 /* The maximum number of address handles supported */ 791 u32 max_ah; 792 793 /* The maximum size of LLQ in bytes */ 794 u32 max_llq_size; 795 796 /* Maximum number of SGEs for a single RDMA read/write WQE */ 797 u16 max_wr_rdma_sges; 798 799 /* 800 * Maximum number of bytes that can be written to SQ between two 801 * consecutive doorbells (in units of 64B). Driver must ensure that only 802 * complete WQEs are written to queue before issuing a doorbell. 803 * Examples: max_tx_batch=16 and WQE size = 64B, means up to 16 WQEs can 804 * be written to SQ between two consecutive doorbells. max_tx_batch=11 805 * and WQE size = 128B, means up to 5 WQEs can be written to SQ between 806 * two consecutive doorbells. Zero means unlimited. 807 */ 808 u16 max_tx_batch; 809 }; 810 811 struct efa_admin_feature_queue_attr_desc_2 { 812 /* Maximum size of data that can be sent inline in a Send WQE */ 813 u16 inline_buf_size_ex; 814 }; 815 816 struct efa_admin_event_queue_attr_desc { 817 /* The maximum number of event queues supported */ 818 u32 max_eq; 819 820 /* Maximum number of EQEs per Event Queue */ 821 u32 max_eq_depth; 822 823 /* Supported events bitmask */ 824 u32 event_bitmask; 825 }; 826 827 struct efa_admin_feature_aenq_desc { 828 /* bitmask for AENQ groups the device can report */ 829 u32 supported_groups; 830 831 /* bitmask for AENQ groups to report */ 832 u32 enabled_groups; 833 }; 834 835 struct efa_admin_feature_network_attr_desc { 836 /* Raw address data in network byte order */ 837 u8 addr[16]; 838 839 /* max packet payload size in bytes */ 840 u32 mtu; 841 }; 842 843 /* 844 * When hint value is 0, hints capabilities are not supported or driver 845 * should use its own predefined value 846 */ 847 struct efa_admin_hw_hints { 848 /* value in ms */ 849 u16 mmio_read_timeout; 850 851 /* value in ms */ 852 u16 driver_watchdog_timeout; 853 854 /* value in ms */ 855 u16 admin_completion_timeout; 856 857 /* poll interval in ms */ 858 u16 poll_interval; 859 }; 860 861 struct efa_admin_get_feature_cmd { 862 struct efa_admin_aq_common_desc aq_common_descriptor; 863 864 struct efa_admin_ctrl_buff_info control_buffer; 865 866 struct efa_admin_get_set_feature_common_desc feature_common; 867 868 u32 raw[11]; 869 }; 870 871 struct efa_admin_get_feature_resp { 872 struct efa_admin_acq_common_desc acq_common_desc; 873 874 union { 875 u32 raw[14]; 876 877 struct efa_admin_feature_device_attr_desc device_attr; 878 879 struct efa_admin_feature_aenq_desc aenq; 880 881 struct efa_admin_feature_network_attr_desc network_attr; 882 883 struct efa_admin_feature_queue_attr_desc_1 queue_attr_1; 884 885 struct efa_admin_feature_queue_attr_desc_2 queue_attr_2; 886 887 struct efa_admin_event_queue_attr_desc event_queue_attr; 888 889 struct efa_admin_hw_hints hw_hints; 890 } u; 891 }; 892 893 struct efa_admin_set_feature_cmd { 894 struct efa_admin_aq_common_desc aq_common_descriptor; 895 896 struct efa_admin_ctrl_buff_info control_buffer; 897 898 struct efa_admin_get_set_feature_common_desc feature_common; 899 900 union { 901 u32 raw[11]; 902 903 /* AENQ configuration */ 904 struct efa_admin_feature_aenq_desc aenq; 905 } u; 906 }; 907 908 struct efa_admin_set_feature_resp { 909 struct efa_admin_acq_common_desc acq_common_desc; 910 911 union { 912 u32 raw[14]; 913 } u; 914 }; 915 916 struct efa_admin_alloc_pd_cmd { 917 struct efa_admin_aq_common_desc aq_common_descriptor; 918 }; 919 920 struct efa_admin_alloc_pd_resp { 921 struct efa_admin_acq_common_desc acq_common_desc; 922 923 /* PD number */ 924 u16 pd; 925 926 /* MBZ */ 927 u16 reserved; 928 }; 929 930 struct efa_admin_dealloc_pd_cmd { 931 struct efa_admin_aq_common_desc aq_common_descriptor; 932 933 /* PD number */ 934 u16 pd; 935 936 /* MBZ */ 937 u16 reserved; 938 }; 939 940 struct efa_admin_dealloc_pd_resp { 941 struct efa_admin_acq_common_desc acq_common_desc; 942 }; 943 944 struct efa_admin_alloc_uar_cmd { 945 struct efa_admin_aq_common_desc aq_common_descriptor; 946 }; 947 948 struct efa_admin_alloc_uar_resp { 949 struct efa_admin_acq_common_desc acq_common_desc; 950 951 /* UAR number */ 952 u16 uar; 953 954 /* MBZ */ 955 u16 reserved; 956 }; 957 958 struct efa_admin_dealloc_uar_cmd { 959 struct efa_admin_aq_common_desc aq_common_descriptor; 960 961 /* UAR number */ 962 u16 uar; 963 964 /* MBZ */ 965 u16 reserved; 966 }; 967 968 struct efa_admin_dealloc_uar_resp { 969 struct efa_admin_acq_common_desc acq_common_desc; 970 }; 971 972 struct efa_admin_create_eq_cmd { 973 struct efa_admin_aq_common_desc aq_common_descriptor; 974 975 /* Size of the EQ in entries, must be power of 2 */ 976 u16 depth; 977 978 /* MSI-X table entry index */ 979 u8 msix_vec; 980 981 /* 982 * 4:0 : entry_size_words - size of EQ entry in 983 * 32-bit words 984 * 7:5 : reserved - MBZ 985 */ 986 u8 caps; 987 988 /* EQ ring base address */ 989 struct efa_common_mem_addr ba; 990 991 /* 992 * Enabled events on this EQ 993 * 0 : completion_events - Enable completion events 994 * 31:1 : reserved - MBZ 995 */ 996 u32 event_bitmask; 997 998 /* MBZ */ 999 u32 reserved; 1000 }; 1001 1002 struct efa_admin_create_eq_resp { 1003 struct efa_admin_acq_common_desc acq_common_desc; 1004 1005 /* EQ number */ 1006 u16 eqn; 1007 1008 /* MBZ */ 1009 u16 reserved; 1010 }; 1011 1012 struct efa_admin_destroy_eq_cmd { 1013 struct efa_admin_aq_common_desc aq_common_descriptor; 1014 1015 /* EQ number */ 1016 u16 eqn; 1017 1018 /* MBZ */ 1019 u16 reserved; 1020 }; 1021 1022 struct efa_admin_destroy_eq_resp { 1023 struct efa_admin_acq_common_desc acq_common_desc; 1024 }; 1025 1026 /* asynchronous event notification groups */ 1027 enum efa_admin_aenq_group { 1028 EFA_ADMIN_FATAL_ERROR = 1, 1029 EFA_ADMIN_WARNING = 2, 1030 EFA_ADMIN_NOTIFICATION = 3, 1031 EFA_ADMIN_KEEP_ALIVE = 4, 1032 EFA_ADMIN_AENQ_GROUPS_NUM = 5, 1033 }; 1034 1035 struct efa_admin_mmio_req_read_less_resp { 1036 u16 req_id; 1037 1038 u16 reg_off; 1039 1040 /* value is valid when poll is cleared */ 1041 u32 reg_val; 1042 }; 1043 1044 enum efa_admin_os_type { 1045 EFA_ADMIN_OS_LINUX = 0, 1046 }; 1047 1048 struct efa_admin_host_info { 1049 /* OS distribution string format */ 1050 u8 os_dist_str[128]; 1051 1052 /* Defined in enum efa_admin_os_type */ 1053 u32 os_type; 1054 1055 /* Kernel version string format */ 1056 u8 kernel_ver_str[32]; 1057 1058 /* Kernel version numeric format */ 1059 u32 kernel_ver; 1060 1061 /* 1062 * 7:0 : driver_module_type 1063 * 15:8 : driver_sub_minor 1064 * 23:16 : driver_minor 1065 * 31:24 : driver_major 1066 */ 1067 u32 driver_ver; 1068 1069 /* 1070 * Device's Bus, Device and Function 1071 * 2:0 : function 1072 * 7:3 : device 1073 * 15:8 : bus 1074 */ 1075 u16 bdf; 1076 1077 /* 1078 * Spec version 1079 * 7:0 : spec_minor 1080 * 15:8 : spec_major 1081 */ 1082 u16 spec_ver; 1083 1084 /* 1085 * 0 : intree - Intree driver 1086 * 1 : gdr - GPUDirect RDMA supported 1087 * 31:2 : reserved2 1088 */ 1089 u32 flags; 1090 }; 1091 1092 /* create_qp_cmd */ 1093 #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0) 1094 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1) 1095 #define EFA_ADMIN_CREATE_QP_CMD_UNSOLICITED_WRITE_RECV_MASK BIT(2) 1096 1097 /* modify_qp_cmd */ 1098 #define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK BIT(0) 1099 #define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK BIT(1) 1100 #define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK BIT(2) 1101 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK BIT(3) 1102 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4) 1103 #define EFA_ADMIN_MODIFY_QP_CMD_RNR_RETRY_MASK BIT(5) 1104 1105 /* reg_mr_cmd */ 1106 #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0) 1107 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7) 1108 #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0) 1109 #define EFA_ADMIN_REG_MR_CMD_REMOTE_WRITE_ENABLE_MASK BIT(1) 1110 #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2) 1111 1112 /* reg_mr_resp */ 1113 #define EFA_ADMIN_REG_MR_RESP_RECV_IC_ID_MASK BIT(0) 1114 #define EFA_ADMIN_REG_MR_RESP_RDMA_READ_IC_ID_MASK BIT(1) 1115 #define EFA_ADMIN_REG_MR_RESP_RDMA_RECV_IC_ID_MASK BIT(2) 1116 1117 /* create_cq_cmd */ 1118 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1119 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6) 1120 #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1121 #define EFA_ADMIN_CREATE_CQ_CMD_SET_SRC_ADDR_MASK BIT(5) 1122 1123 /* create_cq_resp */ 1124 #define EFA_ADMIN_CREATE_CQ_RESP_DB_VALID_MASK BIT(0) 1125 1126 /* feature_device_attr_desc */ 1127 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0) 1128 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RNR_RETRY_MASK BIT(1) 1129 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_DATA_POLLING_128_MASK BIT(2) 1130 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_WRITE_MASK BIT(3) 1131 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_UNSOLICITED_WRITE_RECV_MASK BIT(4) 1132 1133 /* create_eq_cmd */ 1134 #define EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1135 #define EFA_ADMIN_CREATE_EQ_CMD_COMPLETION_EVENTS_MASK BIT(0) 1136 1137 /* host_info */ 1138 #define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0) 1139 #define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8) 1140 #define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16) 1141 #define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24) 1142 #define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1143 #define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1144 #define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1145 #define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0) 1146 #define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8) 1147 #define EFA_ADMIN_HOST_INFO_INTREE_MASK BIT(0) 1148 #define EFA_ADMIN_HOST_INFO_GDR_MASK BIT(1) 1149 1150 #endif /* _EFA_ADMIN_CMDS_H_ */ 1151