1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 /* 3 * Copyright 2018-2026 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef _EFA_ADMIN_CMDS_H_ 7 #define _EFA_ADMIN_CMDS_H_ 8 9 /* EFA admin queue opcodes */ 10 enum efa_admin_aq_opcode { 11 EFA_ADMIN_CREATE_QP = 1, 12 EFA_ADMIN_MODIFY_QP = 2, 13 EFA_ADMIN_QUERY_QP = 3, 14 EFA_ADMIN_DESTROY_QP = 4, 15 EFA_ADMIN_CREATE_AH = 5, 16 EFA_ADMIN_DESTROY_AH = 6, 17 EFA_ADMIN_REG_MR = 7, 18 EFA_ADMIN_DEREG_MR = 8, 19 EFA_ADMIN_CREATE_CQ = 9, 20 EFA_ADMIN_DESTROY_CQ = 10, 21 EFA_ADMIN_GET_FEATURE = 11, 22 EFA_ADMIN_SET_FEATURE = 12, 23 EFA_ADMIN_GET_STATS = 13, 24 EFA_ADMIN_ALLOC_PD = 14, 25 EFA_ADMIN_DEALLOC_PD = 15, 26 EFA_ADMIN_ALLOC_UAR = 16, 27 EFA_ADMIN_DEALLOC_UAR = 17, 28 EFA_ADMIN_CREATE_EQ = 18, 29 EFA_ADMIN_DESTROY_EQ = 19, 30 EFA_ADMIN_ALLOC_MR = 20, 31 EFA_ADMIN_SERVICE = 21, 32 EFA_ADMIN_CREATE_EVENT_COUNTER = 25, 33 EFA_ADMIN_DESTROY_EVENT_COUNTER = 26, 34 EFA_ADMIN_ATTACH_EVENT_COUNTER = 27, 35 EFA_ADMIN_MODIFY_EVENT_COUNTER = 28, 36 EFA_ADMIN_DETACH_EVENT_COUNTER = 29, 37 EFA_ADMIN_MAX_OPCODE = 29, 38 }; 39 40 enum efa_admin_aq_feature_id { 41 EFA_ADMIN_DEVICE_ATTR = 1, 42 EFA_ADMIN_AENQ_CONFIG = 2, 43 EFA_ADMIN_NETWORK_ATTR = 3, 44 EFA_ADMIN_QUEUE_ATTR_1 = 4, 45 EFA_ADMIN_HW_HINTS = 5, 46 EFA_ADMIN_HOST_INFO = 6, 47 EFA_ADMIN_EVENT_QUEUE_ATTR = 7, 48 EFA_ADMIN_QUEUE_ATTR_2 = 9, 49 }; 50 51 /* QP transport type */ 52 enum efa_admin_qp_type { 53 /* Unreliable Datagram */ 54 EFA_ADMIN_QP_TYPE_UD = 1, 55 /* Scalable Reliable Datagram */ 56 EFA_ADMIN_QP_TYPE_SRD = 2, 57 }; 58 59 /* QP state */ 60 enum efa_admin_qp_state { 61 EFA_ADMIN_QP_STATE_RESET = 0, 62 EFA_ADMIN_QP_STATE_INIT = 1, 63 EFA_ADMIN_QP_STATE_RTR = 2, 64 EFA_ADMIN_QP_STATE_RTS = 3, 65 EFA_ADMIN_QP_STATE_SQD = 4, 66 EFA_ADMIN_QP_STATE_SQE = 5, 67 EFA_ADMIN_QP_STATE_ERR = 6, 68 }; 69 70 enum efa_admin_get_stats_type { 71 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0, 72 EFA_ADMIN_GET_STATS_TYPE_MESSAGES = 1, 73 EFA_ADMIN_GET_STATS_TYPE_RDMA_READ = 2, 74 EFA_ADMIN_GET_STATS_TYPE_RDMA_WRITE = 3, 75 EFA_ADMIN_GET_STATS_TYPE_NETWORK = 4, 76 }; 77 78 enum efa_admin_get_stats_scope { 79 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0, 80 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1, 81 }; 82 83 /* 84 * QP allocation sizes, converted by fabric QueuePair (QP) create command 85 * from QP capabilities. 86 */ 87 struct efa_admin_qp_alloc_size { 88 /* Send descriptor ring size in bytes */ 89 u32 send_queue_ring_size; 90 91 /* Max number of WQEs that can be outstanding on send queue. */ 92 u32 send_queue_depth; 93 94 /* 95 * Recv descriptor ring size in bytes, sufficient for user-provided 96 * number of WQEs 97 */ 98 u32 recv_queue_ring_size; 99 100 /* Max number of WQEs that can be outstanding on recv queue */ 101 u32 recv_queue_depth; 102 }; 103 104 struct efa_admin_create_qp_cmd { 105 /* Protection Domain associated with this QP */ 106 u16 pd; 107 108 /* QP type */ 109 u8 qp_type; 110 111 /* 112 * 0 : sq_virt - If set, SQ ring base address is 113 * virtual (IOVA returned by MR registration) 114 * 1 : rq_virt - If set, RQ ring base address is 115 * virtual (IOVA returned by MR registration) 116 * 2 : unsolicited_write_recv - If set, work requests 117 * will not be consumed for incoming RDMA write with 118 * immediate 119 * 3 : sq_64_bit_req_id - If set, requests posted on 120 * SQ will use 64-bit ids. The corresponding CQ must 121 * also have 64-bit ids enabled. 122 * 7:4 : reserved - MBZ 123 */ 124 u8 flags; 125 126 /* 127 * Send queue (SQ) ring base physical address. This field is not 128 * used if this is a Low Latency Queue(LLQ). 129 */ 130 u64 sq_base_addr; 131 132 /* Receive queue (RQ) ring base address. */ 133 u64 rq_base_addr; 134 135 /* Index of CQ to be associated with Send Queue completions */ 136 u32 send_cq_idx; 137 138 /* Index of CQ to be associated with Recv Queue completions */ 139 u32 recv_cq_idx; 140 141 /* 142 * Memory registration key for the SQ ring, used only when not in 143 * LLQ mode and base address is virtual 144 */ 145 u32 sq_l_key; 146 147 /* 148 * Memory registration key for the RQ ring, used only when base 149 * address is virtual 150 */ 151 u32 rq_l_key; 152 153 /* Requested QP allocation sizes */ 154 struct efa_admin_qp_alloc_size qp_alloc_size; 155 156 /* UAR number */ 157 u16 uar; 158 159 /* Requested service level for the QP, 0 is the default SL */ 160 u8 sl; 161 162 /* MBZ */ 163 u8 reserved; 164 165 /* MBZ */ 166 u32 reserved2; 167 } __packed; 168 169 struct efa_admin_create_qp_resp { 170 /* Common Admin Queue completion descriptor */ 171 struct efa_admin_acq_common_desc acq_common_desc; 172 173 /* 174 * Opaque handle to be used for consequent admin operations on the 175 * QP 176 */ 177 u32 qp_handle; 178 179 /* 180 * QP number in the given EFA virtual device. Least-significant bits (as 181 * needed according to max_qp) carry unique QP ID 182 */ 183 u16 qp_num; 184 185 /* MBZ */ 186 u16 reserved; 187 188 /* Index of sub-CQ for Send Queue completions */ 189 u16 send_sub_cq_idx; 190 191 /* Index of sub-CQ for Receive Queue completions */ 192 u16 recv_sub_cq_idx; 193 194 /* SQ doorbell address, as offset to PCIe DB BAR */ 195 u32 sq_db_offset; 196 197 /* RQ doorbell address, as offset to PCIe DB BAR */ 198 u32 rq_db_offset; 199 200 /* 201 * low latency send queue ring base address as an offset to PCIe 202 * MMIO LLQ_MEM BAR 203 */ 204 u32 llq_descriptors_offset; 205 }; 206 207 struct efa_admin_modify_qp_cmd { 208 /* 209 * Mask indicating which fields should be updated 210 * 0 : qp_state 211 * 1 : cur_qp_state 212 * 2 : qkey 213 * 3 : sq_psn 214 * 4 : sq_drained_async_notify 215 * 5 : rnr_retry 216 * 31:6 : reserved 217 */ 218 u32 modify_mask; 219 220 /* QP handle returned by create_qp command */ 221 u32 qp_handle; 222 223 /* QP state */ 224 u32 qp_state; 225 226 /* Override current QP state (before applying the transition) */ 227 u32 cur_qp_state; 228 229 /* QKey */ 230 u32 qkey; 231 232 /* SQ PSN */ 233 u32 sq_psn; 234 235 /* Enable async notification when SQ is drained */ 236 u8 sq_drained_async_notify; 237 238 /* Number of RNR retries (valid only for SRD QPs) */ 239 u8 rnr_retry; 240 241 /* MBZ */ 242 u16 reserved2; 243 } __packed; 244 245 struct efa_admin_modify_qp_resp { 246 /* Common Admin Queue completion descriptor */ 247 struct efa_admin_acq_common_desc acq_common_desc; 248 }; 249 250 struct efa_admin_query_qp_cmd { 251 /* QP handle returned by create_qp command */ 252 u32 qp_handle; 253 } __packed; 254 255 struct efa_admin_query_qp_resp { 256 /* Common Admin Queue completion descriptor */ 257 struct efa_admin_acq_common_desc acq_common_desc; 258 259 /* QP state */ 260 u32 qp_state; 261 262 /* QKey */ 263 u32 qkey; 264 265 /* SQ PSN */ 266 u32 sq_psn; 267 268 /* Indicates that draining is in progress */ 269 u8 sq_draining; 270 271 /* Number of RNR retries (valid only for SRD QPs) */ 272 u8 rnr_retry; 273 274 /* MBZ */ 275 u16 reserved2; 276 }; 277 278 struct efa_admin_destroy_qp_cmd { 279 /* QP handle returned by create_qp command */ 280 u32 qp_handle; 281 } __packed; 282 283 struct efa_admin_destroy_qp_resp { 284 /* Common Admin Queue completion descriptor */ 285 struct efa_admin_acq_common_desc acq_common_desc; 286 }; 287 288 /* 289 * Create Address Handle command parameters. Must not be called more than 290 * once for the same destination 291 */ 292 struct efa_admin_create_ah_cmd { 293 /* Destination address in network byte order */ 294 u8 dest_addr[16]; 295 296 /* PD number */ 297 u16 pd; 298 299 /* MBZ */ 300 u16 reserved; 301 } __packed; 302 303 struct efa_admin_create_ah_resp { 304 /* Common Admin Queue completion descriptor */ 305 struct efa_admin_acq_common_desc acq_common_desc; 306 307 /* Target interface address handle (opaque) */ 308 u16 ah; 309 310 /* MBZ */ 311 u16 reserved; 312 }; 313 314 struct efa_admin_destroy_ah_cmd { 315 /* Target interface address handle (opaque) */ 316 u16 ah; 317 318 /* PD number */ 319 u16 pd; 320 } __packed; 321 322 struct efa_admin_destroy_ah_resp { 323 /* Common Admin Queue completion descriptor */ 324 struct efa_admin_acq_common_desc acq_common_desc; 325 }; 326 327 /* 328 * Registration of MemoryRegion, required for QP working with Virtual 329 * Addresses. In standard verbs semantics, region length is limited to 2GB 330 * space, but EFA offers larger MR support for large memory space, to ease 331 * on users working with very large datasets (i.e. full GPU memory mapping). 332 */ 333 struct efa_admin_reg_mr_cmd { 334 /* Protection Domain */ 335 u16 pd; 336 337 /* MBZ */ 338 u16 reserved16_w1; 339 340 /* Physical Buffer List, each element is page-aligned. */ 341 union { 342 /* 343 * Inline array of guest-physical page addresses of user 344 * memory pages (optimization for short region 345 * registrations) 346 */ 347 u64 inline_pbl_array[4]; 348 349 /* points to PBL (direct or indirect, chained if needed) */ 350 struct efa_admin_ctrl_buff_info pbl; 351 } pbl; 352 353 /* Memory region length, in bytes. */ 354 u64 mr_length; 355 356 /* 357 * flags and page size 358 * 5:0 : phys_page_size_shift - page size is (1 << 359 * phys_page_size_shift). Page size is used for 360 * building the Virtual to Physical address mapping 361 * 6 : reserved - MBZ 362 * 7 : mem_addr_phy_mode_en - Enable bit for physical 363 * memory registration (no translation), can be used 364 * only by privileged clients. If set, PBL must 365 * contain a single entry. 366 */ 367 u8 flags; 368 369 /* 370 * permissions 371 * 0 : local_write_enable - Local write permissions: 372 * must be set for RQ buffers and buffers posted for 373 * RDMA Read requests 374 * 1 : remote_write_enable - Remote write 375 * permissions: must be set to enable RDMA write to 376 * the region 377 * 2 : remote_read_enable - Remote read permissions: 378 * must be set to enable RDMA read from the region 379 * 7:3 : reserved2 - MBZ 380 */ 381 u8 permissions; 382 383 /* MBZ */ 384 u16 reserved16_w5; 385 386 /* number of pages in PBL (redundant, could be calculated) */ 387 u32 page_num; 388 389 /* 390 * IO Virtual Address associated with this MR. If 391 * mem_addr_phy_mode_en is set, contains the physical address of 392 * the region. 393 */ 394 u64 iova; 395 } __packed; 396 397 struct efa_admin_reg_mr_resp { 398 /* Common Admin Queue completion descriptor */ 399 struct efa_admin_acq_common_desc acq_common_desc; 400 401 /* 402 * L_Key, to be used in conjunction with local buffer references in 403 * SQ and RQ WQE, or with virtual RQ/CQ rings 404 */ 405 u32 l_key; 406 407 /* 408 * R_Key, to be used in RDMA messages to refer to remotely accessed 409 * memory region 410 */ 411 u32 r_key; 412 413 /* 414 * Mask indicating which fields have valid values 415 * 0 : recv_ic_id 416 * 1 : rdma_read_ic_id 417 * 2 : rdma_recv_ic_id 418 */ 419 u8 validity; 420 421 /* 422 * Physical interconnect used by the device to reach the MR for receive 423 * operation 424 */ 425 u8 recv_ic_id; 426 427 /* 428 * Physical interconnect used by the device to reach the MR for RDMA 429 * read operation 430 */ 431 u8 rdma_read_ic_id; 432 433 /* 434 * Physical interconnect used by the device to reach the MR for RDMA 435 * write receive 436 */ 437 u8 rdma_recv_ic_id; 438 }; 439 440 struct efa_admin_dereg_mr_cmd { 441 /* L_Key, memory region's l_key */ 442 u32 l_key; 443 } __packed; 444 445 struct efa_admin_dereg_mr_resp { 446 /* Common Admin Queue completion descriptor */ 447 struct efa_admin_acq_common_desc acq_common_desc; 448 }; 449 450 /* 451 * Allocation of MemoryRegion, required for QP working with Virtual 452 * Addresses in kernel verbs semantics, ready for fast registration use. 453 */ 454 struct efa_admin_alloc_mr_cmd { 455 /* Protection Domain */ 456 u16 pd; 457 458 /* MBZ */ 459 u16 reserved1; 460 461 /* Maximum number of pages this MR supports. */ 462 u32 max_pages; 463 } __packed; 464 465 struct efa_admin_alloc_mr_resp { 466 /* Common Admin Queue completion descriptor */ 467 struct efa_admin_acq_common_desc acq_common_desc; 468 469 /* 470 * L_Key, to be used in conjunction with local buffer references in 471 * SQ and RQ WQE, or with virtual RQ/CQ rings 472 */ 473 u32 l_key; 474 475 /* 476 * R_Key, to be used in RDMA messages to refer to remotely accessed 477 * memory region 478 */ 479 u32 r_key; 480 }; 481 482 struct efa_admin_create_cq_cmd { 483 /* 484 * 4:0 : reserved5 - MBZ 485 * 5 : interrupt_mode_enabled - if set, cq operates 486 * in interrupt mode (i.e. CQ events and EQ elements 487 * are generated), otherwise - polling 488 * 6 : virt - If set, ring base address is virtual 489 * (IOVA returned by MR registration) 490 * 7 : reserved6 - MBZ 491 */ 492 u8 cq_caps_1; 493 494 /* 495 * 4:0 : cq_entry_size_words - size of CQ entry in 496 * 32-bit words, valid values: 4, 8. 497 * 5 : set_src_addr - If set, source address will be 498 * filled on RX completions from unknown senders. 499 * Requires 8 words CQ entry size. 500 * 6 : sq_comp_64_bit_req_id - If set, send 501 * completions will use 64-bit work request ids 502 * 7 : reserved7 - MBZ 503 */ 504 u8 cq_caps_2; 505 506 /* Sub completion queue depth in # of entries. must be power of 2 */ 507 u16 sub_cq_depth; 508 509 /* EQ number assigned to this cq */ 510 u16 eqn; 511 512 /* MBZ */ 513 u16 reserved; 514 515 /* 516 * CQ ring base address, virtual or physical depending on 'virt' 517 * flag 518 */ 519 struct efa_common_mem_addr cq_ba; 520 521 /* 522 * Memory registration key for the ring, used only when base 523 * address is virtual 524 */ 525 u32 l_key; 526 527 /* 528 * number of sub cqs - must be equal to sub_cqs_per_cq of queue 529 * attributes. 530 */ 531 u16 num_sub_cqs; 532 533 /* UAR number */ 534 u16 uar; 535 } __packed; 536 537 struct efa_admin_create_cq_resp { 538 struct efa_admin_acq_common_desc acq_common_desc; 539 540 u16 cq_idx; 541 542 /* actual sub cq depth in number of entries */ 543 u16 sub_cq_actual_depth; 544 545 /* CQ doorbell address, as offset to PCIe DB BAR */ 546 u32 db_offset; 547 548 /* 549 * 0 : db_valid - If set, doorbell offset is valid. 550 * Always set when interrupts are requested. 551 */ 552 u32 flags; 553 }; 554 555 struct efa_admin_destroy_cq_cmd { 556 u16 cq_idx; 557 558 /* MBZ */ 559 u16 reserved1; 560 } __packed; 561 562 struct efa_admin_destroy_cq_resp { 563 struct efa_admin_acq_common_desc acq_common_desc; 564 }; 565 566 /* 567 * EFA AQ Get Statistics command. Extended statistics are placed in control 568 * buffer pointed by AQ entry 569 */ 570 struct efa_admin_aq_get_stats_cmd { 571 struct efa_admin_ctrl_buff_info control_buffer; 572 573 /* stats type as defined in enum efa_admin_get_stats_type */ 574 u8 type; 575 576 /* stats scope defined in enum efa_admin_get_stats_scope */ 577 u8 scope; 578 579 u16 scope_modifier; 580 } __packed; 581 582 struct efa_admin_basic_stats { 583 u64 tx_bytes; 584 585 u64 tx_pkts; 586 587 u64 rx_bytes; 588 589 u64 rx_pkts; 590 591 u64 rx_drops; 592 593 u64 qkey_viol; 594 }; 595 596 struct efa_admin_messages_stats { 597 u64 send_bytes; 598 599 u64 send_wrs; 600 601 u64 recv_bytes; 602 603 u64 recv_wrs; 604 }; 605 606 struct efa_admin_rdma_read_stats { 607 u64 read_wrs; 608 609 u64 read_bytes; 610 611 u64 read_wr_err; 612 613 u64 read_resp_bytes; 614 }; 615 616 struct efa_admin_rdma_write_stats { 617 u64 write_wrs; 618 619 u64 write_bytes; 620 621 u64 write_wr_err; 622 623 u64 write_recv_bytes; 624 }; 625 626 struct efa_admin_network_stats { 627 u64 retrans_bytes; 628 629 u64 retrans_pkts; 630 631 u64 retrans_timeout_events; 632 633 u64 unresponsive_remote_events; 634 635 u64 impaired_remote_conn_events; 636 }; 637 638 struct efa_admin_acq_get_stats_resp { 639 struct efa_admin_acq_common_desc acq_common_desc; 640 641 union { 642 struct efa_admin_basic_stats basic_stats; 643 644 struct efa_admin_messages_stats messages_stats; 645 646 struct efa_admin_rdma_read_stats rdma_read_stats; 647 648 struct efa_admin_rdma_write_stats rdma_write_stats; 649 650 struct efa_admin_network_stats network_stats; 651 } u; 652 }; 653 654 struct efa_admin_get_set_feature_common_desc { 655 /* MBZ */ 656 u8 reserved0; 657 658 /* as appears in efa_admin_aq_feature_id */ 659 u8 feature_id; 660 661 /* MBZ */ 662 u16 reserved16; 663 }; 664 665 struct efa_admin_feature_device_attr_desc { 666 /* Bitmap of efa_admin_aq_feature_id */ 667 u64 supported_features; 668 669 /* Bitmap of supported page sizes in MR registrations */ 670 u64 page_size_cap; 671 672 u32 fw_version; 673 674 u32 admin_api_version; 675 676 u32 device_version; 677 678 /* Bar used for SQ and RQ doorbells */ 679 u16 db_bar; 680 681 /* Indicates how many bits are used on physical address access */ 682 u8 phys_addr_width; 683 684 /* Indicates how many bits are used on virtual address access */ 685 u8 virt_addr_width; 686 687 /* 688 * 0 : rdma_read - If set, RDMA Read is supported on 689 * TX queues 690 * 1 : rnr_retry - If set, RNR retry is supported on 691 * modify QP command 692 * 2 : data_polling_128 - If set, 128 bytes data 693 * polling is supported 694 * 3 : rdma_write - If set, RDMA Write is supported 695 * on TX queues 696 * 4 : unsolicited_write_recv - If set, unsolicited 697 * write with imm. receive is supported 698 * 5 : event_counters - If set, event counters are 699 * supported 700 * 9:6 : reserved1 - MBZ 701 * 10 : sq_64_bit_req_id - If set, SQ can use 64-bit 702 * work request ids 703 * 31:11 : reserved2 - MBZ 704 */ 705 u32 device_caps; 706 707 /* Max RDMA transfer size in bytes */ 708 u32 max_rdma_size; 709 710 /* Unique global ID for an EFA device */ 711 u64 guid; 712 713 /* The device maximum link speed in Gbit/sec */ 714 u16 max_link_speed_gbps; 715 716 /* MBZ */ 717 u16 reserved0; 718 719 /* MBZ */ 720 u32 reserved1; 721 }; 722 723 struct efa_admin_feature_queue_attr_desc_1 { 724 /* The maximum number of queue pairs supported */ 725 u32 max_qp; 726 727 /* Maximum number of WQEs per Send Queue */ 728 u32 max_sq_depth; 729 730 /* 731 * Maximum size of data that can be sent inline in a Send WQE 732 * (deprecated by 733 * efa_admin_feature_queue_attr_desc_2::inline_buf_size_ex on 734 * supporting devices) 735 */ 736 u32 inline_buf_size; 737 738 /* Maximum number of buffer descriptors per Recv Queue */ 739 u32 max_rq_depth; 740 741 /* The maximum number of completion queues supported per VF */ 742 u32 max_cq; 743 744 /* Maximum number of CQEs per Completion Queue */ 745 u32 max_cq_depth; 746 747 /* Number of sub-CQs to be created for each CQ */ 748 u16 sub_cqs_per_cq; 749 750 /* Minimum number of WQEs per SQ */ 751 u16 min_sq_depth; 752 753 /* Maximum number of SGEs (buffers) allowed for a single send WQE */ 754 u16 max_wr_send_sges; 755 756 /* Maximum number of SGEs allowed for a single recv WQE */ 757 u16 max_wr_recv_sges; 758 759 /* The maximum number of memory regions supported */ 760 u32 max_mr; 761 762 /* The maximum number of pages can be registered */ 763 u32 max_mr_pages; 764 765 /* The maximum number of protection domains supported */ 766 u32 max_pd; 767 768 /* The maximum number of address handles supported */ 769 u32 max_ah; 770 771 /* The maximum size of LLQ in bytes */ 772 u32 max_llq_size; 773 774 /* Maximum number of SGEs for a single RDMA read/write WQE */ 775 u16 max_wr_rdma_sges; 776 777 /* 778 * Maximum number of bytes that can be written to SQ between two 779 * consecutive doorbells (in units of 64B). Driver must ensure that only 780 * complete WQEs are written to queue before issuing a doorbell. 781 * Examples: max_tx_batch=16 and WQE size = 64B, means up to 16 WQEs can 782 * be written to SQ between two consecutive doorbells. max_tx_batch=11 783 * and WQE size = 128B, means up to 5 WQEs can be written to SQ between 784 * two consecutive doorbells. Zero means unlimited. 785 */ 786 u16 max_tx_batch; 787 }; 788 789 struct efa_admin_feature_queue_attr_desc_2 { 790 /* Maximum size of data that can be sent inline in a Send WQE */ 791 u16 inline_buf_size_ex; 792 793 /* MBZ */ 794 u8 reserved[6]; 795 796 /* 797 * Supported counter QP events 798 * 0 : send_comp 799 * 1 : send_comp_err 800 * 2 : recv_comp 801 * 3 : recv_comp_err 802 * 4 : read_comp 803 * 5 : read_comp_err 804 * 6 : write_comp 805 * 7 : write_comp_err 806 * 8 : remote_read_comp 807 * 9 : remote_write_comp 808 * 31:10 : reserved - MBZ 809 */ 810 u32 supported_event_counter_qp_events; 811 812 /* Maximum number of counters */ 813 u32 max_event_counters; 814 815 /* 816 * Maximum counter value, counter wraps around to 0 after reaching 817 * this value 818 */ 819 u64 event_counter_max_val; 820 }; 821 822 struct efa_admin_event_queue_attr_desc { 823 /* The maximum number of event queues supported */ 824 u32 max_eq; 825 826 /* Maximum number of EQEs per Event Queue */ 827 u32 max_eq_depth; 828 829 /* Supported events bitmask */ 830 u32 event_bitmask; 831 }; 832 833 struct efa_admin_feature_aenq_desc { 834 /* bitmask for AENQ groups the device can report */ 835 u32 supported_groups; 836 837 /* bitmask for AENQ groups to report */ 838 u32 enabled_groups; 839 }; 840 841 struct efa_admin_feature_network_attr_desc { 842 /* Raw address data in network byte order */ 843 u8 addr[16]; 844 845 /* max packet payload size in bytes */ 846 u32 mtu; 847 }; 848 849 /* 850 * When hint value is 0, hints capabilities are not supported or driver 851 * should use its own predefined value 852 */ 853 struct efa_admin_hw_hints { 854 /* value in ms */ 855 u16 mmio_read_timeout; 856 857 /* value in ms */ 858 u16 driver_watchdog_timeout; 859 860 /* value in ms */ 861 u16 admin_completion_timeout; 862 863 /* poll interval in ms */ 864 u16 poll_interval; 865 }; 866 867 struct efa_admin_get_feature_cmd { 868 struct efa_admin_ctrl_buff_info control_buffer; 869 870 struct efa_admin_get_set_feature_common_desc feature_common; 871 872 u32 raw[11]; 873 } __packed; 874 875 struct efa_admin_get_feature_resp { 876 struct efa_admin_acq_common_desc acq_common_desc; 877 878 union { 879 u32 raw[14]; 880 881 struct efa_admin_feature_device_attr_desc device_attr; 882 883 struct efa_admin_feature_aenq_desc aenq; 884 885 struct efa_admin_feature_network_attr_desc network_attr; 886 887 struct efa_admin_feature_queue_attr_desc_1 queue_attr_1; 888 889 struct efa_admin_feature_queue_attr_desc_2 queue_attr_2; 890 891 struct efa_admin_event_queue_attr_desc event_queue_attr; 892 893 struct efa_admin_hw_hints hw_hints; 894 } u; 895 }; 896 897 struct efa_admin_set_feature_cmd { 898 struct efa_admin_ctrl_buff_info control_buffer; 899 900 struct efa_admin_get_set_feature_common_desc feature_common; 901 902 union { 903 u32 raw[11]; 904 905 /* AENQ configuration */ 906 struct efa_admin_feature_aenq_desc aenq; 907 } u; 908 } __packed; 909 910 struct efa_admin_set_feature_resp { 911 struct efa_admin_acq_common_desc acq_common_desc; 912 913 union { 914 u32 raw[14]; 915 } u; 916 }; 917 918 struct efa_admin_alloc_pd_resp { 919 struct efa_admin_acq_common_desc acq_common_desc; 920 921 /* PD number */ 922 u16 pd; 923 924 /* MBZ */ 925 u16 reserved; 926 }; 927 928 struct efa_admin_dealloc_pd_cmd { 929 /* PD number */ 930 u16 pd; 931 932 /* MBZ */ 933 u16 reserved; 934 } __packed; 935 936 struct efa_admin_dealloc_pd_resp { 937 struct efa_admin_acq_common_desc acq_common_desc; 938 }; 939 940 struct efa_admin_alloc_uar_resp { 941 struct efa_admin_acq_common_desc acq_common_desc; 942 943 /* UAR number */ 944 u16 uar; 945 946 /* MBZ */ 947 u16 reserved; 948 }; 949 950 struct efa_admin_dealloc_uar_cmd { 951 /* UAR number */ 952 u16 uar; 953 954 /* MBZ */ 955 u16 reserved; 956 } __packed; 957 958 struct efa_admin_dealloc_uar_resp { 959 struct efa_admin_acq_common_desc acq_common_desc; 960 }; 961 962 struct efa_admin_create_eq_cmd { 963 /* Size of the EQ in entries, must be power of 2 */ 964 u16 depth; 965 966 /* MSI-X table entry index */ 967 u8 msix_vec; 968 969 /* 970 * 4:0 : entry_size_words - size of EQ entry in 971 * 32-bit words 972 * 7:5 : reserved - MBZ 973 */ 974 u8 caps; 975 976 /* EQ ring base address */ 977 struct efa_common_mem_addr ba; 978 979 /* 980 * Enabled events on this EQ 981 * 0 : completion_events - Enable completion events 982 * 31:1 : reserved - MBZ 983 */ 984 u32 event_bitmask; 985 986 /* MBZ */ 987 u32 reserved; 988 } __packed; 989 990 struct efa_admin_create_eq_resp { 991 struct efa_admin_acq_common_desc acq_common_desc; 992 993 /* EQ number */ 994 u16 eqn; 995 996 /* MBZ */ 997 u16 reserved; 998 }; 999 1000 struct efa_admin_destroy_eq_cmd { 1001 /* EQ number */ 1002 u16 eqn; 1003 1004 /* MBZ */ 1005 u16 reserved; 1006 } __packed; 1007 1008 struct efa_admin_destroy_eq_resp { 1009 struct efa_admin_acq_common_desc acq_common_desc; 1010 }; 1011 1012 /* asynchronous event notification groups */ 1013 enum efa_admin_aenq_group { 1014 EFA_ADMIN_FATAL_ERROR = 1, 1015 EFA_ADMIN_WARNING = 2, 1016 EFA_ADMIN_NOTIFICATION = 3, 1017 EFA_ADMIN_KEEP_ALIVE = 4, 1018 EFA_ADMIN_AENQ_GROUPS_NUM = 5, 1019 }; 1020 1021 struct efa_admin_mmio_req_read_less_resp { 1022 u16 req_id; 1023 1024 u16 reg_off; 1025 1026 /* value is valid when poll is cleared */ 1027 u32 reg_val; 1028 }; 1029 1030 enum efa_admin_os_type { 1031 EFA_ADMIN_OS_LINUX = 0, 1032 }; 1033 1034 struct efa_admin_host_info { 1035 /* OS distribution string format */ 1036 u8 os_dist_str[128]; 1037 1038 /* Defined in enum efa_admin_os_type */ 1039 u32 os_type; 1040 1041 /* Kernel version string format */ 1042 u8 kernel_ver_str[32]; 1043 1044 /* Kernel version numeric format */ 1045 u32 kernel_ver; 1046 1047 /* 1048 * 7:0 : driver_module_type 1049 * 15:8 : driver_sub_minor 1050 * 23:16 : driver_minor 1051 * 31:24 : driver_major 1052 */ 1053 u32 driver_ver; 1054 1055 /* 1056 * Device's Bus, Device and Function 1057 * 2:0 : function 1058 * 7:3 : device 1059 * 15:8 : bus 1060 */ 1061 u16 bdf; 1062 1063 /* 1064 * Spec version 1065 * 7:0 : spec_minor 1066 * 15:8 : spec_major 1067 */ 1068 u16 spec_ver; 1069 1070 /* 1071 * 0 : intree - Intree driver 1072 * 1 : gdr - GPUDirect RDMA supported 1073 * 31:2 : reserved2 1074 */ 1075 u32 flags; 1076 }; 1077 1078 struct efa_admin_service_cmd { 1079 u8 buffer[60]; 1080 } __packed; 1081 1082 struct efa_admin_service_resp { 1083 struct efa_admin_acq_common_desc acq_common_desc; 1084 1085 u8 buffer[56]; 1086 }; 1087 1088 /* Create Counter command */ 1089 struct efa_admin_create_event_counter_cmd { 1090 /* UAR number */ 1091 u16 uar; 1092 1093 /* MBZ */ 1094 u16 reserved; 1095 1096 /* Counter physical address */ 1097 u64 paddr; 1098 } __packed; 1099 1100 struct efa_admin_create_event_counter_resp { 1101 struct efa_admin_acq_common_desc acq_common_desc; 1102 1103 /* Counter handle */ 1104 u32 cntr_handle; 1105 1106 /* MBZ */ 1107 u32 reserved; 1108 }; 1109 1110 struct efa_admin_destroy_event_counter_cmd { 1111 /* Counter handle */ 1112 u32 cntr_handle; 1113 } __packed; 1114 1115 struct efa_admin_destroy_event_counter_resp { 1116 struct efa_admin_acq_common_desc acq_common_desc; 1117 }; 1118 1119 enum efa_admin_event_counter_attach_type { 1120 EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS = 0, 1121 }; 1122 1123 struct efa_admin_event_counter_attach_qp_events { 1124 /* QP handle */ 1125 u32 qp_handle; 1126 1127 /* 1128 * Bitmask of counter QP events 1129 * 0 : send_comp 1130 * 1 : send_comp_err 1131 * 2 : recv_comp 1132 * 3 : recv_comp_err 1133 * 4 : read_comp 1134 * 5 : read_comp_err 1135 * 6 : write_comp 1136 * 7 : write_comp_err 1137 * 8 : remote_read_comp 1138 * 9 : remote_write_comp 1139 * 31:10 : reserved - MBZ 1140 */ 1141 u32 events; 1142 }; 1143 1144 struct efa_admin_attach_detach_event_counter_cmd { 1145 /* Counter handle */ 1146 u32 cntr_handle; 1147 1148 /* efa_admin_event_counter_attach_type */ 1149 u8 attach_type; 1150 1151 /* MBZ */ 1152 u8 reserved[3]; 1153 1154 union { 1155 struct efa_admin_event_counter_attach_qp_events qp_events; 1156 } u; 1157 } __packed; 1158 1159 struct efa_admin_attach_detach_event_counter_resp { 1160 struct efa_admin_acq_common_desc acq_common_desc; 1161 }; 1162 1163 /* Counter modify operations */ 1164 enum efa_admin_event_counter_modify_ops { 1165 /* Set counter value */ 1166 EFA_ADMIN_EVENT_COUNTER_MODIFY_SET = 0, 1167 /* Add to counter value */ 1168 EFA_ADMIN_EVENT_COUNTER_MODIFY_ADD = 1, 1169 }; 1170 1171 struct efa_admin_modify_event_counter_cmd { 1172 /* Counter handle */ 1173 u32 cntr_handle; 1174 1175 /* Counter operation type (efa_admin_event_counter_modify_ops) */ 1176 u8 operation; 1177 1178 /* MBZ */ 1179 u8 reserved[7]; 1180 1181 /* Value for SET or ADD */ 1182 u64 value; 1183 } __packed; 1184 1185 struct efa_admin_modify_event_counter_resp { 1186 struct efa_admin_acq_common_desc acq_common_desc; 1187 }; 1188 1189 /* create_qp_cmd */ 1190 #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0) 1191 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1) 1192 #define EFA_ADMIN_CREATE_QP_CMD_UNSOLICITED_WRITE_RECV_MASK BIT(2) 1193 #define EFA_ADMIN_CREATE_QP_CMD_SQ_64_BIT_REQ_ID_SHIFT 3 1194 #define EFA_ADMIN_CREATE_QP_CMD_SQ_64_BIT_REQ_ID_MASK BIT(3) 1195 1196 /* modify_qp_cmd */ 1197 #define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK BIT(0) 1198 #define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK BIT(1) 1199 #define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK BIT(2) 1200 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK BIT(3) 1201 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4) 1202 #define EFA_ADMIN_MODIFY_QP_CMD_RNR_RETRY_MASK BIT(5) 1203 1204 /* reg_mr_cmd */ 1205 #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(5, 0) 1206 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7) 1207 #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0) 1208 #define EFA_ADMIN_REG_MR_CMD_REMOTE_WRITE_ENABLE_MASK BIT(1) 1209 #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2) 1210 1211 /* reg_mr_resp */ 1212 #define EFA_ADMIN_REG_MR_RESP_RECV_IC_ID_MASK BIT(0) 1213 #define EFA_ADMIN_REG_MR_RESP_RDMA_READ_IC_ID_MASK BIT(1) 1214 #define EFA_ADMIN_REG_MR_RESP_RDMA_RECV_IC_ID_MASK BIT(2) 1215 1216 /* create_cq_cmd */ 1217 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1218 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6) 1219 #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1220 #define EFA_ADMIN_CREATE_CQ_CMD_SET_SRC_ADDR_MASK BIT(5) 1221 #define EFA_ADMIN_CREATE_CQ_CMD_SQ_COMP_64_BIT_REQ_ID_SHIFT 6 1222 #define EFA_ADMIN_CREATE_CQ_CMD_SQ_COMP_64_BIT_REQ_ID_MASK BIT(6) 1223 1224 /* create_cq_resp */ 1225 #define EFA_ADMIN_CREATE_CQ_RESP_DB_VALID_MASK BIT(0) 1226 1227 /* feature_device_attr_desc */ 1228 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0) 1229 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RNR_RETRY_MASK BIT(1) 1230 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_DATA_POLLING_128_MASK BIT(2) 1231 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_WRITE_MASK BIT(3) 1232 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_UNSOLICITED_WRITE_RECV_MASK BIT(4) 1233 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_EVENT_COUNTERS_MASK BIT(5) 1234 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_SQ_64_BIT_REQ_ID_SHIFT 10 1235 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_SQ_64_BIT_REQ_ID_MASK BIT(10) 1236 1237 /* feature_queue_attr_desc_2 */ 1238 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_SEND_COMP_MASK BIT(0) 1239 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_SEND_COMP_ERR_MASK BIT(1) 1240 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_RECV_COMP_MASK BIT(2) 1241 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_RECV_COMP_ERR_MASK BIT(3) 1242 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_READ_COMP_MASK BIT(4) 1243 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_READ_COMP_ERR_MASK BIT(5) 1244 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_WRITE_COMP_MASK BIT(6) 1245 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_WRITE_COMP_ERR_MASK BIT(7) 1246 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_REMOTE_READ_COMP_MASK BIT(8) 1247 #define EFA_ADMIN_FEATURE_QUEUE_ATTR_DESC_2_REMOTE_WRITE_COMP_MASK BIT(9) 1248 1249 /* create_eq_cmd */ 1250 #define EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1251 #define EFA_ADMIN_CREATE_EQ_CMD_COMPLETION_EVENTS_MASK BIT(0) 1252 1253 /* host_info */ 1254 #define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0) 1255 #define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8) 1256 #define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16) 1257 #define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24) 1258 #define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1259 #define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1260 #define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1261 #define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0) 1262 #define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8) 1263 #define EFA_ADMIN_HOST_INFO_INTREE_MASK BIT(0) 1264 #define EFA_ADMIN_HOST_INFO_GDR_MASK BIT(1) 1265 1266 /* counter_attach_qp_events */ 1267 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_SEND_COMP_MASK BIT(0) 1268 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_SEND_COMP_ERR_MASK BIT(1) 1269 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_RECV_COMP_MASK BIT(2) 1270 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_RECV_COMP_ERR_MASK BIT(3) 1271 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_READ_COMP_MASK BIT(4) 1272 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_READ_COMP_ERR_MASK BIT(5) 1273 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_WRITE_COMP_MASK BIT(6) 1274 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_WRITE_COMP_ERR_MASK BIT(7) 1275 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_REMOTE_READ_COMP_MASK BIT(8) 1276 #define EFA_ADMIN_EVENT_COUNTER_ATTACH_QP_EVENTS_REMOTE_WRITE_COMP_MASK BIT(9) 1277 1278 #endif /* _EFA_ADMIN_CMDS_H_ */ 1279