1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __T4_H__ 32 #define __T4_H__ 33 34 #include "t4_hw.h" 35 #include "t4_regs.h" 36 #include "t4_values.h" 37 #include "t4_msg.h" 38 #include "t4fw_ri_api.h" 39 40 #define T4_MAX_NUM_PD 65536 41 #define T4_MAX_MR_SIZE (~0ULL) 42 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ 43 #define T4_STAG_UNSET 0xffffffff 44 #define T4_FW_MAJ 0 45 #define PCIE_MA_SYNC_A 0x30b4 46 47 struct t4_status_page { 48 __be32 rsvd1; /* flit 0 - hw owns */ 49 __be16 rsvd2; 50 __be16 qid; 51 __be16 cidx; 52 __be16 pidx; 53 u8 qp_err; /* flit 1 - sw owns */ 54 u8 db_off; 55 u8 pad; 56 u16 host_wq_pidx; 57 u16 host_cidx; 58 u16 host_pidx; 59 }; 60 61 #define T4_EQ_ENTRY_SIZE 64 62 63 #define T4_SQ_NUM_SLOTS 5 64 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 65 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 66 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 67 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 68 sizeof(struct fw_ri_immd))) 69 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 70 sizeof(struct fw_ri_rdma_write_wr) - \ 71 sizeof(struct fw_ri_immd))) 72 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 73 sizeof(struct fw_ri_rdma_write_wr) - \ 74 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 75 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 76 sizeof(struct fw_ri_immd)) & ~31UL) 77 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 78 #define T4_MAX_FR_DSGL 1024 79 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) 80 81 static inline int t4_max_fr_depth(int use_dsgl) 82 { 83 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH; 84 } 85 86 #define T4_RQ_NUM_SLOTS 2 87 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 88 #define T4_MAX_RECV_SGE 4 89 90 union t4_wr { 91 struct fw_ri_res_wr res; 92 struct fw_ri_wr ri; 93 struct fw_ri_rdma_write_wr write; 94 struct fw_ri_send_wr send; 95 struct fw_ri_rdma_read_wr read; 96 struct fw_ri_bind_mw_wr bind; 97 struct fw_ri_fr_nsmr_wr fr; 98 struct fw_ri_inv_lstag_wr inv; 99 struct t4_status_page status; 100 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 101 }; 102 103 union t4_recv_wr { 104 struct fw_ri_recv_wr recv; 105 struct t4_status_page status; 106 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 107 }; 108 109 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 110 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 111 { 112 wqe->send.opcode = (u8)opcode; 113 wqe->send.flags = flags; 114 wqe->send.wrid = wrid; 115 wqe->send.r1[0] = 0; 116 wqe->send.r1[1] = 0; 117 wqe->send.r1[2] = 0; 118 wqe->send.len16 = len16; 119 } 120 121 /* CQE/AE status codes */ 122 #define T4_ERR_SUCCESS 0x0 123 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 124 /* STAG is offlimt, being 0, */ 125 /* or STAG_key mismatch */ 126 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 127 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 128 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 129 #define T4_ERR_WRAP 0x5 /* Wrap error */ 130 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 131 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 132 /* shared memory region */ 133 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 134 /* shared memory region */ 135 #define T4_ERR_ECC 0x9 /* ECC error detected */ 136 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 137 /* reading PSTAG for a MW */ 138 /* Invalidate */ 139 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 140 /* software error */ 141 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 142 #define T4_ERR_CRC 0x10 /* CRC error */ 143 #define T4_ERR_MARKER 0x11 /* Marker error */ 144 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 145 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 146 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 147 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 148 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 149 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 150 #define T4_ERR_MSN 0x18 /* MSN error */ 151 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 152 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 153 /* or READ_REQ */ 154 #define T4_ERR_MSN_GAP 0x1B 155 #define T4_ERR_MSN_RANGE 0x1C 156 #define T4_ERR_IRD_OVERFLOW 0x1D 157 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 158 /* software error */ 159 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 160 /* mismatch) */ 161 /* 162 * CQE defs 163 */ 164 struct t4_cqe { 165 __be32 header; 166 __be32 len; 167 union { 168 struct { 169 __be32 stag; 170 __be32 msn; 171 } rcqe; 172 struct { 173 u32 nada1; 174 u16 nada2; 175 u16 cidx; 176 } scqe; 177 struct { 178 __be32 wrid_hi; 179 __be32 wrid_low; 180 } gen; 181 } u; 182 __be64 reserved; 183 __be64 bits_type_ts; 184 }; 185 186 /* macros for flit 0 of the cqe */ 187 188 #define CQE_QPID_S 12 189 #define CQE_QPID_M 0xFFFFF 190 #define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M) 191 #define CQE_QPID_V(x) ((x)<<CQE_QPID_S) 192 193 #define CQE_SWCQE_S 11 194 #define CQE_SWCQE_M 0x1 195 #define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M) 196 #define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S) 197 198 #define CQE_STATUS_S 5 199 #define CQE_STATUS_M 0x1F 200 #define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M) 201 #define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S) 202 203 #define CQE_TYPE_S 4 204 #define CQE_TYPE_M 0x1 205 #define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M) 206 #define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S) 207 208 #define CQE_OPCODE_S 0 209 #define CQE_OPCODE_M 0xF 210 #define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M) 211 #define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S) 212 213 #define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header))) 214 #define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header))) 215 #define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header))) 216 #define SQ_TYPE(x) (CQE_TYPE((x))) 217 #define RQ_TYPE(x) (!CQE_TYPE((x))) 218 #define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header))) 219 #define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header))) 220 221 #define CQE_SEND_OPCODE(x)( \ 222 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 223 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 224 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 225 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 226 227 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 228 229 /* used for RQ completion processing */ 230 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 231 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 232 233 /* used for SQ completion processing */ 234 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 235 236 /* generic accessor macros */ 237 #define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi)) 238 #define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low)) 239 240 /* macros for flit 3 of the cqe */ 241 #define CQE_GENBIT_S 63 242 #define CQE_GENBIT_M 0x1 243 #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M) 244 #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S) 245 246 #define CQE_OVFBIT_S 62 247 #define CQE_OVFBIT_M 0x1 248 #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M) 249 250 #define CQE_IQTYPE_S 60 251 #define CQE_IQTYPE_M 0x3 252 #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M) 253 254 #define CQE_TS_M 0x0fffffffffffffffULL 255 #define CQE_TS_G(x) ((x) & CQE_TS_M) 256 257 #define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts))) 258 #define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts))) 259 #define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts))) 260 261 struct t4_swsqe { 262 u64 wr_id; 263 struct t4_cqe cqe; 264 int read_len; 265 int opcode; 266 int complete; 267 int signaled; 268 u16 idx; 269 int flushed; 270 struct timespec host_ts; 271 u64 sge_ts; 272 }; 273 274 static inline pgprot_t t4_pgprot_wc(pgprot_t prot) 275 { 276 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 277 return pgprot_writecombine(prot); 278 #else 279 return pgprot_noncached(prot); 280 #endif 281 } 282 283 enum { 284 T4_SQ_ONCHIP = (1<<0), 285 }; 286 287 struct t4_sq { 288 union t4_wr *queue; 289 dma_addr_t dma_addr; 290 DEFINE_DMA_UNMAP_ADDR(mapping); 291 unsigned long phys_addr; 292 struct t4_swsqe *sw_sq; 293 struct t4_swsqe *oldest_read; 294 void __iomem *bar2_va; 295 u64 bar2_pa; 296 size_t memsize; 297 u32 bar2_qid; 298 u32 qid; 299 u16 in_use; 300 u16 size; 301 u16 cidx; 302 u16 pidx; 303 u16 wq_pidx; 304 u16 wq_pidx_inc; 305 u16 flags; 306 short flush_cidx; 307 }; 308 309 struct t4_swrqe { 310 u64 wr_id; 311 struct timespec host_ts; 312 u64 sge_ts; 313 }; 314 315 struct t4_rq { 316 union t4_recv_wr *queue; 317 dma_addr_t dma_addr; 318 DEFINE_DMA_UNMAP_ADDR(mapping); 319 struct t4_swrqe *sw_rq; 320 void __iomem *bar2_va; 321 u64 bar2_pa; 322 size_t memsize; 323 u32 bar2_qid; 324 u32 qid; 325 u32 msn; 326 u32 rqt_hwaddr; 327 u16 rqt_size; 328 u16 in_use; 329 u16 size; 330 u16 cidx; 331 u16 pidx; 332 u16 wq_pidx; 333 u16 wq_pidx_inc; 334 }; 335 336 struct t4_wq { 337 struct t4_sq sq; 338 struct t4_rq rq; 339 void __iomem *db; 340 struct c4iw_rdev *rdev; 341 int flushed; 342 }; 343 344 static inline int t4_rqes_posted(struct t4_wq *wq) 345 { 346 return wq->rq.in_use; 347 } 348 349 static inline int t4_rq_empty(struct t4_wq *wq) 350 { 351 return wq->rq.in_use == 0; 352 } 353 354 static inline int t4_rq_full(struct t4_wq *wq) 355 { 356 return wq->rq.in_use == (wq->rq.size - 1); 357 } 358 359 static inline u32 t4_rq_avail(struct t4_wq *wq) 360 { 361 return wq->rq.size - 1 - wq->rq.in_use; 362 } 363 364 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 365 { 366 wq->rq.in_use++; 367 if (++wq->rq.pidx == wq->rq.size) 368 wq->rq.pidx = 0; 369 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 370 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 371 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 372 } 373 374 static inline void t4_rq_consume(struct t4_wq *wq) 375 { 376 wq->rq.in_use--; 377 wq->rq.msn++; 378 if (++wq->rq.cidx == wq->rq.size) 379 wq->rq.cidx = 0; 380 } 381 382 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 383 { 384 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 385 } 386 387 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 388 { 389 return wq->rq.size * T4_RQ_NUM_SLOTS; 390 } 391 392 static inline int t4_sq_onchip(struct t4_sq *sq) 393 { 394 return sq->flags & T4_SQ_ONCHIP; 395 } 396 397 static inline int t4_sq_empty(struct t4_wq *wq) 398 { 399 return wq->sq.in_use == 0; 400 } 401 402 static inline int t4_sq_full(struct t4_wq *wq) 403 { 404 return wq->sq.in_use == (wq->sq.size - 1); 405 } 406 407 static inline u32 t4_sq_avail(struct t4_wq *wq) 408 { 409 return wq->sq.size - 1 - wq->sq.in_use; 410 } 411 412 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 413 { 414 wq->sq.in_use++; 415 if (++wq->sq.pidx == wq->sq.size) 416 wq->sq.pidx = 0; 417 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 418 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 419 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 420 } 421 422 static inline void t4_sq_consume(struct t4_wq *wq) 423 { 424 BUG_ON(wq->sq.in_use < 1); 425 if (wq->sq.cidx == wq->sq.flush_cidx) 426 wq->sq.flush_cidx = -1; 427 wq->sq.in_use--; 428 if (++wq->sq.cidx == wq->sq.size) 429 wq->sq.cidx = 0; 430 } 431 432 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 433 { 434 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 435 } 436 437 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 438 { 439 return wq->sq.size * T4_SQ_NUM_SLOTS; 440 } 441 442 /* This function copies 64 byte coalesced work request to memory 443 * mapped BAR2 space. For coalesced WRs, the SGE fetches data 444 * from the FIFO instead of from Host. 445 */ 446 static inline void pio_copy(u64 __iomem *dst, u64 *src) 447 { 448 int count = 8; 449 450 while (count) { 451 writeq(*src, dst); 452 src++; 453 dst++; 454 count--; 455 } 456 } 457 458 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, 459 union t4_wr *wqe) 460 { 461 462 /* Flush host queue memory writes. */ 463 wmb(); 464 if (wq->sq.bar2_va) { 465 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) { 466 PDBG("%s: WC wq->sq.pidx = %d\n", 467 __func__, wq->sq.pidx); 468 pio_copy((u64 __iomem *) 469 (wq->sq.bar2_va + SGE_UDB_WCDOORBELL), 470 (u64 *)wqe); 471 } else { 472 PDBG("%s: DB wq->sq.pidx = %d\n", 473 __func__, wq->sq.pidx); 474 writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid), 475 wq->sq.bar2_va + SGE_UDB_KDOORBELL); 476 } 477 478 /* Flush user doorbell area writes. */ 479 wmb(); 480 return; 481 } 482 writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db); 483 } 484 485 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, 486 union t4_recv_wr *wqe) 487 { 488 489 /* Flush host queue memory writes. */ 490 wmb(); 491 if (wq->rq.bar2_va) { 492 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) { 493 PDBG("%s: WC wq->rq.pidx = %d\n", 494 __func__, wq->rq.pidx); 495 pio_copy((u64 __iomem *) 496 (wq->rq.bar2_va + SGE_UDB_WCDOORBELL), 497 (void *)wqe); 498 } else { 499 PDBG("%s: DB wq->rq.pidx = %d\n", 500 __func__, wq->rq.pidx); 501 writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid), 502 wq->rq.bar2_va + SGE_UDB_KDOORBELL); 503 } 504 505 /* Flush user doorbell area writes. */ 506 wmb(); 507 return; 508 } 509 writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db); 510 } 511 512 static inline int t4_wq_in_error(struct t4_wq *wq) 513 { 514 return wq->rq.queue[wq->rq.size].status.qp_err; 515 } 516 517 static inline void t4_set_wq_in_error(struct t4_wq *wq) 518 { 519 wq->rq.queue[wq->rq.size].status.qp_err = 1; 520 } 521 522 static inline void t4_disable_wq_db(struct t4_wq *wq) 523 { 524 wq->rq.queue[wq->rq.size].status.db_off = 1; 525 } 526 527 static inline void t4_enable_wq_db(struct t4_wq *wq) 528 { 529 wq->rq.queue[wq->rq.size].status.db_off = 0; 530 } 531 532 static inline int t4_wq_db_enabled(struct t4_wq *wq) 533 { 534 return !wq->rq.queue[wq->rq.size].status.db_off; 535 } 536 537 enum t4_cq_flags { 538 CQ_ARMED = 1, 539 }; 540 541 struct t4_cq { 542 struct t4_cqe *queue; 543 dma_addr_t dma_addr; 544 DEFINE_DMA_UNMAP_ADDR(mapping); 545 struct t4_cqe *sw_queue; 546 void __iomem *gts; 547 void __iomem *bar2_va; 548 u64 bar2_pa; 549 u32 bar2_qid; 550 struct c4iw_rdev *rdev; 551 size_t memsize; 552 __be64 bits_type_ts; 553 u32 cqid; 554 u32 qid_mask; 555 int vector; 556 u16 size; /* including status page */ 557 u16 cidx; 558 u16 sw_pidx; 559 u16 sw_cidx; 560 u16 sw_in_use; 561 u16 cidx_inc; 562 u8 gen; 563 u8 error; 564 unsigned long flags; 565 }; 566 567 static inline void write_gts(struct t4_cq *cq, u32 val) 568 { 569 if (cq->bar2_va) 570 writel(val | INGRESSQID_V(cq->bar2_qid), 571 cq->bar2_va + SGE_UDB_GTS); 572 else 573 writel(val | INGRESSQID_V(cq->cqid), cq->gts); 574 } 575 576 static inline int t4_clear_cq_armed(struct t4_cq *cq) 577 { 578 return test_and_clear_bit(CQ_ARMED, &cq->flags); 579 } 580 581 static inline int t4_arm_cq(struct t4_cq *cq, int se) 582 { 583 u32 val; 584 585 set_bit(CQ_ARMED, &cq->flags); 586 while (cq->cidx_inc > CIDXINC_M) { 587 val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7); 588 write_gts(cq, val); 589 cq->cidx_inc -= CIDXINC_M; 590 } 591 val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6); 592 write_gts(cq, val); 593 cq->cidx_inc = 0; 594 return 0; 595 } 596 597 static inline void t4_swcq_produce(struct t4_cq *cq) 598 { 599 cq->sw_in_use++; 600 if (cq->sw_in_use == cq->size) { 601 PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid); 602 cq->error = 1; 603 BUG_ON(1); 604 } 605 if (++cq->sw_pidx == cq->size) 606 cq->sw_pidx = 0; 607 } 608 609 static inline void t4_swcq_consume(struct t4_cq *cq) 610 { 611 BUG_ON(cq->sw_in_use < 1); 612 cq->sw_in_use--; 613 if (++cq->sw_cidx == cq->size) 614 cq->sw_cidx = 0; 615 } 616 617 static inline void t4_hwcq_consume(struct t4_cq *cq) 618 { 619 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 620 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) { 621 u32 val; 622 623 val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7); 624 write_gts(cq, val); 625 cq->cidx_inc = 0; 626 } 627 if (++cq->cidx == cq->size) { 628 cq->cidx = 0; 629 cq->gen ^= 1; 630 } 631 } 632 633 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 634 { 635 return (CQE_GENBIT(cqe) == cq->gen); 636 } 637 638 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 639 { 640 int ret; 641 u16 prev_cidx; 642 643 if (cq->cidx == 0) 644 prev_cidx = cq->size - 1; 645 else 646 prev_cidx = cq->cidx - 1; 647 648 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 649 ret = -EOVERFLOW; 650 cq->error = 1; 651 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 652 BUG_ON(1); 653 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 654 655 /* Ensure CQE is flushed to memory */ 656 rmb(); 657 *cqe = &cq->queue[cq->cidx]; 658 ret = 0; 659 } else 660 ret = -ENODATA; 661 return ret; 662 } 663 664 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 665 { 666 if (cq->sw_in_use == cq->size) { 667 PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid); 668 cq->error = 1; 669 BUG_ON(1); 670 return NULL; 671 } 672 if (cq->sw_in_use) 673 return &cq->sw_queue[cq->sw_cidx]; 674 return NULL; 675 } 676 677 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 678 { 679 int ret = 0; 680 681 if (cq->error) 682 ret = -ENODATA; 683 else if (cq->sw_in_use) 684 *cqe = &cq->sw_queue[cq->sw_cidx]; 685 else 686 ret = t4_next_hw_cqe(cq, cqe); 687 return ret; 688 } 689 690 static inline int t4_cq_in_error(struct t4_cq *cq) 691 { 692 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 693 } 694 695 static inline void t4_set_cq_in_error(struct t4_cq *cq) 696 { 697 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 698 } 699 #endif 700 701 struct t4_dev_status_page { 702 u8 db_off; 703 }; 704