1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 35 #include "iw_cxgb4.h" 36 37 static int db_delay_usecs = 1; 38 module_param(db_delay_usecs, int, 0644); 39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain"); 40 41 static int ocqp_support = 1; 42 module_param(ocqp_support, int, 0644); 43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)"); 44 45 int db_fc_threshold = 1000; 46 module_param(db_fc_threshold, int, 0644); 47 MODULE_PARM_DESC(db_fc_threshold, 48 "QP count/threshold that triggers" 49 " automatic db flow control mode (default = 1000)"); 50 51 int db_coalescing_threshold; 52 module_param(db_coalescing_threshold, int, 0644); 53 MODULE_PARM_DESC(db_coalescing_threshold, 54 "QP count/threshold that triggers" 55 " disabling db coalescing (default = 0)"); 56 57 static int max_fr_immd = T4_MAX_FR_IMMD; 58 module_param(max_fr_immd, int, 0644); 59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate"); 60 61 static int alloc_ird(struct c4iw_dev *dev, u32 ird) 62 { 63 int ret = 0; 64 65 spin_lock_irq(&dev->lock); 66 if (ird <= dev->avail_ird) 67 dev->avail_ird -= ird; 68 else 69 ret = -ENOMEM; 70 spin_unlock_irq(&dev->lock); 71 72 if (ret) 73 dev_warn(&dev->rdev.lldi.pdev->dev, 74 "device IRD resources exhausted\n"); 75 76 return ret; 77 } 78 79 static void free_ird(struct c4iw_dev *dev, int ird) 80 { 81 spin_lock_irq(&dev->lock); 82 dev->avail_ird += ird; 83 spin_unlock_irq(&dev->lock); 84 } 85 86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 87 { 88 unsigned long flag; 89 spin_lock_irqsave(&qhp->lock, flag); 90 qhp->attr.state = state; 91 spin_unlock_irqrestore(&qhp->lock, flag); 92 } 93 94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 95 { 96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize); 97 } 98 99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 100 { 101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue, 102 pci_unmap_addr(sq, mapping)); 103 } 104 105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 106 { 107 if (t4_sq_onchip(sq)) 108 dealloc_oc_sq(rdev, sq); 109 else 110 dealloc_host_sq(rdev, sq); 111 } 112 113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 114 { 115 if (!ocqp_support || !ocqp_supported(&rdev->lldi)) 116 return -ENOSYS; 117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); 118 if (!sq->dma_addr) 119 return -ENOMEM; 120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr - 121 rdev->lldi.vr->ocq.start; 122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr - 123 rdev->lldi.vr->ocq.start); 124 sq->flags |= T4_SQ_ONCHIP; 125 return 0; 126 } 127 128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 129 { 130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize, 131 &(sq->dma_addr), GFP_KERNEL); 132 if (!sq->queue) 133 return -ENOMEM; 134 sq->phys_addr = virt_to_phys(sq->queue); 135 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 136 return 0; 137 } 138 139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user) 140 { 141 int ret = -ENOSYS; 142 if (user) 143 ret = alloc_oc_sq(rdev, sq); 144 if (ret) 145 ret = alloc_host_sq(rdev, sq); 146 return ret; 147 } 148 149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 150 struct c4iw_dev_ucontext *uctx) 151 { 152 /* 153 * uP clears EQ contexts when the connection exits rdma mode, 154 * so no need to post a RESET WR for these EQs. 155 */ 156 dma_free_coherent(&(rdev->lldi.pdev->dev), 157 wq->rq.memsize, wq->rq.queue, 158 dma_unmap_addr(&wq->rq, mapping)); 159 dealloc_sq(rdev, &wq->sq); 160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 161 kfree(wq->rq.sw_rq); 162 kfree(wq->sq.sw_sq); 163 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 164 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 165 return 0; 166 } 167 168 /* 169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL, 170 * then this is a user mapping so compute the page-aligned physical address 171 * for mapping. 172 */ 173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid, 174 enum cxgb4_bar2_qtype qtype, 175 unsigned int *pbar2_qid, u64 *pbar2_pa) 176 { 177 u64 bar2_qoffset; 178 int ret; 179 180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype, 181 pbar2_pa ? 1 : 0, 182 &bar2_qoffset, pbar2_qid); 183 if (ret) 184 return NULL; 185 186 if (pbar2_pa) 187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK; 188 189 if (is_t4(rdev->lldi.adapter_type)) 190 return NULL; 191 192 return rdev->bar2_kva + bar2_qoffset; 193 } 194 195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 196 struct t4_cq *rcq, struct t4_cq *scq, 197 struct c4iw_dev_ucontext *uctx) 198 { 199 int user = (uctx != &rdev->uctx); 200 struct fw_ri_res_wr *res_wr; 201 struct fw_ri_res *res; 202 int wr_len; 203 struct c4iw_wr_wait wr_wait; 204 struct sk_buff *skb; 205 int ret = 0; 206 int eqsize; 207 208 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 209 if (!wq->sq.qid) 210 return -ENOMEM; 211 212 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 213 if (!wq->rq.qid) { 214 ret = -ENOMEM; 215 goto free_sq_qid; 216 } 217 218 if (!user) { 219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 220 GFP_KERNEL); 221 if (!wq->sq.sw_sq) { 222 ret = -ENOMEM; 223 goto free_rq_qid; 224 } 225 226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 227 GFP_KERNEL); 228 if (!wq->rq.sw_rq) { 229 ret = -ENOMEM; 230 goto free_sw_sq; 231 } 232 } 233 234 /* 235 * RQT must be a power of 2 and at least 16 deep. 236 */ 237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16)); 238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 239 if (!wq->rq.rqt_hwaddr) { 240 ret = -ENOMEM; 241 goto free_sw_rq; 242 } 243 244 ret = alloc_sq(rdev, &wq->sq, user); 245 if (ret) 246 goto free_hwaddr; 247 memset(wq->sq.queue, 0, wq->sq.memsize); 248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 249 250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), 251 wq->rq.memsize, &(wq->rq.dma_addr), 252 GFP_KERNEL); 253 if (!wq->rq.queue) { 254 ret = -ENOMEM; 255 goto free_sq; 256 } 257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n", 258 __func__, wq->sq.queue, 259 (unsigned long long)virt_to_phys(wq->sq.queue), 260 wq->rq.queue, 261 (unsigned long long)virt_to_phys(wq->rq.queue)); 262 memset(wq->rq.queue, 0, wq->rq.memsize); 263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 264 265 wq->db = rdev->lldi.db_reg; 266 267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, 268 &wq->sq.bar2_qid, 269 user ? &wq->sq.bar2_pa : NULL); 270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, 271 &wq->rq.bar2_qid, 272 user ? &wq->rq.bar2_pa : NULL); 273 274 /* 275 * User mode must have bar2 access. 276 */ 277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) { 278 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n", 279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid); 280 goto free_dma; 281 } 282 283 wq->rdev = rdev; 284 wq->rq.msn = 1; 285 286 /* build fw_ri_res_wr */ 287 wr_len = sizeof *res_wr + 2 * sizeof *res; 288 289 skb = alloc_skb(wr_len, GFP_KERNEL); 290 if (!skb) { 291 ret = -ENOMEM; 292 goto free_dma; 293 } 294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 295 296 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); 297 memset(res_wr, 0, wr_len); 298 res_wr->op_nres = cpu_to_be32( 299 FW_WR_OP_V(FW_RI_RES_WR) | 300 FW_RI_RES_WR_NRES_V(2) | 301 FW_WR_COMPL_F); 302 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 303 res_wr->cookie = (uintptr_t)&wr_wait; 304 res = res_wr->res; 305 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 306 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 307 308 /* 309 * eqsize is the number of 64B entries plus the status page size. 310 */ 311 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 312 rdev->hw_queue.t4_eq_status_entries; 313 314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 318 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) | 319 FW_RI_RES_WR_IQID_V(scq->cqid)); 320 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 321 FW_RI_RES_WR_DCAEN_V(0) | 322 FW_RI_RES_WR_DCACPU_V(0) | 323 FW_RI_RES_WR_FBMIN_V(2) | 324 FW_RI_RES_WR_FBMAX_V(2) | 325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 326 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 327 FW_RI_RES_WR_EQSIZE_V(eqsize)); 328 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 329 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 330 res++; 331 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 332 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 333 334 /* 335 * eqsize is the number of 64B entries plus the status page size. 336 */ 337 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 338 rdev->hw_queue.t4_eq_status_entries; 339 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */ 341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */ 342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */ 343 FW_RI_RES_WR_IQID_V(rcq->cqid)); 344 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 345 FW_RI_RES_WR_DCAEN_V(0) | 346 FW_RI_RES_WR_DCACPU_V(0) | 347 FW_RI_RES_WR_FBMIN_V(2) | 348 FW_RI_RES_WR_FBMAX_V(2) | 349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) | 350 FW_RI_RES_WR_CIDXFTHRESH_V(0) | 351 FW_RI_RES_WR_EQSIZE_V(eqsize)); 352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 354 355 c4iw_init_wr_wait(&wr_wait); 356 357 ret = c4iw_ofld_send(rdev, skb); 358 if (ret) 359 goto free_dma; 360 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 361 if (ret) 362 goto free_dma; 363 364 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n", 365 __func__, wq->sq.qid, wq->rq.qid, wq->db, 366 wq->sq.bar2_va, wq->rq.bar2_va); 367 368 return 0; 369 free_dma: 370 dma_free_coherent(&(rdev->lldi.pdev->dev), 371 wq->rq.memsize, wq->rq.queue, 372 dma_unmap_addr(&wq->rq, mapping)); 373 free_sq: 374 dealloc_sq(rdev, &wq->sq); 375 free_hwaddr: 376 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 377 free_sw_rq: 378 kfree(wq->rq.sw_rq); 379 free_sw_sq: 380 kfree(wq->sq.sw_sq); 381 free_rq_qid: 382 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 383 free_sq_qid: 384 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 385 return ret; 386 } 387 388 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 389 struct ib_send_wr *wr, int max, u32 *plenp) 390 { 391 u8 *dstp, *srcp; 392 u32 plen = 0; 393 int i; 394 int rem, len; 395 396 dstp = (u8 *)immdp->data; 397 for (i = 0; i < wr->num_sge; i++) { 398 if ((plen + wr->sg_list[i].length) > max) 399 return -EMSGSIZE; 400 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 401 plen += wr->sg_list[i].length; 402 rem = wr->sg_list[i].length; 403 while (rem) { 404 if (dstp == (u8 *)&sq->queue[sq->size]) 405 dstp = (u8 *)sq->queue; 406 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 407 len = rem; 408 else 409 len = (u8 *)&sq->queue[sq->size] - dstp; 410 memcpy(dstp, srcp, len); 411 dstp += len; 412 srcp += len; 413 rem -= len; 414 } 415 } 416 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 417 if (len) 418 memset(dstp, 0, len); 419 immdp->op = FW_RI_DATA_IMMD; 420 immdp->r1 = 0; 421 immdp->r2 = 0; 422 immdp->immdlen = cpu_to_be32(plen); 423 *plenp = plen; 424 return 0; 425 } 426 427 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 428 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 429 int num_sge, u32 *plenp) 430 431 { 432 int i; 433 u32 plen = 0; 434 __be64 *flitp = (__be64 *)isglp->sge; 435 436 for (i = 0; i < num_sge; i++) { 437 if ((plen + sg_list[i].length) < plen) 438 return -EMSGSIZE; 439 plen += sg_list[i].length; 440 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 441 sg_list[i].length); 442 if (++flitp == queue_end) 443 flitp = queue_start; 444 *flitp = cpu_to_be64(sg_list[i].addr); 445 if (++flitp == queue_end) 446 flitp = queue_start; 447 } 448 *flitp = (__force __be64)0; 449 isglp->op = FW_RI_DATA_ISGL; 450 isglp->r1 = 0; 451 isglp->nsge = cpu_to_be16(num_sge); 452 isglp->r2 = 0; 453 if (plenp) 454 *plenp = plen; 455 return 0; 456 } 457 458 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 459 struct ib_send_wr *wr, u8 *len16) 460 { 461 u32 plen; 462 int size; 463 int ret; 464 465 if (wr->num_sge > T4_MAX_SEND_SGE) 466 return -EINVAL; 467 switch (wr->opcode) { 468 case IB_WR_SEND: 469 if (wr->send_flags & IB_SEND_SOLICITED) 470 wqe->send.sendop_pkd = cpu_to_be32( 471 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE)); 472 else 473 wqe->send.sendop_pkd = cpu_to_be32( 474 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND)); 475 wqe->send.stag_inv = 0; 476 break; 477 case IB_WR_SEND_WITH_INV: 478 if (wr->send_flags & IB_SEND_SOLICITED) 479 wqe->send.sendop_pkd = cpu_to_be32( 480 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV)); 481 else 482 wqe->send.sendop_pkd = cpu_to_be32( 483 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV)); 484 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 485 break; 486 487 default: 488 return -EINVAL; 489 } 490 wqe->send.r3 = 0; 491 wqe->send.r4 = 0; 492 493 plen = 0; 494 if (wr->num_sge) { 495 if (wr->send_flags & IB_SEND_INLINE) { 496 ret = build_immd(sq, wqe->send.u.immd_src, wr, 497 T4_MAX_SEND_INLINE, &plen); 498 if (ret) 499 return ret; 500 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 501 plen; 502 } else { 503 ret = build_isgl((__be64 *)sq->queue, 504 (__be64 *)&sq->queue[sq->size], 505 wqe->send.u.isgl_src, 506 wr->sg_list, wr->num_sge, &plen); 507 if (ret) 508 return ret; 509 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 510 wr->num_sge * sizeof(struct fw_ri_sge); 511 } 512 } else { 513 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 514 wqe->send.u.immd_src[0].r1 = 0; 515 wqe->send.u.immd_src[0].r2 = 0; 516 wqe->send.u.immd_src[0].immdlen = 0; 517 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 518 plen = 0; 519 } 520 *len16 = DIV_ROUND_UP(size, 16); 521 wqe->send.plen = cpu_to_be32(plen); 522 return 0; 523 } 524 525 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 526 struct ib_send_wr *wr, u8 *len16) 527 { 528 u32 plen; 529 int size; 530 int ret; 531 532 if (wr->num_sge > T4_MAX_SEND_SGE) 533 return -EINVAL; 534 wqe->write.r2 = 0; 535 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey); 536 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr); 537 if (wr->num_sge) { 538 if (wr->send_flags & IB_SEND_INLINE) { 539 ret = build_immd(sq, wqe->write.u.immd_src, wr, 540 T4_MAX_WRITE_INLINE, &plen); 541 if (ret) 542 return ret; 543 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 544 plen; 545 } else { 546 ret = build_isgl((__be64 *)sq->queue, 547 (__be64 *)&sq->queue[sq->size], 548 wqe->write.u.isgl_src, 549 wr->sg_list, wr->num_sge, &plen); 550 if (ret) 551 return ret; 552 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 553 wr->num_sge * sizeof(struct fw_ri_sge); 554 } 555 } else { 556 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 557 wqe->write.u.immd_src[0].r1 = 0; 558 wqe->write.u.immd_src[0].r2 = 0; 559 wqe->write.u.immd_src[0].immdlen = 0; 560 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 561 plen = 0; 562 } 563 *len16 = DIV_ROUND_UP(size, 16); 564 wqe->write.plen = cpu_to_be32(plen); 565 return 0; 566 } 567 568 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 569 { 570 if (wr->num_sge > 1) 571 return -EINVAL; 572 if (wr->num_sge) { 573 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey); 574 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr 575 >> 32)); 576 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr); 577 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 578 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 579 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 580 >> 32)); 581 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 582 } else { 583 wqe->read.stag_src = cpu_to_be32(2); 584 wqe->read.to_src_hi = 0; 585 wqe->read.to_src_lo = 0; 586 wqe->read.stag_sink = cpu_to_be32(2); 587 wqe->read.plen = 0; 588 wqe->read.to_sink_hi = 0; 589 wqe->read.to_sink_lo = 0; 590 } 591 wqe->read.r2 = 0; 592 wqe->read.r5 = 0; 593 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 594 return 0; 595 } 596 597 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 598 struct ib_recv_wr *wr, u8 *len16) 599 { 600 int ret; 601 602 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 603 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 604 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 605 if (ret) 606 return ret; 607 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 608 wr->num_sge * sizeof(struct fw_ri_sge), 16); 609 return 0; 610 } 611 612 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr, 613 struct ib_reg_wr *wr, struct c4iw_mr *mhp, 614 u8 *len16) 615 { 616 __be64 *p = (__be64 *)fr->pbl; 617 618 fr->r2 = cpu_to_be32(0); 619 fr->stag = cpu_to_be32(mhp->ibmr.rkey); 620 621 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 622 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) | 623 FW_RI_TPTE_STAGSTATE_V(1) | 624 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) | 625 FW_RI_TPTE_PDID_V(mhp->attr.pdid)); 626 fr->tpte.locread_to_qpid = cpu_to_be32( 627 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) | 628 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) | 629 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12)); 630 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V( 631 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3)); 632 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0); 633 fr->tpte.len_hi = cpu_to_be32(0); 634 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length); 635 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 636 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 637 638 p[0] = cpu_to_be64((u64)mhp->mpl[0]); 639 p[1] = cpu_to_be64((u64)mhp->mpl[1]); 640 641 *len16 = DIV_ROUND_UP(sizeof(*fr), 16); 642 } 643 644 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe, 645 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16, 646 bool dsgl_supported) 647 { 648 struct fw_ri_immd *imdp; 649 __be64 *p; 650 int i; 651 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32); 652 int rem; 653 654 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl)) 655 return -EINVAL; 656 657 wqe->fr.qpbinde_to_dcacpu = 0; 658 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12; 659 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 660 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access); 661 wqe->fr.len_hi = 0; 662 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length); 663 wqe->fr.stag = cpu_to_be32(wr->key); 664 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 665 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 666 0xffffffff); 667 668 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) { 669 struct fw_ri_dsgl *sglp; 670 671 for (i = 0; i < mhp->mpl_len; i++) 672 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]); 673 674 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); 675 sglp->op = FW_RI_DATA_DSGL; 676 sglp->r1 = 0; 677 sglp->nsge = cpu_to_be16(1); 678 sglp->addr0 = cpu_to_be64(mhp->mpl_addr); 679 sglp->len0 = cpu_to_be32(pbllen); 680 681 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); 682 } else { 683 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 684 imdp->op = FW_RI_DATA_IMMD; 685 imdp->r1 = 0; 686 imdp->r2 = 0; 687 imdp->immdlen = cpu_to_be32(pbllen); 688 p = (__be64 *)(imdp + 1); 689 rem = pbllen; 690 for (i = 0; i < mhp->mpl_len; i++) { 691 *p = cpu_to_be64((u64)mhp->mpl[i]); 692 rem -= sizeof(*p); 693 if (++p == (__be64 *)&sq->queue[sq->size]) 694 p = (__be64 *)sq->queue; 695 } 696 BUG_ON(rem < 0); 697 while (rem) { 698 *p = 0; 699 rem -= sizeof(*p); 700 if (++p == (__be64 *)&sq->queue[sq->size]) 701 p = (__be64 *)sq->queue; 702 } 703 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) 704 + pbllen, 16); 705 } 706 return 0; 707 } 708 709 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 710 { 711 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 712 wqe->inv.r2 = 0; 713 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 714 return 0; 715 } 716 717 static void _free_qp(struct kref *kref) 718 { 719 struct c4iw_qp *qhp; 720 721 qhp = container_of(kref, struct c4iw_qp, kref); 722 PDBG("%s qhp %p\n", __func__, qhp); 723 kfree(qhp); 724 } 725 726 void c4iw_qp_add_ref(struct ib_qp *qp) 727 { 728 PDBG("%s ib_qp %p\n", __func__, qp); 729 kref_get(&to_c4iw_qp(qp)->kref); 730 } 731 732 void c4iw_qp_rem_ref(struct ib_qp *qp) 733 { 734 PDBG("%s ib_qp %p\n", __func__, qp); 735 kref_put(&to_c4iw_qp(qp)->kref, _free_qp); 736 } 737 738 static void add_to_fc_list(struct list_head *head, struct list_head *entry) 739 { 740 if (list_empty(entry)) 741 list_add_tail(entry, head); 742 } 743 744 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc) 745 { 746 unsigned long flags; 747 748 spin_lock_irqsave(&qhp->rhp->lock, flags); 749 spin_lock(&qhp->lock); 750 if (qhp->rhp->db_state == NORMAL) 751 t4_ring_sq_db(&qhp->wq, inc, NULL); 752 else { 753 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 754 qhp->wq.sq.wq_pidx_inc += inc; 755 } 756 spin_unlock(&qhp->lock); 757 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 758 return 0; 759 } 760 761 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc) 762 { 763 unsigned long flags; 764 765 spin_lock_irqsave(&qhp->rhp->lock, flags); 766 spin_lock(&qhp->lock); 767 if (qhp->rhp->db_state == NORMAL) 768 t4_ring_rq_db(&qhp->wq, inc, NULL); 769 else { 770 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); 771 qhp->wq.rq.wq_pidx_inc += inc; 772 } 773 spin_unlock(&qhp->lock); 774 spin_unlock_irqrestore(&qhp->rhp->lock, flags); 775 return 0; 776 } 777 778 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 779 struct ib_send_wr **bad_wr) 780 { 781 int err = 0; 782 u8 len16 = 0; 783 enum fw_wr_opcodes fw_opcode = 0; 784 enum fw_ri_wr_flags fw_flags; 785 struct c4iw_qp *qhp; 786 union t4_wr *wqe = NULL; 787 u32 num_wrs; 788 struct t4_swsqe *swsqe; 789 unsigned long flag; 790 u16 idx = 0; 791 792 qhp = to_c4iw_qp(ibqp); 793 spin_lock_irqsave(&qhp->lock, flag); 794 if (t4_wq_in_error(&qhp->wq)) { 795 spin_unlock_irqrestore(&qhp->lock, flag); 796 *bad_wr = wr; 797 return -EINVAL; 798 } 799 num_wrs = t4_sq_avail(&qhp->wq); 800 if (num_wrs == 0) { 801 spin_unlock_irqrestore(&qhp->lock, flag); 802 *bad_wr = wr; 803 return -ENOMEM; 804 } 805 while (wr) { 806 if (num_wrs == 0) { 807 err = -ENOMEM; 808 *bad_wr = wr; 809 break; 810 } 811 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 812 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 813 814 fw_flags = 0; 815 if (wr->send_flags & IB_SEND_SOLICITED) 816 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 817 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 818 fw_flags |= FW_RI_COMPLETION_FLAG; 819 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 820 switch (wr->opcode) { 821 case IB_WR_SEND_WITH_INV: 822 case IB_WR_SEND: 823 if (wr->send_flags & IB_SEND_FENCE) 824 fw_flags |= FW_RI_READ_FENCE_FLAG; 825 fw_opcode = FW_RI_SEND_WR; 826 if (wr->opcode == IB_WR_SEND) 827 swsqe->opcode = FW_RI_SEND; 828 else 829 swsqe->opcode = FW_RI_SEND_WITH_INV; 830 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 831 break; 832 case IB_WR_RDMA_WRITE: 833 fw_opcode = FW_RI_RDMA_WRITE_WR; 834 swsqe->opcode = FW_RI_RDMA_WRITE; 835 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 836 break; 837 case IB_WR_RDMA_READ: 838 case IB_WR_RDMA_READ_WITH_INV: 839 fw_opcode = FW_RI_RDMA_READ_WR; 840 swsqe->opcode = FW_RI_READ_REQ; 841 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) { 842 c4iw_invalidate_mr(qhp->rhp, 843 wr->sg_list[0].lkey); 844 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 845 } else { 846 fw_flags = 0; 847 } 848 err = build_rdma_read(wqe, wr, &len16); 849 if (err) 850 break; 851 swsqe->read_len = wr->sg_list[0].length; 852 if (!qhp->wq.sq.oldest_read) 853 qhp->wq.sq.oldest_read = swsqe; 854 break; 855 case IB_WR_REG_MR: { 856 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr); 857 858 swsqe->opcode = FW_RI_FAST_REGISTER; 859 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support && 860 !mhp->attr.state && mhp->mpl_len <= 2) { 861 fw_opcode = FW_RI_FR_NSMR_TPTE_WR; 862 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr), 863 mhp, &len16); 864 } else { 865 fw_opcode = FW_RI_FR_NSMR_WR; 866 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), 867 mhp, &len16, 868 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl); 869 if (err) 870 break; 871 } 872 mhp->attr.state = 1; 873 break; 874 } 875 case IB_WR_LOCAL_INV: 876 if (wr->send_flags & IB_SEND_FENCE) 877 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 878 fw_opcode = FW_RI_INV_LSTAG_WR; 879 swsqe->opcode = FW_RI_LOCAL_INV; 880 err = build_inv_stag(wqe, wr, &len16); 881 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey); 882 break; 883 default: 884 PDBG("%s post of type=%d TBD!\n", __func__, 885 wr->opcode); 886 err = -EINVAL; 887 } 888 if (err) { 889 *bad_wr = wr; 890 break; 891 } 892 swsqe->idx = qhp->wq.sq.pidx; 893 swsqe->complete = 0; 894 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 895 qhp->sq_sig_all; 896 swsqe->flushed = 0; 897 swsqe->wr_id = wr->wr_id; 898 if (c4iw_wr_log) { 899 swsqe->sge_ts = cxgb4_read_sge_timestamp( 900 qhp->rhp->rdev.lldi.ports[0]); 901 getnstimeofday(&swsqe->host_ts); 902 } 903 904 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 905 906 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n", 907 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 908 swsqe->opcode, swsqe->read_len); 909 wr = wr->next; 910 num_wrs--; 911 t4_sq_produce(&qhp->wq, len16); 912 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 913 } 914 if (!qhp->rhp->rdev.status_page->db_off) { 915 t4_ring_sq_db(&qhp->wq, idx, wqe); 916 spin_unlock_irqrestore(&qhp->lock, flag); 917 } else { 918 spin_unlock_irqrestore(&qhp->lock, flag); 919 ring_kernel_sq_db(qhp, idx); 920 } 921 return err; 922 } 923 924 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 925 struct ib_recv_wr **bad_wr) 926 { 927 int err = 0; 928 struct c4iw_qp *qhp; 929 union t4_recv_wr *wqe = NULL; 930 u32 num_wrs; 931 u8 len16 = 0; 932 unsigned long flag; 933 u16 idx = 0; 934 935 qhp = to_c4iw_qp(ibqp); 936 spin_lock_irqsave(&qhp->lock, flag); 937 if (t4_wq_in_error(&qhp->wq)) { 938 spin_unlock_irqrestore(&qhp->lock, flag); 939 *bad_wr = wr; 940 return -EINVAL; 941 } 942 num_wrs = t4_rq_avail(&qhp->wq); 943 if (num_wrs == 0) { 944 spin_unlock_irqrestore(&qhp->lock, flag); 945 *bad_wr = wr; 946 return -ENOMEM; 947 } 948 while (wr) { 949 if (wr->num_sge > T4_MAX_RECV_SGE) { 950 err = -EINVAL; 951 *bad_wr = wr; 952 break; 953 } 954 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 955 qhp->wq.rq.wq_pidx * 956 T4_EQ_ENTRY_SIZE); 957 if (num_wrs) 958 err = build_rdma_recv(qhp, wqe, wr, &len16); 959 else 960 err = -ENOMEM; 961 if (err) { 962 *bad_wr = wr; 963 break; 964 } 965 966 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 967 if (c4iw_wr_log) { 968 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts = 969 cxgb4_read_sge_timestamp( 970 qhp->rhp->rdev.lldi.ports[0]); 971 getnstimeofday( 972 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts); 973 } 974 975 wqe->recv.opcode = FW_RI_RECV_WR; 976 wqe->recv.r1 = 0; 977 wqe->recv.wrid = qhp->wq.rq.pidx; 978 wqe->recv.r2[0] = 0; 979 wqe->recv.r2[1] = 0; 980 wqe->recv.r2[2] = 0; 981 wqe->recv.len16 = len16; 982 PDBG("%s cookie 0x%llx pidx %u\n", __func__, 983 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 984 t4_rq_produce(&qhp->wq, len16); 985 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 986 wr = wr->next; 987 num_wrs--; 988 } 989 if (!qhp->rhp->rdev.status_page->db_off) { 990 t4_ring_rq_db(&qhp->wq, idx, wqe); 991 spin_unlock_irqrestore(&qhp->lock, flag); 992 } else { 993 spin_unlock_irqrestore(&qhp->lock, flag); 994 ring_kernel_rq_db(qhp, idx); 995 } 996 return err; 997 } 998 999 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 1000 u8 *ecode) 1001 { 1002 int status; 1003 int tagged; 1004 int opcode; 1005 int rqtype; 1006 int send_inv; 1007 1008 if (!err_cqe) { 1009 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1010 *ecode = 0; 1011 return; 1012 } 1013 1014 status = CQE_STATUS(err_cqe); 1015 opcode = CQE_OPCODE(err_cqe); 1016 rqtype = RQ_TYPE(err_cqe); 1017 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 1018 (opcode == FW_RI_SEND_WITH_SE_INV); 1019 tagged = (opcode == FW_RI_RDMA_WRITE) || 1020 (rqtype && (opcode == FW_RI_READ_RESP)); 1021 1022 switch (status) { 1023 case T4_ERR_STAG: 1024 if (send_inv) { 1025 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1026 *ecode = RDMAP_CANT_INV_STAG; 1027 } else { 1028 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1029 *ecode = RDMAP_INV_STAG; 1030 } 1031 break; 1032 case T4_ERR_PDID: 1033 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1034 if ((opcode == FW_RI_SEND_WITH_INV) || 1035 (opcode == FW_RI_SEND_WITH_SE_INV)) 1036 *ecode = RDMAP_CANT_INV_STAG; 1037 else 1038 *ecode = RDMAP_STAG_NOT_ASSOC; 1039 break; 1040 case T4_ERR_QPID: 1041 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1042 *ecode = RDMAP_STAG_NOT_ASSOC; 1043 break; 1044 case T4_ERR_ACCESS: 1045 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1046 *ecode = RDMAP_ACC_VIOL; 1047 break; 1048 case T4_ERR_WRAP: 1049 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1050 *ecode = RDMAP_TO_WRAP; 1051 break; 1052 case T4_ERR_BOUND: 1053 if (tagged) { 1054 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1055 *ecode = DDPT_BASE_BOUNDS; 1056 } else { 1057 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1058 *ecode = RDMAP_BASE_BOUNDS; 1059 } 1060 break; 1061 case T4_ERR_INVALIDATE_SHARED_MR: 1062 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 1063 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1064 *ecode = RDMAP_CANT_INV_STAG; 1065 break; 1066 case T4_ERR_ECC: 1067 case T4_ERR_ECC_PSTAG: 1068 case T4_ERR_INTERNAL_ERR: 1069 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 1070 *ecode = 0; 1071 break; 1072 case T4_ERR_OUT_OF_RQE: 1073 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1074 *ecode = DDPU_INV_MSN_NOBUF; 1075 break; 1076 case T4_ERR_PBL_ADDR_BOUND: 1077 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1078 *ecode = DDPT_BASE_BOUNDS; 1079 break; 1080 case T4_ERR_CRC: 1081 *layer_type = LAYER_MPA|DDP_LLP; 1082 *ecode = MPA_CRC_ERR; 1083 break; 1084 case T4_ERR_MARKER: 1085 *layer_type = LAYER_MPA|DDP_LLP; 1086 *ecode = MPA_MARKER_ERR; 1087 break; 1088 case T4_ERR_PDU_LEN_ERR: 1089 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1090 *ecode = DDPU_MSG_TOOBIG; 1091 break; 1092 case T4_ERR_DDP_VERSION: 1093 if (tagged) { 1094 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1095 *ecode = DDPT_INV_VERS; 1096 } else { 1097 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1098 *ecode = DDPU_INV_VERS; 1099 } 1100 break; 1101 case T4_ERR_RDMA_VERSION: 1102 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1103 *ecode = RDMAP_INV_VERS; 1104 break; 1105 case T4_ERR_OPCODE: 1106 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1107 *ecode = RDMAP_INV_OPCODE; 1108 break; 1109 case T4_ERR_DDP_QUEUE_NUM: 1110 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1111 *ecode = DDPU_INV_QN; 1112 break; 1113 case T4_ERR_MSN: 1114 case T4_ERR_MSN_GAP: 1115 case T4_ERR_MSN_RANGE: 1116 case T4_ERR_IRD_OVERFLOW: 1117 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1118 *ecode = DDPU_INV_MSN_RANGE; 1119 break; 1120 case T4_ERR_TBIT: 1121 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 1122 *ecode = 0; 1123 break; 1124 case T4_ERR_MO: 1125 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1126 *ecode = DDPU_INV_MO; 1127 break; 1128 default: 1129 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1130 *ecode = 0; 1131 break; 1132 } 1133 } 1134 1135 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 1136 gfp_t gfp) 1137 { 1138 struct fw_ri_wr *wqe; 1139 struct sk_buff *skb; 1140 struct terminate_message *term; 1141 1142 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1143 qhp->ep->hwtid); 1144 1145 skb = skb_dequeue(&qhp->ep->com.ep_skb_list); 1146 if (WARN_ON(!skb)) 1147 return; 1148 1149 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1150 1151 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1152 memset(wqe, 0, sizeof *wqe); 1153 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR)); 1154 wqe->flowid_len16 = cpu_to_be32( 1155 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1156 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1157 1158 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 1159 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 1160 term = (struct terminate_message *)wqe->u.terminate.termmsg; 1161 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 1162 term->layer_etype = qhp->attr.layer_etype; 1163 term->ecode = qhp->attr.ecode; 1164 } else 1165 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 1166 c4iw_ofld_send(&qhp->rhp->rdev, skb); 1167 } 1168 1169 /* 1170 * Assumes qhp lock is held. 1171 */ 1172 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1173 struct c4iw_cq *schp) 1174 { 1175 int count; 1176 int rq_flushed, sq_flushed; 1177 unsigned long flag; 1178 1179 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); 1180 1181 /* locking hierarchy: cq lock first, then qp lock. */ 1182 spin_lock_irqsave(&rchp->lock, flag); 1183 spin_lock(&qhp->lock); 1184 1185 if (qhp->wq.flushed) { 1186 spin_unlock(&qhp->lock); 1187 spin_unlock_irqrestore(&rchp->lock, flag); 1188 return; 1189 } 1190 qhp->wq.flushed = 1; 1191 1192 c4iw_flush_hw_cq(rchp); 1193 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1194 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1195 spin_unlock(&qhp->lock); 1196 spin_unlock_irqrestore(&rchp->lock, flag); 1197 1198 /* locking hierarchy: cq lock first, then qp lock. */ 1199 spin_lock_irqsave(&schp->lock, flag); 1200 spin_lock(&qhp->lock); 1201 if (schp != rchp) 1202 c4iw_flush_hw_cq(schp); 1203 sq_flushed = c4iw_flush_sq(qhp); 1204 spin_unlock(&qhp->lock); 1205 spin_unlock_irqrestore(&schp->lock, flag); 1206 1207 if (schp == rchp) { 1208 if (t4_clear_cq_armed(&rchp->cq) && 1209 (rq_flushed || sq_flushed)) { 1210 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1211 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1212 rchp->ibcq.cq_context); 1213 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1214 } 1215 } else { 1216 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) { 1217 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1218 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1219 rchp->ibcq.cq_context); 1220 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1221 } 1222 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) { 1223 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1224 (*schp->ibcq.comp_handler)(&schp->ibcq, 1225 schp->ibcq.cq_context); 1226 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1227 } 1228 } 1229 } 1230 1231 static void flush_qp(struct c4iw_qp *qhp) 1232 { 1233 struct c4iw_cq *rchp, *schp; 1234 unsigned long flag; 1235 1236 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 1237 schp = to_c4iw_cq(qhp->ibqp.send_cq); 1238 1239 t4_set_wq_in_error(&qhp->wq); 1240 if (qhp->ibqp.uobject) { 1241 t4_set_cq_in_error(&rchp->cq); 1242 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1243 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1244 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1245 if (schp != rchp) { 1246 t4_set_cq_in_error(&schp->cq); 1247 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1248 (*schp->ibcq.comp_handler)(&schp->ibcq, 1249 schp->ibcq.cq_context); 1250 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1251 } 1252 return; 1253 } 1254 __flush_qp(qhp, rchp, schp); 1255 } 1256 1257 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1258 struct c4iw_ep *ep) 1259 { 1260 struct fw_ri_wr *wqe; 1261 int ret; 1262 struct sk_buff *skb; 1263 1264 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1265 ep->hwtid); 1266 1267 skb = skb_dequeue(&ep->com.ep_skb_list); 1268 if (WARN_ON(!skb)) 1269 return -ENOMEM; 1270 1271 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx); 1272 1273 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1274 memset(wqe, 0, sizeof *wqe); 1275 wqe->op_compl = cpu_to_be32( 1276 FW_WR_OP_V(FW_RI_INIT_WR) | 1277 FW_WR_COMPL_F); 1278 wqe->flowid_len16 = cpu_to_be32( 1279 FW_WR_FLOWID_V(ep->hwtid) | 1280 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1281 wqe->cookie = (uintptr_t)&ep->com.wr_wait; 1282 1283 wqe->u.fini.type = FW_RI_TYPE_FINI; 1284 ret = c4iw_ofld_send(&rhp->rdev, skb); 1285 if (ret) 1286 goto out; 1287 1288 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid, 1289 qhp->wq.sq.qid, __func__); 1290 out: 1291 PDBG("%s ret %d\n", __func__, ret); 1292 return ret; 1293 } 1294 1295 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1296 { 1297 PDBG("%s p2p_type = %d\n", __func__, p2p_type); 1298 memset(&init->u, 0, sizeof init->u); 1299 switch (p2p_type) { 1300 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1301 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1302 init->u.write.stag_sink = cpu_to_be32(1); 1303 init->u.write.to_sink = cpu_to_be64(1); 1304 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1305 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1306 sizeof(struct fw_ri_immd), 1307 16); 1308 break; 1309 case FW_RI_INIT_P2PTYPE_READ_REQ: 1310 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1311 init->u.read.stag_src = cpu_to_be32(1); 1312 init->u.read.to_src_lo = cpu_to_be32(1); 1313 init->u.read.stag_sink = cpu_to_be32(1); 1314 init->u.read.to_sink_lo = cpu_to_be32(1); 1315 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1316 break; 1317 } 1318 } 1319 1320 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1321 { 1322 struct fw_ri_wr *wqe; 1323 int ret; 1324 struct sk_buff *skb; 1325 1326 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp, 1327 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord); 1328 1329 skb = alloc_skb(sizeof *wqe, GFP_KERNEL); 1330 if (!skb) { 1331 ret = -ENOMEM; 1332 goto out; 1333 } 1334 ret = alloc_ird(rhp, qhp->attr.max_ird); 1335 if (ret) { 1336 qhp->attr.max_ird = 0; 1337 kfree_skb(skb); 1338 goto out; 1339 } 1340 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 1341 1342 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); 1343 memset(wqe, 0, sizeof *wqe); 1344 wqe->op_compl = cpu_to_be32( 1345 FW_WR_OP_V(FW_RI_INIT_WR) | 1346 FW_WR_COMPL_F); 1347 wqe->flowid_len16 = cpu_to_be32( 1348 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1349 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1350 1351 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait; 1352 1353 wqe->u.init.type = FW_RI_TYPE_INIT; 1354 wqe->u.init.mpareqbit_p2ptype = 1355 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) | 1356 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type); 1357 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1358 if (qhp->attr.mpa_attr.recv_marker_enabled) 1359 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1360 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1361 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1362 if (qhp->attr.mpa_attr.crc_enabled) 1363 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1364 1365 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1366 FW_RI_QP_RDMA_WRITE_ENABLE | 1367 FW_RI_QP_BIND_ENABLE; 1368 if (!qhp->ibqp.uobject) 1369 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1370 FW_RI_QP_STAG0_ENABLE; 1371 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1372 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1373 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1374 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1375 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1376 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1377 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1378 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1379 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1380 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq); 1381 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq); 1382 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1383 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1384 rhp->rdev.lldi.vr->rq.start); 1385 if (qhp->attr.mpa_attr.initiator) 1386 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1387 1388 ret = c4iw_ofld_send(&rhp->rdev, skb); 1389 if (ret) 1390 goto err1; 1391 1392 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait, 1393 qhp->ep->hwtid, qhp->wq.sq.qid, __func__); 1394 if (!ret) 1395 goto out; 1396 err1: 1397 free_ird(rhp, qhp->attr.max_ird); 1398 out: 1399 PDBG("%s ret %d\n", __func__, ret); 1400 return ret; 1401 } 1402 1403 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1404 enum c4iw_qp_attr_mask mask, 1405 struct c4iw_qp_attributes *attrs, 1406 int internal) 1407 { 1408 int ret = 0; 1409 struct c4iw_qp_attributes newattr = qhp->attr; 1410 int disconnect = 0; 1411 int terminate = 0; 1412 int abort = 0; 1413 int free = 0; 1414 struct c4iw_ep *ep = NULL; 1415 1416 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__, 1417 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, 1418 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1419 1420 mutex_lock(&qhp->mutex); 1421 1422 /* Process attr changes if in IDLE */ 1423 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1424 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1425 ret = -EIO; 1426 goto out; 1427 } 1428 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1429 newattr.enable_rdma_read = attrs->enable_rdma_read; 1430 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1431 newattr.enable_rdma_write = attrs->enable_rdma_write; 1432 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1433 newattr.enable_bind = attrs->enable_bind; 1434 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1435 if (attrs->max_ord > c4iw_max_read_depth) { 1436 ret = -EINVAL; 1437 goto out; 1438 } 1439 newattr.max_ord = attrs->max_ord; 1440 } 1441 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1442 if (attrs->max_ird > cur_max_read_depth(rhp)) { 1443 ret = -EINVAL; 1444 goto out; 1445 } 1446 newattr.max_ird = attrs->max_ird; 1447 } 1448 qhp->attr = newattr; 1449 } 1450 1451 if (mask & C4IW_QP_ATTR_SQ_DB) { 1452 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc); 1453 goto out; 1454 } 1455 if (mask & C4IW_QP_ATTR_RQ_DB) { 1456 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc); 1457 goto out; 1458 } 1459 1460 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1461 goto out; 1462 if (qhp->attr.state == attrs->next_state) 1463 goto out; 1464 1465 switch (qhp->attr.state) { 1466 case C4IW_QP_STATE_IDLE: 1467 switch (attrs->next_state) { 1468 case C4IW_QP_STATE_RTS: 1469 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1470 ret = -EINVAL; 1471 goto out; 1472 } 1473 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1474 ret = -EINVAL; 1475 goto out; 1476 } 1477 qhp->attr.mpa_attr = attrs->mpa_attr; 1478 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1479 qhp->ep = qhp->attr.llp_stream_handle; 1480 set_state(qhp, C4IW_QP_STATE_RTS); 1481 1482 /* 1483 * Ref the endpoint here and deref when we 1484 * disassociate the endpoint from the QP. This 1485 * happens in CLOSING->IDLE transition or *->ERROR 1486 * transition. 1487 */ 1488 c4iw_get_ep(&qhp->ep->com); 1489 ret = rdma_init(rhp, qhp); 1490 if (ret) 1491 goto err; 1492 break; 1493 case C4IW_QP_STATE_ERROR: 1494 set_state(qhp, C4IW_QP_STATE_ERROR); 1495 flush_qp(qhp); 1496 break; 1497 default: 1498 ret = -EINVAL; 1499 goto out; 1500 } 1501 break; 1502 case C4IW_QP_STATE_RTS: 1503 switch (attrs->next_state) { 1504 case C4IW_QP_STATE_CLOSING: 1505 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1506 t4_set_wq_in_error(&qhp->wq); 1507 set_state(qhp, C4IW_QP_STATE_CLOSING); 1508 ep = qhp->ep; 1509 if (!internal) { 1510 abort = 0; 1511 disconnect = 1; 1512 c4iw_get_ep(&qhp->ep->com); 1513 } 1514 ret = rdma_fini(rhp, qhp, ep); 1515 if (ret) 1516 goto err; 1517 break; 1518 case C4IW_QP_STATE_TERMINATE: 1519 t4_set_wq_in_error(&qhp->wq); 1520 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1521 qhp->attr.layer_etype = attrs->layer_etype; 1522 qhp->attr.ecode = attrs->ecode; 1523 ep = qhp->ep; 1524 if (!internal) { 1525 c4iw_get_ep(&qhp->ep->com); 1526 terminate = 1; 1527 disconnect = 1; 1528 } else { 1529 terminate = qhp->attr.send_term; 1530 ret = rdma_fini(rhp, qhp, ep); 1531 if (ret) 1532 goto err; 1533 } 1534 break; 1535 case C4IW_QP_STATE_ERROR: 1536 t4_set_wq_in_error(&qhp->wq); 1537 set_state(qhp, C4IW_QP_STATE_ERROR); 1538 if (!internal) { 1539 abort = 1; 1540 disconnect = 1; 1541 ep = qhp->ep; 1542 c4iw_get_ep(&qhp->ep->com); 1543 } 1544 goto err; 1545 break; 1546 default: 1547 ret = -EINVAL; 1548 goto out; 1549 } 1550 break; 1551 case C4IW_QP_STATE_CLOSING: 1552 if (!internal) { 1553 ret = -EINVAL; 1554 goto out; 1555 } 1556 switch (attrs->next_state) { 1557 case C4IW_QP_STATE_IDLE: 1558 flush_qp(qhp); 1559 set_state(qhp, C4IW_QP_STATE_IDLE); 1560 qhp->attr.llp_stream_handle = NULL; 1561 c4iw_put_ep(&qhp->ep->com); 1562 qhp->ep = NULL; 1563 wake_up(&qhp->wait); 1564 break; 1565 case C4IW_QP_STATE_ERROR: 1566 goto err; 1567 default: 1568 ret = -EINVAL; 1569 goto err; 1570 } 1571 break; 1572 case C4IW_QP_STATE_ERROR: 1573 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1574 ret = -EINVAL; 1575 goto out; 1576 } 1577 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1578 ret = -EINVAL; 1579 goto out; 1580 } 1581 set_state(qhp, C4IW_QP_STATE_IDLE); 1582 break; 1583 case C4IW_QP_STATE_TERMINATE: 1584 if (!internal) { 1585 ret = -EINVAL; 1586 goto out; 1587 } 1588 goto err; 1589 break; 1590 default: 1591 printk(KERN_ERR "%s in a bad state %d\n", 1592 __func__, qhp->attr.state); 1593 ret = -EINVAL; 1594 goto err; 1595 break; 1596 } 1597 goto out; 1598 err: 1599 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep, 1600 qhp->wq.sq.qid); 1601 1602 /* disassociate the LLP connection */ 1603 qhp->attr.llp_stream_handle = NULL; 1604 if (!ep) 1605 ep = qhp->ep; 1606 qhp->ep = NULL; 1607 set_state(qhp, C4IW_QP_STATE_ERROR); 1608 free = 1; 1609 abort = 1; 1610 BUG_ON(!ep); 1611 flush_qp(qhp); 1612 wake_up(&qhp->wait); 1613 out: 1614 mutex_unlock(&qhp->mutex); 1615 1616 if (terminate) 1617 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1618 1619 /* 1620 * If disconnect is 1, then we need to initiate a disconnect 1621 * on the EP. This can be a normal close (RTS->CLOSING) or 1622 * an abnormal close (RTS/CLOSING->ERROR). 1623 */ 1624 if (disconnect) { 1625 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1626 GFP_KERNEL); 1627 c4iw_put_ep(&ep->com); 1628 } 1629 1630 /* 1631 * If free is 1, then we've disassociated the EP from the QP 1632 * and we need to dereference the EP. 1633 */ 1634 if (free) 1635 c4iw_put_ep(&ep->com); 1636 PDBG("%s exit state %d\n", __func__, qhp->attr.state); 1637 return ret; 1638 } 1639 1640 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1641 { 1642 struct c4iw_dev *rhp; 1643 struct c4iw_qp *qhp; 1644 struct c4iw_qp_attributes attrs; 1645 struct c4iw_ucontext *ucontext; 1646 1647 qhp = to_c4iw_qp(ib_qp); 1648 rhp = qhp->rhp; 1649 1650 attrs.next_state = C4IW_QP_STATE_ERROR; 1651 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1652 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1653 else 1654 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1655 wait_event(qhp->wait, !qhp->ep); 1656 1657 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1658 1659 spin_lock_irq(&rhp->lock); 1660 if (!list_empty(&qhp->db_fc_entry)) 1661 list_del_init(&qhp->db_fc_entry); 1662 spin_unlock_irq(&rhp->lock); 1663 free_ird(rhp, qhp->attr.max_ird); 1664 1665 ucontext = ib_qp->uobject ? 1666 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1667 destroy_qp(&rhp->rdev, &qhp->wq, 1668 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1669 1670 c4iw_qp_rem_ref(ib_qp); 1671 1672 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid); 1673 return 0; 1674 } 1675 1676 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1677 struct ib_udata *udata) 1678 { 1679 struct c4iw_dev *rhp; 1680 struct c4iw_qp *qhp; 1681 struct c4iw_pd *php; 1682 struct c4iw_cq *schp; 1683 struct c4iw_cq *rchp; 1684 struct c4iw_create_qp_resp uresp; 1685 unsigned int sqsize, rqsize; 1686 struct c4iw_ucontext *ucontext; 1687 int ret; 1688 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm; 1689 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL; 1690 1691 PDBG("%s ib_pd %p\n", __func__, pd); 1692 1693 if (attrs->qp_type != IB_QPT_RC) 1694 return ERR_PTR(-EINVAL); 1695 1696 php = to_c4iw_pd(pd); 1697 rhp = php->rhp; 1698 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1699 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1700 if (!schp || !rchp) 1701 return ERR_PTR(-EINVAL); 1702 1703 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1704 return ERR_PTR(-EINVAL); 1705 1706 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size) 1707 return ERR_PTR(-E2BIG); 1708 rqsize = attrs->cap.max_recv_wr + 1; 1709 if (rqsize < 8) 1710 rqsize = 8; 1711 1712 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size) 1713 return ERR_PTR(-E2BIG); 1714 sqsize = attrs->cap.max_send_wr + 1; 1715 if (sqsize < 8) 1716 sqsize = 8; 1717 1718 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1719 1720 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1721 if (!qhp) 1722 return ERR_PTR(-ENOMEM); 1723 qhp->wq.sq.size = sqsize; 1724 qhp->wq.sq.memsize = 1725 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1726 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64); 1727 qhp->wq.sq.flush_cidx = -1; 1728 qhp->wq.rq.size = rqsize; 1729 qhp->wq.rq.memsize = 1730 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1731 sizeof(*qhp->wq.rq.queue); 1732 1733 if (ucontext) { 1734 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1735 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1736 } 1737 1738 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1739 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1740 if (ret) 1741 goto err1; 1742 1743 attrs->cap.max_recv_wr = rqsize - 1; 1744 attrs->cap.max_send_wr = sqsize - 1; 1745 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1746 1747 qhp->rhp = rhp; 1748 qhp->attr.pd = php->pdid; 1749 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1750 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1751 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1752 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1753 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1754 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1755 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1756 qhp->attr.state = C4IW_QP_STATE_IDLE; 1757 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1758 qhp->attr.enable_rdma_read = 1; 1759 qhp->attr.enable_rdma_write = 1; 1760 qhp->attr.enable_bind = 1; 1761 qhp->attr.max_ord = 0; 1762 qhp->attr.max_ird = 0; 1763 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1764 spin_lock_init(&qhp->lock); 1765 init_completion(&qhp->sq_drained); 1766 init_completion(&qhp->rq_drained); 1767 mutex_init(&qhp->mutex); 1768 init_waitqueue_head(&qhp->wait); 1769 kref_init(&qhp->kref); 1770 1771 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1772 if (ret) 1773 goto err2; 1774 1775 if (udata) { 1776 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL); 1777 if (!sq_key_mm) { 1778 ret = -ENOMEM; 1779 goto err3; 1780 } 1781 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL); 1782 if (!rq_key_mm) { 1783 ret = -ENOMEM; 1784 goto err4; 1785 } 1786 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL); 1787 if (!sq_db_key_mm) { 1788 ret = -ENOMEM; 1789 goto err5; 1790 } 1791 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL); 1792 if (!rq_db_key_mm) { 1793 ret = -ENOMEM; 1794 goto err6; 1795 } 1796 if (t4_sq_onchip(&qhp->wq.sq)) { 1797 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm), 1798 GFP_KERNEL); 1799 if (!ma_sync_key_mm) { 1800 ret = -ENOMEM; 1801 goto err7; 1802 } 1803 uresp.flags = C4IW_QPF_ONCHIP; 1804 } else 1805 uresp.flags = 0; 1806 uresp.qid_mask = rhp->rdev.qpmask; 1807 uresp.sqid = qhp->wq.sq.qid; 1808 uresp.sq_size = qhp->wq.sq.size; 1809 uresp.sq_memsize = qhp->wq.sq.memsize; 1810 uresp.rqid = qhp->wq.rq.qid; 1811 uresp.rq_size = qhp->wq.rq.size; 1812 uresp.rq_memsize = qhp->wq.rq.memsize; 1813 spin_lock(&ucontext->mmap_lock); 1814 if (ma_sync_key_mm) { 1815 uresp.ma_sync_key = ucontext->key; 1816 ucontext->key += PAGE_SIZE; 1817 } else { 1818 uresp.ma_sync_key = 0; 1819 } 1820 uresp.sq_key = ucontext->key; 1821 ucontext->key += PAGE_SIZE; 1822 uresp.rq_key = ucontext->key; 1823 ucontext->key += PAGE_SIZE; 1824 uresp.sq_db_gts_key = ucontext->key; 1825 ucontext->key += PAGE_SIZE; 1826 uresp.rq_db_gts_key = ucontext->key; 1827 ucontext->key += PAGE_SIZE; 1828 spin_unlock(&ucontext->mmap_lock); 1829 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1830 if (ret) 1831 goto err8; 1832 sq_key_mm->key = uresp.sq_key; 1833 sq_key_mm->addr = qhp->wq.sq.phys_addr; 1834 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1835 insert_mmap(ucontext, sq_key_mm); 1836 rq_key_mm->key = uresp.rq_key; 1837 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue); 1838 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1839 insert_mmap(ucontext, rq_key_mm); 1840 sq_db_key_mm->key = uresp.sq_db_gts_key; 1841 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa; 1842 sq_db_key_mm->len = PAGE_SIZE; 1843 insert_mmap(ucontext, sq_db_key_mm); 1844 rq_db_key_mm->key = uresp.rq_db_gts_key; 1845 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa; 1846 rq_db_key_mm->len = PAGE_SIZE; 1847 insert_mmap(ucontext, rq_db_key_mm); 1848 if (ma_sync_key_mm) { 1849 ma_sync_key_mm->key = uresp.ma_sync_key; 1850 ma_sync_key_mm->addr = 1851 (pci_resource_start(rhp->rdev.lldi.pdev, 0) + 1852 PCIE_MA_SYNC_A) & PAGE_MASK; 1853 ma_sync_key_mm->len = PAGE_SIZE; 1854 insert_mmap(ucontext, ma_sync_key_mm); 1855 } 1856 } 1857 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1858 init_timer(&(qhp->timer)); 1859 INIT_LIST_HEAD(&qhp->db_fc_entry); 1860 PDBG("%s sq id %u size %u memsize %zu num_entries %u " 1861 "rq id %u size %u memsize %zu num_entries %u\n", __func__, 1862 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize, 1863 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size, 1864 qhp->wq.rq.memsize, attrs->cap.max_recv_wr); 1865 return &qhp->ibqp; 1866 err8: 1867 kfree(ma_sync_key_mm); 1868 err7: 1869 kfree(rq_db_key_mm); 1870 err6: 1871 kfree(sq_db_key_mm); 1872 err5: 1873 kfree(rq_key_mm); 1874 err4: 1875 kfree(sq_key_mm); 1876 err3: 1877 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1878 err2: 1879 destroy_qp(&rhp->rdev, &qhp->wq, 1880 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1881 err1: 1882 kfree(qhp); 1883 return ERR_PTR(ret); 1884 } 1885 1886 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1887 int attr_mask, struct ib_udata *udata) 1888 { 1889 struct c4iw_dev *rhp; 1890 struct c4iw_qp *qhp; 1891 enum c4iw_qp_attr_mask mask = 0; 1892 struct c4iw_qp_attributes attrs; 1893 1894 PDBG("%s ib_qp %p\n", __func__, ibqp); 1895 1896 /* iwarp does not support the RTR state */ 1897 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1898 attr_mask &= ~IB_QP_STATE; 1899 1900 /* Make sure we still have something left to do */ 1901 if (!attr_mask) 1902 return 0; 1903 1904 memset(&attrs, 0, sizeof attrs); 1905 qhp = to_c4iw_qp(ibqp); 1906 rhp = qhp->rhp; 1907 1908 attrs.next_state = c4iw_convert_state(attr->qp_state); 1909 attrs.enable_rdma_read = (attr->qp_access_flags & 1910 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1911 attrs.enable_rdma_write = (attr->qp_access_flags & 1912 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1913 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1914 1915 1916 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1917 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1918 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1919 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1920 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1921 1922 /* 1923 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for 1924 * ringing the queue db when we're in DB_FULL mode. 1925 * Only allow this on T4 devices. 1926 */ 1927 attrs.sq_db_inc = attr->sq_psn; 1928 attrs.rq_db_inc = attr->rq_psn; 1929 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; 1930 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; 1931 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) && 1932 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB))) 1933 return -EINVAL; 1934 1935 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1936 } 1937 1938 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1939 { 1940 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn); 1941 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1942 } 1943 1944 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1945 int attr_mask, struct ib_qp_init_attr *init_attr) 1946 { 1947 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1948 1949 memset(attr, 0, sizeof *attr); 1950 memset(init_attr, 0, sizeof *init_attr); 1951 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1952 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 1953 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 1954 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 1955 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 1956 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 1957 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 1958 return 0; 1959 } 1960 1961 static void move_qp_to_err(struct c4iw_qp *qp) 1962 { 1963 struct c4iw_qp_attributes attrs = { .next_state = C4IW_QP_STATE_ERROR }; 1964 1965 (void)c4iw_modify_qp(qp->rhp, qp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1966 } 1967 1968 void c4iw_drain_sq(struct ib_qp *ibqp) 1969 { 1970 struct c4iw_qp *qp = to_c4iw_qp(ibqp); 1971 unsigned long flag; 1972 bool need_to_wait; 1973 1974 move_qp_to_err(qp); 1975 spin_lock_irqsave(&qp->lock, flag); 1976 need_to_wait = !t4_sq_empty(&qp->wq); 1977 spin_unlock_irqrestore(&qp->lock, flag); 1978 1979 if (need_to_wait) 1980 wait_for_completion(&qp->sq_drained); 1981 } 1982 1983 void c4iw_drain_rq(struct ib_qp *ibqp) 1984 { 1985 struct c4iw_qp *qp = to_c4iw_qp(ibqp); 1986 unsigned long flag; 1987 bool need_to_wait; 1988 1989 move_qp_to_err(qp); 1990 spin_lock_irqsave(&qp->lock, flag); 1991 need_to_wait = !t4_rq_empty(&qp->wq); 1992 spin_unlock_irqrestore(&qp->lock, flag); 1993 1994 if (need_to_wait) 1995 wait_for_completion(&qp->rq_drained); 1996 } 1997