1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/module.h> 33 #include <linux/moduleparam.h> 34 #include <linux/debugfs.h> 35 #include <linux/vmalloc.h> 36 #include <linux/math64.h> 37 38 #include <rdma/ib_verbs.h> 39 40 #include "iw_cxgb4.h" 41 42 #define DRV_VERSION "0.1" 43 44 MODULE_AUTHOR("Steve Wise"); 45 MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver"); 46 MODULE_LICENSE("Dual BSD/GPL"); 47 MODULE_VERSION(DRV_VERSION); 48 49 static int allow_db_fc_on_t5; 50 module_param(allow_db_fc_on_t5, int, 0644); 51 MODULE_PARM_DESC(allow_db_fc_on_t5, 52 "Allow DB Flow Control on T5 (default = 0)"); 53 54 static int allow_db_coalescing_on_t5; 55 module_param(allow_db_coalescing_on_t5, int, 0644); 56 MODULE_PARM_DESC(allow_db_coalescing_on_t5, 57 "Allow DB Coalescing on T5 (default = 0)"); 58 59 int c4iw_wr_log = 0; 60 module_param(c4iw_wr_log, int, 0444); 61 MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data."); 62 63 int c4iw_wr_log_size_order = 12; 64 module_param(c4iw_wr_log_size_order, int, 0444); 65 MODULE_PARM_DESC(c4iw_wr_log_size_order, 66 "Number of entries (log2) in the work request timing log."); 67 68 struct uld_ctx { 69 struct list_head entry; 70 struct cxgb4_lld_info lldi; 71 struct c4iw_dev *dev; 72 }; 73 74 static LIST_HEAD(uld_ctx_list); 75 static DEFINE_MUTEX(dev_mutex); 76 77 #define DB_FC_RESUME_SIZE 64 78 #define DB_FC_RESUME_DELAY 1 79 #define DB_FC_DRAIN_THRESH 0 80 81 static struct dentry *c4iw_debugfs_root; 82 83 struct c4iw_debugfs_data { 84 struct c4iw_dev *devp; 85 char *buf; 86 int bufsize; 87 int pos; 88 }; 89 90 /* registered cxgb4 netlink callbacks */ 91 static struct ibnl_client_cbs c4iw_nl_cb_table[] = { 92 [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb}, 93 [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb}, 94 [RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb}, 95 [RDMA_NL_IWPM_HANDLE_ERR] = {.dump = iwpm_mapping_error_cb}, 96 [RDMA_NL_IWPM_MAPINFO] = {.dump = iwpm_mapping_info_cb}, 97 [RDMA_NL_IWPM_MAPINFO_NUM] = {.dump = iwpm_ack_mapping_info_cb} 98 }; 99 100 static int count_idrs(int id, void *p, void *data) 101 { 102 int *countp = data; 103 104 *countp = *countp + 1; 105 return 0; 106 } 107 108 static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count, 109 loff_t *ppos) 110 { 111 struct c4iw_debugfs_data *d = file->private_data; 112 113 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos); 114 } 115 116 void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe) 117 { 118 struct wr_log_entry le; 119 int idx; 120 121 if (!wq->rdev->wr_log) 122 return; 123 124 idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) & 125 (wq->rdev->wr_log_size - 1); 126 le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]); 127 getnstimeofday(&le.poll_host_ts); 128 le.valid = 1; 129 le.cqe_sge_ts = CQE_TS(cqe); 130 if (SQ_TYPE(cqe)) { 131 le.qid = wq->sq.qid; 132 le.opcode = CQE_OPCODE(cqe); 133 le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts; 134 le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts; 135 le.wr_id = CQE_WRID_SQ_IDX(cqe); 136 } else { 137 le.qid = wq->rq.qid; 138 le.opcode = FW_RI_RECEIVE; 139 le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts; 140 le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts; 141 le.wr_id = CQE_WRID_MSN(cqe); 142 } 143 wq->rdev->wr_log[idx] = le; 144 } 145 146 static int wr_log_show(struct seq_file *seq, void *v) 147 { 148 struct c4iw_dev *dev = seq->private; 149 struct timespec prev_ts = {0, 0}; 150 struct wr_log_entry *lep; 151 int prev_ts_set = 0; 152 int idx, end; 153 154 #define ts2ns(ts) div64_ul((ts) * dev->rdev.lldi.cclk_ps, 1000) 155 156 idx = atomic_read(&dev->rdev.wr_log_idx) & 157 (dev->rdev.wr_log_size - 1); 158 end = idx - 1; 159 if (end < 0) 160 end = dev->rdev.wr_log_size - 1; 161 lep = &dev->rdev.wr_log[idx]; 162 while (idx != end) { 163 if (lep->valid) { 164 if (!prev_ts_set) { 165 prev_ts_set = 1; 166 prev_ts = lep->poll_host_ts; 167 } 168 seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode " 169 "%u %s 0x%x host_wr_delta sec %lu nsec %lu " 170 "post_sge_ts 0x%llx cqe_sge_ts 0x%llx " 171 "poll_sge_ts 0x%llx post_poll_delta_ns %llu " 172 "cqe_poll_delta_ns %llu\n", 173 idx, 174 timespec_sub(lep->poll_host_ts, 175 prev_ts).tv_sec, 176 timespec_sub(lep->poll_host_ts, 177 prev_ts).tv_nsec, 178 lep->qid, lep->opcode, 179 lep->opcode == FW_RI_RECEIVE ? 180 "msn" : "wrid", 181 lep->wr_id, 182 timespec_sub(lep->poll_host_ts, 183 lep->post_host_ts).tv_sec, 184 timespec_sub(lep->poll_host_ts, 185 lep->post_host_ts).tv_nsec, 186 lep->post_sge_ts, lep->cqe_sge_ts, 187 lep->poll_sge_ts, 188 ts2ns(lep->poll_sge_ts - lep->post_sge_ts), 189 ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts)); 190 prev_ts = lep->poll_host_ts; 191 } 192 idx++; 193 if (idx > (dev->rdev.wr_log_size - 1)) 194 idx = 0; 195 lep = &dev->rdev.wr_log[idx]; 196 } 197 #undef ts2ns 198 return 0; 199 } 200 201 static int wr_log_open(struct inode *inode, struct file *file) 202 { 203 return single_open(file, wr_log_show, inode->i_private); 204 } 205 206 static ssize_t wr_log_clear(struct file *file, const char __user *buf, 207 size_t count, loff_t *pos) 208 { 209 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private; 210 int i; 211 212 if (dev->rdev.wr_log) 213 for (i = 0; i < dev->rdev.wr_log_size; i++) 214 dev->rdev.wr_log[i].valid = 0; 215 return count; 216 } 217 218 static const struct file_operations wr_log_debugfs_fops = { 219 .owner = THIS_MODULE, 220 .open = wr_log_open, 221 .release = single_release, 222 .read = seq_read, 223 .llseek = seq_lseek, 224 .write = wr_log_clear, 225 }; 226 227 static int dump_qp(int id, void *p, void *data) 228 { 229 struct c4iw_qp *qp = p; 230 struct c4iw_debugfs_data *qpd = data; 231 int space; 232 int cc; 233 234 if (id != qp->wq.sq.qid) 235 return 0; 236 237 space = qpd->bufsize - qpd->pos - 1; 238 if (space == 0) 239 return 1; 240 241 if (qp->ep) { 242 if (qp->ep->com.local_addr.ss_family == AF_INET) { 243 struct sockaddr_in *lsin = (struct sockaddr_in *) 244 &qp->ep->com.local_addr; 245 struct sockaddr_in *rsin = (struct sockaddr_in *) 246 &qp->ep->com.remote_addr; 247 struct sockaddr_in *mapped_lsin = (struct sockaddr_in *) 248 &qp->ep->com.mapped_local_addr; 249 struct sockaddr_in *mapped_rsin = (struct sockaddr_in *) 250 &qp->ep->com.mapped_remote_addr; 251 252 cc = snprintf(qpd->buf + qpd->pos, space, 253 "rc qp sq id %u rq id %u state %u " 254 "onchip %u ep tid %u state %u " 255 "%pI4:%u/%u->%pI4:%u/%u\n", 256 qp->wq.sq.qid, qp->wq.rq.qid, 257 (int)qp->attr.state, 258 qp->wq.sq.flags & T4_SQ_ONCHIP, 259 qp->ep->hwtid, (int)qp->ep->com.state, 260 &lsin->sin_addr, ntohs(lsin->sin_port), 261 ntohs(mapped_lsin->sin_port), 262 &rsin->sin_addr, ntohs(rsin->sin_port), 263 ntohs(mapped_rsin->sin_port)); 264 } else { 265 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *) 266 &qp->ep->com.local_addr; 267 struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *) 268 &qp->ep->com.remote_addr; 269 struct sockaddr_in6 *mapped_lsin6 = 270 (struct sockaddr_in6 *) 271 &qp->ep->com.mapped_local_addr; 272 struct sockaddr_in6 *mapped_rsin6 = 273 (struct sockaddr_in6 *) 274 &qp->ep->com.mapped_remote_addr; 275 276 cc = snprintf(qpd->buf + qpd->pos, space, 277 "rc qp sq id %u rq id %u state %u " 278 "onchip %u ep tid %u state %u " 279 "%pI6:%u/%u->%pI6:%u/%u\n", 280 qp->wq.sq.qid, qp->wq.rq.qid, 281 (int)qp->attr.state, 282 qp->wq.sq.flags & T4_SQ_ONCHIP, 283 qp->ep->hwtid, (int)qp->ep->com.state, 284 &lsin6->sin6_addr, 285 ntohs(lsin6->sin6_port), 286 ntohs(mapped_lsin6->sin6_port), 287 &rsin6->sin6_addr, 288 ntohs(rsin6->sin6_port), 289 ntohs(mapped_rsin6->sin6_port)); 290 } 291 } else 292 cc = snprintf(qpd->buf + qpd->pos, space, 293 "qp sq id %u rq id %u state %u onchip %u\n", 294 qp->wq.sq.qid, qp->wq.rq.qid, 295 (int)qp->attr.state, 296 qp->wq.sq.flags & T4_SQ_ONCHIP); 297 if (cc < space) 298 qpd->pos += cc; 299 return 0; 300 } 301 302 static int qp_release(struct inode *inode, struct file *file) 303 { 304 struct c4iw_debugfs_data *qpd = file->private_data; 305 if (!qpd) { 306 printk(KERN_INFO "%s null qpd?\n", __func__); 307 return 0; 308 } 309 vfree(qpd->buf); 310 kfree(qpd); 311 return 0; 312 } 313 314 static int qp_open(struct inode *inode, struct file *file) 315 { 316 struct c4iw_debugfs_data *qpd; 317 int ret = 0; 318 int count = 1; 319 320 qpd = kmalloc(sizeof *qpd, GFP_KERNEL); 321 if (!qpd) { 322 ret = -ENOMEM; 323 goto out; 324 } 325 qpd->devp = inode->i_private; 326 qpd->pos = 0; 327 328 spin_lock_irq(&qpd->devp->lock); 329 idr_for_each(&qpd->devp->qpidr, count_idrs, &count); 330 spin_unlock_irq(&qpd->devp->lock); 331 332 qpd->bufsize = count * 128; 333 qpd->buf = vmalloc(qpd->bufsize); 334 if (!qpd->buf) { 335 ret = -ENOMEM; 336 goto err1; 337 } 338 339 spin_lock_irq(&qpd->devp->lock); 340 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd); 341 spin_unlock_irq(&qpd->devp->lock); 342 343 qpd->buf[qpd->pos++] = 0; 344 file->private_data = qpd; 345 goto out; 346 err1: 347 kfree(qpd); 348 out: 349 return ret; 350 } 351 352 static const struct file_operations qp_debugfs_fops = { 353 .owner = THIS_MODULE, 354 .open = qp_open, 355 .release = qp_release, 356 .read = debugfs_read, 357 .llseek = default_llseek, 358 }; 359 360 static int dump_stag(int id, void *p, void *data) 361 { 362 struct c4iw_debugfs_data *stagd = data; 363 int space; 364 int cc; 365 struct fw_ri_tpte tpte; 366 int ret; 367 368 space = stagd->bufsize - stagd->pos - 1; 369 if (space == 0) 370 return 1; 371 372 ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8, 373 (__be32 *)&tpte); 374 if (ret) { 375 dev_err(&stagd->devp->rdev.lldi.pdev->dev, 376 "%s cxgb4_read_tpte err %d\n", __func__, ret); 377 return ret; 378 } 379 cc = snprintf(stagd->buf + stagd->pos, space, 380 "stag: idx 0x%x valid %d key 0x%x state %d pdid %d " 381 "perm 0x%x ps %d len 0x%llx va 0x%llx\n", 382 (u32)id<<8, 383 G_FW_RI_TPTE_VALID(ntohl(tpte.valid_to_pdid)), 384 G_FW_RI_TPTE_STAGKEY(ntohl(tpte.valid_to_pdid)), 385 G_FW_RI_TPTE_STAGSTATE(ntohl(tpte.valid_to_pdid)), 386 G_FW_RI_TPTE_PDID(ntohl(tpte.valid_to_pdid)), 387 G_FW_RI_TPTE_PERM(ntohl(tpte.locread_to_qpid)), 388 G_FW_RI_TPTE_PS(ntohl(tpte.locread_to_qpid)), 389 ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo), 390 ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo)); 391 if (cc < space) 392 stagd->pos += cc; 393 return 0; 394 } 395 396 static int stag_release(struct inode *inode, struct file *file) 397 { 398 struct c4iw_debugfs_data *stagd = file->private_data; 399 if (!stagd) { 400 printk(KERN_INFO "%s null stagd?\n", __func__); 401 return 0; 402 } 403 vfree(stagd->buf); 404 kfree(stagd); 405 return 0; 406 } 407 408 static int stag_open(struct inode *inode, struct file *file) 409 { 410 struct c4iw_debugfs_data *stagd; 411 int ret = 0; 412 int count = 1; 413 414 stagd = kmalloc(sizeof *stagd, GFP_KERNEL); 415 if (!stagd) { 416 ret = -ENOMEM; 417 goto out; 418 } 419 stagd->devp = inode->i_private; 420 stagd->pos = 0; 421 422 spin_lock_irq(&stagd->devp->lock); 423 idr_for_each(&stagd->devp->mmidr, count_idrs, &count); 424 spin_unlock_irq(&stagd->devp->lock); 425 426 stagd->bufsize = count * 256; 427 stagd->buf = vmalloc(stagd->bufsize); 428 if (!stagd->buf) { 429 ret = -ENOMEM; 430 goto err1; 431 } 432 433 spin_lock_irq(&stagd->devp->lock); 434 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd); 435 spin_unlock_irq(&stagd->devp->lock); 436 437 stagd->buf[stagd->pos++] = 0; 438 file->private_data = stagd; 439 goto out; 440 err1: 441 kfree(stagd); 442 out: 443 return ret; 444 } 445 446 static const struct file_operations stag_debugfs_fops = { 447 .owner = THIS_MODULE, 448 .open = stag_open, 449 .release = stag_release, 450 .read = debugfs_read, 451 .llseek = default_llseek, 452 }; 453 454 static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"}; 455 456 static int stats_show(struct seq_file *seq, void *v) 457 { 458 struct c4iw_dev *dev = seq->private; 459 460 seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current", 461 "Max", "Fail"); 462 seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n", 463 dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur, 464 dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail); 465 seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n", 466 dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur, 467 dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail); 468 seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n", 469 dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur, 470 dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail); 471 seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n", 472 dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur, 473 dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail); 474 seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n", 475 dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur, 476 dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail); 477 seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n", 478 dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur, 479 dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail); 480 seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full); 481 seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty); 482 seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop); 483 seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n", 484 db_state_str[dev->db_state], 485 dev->rdev.stats.db_state_transitions, 486 dev->rdev.stats.db_fc_interruptions); 487 seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full); 488 seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n", 489 dev->rdev.stats.act_ofld_conn_fails); 490 seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n", 491 dev->rdev.stats.pas_ofld_conn_fails); 492 seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird); 493 return 0; 494 } 495 496 static int stats_open(struct inode *inode, struct file *file) 497 { 498 return single_open(file, stats_show, inode->i_private); 499 } 500 501 static ssize_t stats_clear(struct file *file, const char __user *buf, 502 size_t count, loff_t *pos) 503 { 504 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private; 505 506 mutex_lock(&dev->rdev.stats.lock); 507 dev->rdev.stats.pd.max = 0; 508 dev->rdev.stats.pd.fail = 0; 509 dev->rdev.stats.qid.max = 0; 510 dev->rdev.stats.qid.fail = 0; 511 dev->rdev.stats.stag.max = 0; 512 dev->rdev.stats.stag.fail = 0; 513 dev->rdev.stats.pbl.max = 0; 514 dev->rdev.stats.pbl.fail = 0; 515 dev->rdev.stats.rqt.max = 0; 516 dev->rdev.stats.rqt.fail = 0; 517 dev->rdev.stats.ocqp.max = 0; 518 dev->rdev.stats.ocqp.fail = 0; 519 dev->rdev.stats.db_full = 0; 520 dev->rdev.stats.db_empty = 0; 521 dev->rdev.stats.db_drop = 0; 522 dev->rdev.stats.db_state_transitions = 0; 523 dev->rdev.stats.tcam_full = 0; 524 dev->rdev.stats.act_ofld_conn_fails = 0; 525 dev->rdev.stats.pas_ofld_conn_fails = 0; 526 mutex_unlock(&dev->rdev.stats.lock); 527 return count; 528 } 529 530 static const struct file_operations stats_debugfs_fops = { 531 .owner = THIS_MODULE, 532 .open = stats_open, 533 .release = single_release, 534 .read = seq_read, 535 .llseek = seq_lseek, 536 .write = stats_clear, 537 }; 538 539 static int dump_ep(int id, void *p, void *data) 540 { 541 struct c4iw_ep *ep = p; 542 struct c4iw_debugfs_data *epd = data; 543 int space; 544 int cc; 545 546 space = epd->bufsize - epd->pos - 1; 547 if (space == 0) 548 return 1; 549 550 if (ep->com.local_addr.ss_family == AF_INET) { 551 struct sockaddr_in *lsin = (struct sockaddr_in *) 552 &ep->com.local_addr; 553 struct sockaddr_in *rsin = (struct sockaddr_in *) 554 &ep->com.remote_addr; 555 struct sockaddr_in *mapped_lsin = (struct sockaddr_in *) 556 &ep->com.mapped_local_addr; 557 struct sockaddr_in *mapped_rsin = (struct sockaddr_in *) 558 &ep->com.mapped_remote_addr; 559 560 cc = snprintf(epd->buf + epd->pos, space, 561 "ep %p cm_id %p qp %p state %d flags 0x%lx " 562 "history 0x%lx hwtid %d atid %d " 563 "%pI4:%d/%d <-> %pI4:%d/%d\n", 564 ep, ep->com.cm_id, ep->com.qp, 565 (int)ep->com.state, ep->com.flags, 566 ep->com.history, ep->hwtid, ep->atid, 567 &lsin->sin_addr, ntohs(lsin->sin_port), 568 ntohs(mapped_lsin->sin_port), 569 &rsin->sin_addr, ntohs(rsin->sin_port), 570 ntohs(mapped_rsin->sin_port)); 571 } else { 572 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *) 573 &ep->com.local_addr; 574 struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *) 575 &ep->com.remote_addr; 576 struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *) 577 &ep->com.mapped_local_addr; 578 struct sockaddr_in6 *mapped_rsin6 = (struct sockaddr_in6 *) 579 &ep->com.mapped_remote_addr; 580 581 cc = snprintf(epd->buf + epd->pos, space, 582 "ep %p cm_id %p qp %p state %d flags 0x%lx " 583 "history 0x%lx hwtid %d atid %d " 584 "%pI6:%d/%d <-> %pI6:%d/%d\n", 585 ep, ep->com.cm_id, ep->com.qp, 586 (int)ep->com.state, ep->com.flags, 587 ep->com.history, ep->hwtid, ep->atid, 588 &lsin6->sin6_addr, ntohs(lsin6->sin6_port), 589 ntohs(mapped_lsin6->sin6_port), 590 &rsin6->sin6_addr, ntohs(rsin6->sin6_port), 591 ntohs(mapped_rsin6->sin6_port)); 592 } 593 if (cc < space) 594 epd->pos += cc; 595 return 0; 596 } 597 598 static int dump_listen_ep(int id, void *p, void *data) 599 { 600 struct c4iw_listen_ep *ep = p; 601 struct c4iw_debugfs_data *epd = data; 602 int space; 603 int cc; 604 605 space = epd->bufsize - epd->pos - 1; 606 if (space == 0) 607 return 1; 608 609 if (ep->com.local_addr.ss_family == AF_INET) { 610 struct sockaddr_in *lsin = (struct sockaddr_in *) 611 &ep->com.local_addr; 612 struct sockaddr_in *mapped_lsin = (struct sockaddr_in *) 613 &ep->com.mapped_local_addr; 614 615 cc = snprintf(epd->buf + epd->pos, space, 616 "ep %p cm_id %p state %d flags 0x%lx stid %d " 617 "backlog %d %pI4:%d/%d\n", 618 ep, ep->com.cm_id, (int)ep->com.state, 619 ep->com.flags, ep->stid, ep->backlog, 620 &lsin->sin_addr, ntohs(lsin->sin_port), 621 ntohs(mapped_lsin->sin_port)); 622 } else { 623 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *) 624 &ep->com.local_addr; 625 struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *) 626 &ep->com.mapped_local_addr; 627 628 cc = snprintf(epd->buf + epd->pos, space, 629 "ep %p cm_id %p state %d flags 0x%lx stid %d " 630 "backlog %d %pI6:%d/%d\n", 631 ep, ep->com.cm_id, (int)ep->com.state, 632 ep->com.flags, ep->stid, ep->backlog, 633 &lsin6->sin6_addr, ntohs(lsin6->sin6_port), 634 ntohs(mapped_lsin6->sin6_port)); 635 } 636 if (cc < space) 637 epd->pos += cc; 638 return 0; 639 } 640 641 static int ep_release(struct inode *inode, struct file *file) 642 { 643 struct c4iw_debugfs_data *epd = file->private_data; 644 if (!epd) { 645 pr_info("%s null qpd?\n", __func__); 646 return 0; 647 } 648 vfree(epd->buf); 649 kfree(epd); 650 return 0; 651 } 652 653 static int ep_open(struct inode *inode, struct file *file) 654 { 655 struct c4iw_debugfs_data *epd; 656 int ret = 0; 657 int count = 1; 658 659 epd = kmalloc(sizeof(*epd), GFP_KERNEL); 660 if (!epd) { 661 ret = -ENOMEM; 662 goto out; 663 } 664 epd->devp = inode->i_private; 665 epd->pos = 0; 666 667 spin_lock_irq(&epd->devp->lock); 668 idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count); 669 idr_for_each(&epd->devp->atid_idr, count_idrs, &count); 670 idr_for_each(&epd->devp->stid_idr, count_idrs, &count); 671 spin_unlock_irq(&epd->devp->lock); 672 673 epd->bufsize = count * 160; 674 epd->buf = vmalloc(epd->bufsize); 675 if (!epd->buf) { 676 ret = -ENOMEM; 677 goto err1; 678 } 679 680 spin_lock_irq(&epd->devp->lock); 681 idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd); 682 idr_for_each(&epd->devp->atid_idr, dump_ep, epd); 683 idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd); 684 spin_unlock_irq(&epd->devp->lock); 685 686 file->private_data = epd; 687 goto out; 688 err1: 689 kfree(epd); 690 out: 691 return ret; 692 } 693 694 static const struct file_operations ep_debugfs_fops = { 695 .owner = THIS_MODULE, 696 .open = ep_open, 697 .release = ep_release, 698 .read = debugfs_read, 699 }; 700 701 static int setup_debugfs(struct c4iw_dev *devp) 702 { 703 struct dentry *de; 704 705 if (!devp->debugfs_root) 706 return -1; 707 708 de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root, 709 (void *)devp, &qp_debugfs_fops); 710 if (de && de->d_inode) 711 de->d_inode->i_size = 4096; 712 713 de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root, 714 (void *)devp, &stag_debugfs_fops); 715 if (de && de->d_inode) 716 de->d_inode->i_size = 4096; 717 718 de = debugfs_create_file("stats", S_IWUSR, devp->debugfs_root, 719 (void *)devp, &stats_debugfs_fops); 720 if (de && de->d_inode) 721 de->d_inode->i_size = 4096; 722 723 de = debugfs_create_file("eps", S_IWUSR, devp->debugfs_root, 724 (void *)devp, &ep_debugfs_fops); 725 if (de && de->d_inode) 726 de->d_inode->i_size = 4096; 727 728 if (c4iw_wr_log) { 729 de = debugfs_create_file("wr_log", S_IWUSR, devp->debugfs_root, 730 (void *)devp, &wr_log_debugfs_fops); 731 if (de && de->d_inode) 732 de->d_inode->i_size = 4096; 733 } 734 return 0; 735 } 736 737 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 738 struct c4iw_dev_ucontext *uctx) 739 { 740 struct list_head *pos, *nxt; 741 struct c4iw_qid_list *entry; 742 743 mutex_lock(&uctx->lock); 744 list_for_each_safe(pos, nxt, &uctx->qpids) { 745 entry = list_entry(pos, struct c4iw_qid_list, entry); 746 list_del_init(&entry->entry); 747 if (!(entry->qid & rdev->qpmask)) { 748 c4iw_put_resource(&rdev->resource.qid_table, 749 entry->qid); 750 mutex_lock(&rdev->stats.lock); 751 rdev->stats.qid.cur -= rdev->qpmask + 1; 752 mutex_unlock(&rdev->stats.lock); 753 } 754 kfree(entry); 755 } 756 757 list_for_each_safe(pos, nxt, &uctx->qpids) { 758 entry = list_entry(pos, struct c4iw_qid_list, entry); 759 list_del_init(&entry->entry); 760 kfree(entry); 761 } 762 mutex_unlock(&uctx->lock); 763 } 764 765 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 766 struct c4iw_dev_ucontext *uctx) 767 { 768 INIT_LIST_HEAD(&uctx->qpids); 769 INIT_LIST_HEAD(&uctx->cqids); 770 mutex_init(&uctx->lock); 771 } 772 773 /* Caller takes care of locking if needed */ 774 static int c4iw_rdev_open(struct c4iw_rdev *rdev) 775 { 776 int err; 777 778 c4iw_init_dev_ucontext(rdev, &rdev->uctx); 779 780 /* 781 * qpshift is the number of bits to shift the qpid left in order 782 * to get the correct address of the doorbell for that qp. 783 */ 784 rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density); 785 rdev->qpmask = rdev->lldi.udb_density - 1; 786 rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density); 787 rdev->cqmask = rdev->lldi.ucq_density - 1; 788 PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d " 789 "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x " 790 "qp qid start %u size %u cq qid start %u size %u\n", 791 __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start, 792 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev), 793 rdev->lldi.vr->pbl.start, 794 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start, 795 rdev->lldi.vr->rq.size, 796 rdev->lldi.vr->qp.start, 797 rdev->lldi.vr->qp.size, 798 rdev->lldi.vr->cq.start, 799 rdev->lldi.vr->cq.size); 800 PDBG("udb len 0x%x udb base %llx db_reg %p gts_reg %p qpshift %lu " 801 "qpmask 0x%x cqshift %lu cqmask 0x%x\n", 802 (unsigned)pci_resource_len(rdev->lldi.pdev, 2), 803 (u64)pci_resource_start(rdev->lldi.pdev, 2), 804 rdev->lldi.db_reg, 805 rdev->lldi.gts_reg, 806 rdev->qpshift, rdev->qpmask, 807 rdev->cqshift, rdev->cqmask); 808 809 if (c4iw_num_stags(rdev) == 0) { 810 err = -EINVAL; 811 goto err1; 812 } 813 814 rdev->stats.pd.total = T4_MAX_NUM_PD; 815 rdev->stats.stag.total = rdev->lldi.vr->stag.size; 816 rdev->stats.pbl.total = rdev->lldi.vr->pbl.size; 817 rdev->stats.rqt.total = rdev->lldi.vr->rq.size; 818 rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size; 819 rdev->stats.qid.total = rdev->lldi.vr->qp.size; 820 821 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD); 822 if (err) { 823 printk(KERN_ERR MOD "error %d initializing resources\n", err); 824 goto err1; 825 } 826 err = c4iw_pblpool_create(rdev); 827 if (err) { 828 printk(KERN_ERR MOD "error %d initializing pbl pool\n", err); 829 goto err2; 830 } 831 err = c4iw_rqtpool_create(rdev); 832 if (err) { 833 printk(KERN_ERR MOD "error %d initializing rqt pool\n", err); 834 goto err3; 835 } 836 err = c4iw_ocqp_pool_create(rdev); 837 if (err) { 838 printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err); 839 goto err4; 840 } 841 rdev->status_page = (struct t4_dev_status_page *) 842 __get_free_page(GFP_KERNEL); 843 if (!rdev->status_page) { 844 pr_err(MOD "error allocating status page\n"); 845 goto err4; 846 } 847 848 if (c4iw_wr_log) { 849 rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) * 850 sizeof(*rdev->wr_log), GFP_KERNEL); 851 if (rdev->wr_log) { 852 rdev->wr_log_size = 1 << c4iw_wr_log_size_order; 853 atomic_set(&rdev->wr_log_idx, 0); 854 } else { 855 pr_err(MOD "error allocating wr_log. Logging disabled\n"); 856 } 857 } 858 859 rdev->status_page->db_off = 0; 860 861 return 0; 862 err4: 863 c4iw_rqtpool_destroy(rdev); 864 err3: 865 c4iw_pblpool_destroy(rdev); 866 err2: 867 c4iw_destroy_resource(&rdev->resource); 868 err1: 869 return err; 870 } 871 872 static void c4iw_rdev_close(struct c4iw_rdev *rdev) 873 { 874 kfree(rdev->wr_log); 875 free_page((unsigned long)rdev->status_page); 876 c4iw_pblpool_destroy(rdev); 877 c4iw_rqtpool_destroy(rdev); 878 c4iw_destroy_resource(&rdev->resource); 879 } 880 881 static void c4iw_dealloc(struct uld_ctx *ctx) 882 { 883 c4iw_rdev_close(&ctx->dev->rdev); 884 idr_destroy(&ctx->dev->cqidr); 885 idr_destroy(&ctx->dev->qpidr); 886 idr_destroy(&ctx->dev->mmidr); 887 idr_destroy(&ctx->dev->hwtid_idr); 888 idr_destroy(&ctx->dev->stid_idr); 889 idr_destroy(&ctx->dev->atid_idr); 890 if (ctx->dev->rdev.bar2_kva) 891 iounmap(ctx->dev->rdev.bar2_kva); 892 if (ctx->dev->rdev.oc_mw_kva) 893 iounmap(ctx->dev->rdev.oc_mw_kva); 894 ib_dealloc_device(&ctx->dev->ibdev); 895 ctx->dev = NULL; 896 } 897 898 static void c4iw_remove(struct uld_ctx *ctx) 899 { 900 PDBG("%s c4iw_dev %p\n", __func__, ctx->dev); 901 c4iw_unregister_device(ctx->dev); 902 c4iw_dealloc(ctx); 903 } 904 905 static int rdma_supported(const struct cxgb4_lld_info *infop) 906 { 907 return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 && 908 infop->vr->rq.size > 0 && infop->vr->qp.size > 0 && 909 infop->vr->cq.size > 0; 910 } 911 912 static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop) 913 { 914 struct c4iw_dev *devp; 915 int ret; 916 917 if (!rdma_supported(infop)) { 918 printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n", 919 pci_name(infop->pdev)); 920 return ERR_PTR(-ENOSYS); 921 } 922 if (!ocqp_supported(infop)) 923 pr_info("%s: On-Chip Queues not supported on this device.\n", 924 pci_name(infop->pdev)); 925 926 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp)); 927 if (!devp) { 928 printk(KERN_ERR MOD "Cannot allocate ib device\n"); 929 return ERR_PTR(-ENOMEM); 930 } 931 devp->rdev.lldi = *infop; 932 933 /* init various hw-queue params based on lld info */ 934 PDBG("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n", 935 __func__, devp->rdev.lldi.sge_ingpadboundary, 936 devp->rdev.lldi.sge_egrstatuspagesize); 937 938 devp->rdev.hw_queue.t4_eq_status_entries = 939 devp->rdev.lldi.sge_ingpadboundary > 64 ? 2 : 1; 940 devp->rdev.hw_queue.t4_max_eq_size = 65520; 941 devp->rdev.hw_queue.t4_max_iq_size = 65520; 942 devp->rdev.hw_queue.t4_max_rq_size = 8192 - 943 devp->rdev.hw_queue.t4_eq_status_entries - 1; 944 devp->rdev.hw_queue.t4_max_sq_size = 945 devp->rdev.hw_queue.t4_max_eq_size - 946 devp->rdev.hw_queue.t4_eq_status_entries - 1; 947 devp->rdev.hw_queue.t4_max_qp_depth = 948 devp->rdev.hw_queue.t4_max_rq_size; 949 devp->rdev.hw_queue.t4_max_cq_depth = 950 devp->rdev.hw_queue.t4_max_iq_size - 2; 951 devp->rdev.hw_queue.t4_stat_len = 952 devp->rdev.lldi.sge_egrstatuspagesize; 953 954 /* 955 * For T5 devices, we map all of BAR2 with WC. 956 * For T4 devices with onchip qp mem, we map only that part 957 * of BAR2 with WC. 958 */ 959 devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2); 960 if (is_t5(devp->rdev.lldi.adapter_type)) { 961 devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa, 962 pci_resource_len(devp->rdev.lldi.pdev, 2)); 963 if (!devp->rdev.bar2_kva) { 964 pr_err(MOD "Unable to ioremap BAR2\n"); 965 ib_dealloc_device(&devp->ibdev); 966 return ERR_PTR(-EINVAL); 967 } 968 } else if (ocqp_supported(infop)) { 969 devp->rdev.oc_mw_pa = 970 pci_resource_start(devp->rdev.lldi.pdev, 2) + 971 pci_resource_len(devp->rdev.lldi.pdev, 2) - 972 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size); 973 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa, 974 devp->rdev.lldi.vr->ocq.size); 975 if (!devp->rdev.oc_mw_kva) { 976 pr_err(MOD "Unable to ioremap onchip mem\n"); 977 ib_dealloc_device(&devp->ibdev); 978 return ERR_PTR(-EINVAL); 979 } 980 } 981 982 PDBG(KERN_INFO MOD "ocq memory: " 983 "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n", 984 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size, 985 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva); 986 987 ret = c4iw_rdev_open(&devp->rdev); 988 if (ret) { 989 printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret); 990 ib_dealloc_device(&devp->ibdev); 991 return ERR_PTR(ret); 992 } 993 994 idr_init(&devp->cqidr); 995 idr_init(&devp->qpidr); 996 idr_init(&devp->mmidr); 997 idr_init(&devp->hwtid_idr); 998 idr_init(&devp->stid_idr); 999 idr_init(&devp->atid_idr); 1000 spin_lock_init(&devp->lock); 1001 mutex_init(&devp->rdev.stats.lock); 1002 mutex_init(&devp->db_mutex); 1003 INIT_LIST_HEAD(&devp->db_fc_list); 1004 devp->avail_ird = devp->rdev.lldi.max_ird_adapter; 1005 1006 if (c4iw_debugfs_root) { 1007 devp->debugfs_root = debugfs_create_dir( 1008 pci_name(devp->rdev.lldi.pdev), 1009 c4iw_debugfs_root); 1010 setup_debugfs(devp); 1011 } 1012 1013 1014 return devp; 1015 } 1016 1017 static void *c4iw_uld_add(const struct cxgb4_lld_info *infop) 1018 { 1019 struct uld_ctx *ctx; 1020 static int vers_printed; 1021 int i; 1022 1023 if (!vers_printed++) 1024 pr_info("Chelsio T4/T5 RDMA Driver - version %s\n", 1025 DRV_VERSION); 1026 1027 ctx = kzalloc(sizeof *ctx, GFP_KERNEL); 1028 if (!ctx) { 1029 ctx = ERR_PTR(-ENOMEM); 1030 goto out; 1031 } 1032 ctx->lldi = *infop; 1033 1034 PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n", 1035 __func__, pci_name(ctx->lldi.pdev), 1036 ctx->lldi.nchan, ctx->lldi.nrxq, 1037 ctx->lldi.ntxq, ctx->lldi.nports); 1038 1039 mutex_lock(&dev_mutex); 1040 list_add_tail(&ctx->entry, &uld_ctx_list); 1041 mutex_unlock(&dev_mutex); 1042 1043 for (i = 0; i < ctx->lldi.nrxq; i++) 1044 PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]); 1045 out: 1046 return ctx; 1047 } 1048 1049 static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl, 1050 const __be64 *rsp, 1051 u32 pktshift) 1052 { 1053 struct sk_buff *skb; 1054 1055 /* 1056 * Allocate space for cpl_pass_accept_req which will be synthesized by 1057 * driver. Once the driver synthesizes the request the skb will go 1058 * through the regular cpl_pass_accept_req processing. 1059 * The math here assumes sizeof cpl_pass_accept_req >= sizeof 1060 * cpl_rx_pkt. 1061 */ 1062 skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1063 sizeof(struct rss_header) - pktshift, GFP_ATOMIC); 1064 if (unlikely(!skb)) 1065 return NULL; 1066 1067 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1068 sizeof(struct rss_header) - pktshift); 1069 1070 /* 1071 * This skb will contain: 1072 * rss_header from the rspq descriptor (1 flit) 1073 * cpl_rx_pkt struct from the rspq descriptor (2 flits) 1074 * space for the difference between the size of an 1075 * rx_pkt and pass_accept_req cpl (1 flit) 1076 * the packet data from the gl 1077 */ 1078 skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) + 1079 sizeof(struct rss_header)); 1080 skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) + 1081 sizeof(struct cpl_pass_accept_req), 1082 gl->va + pktshift, 1083 gl->tot_len - pktshift); 1084 return skb; 1085 } 1086 1087 static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl, 1088 const __be64 *rsp) 1089 { 1090 unsigned int opcode = *(u8 *)rsp; 1091 struct sk_buff *skb; 1092 1093 if (opcode != CPL_RX_PKT) 1094 goto out; 1095 1096 skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift); 1097 if (skb == NULL) 1098 goto out; 1099 1100 if (c4iw_handlers[opcode] == NULL) { 1101 pr_info("%s no handler opcode 0x%x...\n", __func__, 1102 opcode); 1103 kfree_skb(skb); 1104 goto out; 1105 } 1106 c4iw_handlers[opcode](dev, skb); 1107 return 1; 1108 out: 1109 return 0; 1110 } 1111 1112 static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp, 1113 const struct pkt_gl *gl) 1114 { 1115 struct uld_ctx *ctx = handle; 1116 struct c4iw_dev *dev = ctx->dev; 1117 struct sk_buff *skb; 1118 u8 opcode; 1119 1120 if (gl == NULL) { 1121 /* omit RSS and rsp_ctrl at end of descriptor */ 1122 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8; 1123 1124 skb = alloc_skb(256, GFP_ATOMIC); 1125 if (!skb) 1126 goto nomem; 1127 __skb_put(skb, len); 1128 skb_copy_to_linear_data(skb, &rsp[1], len); 1129 } else if (gl == CXGB4_MSG_AN) { 1130 const struct rsp_ctrl *rc = (void *)rsp; 1131 1132 u32 qid = be32_to_cpu(rc->pldbuflen_qid); 1133 c4iw_ev_handler(dev, qid); 1134 return 0; 1135 } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) { 1136 if (recv_rx_pkt(dev, gl, rsp)) 1137 return 0; 1138 1139 pr_info("%s: unexpected FL contents at %p, " \ 1140 "RSS %#llx, FL %#llx, len %u\n", 1141 pci_name(ctx->lldi.pdev), gl->va, 1142 (unsigned long long)be64_to_cpu(*rsp), 1143 (unsigned long long)be64_to_cpu( 1144 *(__force __be64 *)gl->va), 1145 gl->tot_len); 1146 1147 return 0; 1148 } else { 1149 skb = cxgb4_pktgl_to_skb(gl, 128, 128); 1150 if (unlikely(!skb)) 1151 goto nomem; 1152 } 1153 1154 opcode = *(u8 *)rsp; 1155 if (c4iw_handlers[opcode]) { 1156 c4iw_handlers[opcode](dev, skb); 1157 } else { 1158 pr_info("%s no handler opcode 0x%x...\n", __func__, 1159 opcode); 1160 kfree_skb(skb); 1161 } 1162 1163 return 0; 1164 nomem: 1165 return -1; 1166 } 1167 1168 static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state) 1169 { 1170 struct uld_ctx *ctx = handle; 1171 1172 PDBG("%s new_state %u\n", __func__, new_state); 1173 switch (new_state) { 1174 case CXGB4_STATE_UP: 1175 printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev)); 1176 if (!ctx->dev) { 1177 int ret; 1178 1179 ctx->dev = c4iw_alloc(&ctx->lldi); 1180 if (IS_ERR(ctx->dev)) { 1181 printk(KERN_ERR MOD 1182 "%s: initialization failed: %ld\n", 1183 pci_name(ctx->lldi.pdev), 1184 PTR_ERR(ctx->dev)); 1185 ctx->dev = NULL; 1186 break; 1187 } 1188 ret = c4iw_register_device(ctx->dev); 1189 if (ret) { 1190 printk(KERN_ERR MOD 1191 "%s: RDMA registration failed: %d\n", 1192 pci_name(ctx->lldi.pdev), ret); 1193 c4iw_dealloc(ctx); 1194 } 1195 } 1196 break; 1197 case CXGB4_STATE_DOWN: 1198 printk(KERN_INFO MOD "%s: Down\n", 1199 pci_name(ctx->lldi.pdev)); 1200 if (ctx->dev) 1201 c4iw_remove(ctx); 1202 break; 1203 case CXGB4_STATE_START_RECOVERY: 1204 printk(KERN_INFO MOD "%s: Fatal Error\n", 1205 pci_name(ctx->lldi.pdev)); 1206 if (ctx->dev) { 1207 struct ib_event event; 1208 1209 ctx->dev->rdev.flags |= T4_FATAL_ERROR; 1210 memset(&event, 0, sizeof event); 1211 event.event = IB_EVENT_DEVICE_FATAL; 1212 event.device = &ctx->dev->ibdev; 1213 ib_dispatch_event(&event); 1214 c4iw_remove(ctx); 1215 } 1216 break; 1217 case CXGB4_STATE_DETACH: 1218 printk(KERN_INFO MOD "%s: Detach\n", 1219 pci_name(ctx->lldi.pdev)); 1220 if (ctx->dev) 1221 c4iw_remove(ctx); 1222 break; 1223 } 1224 return 0; 1225 } 1226 1227 static int disable_qp_db(int id, void *p, void *data) 1228 { 1229 struct c4iw_qp *qp = p; 1230 1231 t4_disable_wq_db(&qp->wq); 1232 return 0; 1233 } 1234 1235 static void stop_queues(struct uld_ctx *ctx) 1236 { 1237 unsigned long flags; 1238 1239 spin_lock_irqsave(&ctx->dev->lock, flags); 1240 ctx->dev->rdev.stats.db_state_transitions++; 1241 ctx->dev->db_state = STOPPED; 1242 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) 1243 idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL); 1244 else 1245 ctx->dev->rdev.status_page->db_off = 1; 1246 spin_unlock_irqrestore(&ctx->dev->lock, flags); 1247 } 1248 1249 static int enable_qp_db(int id, void *p, void *data) 1250 { 1251 struct c4iw_qp *qp = p; 1252 1253 t4_enable_wq_db(&qp->wq); 1254 return 0; 1255 } 1256 1257 static void resume_rc_qp(struct c4iw_qp *qp) 1258 { 1259 spin_lock(&qp->lock); 1260 t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, 1261 is_t5(qp->rhp->rdev.lldi.adapter_type), NULL); 1262 qp->wq.sq.wq_pidx_inc = 0; 1263 t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, 1264 is_t5(qp->rhp->rdev.lldi.adapter_type), NULL); 1265 qp->wq.rq.wq_pidx_inc = 0; 1266 spin_unlock(&qp->lock); 1267 } 1268 1269 static void resume_a_chunk(struct uld_ctx *ctx) 1270 { 1271 int i; 1272 struct c4iw_qp *qp; 1273 1274 for (i = 0; i < DB_FC_RESUME_SIZE; i++) { 1275 qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp, 1276 db_fc_entry); 1277 list_del_init(&qp->db_fc_entry); 1278 resume_rc_qp(qp); 1279 if (list_empty(&ctx->dev->db_fc_list)) 1280 break; 1281 } 1282 } 1283 1284 static void resume_queues(struct uld_ctx *ctx) 1285 { 1286 spin_lock_irq(&ctx->dev->lock); 1287 if (ctx->dev->db_state != STOPPED) 1288 goto out; 1289 ctx->dev->db_state = FLOW_CONTROL; 1290 while (1) { 1291 if (list_empty(&ctx->dev->db_fc_list)) { 1292 WARN_ON(ctx->dev->db_state != FLOW_CONTROL); 1293 ctx->dev->db_state = NORMAL; 1294 ctx->dev->rdev.stats.db_state_transitions++; 1295 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) { 1296 idr_for_each(&ctx->dev->qpidr, enable_qp_db, 1297 NULL); 1298 } else { 1299 ctx->dev->rdev.status_page->db_off = 0; 1300 } 1301 break; 1302 } else { 1303 if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1) 1304 < (ctx->dev->rdev.lldi.dbfifo_int_thresh << 1305 DB_FC_DRAIN_THRESH)) { 1306 resume_a_chunk(ctx); 1307 } 1308 if (!list_empty(&ctx->dev->db_fc_list)) { 1309 spin_unlock_irq(&ctx->dev->lock); 1310 if (DB_FC_RESUME_DELAY) { 1311 set_current_state(TASK_UNINTERRUPTIBLE); 1312 schedule_timeout(DB_FC_RESUME_DELAY); 1313 } 1314 spin_lock_irq(&ctx->dev->lock); 1315 if (ctx->dev->db_state != FLOW_CONTROL) 1316 break; 1317 } 1318 } 1319 } 1320 out: 1321 if (ctx->dev->db_state != NORMAL) 1322 ctx->dev->rdev.stats.db_fc_interruptions++; 1323 spin_unlock_irq(&ctx->dev->lock); 1324 } 1325 1326 struct qp_list { 1327 unsigned idx; 1328 struct c4iw_qp **qps; 1329 }; 1330 1331 static int add_and_ref_qp(int id, void *p, void *data) 1332 { 1333 struct qp_list *qp_listp = data; 1334 struct c4iw_qp *qp = p; 1335 1336 c4iw_qp_add_ref(&qp->ibqp); 1337 qp_listp->qps[qp_listp->idx++] = qp; 1338 return 0; 1339 } 1340 1341 static int count_qps(int id, void *p, void *data) 1342 { 1343 unsigned *countp = data; 1344 (*countp)++; 1345 return 0; 1346 } 1347 1348 static void deref_qps(struct qp_list *qp_list) 1349 { 1350 int idx; 1351 1352 for (idx = 0; idx < qp_list->idx; idx++) 1353 c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp); 1354 } 1355 1356 static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list) 1357 { 1358 int idx; 1359 int ret; 1360 1361 for (idx = 0; idx < qp_list->idx; idx++) { 1362 struct c4iw_qp *qp = qp_list->qps[idx]; 1363 1364 spin_lock_irq(&qp->rhp->lock); 1365 spin_lock(&qp->lock); 1366 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0], 1367 qp->wq.sq.qid, 1368 t4_sq_host_wq_pidx(&qp->wq), 1369 t4_sq_wq_size(&qp->wq)); 1370 if (ret) { 1371 pr_err(KERN_ERR MOD "%s: Fatal error - " 1372 "DB overflow recovery failed - " 1373 "error syncing SQ qid %u\n", 1374 pci_name(ctx->lldi.pdev), qp->wq.sq.qid); 1375 spin_unlock(&qp->lock); 1376 spin_unlock_irq(&qp->rhp->lock); 1377 return; 1378 } 1379 qp->wq.sq.wq_pidx_inc = 0; 1380 1381 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0], 1382 qp->wq.rq.qid, 1383 t4_rq_host_wq_pidx(&qp->wq), 1384 t4_rq_wq_size(&qp->wq)); 1385 1386 if (ret) { 1387 pr_err(KERN_ERR MOD "%s: Fatal error - " 1388 "DB overflow recovery failed - " 1389 "error syncing RQ qid %u\n", 1390 pci_name(ctx->lldi.pdev), qp->wq.rq.qid); 1391 spin_unlock(&qp->lock); 1392 spin_unlock_irq(&qp->rhp->lock); 1393 return; 1394 } 1395 qp->wq.rq.wq_pidx_inc = 0; 1396 spin_unlock(&qp->lock); 1397 spin_unlock_irq(&qp->rhp->lock); 1398 1399 /* Wait for the dbfifo to drain */ 1400 while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) { 1401 set_current_state(TASK_UNINTERRUPTIBLE); 1402 schedule_timeout(usecs_to_jiffies(10)); 1403 } 1404 } 1405 } 1406 1407 static void recover_queues(struct uld_ctx *ctx) 1408 { 1409 int count = 0; 1410 struct qp_list qp_list; 1411 int ret; 1412 1413 /* slow everybody down */ 1414 set_current_state(TASK_UNINTERRUPTIBLE); 1415 schedule_timeout(usecs_to_jiffies(1000)); 1416 1417 /* flush the SGE contexts */ 1418 ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]); 1419 if (ret) { 1420 printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n", 1421 pci_name(ctx->lldi.pdev)); 1422 return; 1423 } 1424 1425 /* Count active queues so we can build a list of queues to recover */ 1426 spin_lock_irq(&ctx->dev->lock); 1427 WARN_ON(ctx->dev->db_state != STOPPED); 1428 ctx->dev->db_state = RECOVERY; 1429 idr_for_each(&ctx->dev->qpidr, count_qps, &count); 1430 1431 qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC); 1432 if (!qp_list.qps) { 1433 printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n", 1434 pci_name(ctx->lldi.pdev)); 1435 spin_unlock_irq(&ctx->dev->lock); 1436 return; 1437 } 1438 qp_list.idx = 0; 1439 1440 /* add and ref each qp so it doesn't get freed */ 1441 idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list); 1442 1443 spin_unlock_irq(&ctx->dev->lock); 1444 1445 /* now traverse the list in a safe context to recover the db state*/ 1446 recover_lost_dbs(ctx, &qp_list); 1447 1448 /* we're almost done! deref the qps and clean up */ 1449 deref_qps(&qp_list); 1450 kfree(qp_list.qps); 1451 1452 spin_lock_irq(&ctx->dev->lock); 1453 WARN_ON(ctx->dev->db_state != RECOVERY); 1454 ctx->dev->db_state = STOPPED; 1455 spin_unlock_irq(&ctx->dev->lock); 1456 } 1457 1458 static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...) 1459 { 1460 struct uld_ctx *ctx = handle; 1461 1462 switch (control) { 1463 case CXGB4_CONTROL_DB_FULL: 1464 stop_queues(ctx); 1465 ctx->dev->rdev.stats.db_full++; 1466 break; 1467 case CXGB4_CONTROL_DB_EMPTY: 1468 resume_queues(ctx); 1469 mutex_lock(&ctx->dev->rdev.stats.lock); 1470 ctx->dev->rdev.stats.db_empty++; 1471 mutex_unlock(&ctx->dev->rdev.stats.lock); 1472 break; 1473 case CXGB4_CONTROL_DB_DROP: 1474 recover_queues(ctx); 1475 mutex_lock(&ctx->dev->rdev.stats.lock); 1476 ctx->dev->rdev.stats.db_drop++; 1477 mutex_unlock(&ctx->dev->rdev.stats.lock); 1478 break; 1479 default: 1480 printk(KERN_WARNING MOD "%s: unknown control cmd %u\n", 1481 pci_name(ctx->lldi.pdev), control); 1482 break; 1483 } 1484 return 0; 1485 } 1486 1487 static struct cxgb4_uld_info c4iw_uld_info = { 1488 .name = DRV_NAME, 1489 .add = c4iw_uld_add, 1490 .rx_handler = c4iw_uld_rx_handler, 1491 .state_change = c4iw_uld_state_change, 1492 .control = c4iw_uld_control, 1493 }; 1494 1495 static int __init c4iw_init_module(void) 1496 { 1497 int err; 1498 1499 err = c4iw_cm_init(); 1500 if (err) 1501 return err; 1502 1503 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL); 1504 if (!c4iw_debugfs_root) 1505 printk(KERN_WARNING MOD 1506 "could not create debugfs entry, continuing\n"); 1507 1508 if (ibnl_add_client(RDMA_NL_C4IW, RDMA_NL_IWPM_NUM_OPS, 1509 c4iw_nl_cb_table)) 1510 pr_err("%s[%u]: Failed to add netlink callback\n" 1511 , __func__, __LINE__); 1512 1513 err = iwpm_init(RDMA_NL_C4IW); 1514 if (err) { 1515 pr_err("port mapper initialization failed with %d\n", err); 1516 ibnl_remove_client(RDMA_NL_C4IW); 1517 c4iw_cm_term(); 1518 debugfs_remove_recursive(c4iw_debugfs_root); 1519 return err; 1520 } 1521 1522 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info); 1523 1524 return 0; 1525 } 1526 1527 static void __exit c4iw_exit_module(void) 1528 { 1529 struct uld_ctx *ctx, *tmp; 1530 1531 mutex_lock(&dev_mutex); 1532 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) { 1533 if (ctx->dev) 1534 c4iw_remove(ctx); 1535 kfree(ctx); 1536 } 1537 mutex_unlock(&dev_mutex); 1538 cxgb4_unregister_uld(CXGB4_ULD_RDMA); 1539 iwpm_exit(RDMA_NL_C4IW); 1540 ibnl_remove_client(RDMA_NL_C4IW); 1541 c4iw_cm_term(); 1542 debugfs_remove_recursive(c4iw_debugfs_root); 1543 } 1544 1545 module_init(c4iw_init_module); 1546 module_exit(c4iw_exit_module); 1547