1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_tlv.h" 52 53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56 /* Device */ 57 58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59 { 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67 } 68 69 void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw) 70 { 71 struct creq_query_version_resp resp = {}; 72 struct bnxt_qplib_cmdqmsg msg = {}; 73 struct cmdq_query_version req = {}; 74 struct bnxt_qplib_dev_attr *attr; 75 int rc; 76 77 attr = rcfw->res->dattr; 78 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 79 CMDQ_BASE_OPCODE_QUERY_VERSION, 80 sizeof(req)); 81 82 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 83 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 84 if (rc) 85 return; 86 attr->fw_ver[0] = resp.fw_maj; 87 attr->fw_ver[1] = resp.fw_minor; 88 attr->fw_ver[2] = resp.fw_bld; 89 attr->fw_ver[3] = resp.fw_rsvd; 90 } 91 92 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw) 93 { 94 struct bnxt_qplib_dev_attr *attr = rcfw->res->dattr; 95 struct creq_query_func_resp resp = {}; 96 struct bnxt_qplib_cmdqmsg msg = {}; 97 struct creq_query_func_resp_sb *sb; 98 struct bnxt_qplib_rcfw_sbuf sbuf; 99 struct bnxt_qplib_chip_ctx *cctx; 100 struct cmdq_query_func req = {}; 101 u8 *tqm_alloc; 102 int i, rc; 103 u32 temp; 104 105 cctx = rcfw->res->cctx; 106 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 107 CMDQ_BASE_OPCODE_QUERY_FUNC, 108 sizeof(req)); 109 110 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 111 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 112 &sbuf.dma_addr, GFP_KERNEL); 113 if (!sbuf.sb) 114 return -ENOMEM; 115 sb = sbuf.sb; 116 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 117 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 118 sizeof(resp), 0); 119 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 120 if (rc) 121 goto bail; 122 123 /* Extract the context from the side buffer */ 124 attr->max_qp = le32_to_cpu(sb->max_qp); 125 /* max_qp value reported by FW doesn't include the QP1 */ 126 attr->max_qp += 1; 127 attr->max_qp_rd_atom = 128 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 130 attr->max_qp_init_rd_atom = 131 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 132 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 133 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr) - 1; 134 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) { 135 /* 136 * 128 WQEs needs to be reserved for the HW (8916). Prevent 137 * reporting the max number on legacy devices 138 */ 139 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 140 } 141 142 /* Adjust for max_qp_wqes for variable wqe */ 143 if (cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 144 attr->max_qp_wqes = BNXT_VAR_MAX_WQE - 1; 145 146 attr->max_qp_sges = cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE ? 147 min_t(u32, sb->max_sge_var_wqe, BNXT_VAR_MAX_SGE) : 6; 148 attr->max_cq = le32_to_cpu(sb->max_cq); 149 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 150 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 151 attr->max_cq_wqes = min_t(u32, BNXT_QPLIB_MAX_CQ_WQES, attr->max_cq_wqes); 152 attr->max_cq_sges = attr->max_qp_sges; 153 attr->max_mr = le32_to_cpu(sb->max_mr); 154 attr->max_mw = le32_to_cpu(sb->max_mw); 155 156 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 157 attr->max_pd = 64 * 1024; 158 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 159 attr->max_ah = le32_to_cpu(sb->max_ah); 160 161 attr->max_srq = le16_to_cpu(sb->max_srq); 162 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 163 attr->max_srq_sges = sb->max_srq_sge; 164 attr->max_pkey = 1; 165 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 166 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 167 attr->l2_db_size = (sb->l2_db_space_size + 1) * 168 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 169 /* 170 * Read the max gid supported by HW. 171 * For each entry in HW GID in HW table, we consume 2 172 * GID entries in the kernel GID table. So max_gid reported 173 * to stack can be up to twice the value reported by the HW, up to 256 gids. 174 */ 175 attr->max_sgid = le32_to_cpu(sb->max_gid); 176 attr->max_sgid = min_t(u32, BNXT_QPLIB_NUM_GIDS_SUPPORTED, 2 * attr->max_sgid); 177 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 178 attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2); 179 180 if (_is_max_srq_ext_supported(attr->dev_cap_flags2)) 181 attr->max_srq += le16_to_cpu(sb->max_srq_ext); 182 183 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 184 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 185 tqm_alloc = (u8 *)&temp; 186 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 187 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 188 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 189 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 190 } 191 192 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 193 attr->max_dpi = le32_to_cpu(sb->max_dpi); 194 195 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 196 bail: 197 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 198 sbuf.sb, sbuf.dma_addr); 199 return rc; 200 } 201 202 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 203 struct bnxt_qplib_rcfw *rcfw, 204 struct bnxt_qplib_ctx *ctx) 205 { 206 struct creq_set_func_resources_resp resp = {}; 207 struct cmdq_set_func_resources req = {}; 208 struct bnxt_qplib_cmdqmsg msg = {}; 209 int rc; 210 211 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 212 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 213 sizeof(req)); 214 215 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 216 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 217 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 218 req.number_of_cq = cpu_to_le32(ctx->cq_count); 219 220 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 221 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 222 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 223 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 224 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 225 226 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 227 sizeof(resp), 0); 228 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 229 if (rc) { 230 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 231 } 232 return rc; 233 } 234 235 /* SGID */ 236 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 237 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 238 struct bnxt_qplib_gid *gid) 239 { 240 if (index >= sgid_tbl->max) { 241 dev_err(&res->pdev->dev, 242 "Index %d exceeded SGID table max (%d)\n", 243 index, sgid_tbl->max); 244 return -EINVAL; 245 } 246 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 247 return 0; 248 } 249 250 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 251 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 252 { 253 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 254 struct bnxt_qplib_res, 255 sgid_tbl); 256 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 257 int index; 258 259 /* Do we need a sgid_lock here? */ 260 if (!sgid_tbl->active) { 261 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 262 return -ENOMEM; 263 } 264 for (index = 0; index < sgid_tbl->max; index++) { 265 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 266 vlan_id == sgid_tbl->tbl[index].vlan_id) 267 break; 268 } 269 if (index == sgid_tbl->max) { 270 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 271 return 0; 272 } 273 /* Remove GID from the SGID table */ 274 if (update) { 275 struct creq_delete_gid_resp resp = {}; 276 struct bnxt_qplib_cmdqmsg msg = {}; 277 struct cmdq_delete_gid req = {}; 278 int rc; 279 280 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 281 CMDQ_BASE_OPCODE_DELETE_GID, 282 sizeof(req)); 283 if (sgid_tbl->hw_id[index] == 0xFFFF) { 284 dev_err(&res->pdev->dev, 285 "GID entry contains an invalid HW id\n"); 286 return -EINVAL; 287 } 288 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 289 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 290 sizeof(resp), 0); 291 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 292 if (rc) 293 return rc; 294 } 295 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 296 sizeof(bnxt_qplib_gid_zero)); 297 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 298 sgid_tbl->vlan[index] = 0; 299 sgid_tbl->active--; 300 dev_dbg(&res->pdev->dev, 301 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 302 index, sgid_tbl->hw_id[index], sgid_tbl->active); 303 sgid_tbl->hw_id[index] = (u16)-1; 304 305 /* unlock */ 306 return 0; 307 } 308 309 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 310 struct bnxt_qplib_gid *gid, const u8 *smac, 311 u16 vlan_id, bool update, u32 *index, 312 bool is_ugid, u32 stats_ctx_id) 313 { 314 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 315 struct bnxt_qplib_res, 316 sgid_tbl); 317 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 318 int i, free_idx; 319 320 /* Do we need a sgid_lock here? */ 321 if (sgid_tbl->active == sgid_tbl->max) { 322 dev_err(&res->pdev->dev, "SGID table is full\n"); 323 return -ENOMEM; 324 } 325 free_idx = sgid_tbl->max; 326 for (i = 0; i < sgid_tbl->max; i++) { 327 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 328 sgid_tbl->tbl[i].vlan_id == vlan_id) { 329 dev_dbg(&res->pdev->dev, 330 "SGID entry already exist in entry %d!\n", i); 331 *index = i; 332 return -EALREADY; 333 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 334 sizeof(bnxt_qplib_gid_zero)) && 335 free_idx == sgid_tbl->max) { 336 free_idx = i; 337 } 338 } 339 if (free_idx == sgid_tbl->max) { 340 dev_err(&res->pdev->dev, 341 "SGID table is FULL but count is not MAX??\n"); 342 return -ENOMEM; 343 } 344 if (update) { 345 struct creq_add_gid_resp resp = {}; 346 struct bnxt_qplib_cmdqmsg msg = {}; 347 struct cmdq_add_gid req = {}; 348 int rc; 349 350 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 351 CMDQ_BASE_OPCODE_ADD_GID, 352 sizeof(req)); 353 354 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 355 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 356 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 357 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 358 /* 359 * driver should ensure that all RoCE traffic is always VLAN 360 * tagged if RoCE traffic is running on non-zero VLAN ID or 361 * RoCE traffic is running on non-zero Priority. 362 */ 363 if ((vlan_id != 0xFFFF) || res->prio) { 364 if (vlan_id != 0xFFFF) 365 req.vlan = cpu_to_le16 366 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 367 req.vlan |= cpu_to_le16 368 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 369 CMDQ_ADD_GID_VLAN_VLAN_EN); 370 } 371 372 /* MAC in network format */ 373 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 374 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 375 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 376 377 req.stats_ctx = cpu_to_le16(CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID | 378 (u16)stats_ctx_id); 379 380 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 381 sizeof(resp), 0); 382 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 383 if (rc) 384 return rc; 385 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 386 } 387 /* Add GID to the sgid_tbl */ 388 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 389 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 390 sgid_tbl->active++; 391 if (vlan_id != 0xFFFF) 392 sgid_tbl->vlan[free_idx] = 1; 393 394 dev_dbg(&res->pdev->dev, 395 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 396 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 397 398 *index = free_idx; 399 /* unlock */ 400 return 0; 401 } 402 403 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 404 struct bnxt_qplib_gid *gid, u16 gid_idx, 405 const u8 *smac) 406 { 407 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 408 struct bnxt_qplib_res, 409 sgid_tbl); 410 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 411 struct creq_modify_gid_resp resp = {}; 412 struct bnxt_qplib_cmdqmsg msg = {}; 413 struct cmdq_modify_gid req = {}; 414 int rc; 415 416 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 417 CMDQ_BASE_OPCODE_MODIFY_GID, 418 sizeof(req)); 419 420 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 421 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 422 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 423 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 424 if (res->prio) { 425 req.vlan |= cpu_to_le16 426 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 427 CMDQ_ADD_GID_VLAN_VLAN_EN); 428 } 429 430 /* MAC in network format */ 431 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 432 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 433 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 434 435 req.gid_index = cpu_to_le16(gid_idx); 436 437 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 438 sizeof(resp), 0); 439 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 440 return rc; 441 } 442 443 /* AH */ 444 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 445 bool block) 446 { 447 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 448 struct creq_create_ah_resp resp = {}; 449 struct bnxt_qplib_cmdqmsg msg = {}; 450 struct cmdq_create_ah req = {}; 451 u32 temp32[4]; 452 u16 temp16[3]; 453 int rc; 454 455 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 456 CMDQ_BASE_OPCODE_CREATE_AH, 457 sizeof(req)); 458 459 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 460 req.dgid[0] = cpu_to_le32(temp32[0]); 461 req.dgid[1] = cpu_to_le32(temp32[1]); 462 req.dgid[2] = cpu_to_le32(temp32[2]); 463 req.dgid[3] = cpu_to_le32(temp32[3]); 464 465 req.type = ah->nw_type; 466 req.hop_limit = ah->hop_limit; 467 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 468 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 469 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 470 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 471 req.pd_id = cpu_to_le32(ah->pd->id); 472 req.traffic_class = ah->traffic_class; 473 474 /* MAC in network format */ 475 memcpy(temp16, ah->dmac, 6); 476 req.dest_mac[0] = cpu_to_le16(temp16[0]); 477 req.dest_mac[1] = cpu_to_le16(temp16[1]); 478 req.dest_mac[2] = cpu_to_le16(temp16[2]); 479 480 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 481 sizeof(resp), block); 482 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 483 if (rc) 484 return rc; 485 486 ah->id = le32_to_cpu(resp.xid); 487 return 0; 488 } 489 490 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 491 bool block) 492 { 493 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 494 struct creq_destroy_ah_resp resp = {}; 495 struct bnxt_qplib_cmdqmsg msg = {}; 496 struct cmdq_destroy_ah req = {}; 497 int rc; 498 499 /* Clean up the AH table in the device */ 500 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 501 CMDQ_BASE_OPCODE_DESTROY_AH, 502 sizeof(req)); 503 504 req.ah_cid = cpu_to_le32(ah->id); 505 506 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 507 sizeof(resp), block); 508 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 509 return rc; 510 } 511 512 /* MRW */ 513 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 514 { 515 struct creq_deallocate_key_resp resp = {}; 516 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 517 struct cmdq_deallocate_key req = {}; 518 struct bnxt_qplib_cmdqmsg msg = {}; 519 int rc; 520 521 if (mrw->lkey == 0xFFFFFFFF) { 522 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 523 return 0; 524 } 525 526 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 527 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 528 sizeof(req)); 529 530 req.mrw_flags = mrw->type; 531 532 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 533 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 534 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 535 req.key = cpu_to_le32(mrw->rkey); 536 else 537 req.key = cpu_to_le32(mrw->lkey); 538 539 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 540 sizeof(resp), 0); 541 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 542 if (rc) 543 return rc; 544 545 /* Free the qplib's MRW memory */ 546 if (mrw->hwq.max_elements) 547 bnxt_qplib_free_hwq(res, &mrw->hwq); 548 549 return 0; 550 } 551 552 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 553 { 554 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 555 struct creq_allocate_mrw_resp resp = {}; 556 struct bnxt_qplib_cmdqmsg msg = {}; 557 struct cmdq_allocate_mrw req = {}; 558 unsigned long tmp; 559 int rc; 560 561 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 562 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 563 sizeof(req)); 564 565 req.pd_id = cpu_to_le32(mrw->pd->id); 566 req.mrw_flags = mrw->type; 567 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 568 mrw->access_flags & BNXT_QPLIB_FR_PMR) || 569 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 570 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 571 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 572 tmp = (unsigned long)mrw; 573 req.mrw_handle = cpu_to_le64(tmp); 574 575 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 576 sizeof(resp), 0); 577 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 578 if (rc) 579 return rc; 580 581 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 582 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 583 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 584 mrw->rkey = le32_to_cpu(resp.xid); 585 else 586 mrw->lkey = le32_to_cpu(resp.xid); 587 return 0; 588 } 589 590 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 591 bool block) 592 { 593 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 594 struct creq_deregister_mr_resp resp = {}; 595 struct bnxt_qplib_cmdqmsg msg = {}; 596 struct cmdq_deregister_mr req = {}; 597 int rc; 598 599 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 600 CMDQ_BASE_OPCODE_DEREGISTER_MR, 601 sizeof(req)); 602 603 req.lkey = cpu_to_le32(mrw->lkey); 604 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 605 sizeof(resp), block); 606 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 607 if (rc) 608 return rc; 609 610 /* Free the qplib's MR memory */ 611 if (mrw->hwq.max_elements) { 612 mrw->va = 0; 613 mrw->total_size = 0; 614 bnxt_qplib_free_hwq(res, &mrw->hwq); 615 } 616 617 return 0; 618 } 619 620 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 621 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 622 { 623 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 624 struct bnxt_qplib_hwq_attr hwq_attr = {}; 625 struct bnxt_qplib_sg_info sginfo = {}; 626 struct creq_register_mr_resp resp = {}; 627 struct bnxt_qplib_cmdqmsg msg = {}; 628 struct cmdq_register_mr req = {}; 629 int pages, rc; 630 u32 pg_size; 631 u16 level; 632 633 if (num_pbls) { 634 pages = roundup_pow_of_two(num_pbls); 635 /* Allocate memory for the non-leaf pages to store buf ptrs. 636 * Non-leaf pages always uses system PAGE_SIZE 637 */ 638 /* Free the hwq if it already exist, must be a rereg */ 639 if (mr->hwq.max_elements) 640 bnxt_qplib_free_hwq(res, &mr->hwq); 641 hwq_attr.res = res; 642 hwq_attr.depth = pages; 643 hwq_attr.stride = sizeof(dma_addr_t); 644 hwq_attr.type = HWQ_TYPE_MR; 645 hwq_attr.sginfo = &sginfo; 646 hwq_attr.sginfo->umem = umem; 647 hwq_attr.sginfo->npages = pages; 648 hwq_attr.sginfo->pgsize = buf_pg_size; 649 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 650 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 651 if (rc) { 652 dev_err(&res->pdev->dev, 653 "SP: Reg MR memory allocation failed\n"); 654 return -ENOMEM; 655 } 656 } 657 658 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 659 CMDQ_BASE_OPCODE_REGISTER_MR, 660 sizeof(req)); 661 662 /* Configure the request */ 663 if (mr->hwq.level == PBL_LVL_MAX) { 664 /* No PBL provided, just use system PAGE_SIZE */ 665 level = 0; 666 req.pbl = 0; 667 pg_size = PAGE_SIZE; 668 } else { 669 level = mr->hwq.level; 670 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 671 } 672 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 673 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 674 ((ilog2(pg_size) << 675 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 676 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 677 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 678 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 679 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 680 req.access = (mr->access_flags & BNXT_QPLIB_MR_ACCESS_MASK); 681 req.va = cpu_to_le64(mr->va); 682 req.key = cpu_to_le32(mr->lkey); 683 if (_is_alloc_mr_unified(res->dattr->dev_cap_flags)) 684 req.key = cpu_to_le32(mr->pd->id); 685 req.flags = cpu_to_le16(mr->flags); 686 req.mr_size = cpu_to_le64(mr->total_size); 687 688 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 689 sizeof(resp), 0); 690 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 691 if (rc) 692 goto fail; 693 694 if (_is_alloc_mr_unified(res->dattr->dev_cap_flags)) { 695 mr->lkey = le32_to_cpu(resp.xid); 696 mr->rkey = mr->lkey; 697 } 698 699 return 0; 700 701 fail: 702 if (mr->hwq.max_elements) 703 bnxt_qplib_free_hwq(res, &mr->hwq); 704 return rc; 705 } 706 707 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 708 struct bnxt_qplib_frpl *frpl, 709 int max_pg_ptrs) 710 { 711 struct bnxt_qplib_hwq_attr hwq_attr = {}; 712 struct bnxt_qplib_sg_info sginfo = {}; 713 int pg_ptrs, pages, rc; 714 715 /* Re-calculate the max to fit the HWQ allocation model */ 716 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 717 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 718 if (!pages) 719 pages++; 720 721 if (pages > MAX_PBL_LVL_1_PGS) 722 return -ENOMEM; 723 724 sginfo.pgsize = PAGE_SIZE; 725 sginfo.nopte = true; 726 727 hwq_attr.res = res; 728 hwq_attr.depth = pg_ptrs; 729 hwq_attr.stride = PAGE_SIZE; 730 hwq_attr.sginfo = &sginfo; 731 hwq_attr.type = HWQ_TYPE_CTX; 732 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 733 if (!rc) 734 frpl->max_pg_ptrs = pg_ptrs; 735 736 return rc; 737 } 738 739 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 740 struct bnxt_qplib_frpl *frpl) 741 { 742 bnxt_qplib_free_hwq(res, &frpl->hwq); 743 return 0; 744 } 745 746 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 747 struct bnxt_qplib_roce_stats *stats) 748 { 749 struct creq_query_roce_stats_resp resp = {}; 750 struct creq_query_roce_stats_resp_sb *sb; 751 struct cmdq_query_roce_stats req = {}; 752 struct bnxt_qplib_cmdqmsg msg = {}; 753 struct bnxt_qplib_rcfw_sbuf sbuf; 754 int rc; 755 756 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 757 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 758 sizeof(req)); 759 760 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 761 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 762 &sbuf.dma_addr, GFP_KERNEL); 763 if (!sbuf.sb) 764 return -ENOMEM; 765 sb = sbuf.sb; 766 767 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 768 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 769 sizeof(resp), 0); 770 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 771 if (rc) 772 goto bail; 773 /* Extract the context from the side buffer */ 774 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 775 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 776 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 777 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 778 stats->missing_resp = le64_to_cpu(sb->missing_resp); 779 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 780 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 781 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 782 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 783 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 784 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 785 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 786 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 787 stats->dup_req = le64_to_cpu(sb->dup_req); 788 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 789 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 790 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 791 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 792 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 793 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 794 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 795 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 796 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 797 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 798 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 799 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 800 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 801 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 802 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 803 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 804 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 805 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 806 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 807 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 808 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 809 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 810 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 811 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 812 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 813 if (!rcfw->init_oos_stats) { 814 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 815 rcfw->init_oos_stats = 1; 816 } else { 817 stats->res_oos_drop_count += 818 (le64_to_cpu(sb->res_oos_drop_count) - 819 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 820 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 821 } 822 823 bail: 824 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 825 sbuf.sb, sbuf.dma_addr); 826 return rc; 827 } 828 829 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 830 struct bnxt_qplib_ext_stat *estat) 831 { 832 struct creq_query_roce_stats_ext_resp resp = {}; 833 struct creq_query_roce_stats_ext_resp_sb *sb; 834 struct cmdq_query_roce_stats_ext req = {}; 835 struct bnxt_qplib_cmdqmsg msg = {}; 836 struct bnxt_qplib_rcfw_sbuf sbuf; 837 int rc; 838 839 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 840 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 841 &sbuf.dma_addr, GFP_KERNEL); 842 if (!sbuf.sb) 843 return -ENOMEM; 844 845 sb = sbuf.sb; 846 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 847 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 848 sizeof(req)); 849 850 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 851 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 852 if (bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx) && rcfw->res->is_vf) 853 req.function_id = 854 cpu_to_le32(CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID | 855 (fid << CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT)); 856 else 857 req.function_id = cpu_to_le32(fid); 858 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 859 860 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 861 sizeof(resp), 0); 862 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 863 if (rc) 864 goto bail; 865 866 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 867 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 868 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 869 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 870 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 871 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 872 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 873 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 874 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 875 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 876 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 877 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 878 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 879 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 880 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 881 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 882 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 883 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 884 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 885 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 886 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 887 888 bail: 889 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 890 sbuf.sb, sbuf.dma_addr); 891 return rc; 892 } 893 894 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 895 struct bnxt_qplib_cc_param_ext *cc_ext) 896 { 897 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 898 cc_ext->ext_mask = 0; 899 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 900 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 901 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 902 ext_req->tr_update_mode = cc_ext->tr_update_mode; 903 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 904 ext_req->fr_num_rtts = cc_ext->fr_rtt; 905 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 906 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 907 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 908 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 909 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 910 ext_req->actual_cr_factor = cc_ext->cr_factor; 911 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 912 ext_req->cp_bias_en = cc_ext->cp_bias_en; 913 ext_req->cp_bias = cc_ext->cp_bias; 914 ext_req->cnp_ecn = cc_ext->cnp_ecn; 915 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 916 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 917 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 918 ext_req->cr_width = cc_ext->cr_width; 919 ext_req->quota_period_min = cc_ext->min_quota; 920 ext_req->quota_period_max = cc_ext->max_quota; 921 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 922 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 923 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 924 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 925 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 926 ext_req->red_div = cc_ext->red_div; 927 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 928 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 929 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 930 ext_req->use_rate_table = cc_ext->low_rate_en; 931 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 932 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 933 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 934 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 935 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 936 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 937 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 938 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 939 } 940 941 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 942 struct bnxt_qplib_cc_param *cc_param) 943 { 944 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 945 struct creq_modify_roce_cc_resp resp = {}; 946 struct bnxt_qplib_cmdqmsg msg = {}; 947 struct cmdq_modify_roce_cc *req; 948 int req_size; 949 void *cmd; 950 int rc; 951 952 /* Prepare the older base command */ 953 req = &tlv_req.base_req; 954 cmd = req; 955 req_size = sizeof(*req); 956 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 957 sizeof(*req)); 958 req->modify_mask = cpu_to_le32(cc_param->mask); 959 req->enable_cc = cc_param->enable; 960 req->g = cc_param->g; 961 req->num_phases_per_state = cc_param->nph_per_state; 962 req->time_per_phase = cc_param->time_pph; 963 req->pkts_per_phase = cc_param->pkts_pph; 964 req->init_cr = cpu_to_le16(cc_param->init_cr); 965 req->init_tr = cpu_to_le16(cc_param->init_tr); 966 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 967 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 968 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 969 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 970 req->rtt = cpu_to_le16(cc_param->rtt); 971 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 972 req->cc_mode = cc_param->cc_mode; 973 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 974 975 /* For chip gen P5 onwards fill extended cmd and header */ 976 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 977 struct roce_tlv *hdr; 978 u32 payload; 979 u32 chunks; 980 981 cmd = &tlv_req; 982 req_size = sizeof(tlv_req); 983 /* Prepare primary tlv header */ 984 hdr = &tlv_req.tlv_hdr; 985 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 986 payload = sizeof(struct cmdq_modify_roce_cc); 987 __roce_1st_tlv_prep(hdr, chunks, payload, true); 988 /* Prepare secondary tlv header */ 989 hdr = (struct roce_tlv *)&tlv_req.ext_req; 990 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 991 sizeof(struct roce_tlv); 992 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 993 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 994 } 995 996 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 997 sizeof(resp), 0); 998 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 999 return rc; 1000 } 1001 1002 int bnxt_qplib_read_context(struct bnxt_qplib_rcfw *rcfw, u8 res_type, 1003 u32 xid, u32 resp_size, void *resp_va) 1004 { 1005 struct creq_read_context resp = {}; 1006 struct bnxt_qplib_cmdqmsg msg = {}; 1007 struct cmdq_read_context req = {}; 1008 struct bnxt_qplib_rcfw_sbuf sbuf; 1009 int rc; 1010 1011 sbuf.size = resp_size; 1012 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 1013 &sbuf.dma_addr, GFP_KERNEL); 1014 if (!sbuf.sb) 1015 return -ENOMEM; 1016 1017 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 1018 CMDQ_BASE_OPCODE_READ_CONTEXT, sizeof(req)); 1019 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 1020 req.resp_size = resp_size / BNXT_QPLIB_CMDQE_UNITS; 1021 1022 req.xid = cpu_to_le32(xid); 1023 req.type = res_type; 1024 1025 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 1026 sizeof(resp), 0); 1027 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 1028 if (rc) 1029 goto free_mem; 1030 1031 memcpy(resp_va, sbuf.sb, resp_size); 1032 free_mem: 1033 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 1034 return rc; 1035 } 1036 1037 static void bnxt_qplib_read_cc_gen1(struct bnxt_qplib_cc_param_ext *cc_ext, 1038 struct creq_query_roce_cc_gen1_resp_sb_tlv *sb) 1039 { 1040 cc_ext->inact_th_hi = le16_to_cpu(sb->inactivity_th_hi); 1041 cc_ext->min_delta_cnp = le16_to_cpu(sb->min_time_between_cnps); 1042 cc_ext->init_cp = le16_to_cpu(sb->init_cp); 1043 cc_ext->tr_update_mode = sb->tr_update_mode; 1044 cc_ext->tr_update_cyls = sb->tr_update_cycles; 1045 cc_ext->fr_rtt = sb->fr_num_rtts; 1046 cc_ext->ai_rate_incr = sb->ai_rate_increase; 1047 cc_ext->rr_rtt_th = le16_to_cpu(sb->reduction_relax_rtts_th); 1048 cc_ext->ar_cr_th = le16_to_cpu(sb->additional_relax_cr_th); 1049 cc_ext->cr_min_th = le16_to_cpu(sb->cr_min_th); 1050 cc_ext->bw_avg_weight = sb->bw_avg_weight; 1051 cc_ext->cr_factor = sb->actual_cr_factor; 1052 cc_ext->cr_th_max_cp = le16_to_cpu(sb->max_cp_cr_th); 1053 cc_ext->cp_bias_en = sb->cp_bias_en; 1054 cc_ext->cp_bias = sb->cp_bias; 1055 cc_ext->cnp_ecn = sb->cnp_ecn; 1056 cc_ext->rtt_jitter_en = sb->rtt_jitter_en; 1057 cc_ext->bytes_per_usec = le16_to_cpu(sb->link_bytes_per_usec); 1058 cc_ext->cc_cr_reset_th = le16_to_cpu(sb->reset_cc_cr_th); 1059 cc_ext->cr_width = sb->cr_width; 1060 cc_ext->min_quota = sb->quota_period_min; 1061 cc_ext->max_quota = sb->quota_period_max; 1062 cc_ext->abs_max_quota = sb->quota_period_abs_max; 1063 cc_ext->tr_lb = le16_to_cpu(sb->tr_lower_bound); 1064 cc_ext->cr_prob_fac = sb->cr_prob_factor; 1065 cc_ext->tr_prob_fac = sb->tr_prob_factor; 1066 cc_ext->fair_cr_th = le16_to_cpu(sb->fairness_cr_th); 1067 cc_ext->red_div = sb->red_div; 1068 cc_ext->cnp_ratio_th = sb->cnp_ratio_th; 1069 cc_ext->ai_ext_rtt = le16_to_cpu(sb->exp_ai_rtts); 1070 cc_ext->exp_crcp_ratio = sb->exp_ai_cr_cp_ratio; 1071 cc_ext->low_rate_en = sb->use_rate_table; 1072 cc_ext->cpcr_update_th = le16_to_cpu(sb->cp_exp_update_th); 1073 cc_ext->ai_rtt_th1 = le16_to_cpu(sb->high_exp_ai_rtts_th1); 1074 cc_ext->ai_rtt_th2 = le16_to_cpu(sb->high_exp_ai_rtts_th2); 1075 cc_ext->cf_rtt_th = le16_to_cpu(sb->actual_cr_cong_free_rtts_th); 1076 cc_ext->sc_cr_th1 = le16_to_cpu(sb->severe_cong_cr_th1); 1077 cc_ext->sc_cr_th2 = le16_to_cpu(sb->severe_cong_cr_th2); 1078 cc_ext->l64B_per_rtt = le32_to_cpu(sb->link64B_per_rtt); 1079 cc_ext->cc_ack_bytes = sb->cc_ack_bytes; 1080 cc_ext->reduce_cf_rtt_th = le16_to_cpu(sb->reduce_init_cong_free_rtts_th); 1081 } 1082 1083 int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res, 1084 struct bnxt_qplib_cc_param *cc_param) 1085 { 1086 struct bnxt_qplib_tlv_query_rcc_sb *ext_sb; 1087 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1088 struct creq_query_roce_cc_resp resp = {}; 1089 struct creq_query_roce_cc_resp_sb *sb; 1090 struct bnxt_qplib_cmdqmsg msg = {}; 1091 struct cmdq_query_roce_cc req = {}; 1092 struct bnxt_qplib_rcfw_sbuf sbuf; 1093 size_t resp_size; 1094 int rc; 1095 1096 /* Query the parameters from chip */ 1097 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, CMDQ_BASE_OPCODE_QUERY_ROCE_CC, 1098 sizeof(req)); 1099 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) 1100 resp_size = sizeof(*ext_sb); 1101 else 1102 resp_size = sizeof(*sb); 1103 1104 sbuf.size = ALIGN(resp_size, BNXT_QPLIB_CMDQE_UNITS); 1105 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 1106 &sbuf.dma_addr, GFP_KERNEL); 1107 if (!sbuf.sb) 1108 return -ENOMEM; 1109 1110 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 1111 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 1112 sizeof(resp), 0); 1113 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 1114 if (rc) 1115 goto out; 1116 1117 ext_sb = sbuf.sb; 1118 sb = bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? &ext_sb->base_sb : 1119 (struct creq_query_roce_cc_resp_sb *)ext_sb; 1120 1121 cc_param->enable = sb->enable_cc & CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC; 1122 cc_param->tos_ecn = (sb->tos_dscp_tos_ecn & 1123 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK) >> 1124 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT; 1125 cc_param->tos_dscp = (sb->tos_dscp_tos_ecn & 1126 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK) >> 1127 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT; 1128 cc_param->alt_tos_dscp = sb->alt_tos_dscp; 1129 cc_param->alt_vlan_pcp = sb->alt_vlan_pcp; 1130 1131 cc_param->g = sb->g; 1132 cc_param->nph_per_state = sb->num_phases_per_state; 1133 cc_param->init_cr = le16_to_cpu(sb->init_cr); 1134 cc_param->init_tr = le16_to_cpu(sb->init_tr); 1135 cc_param->cc_mode = sb->cc_mode; 1136 cc_param->inact_th = le16_to_cpu(sb->inactivity_th); 1137 cc_param->rtt = le16_to_cpu(sb->rtt); 1138 cc_param->tcp_cp = le16_to_cpu(sb->tcp_cp); 1139 cc_param->time_pph = sb->time_per_phase; 1140 cc_param->pkts_pph = sb->pkts_per_phase; 1141 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 1142 bnxt_qplib_read_cc_gen1(&cc_param->cc_ext, &ext_sb->gen1_sb); 1143 cc_param->inact_th |= (cc_param->cc_ext.inact_th_hi & 0x3F) << 16; 1144 } 1145 out: 1146 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 1147 return rc; 1148 } 1149 1150 int bnxt_qplib_create_flow(struct bnxt_qplib_res *res) 1151 { 1152 struct creq_roce_mirror_cfg_resp resp = {}; 1153 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1154 struct cmdq_roce_mirror_cfg req = {}; 1155 struct bnxt_qplib_cmdqmsg msg = {}; 1156 1157 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 1158 CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG, 1159 sizeof(req)); 1160 1161 req.mirror_flags = (u8)CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE; 1162 1163 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 1164 sizeof(resp), 0); 1165 return bnxt_qplib_rcfw_send_message(rcfw, &msg); 1166 } 1167 1168 int bnxt_qplib_destroy_flow(struct bnxt_qplib_res *res) 1169 { 1170 struct creq_roce_mirror_cfg_resp resp = {}; 1171 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1172 struct cmdq_roce_mirror_cfg req = {}; 1173 struct bnxt_qplib_cmdqmsg msg = {}; 1174 1175 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 1176 CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG, 1177 sizeof(req)); 1178 1179 req.mirror_flags &= ~((u8)CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE); 1180 1181 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 1182 sizeof(resp), 0); 1183 1184 return bnxt_qplib_rcfw_send_message(rcfw, &msg); 1185 } 1186