1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_tlv.h" 52 53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56 /* Device */ 57 58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59 { 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67 } 68 69 void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw) 70 { 71 struct creq_query_version_resp resp = {}; 72 struct bnxt_qplib_cmdqmsg msg = {}; 73 struct cmdq_query_version req = {}; 74 struct bnxt_qplib_dev_attr *attr; 75 int rc; 76 77 attr = rcfw->res->dattr; 78 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 79 CMDQ_BASE_OPCODE_QUERY_VERSION, 80 sizeof(req)); 81 82 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 83 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 84 if (rc) 85 return; 86 attr->fw_ver[0] = resp.fw_maj; 87 attr->fw_ver[1] = resp.fw_minor; 88 attr->fw_ver[2] = resp.fw_bld; 89 attr->fw_ver[3] = resp.fw_rsvd; 90 } 91 92 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw) 93 { 94 struct bnxt_qplib_dev_attr *attr = rcfw->res->dattr; 95 struct creq_query_func_resp resp = {}; 96 struct bnxt_qplib_cmdqmsg msg = {}; 97 struct creq_query_func_resp_sb *sb; 98 struct bnxt_qplib_rcfw_sbuf sbuf; 99 struct bnxt_qplib_chip_ctx *cctx; 100 struct cmdq_query_func req = {}; 101 u8 *tqm_alloc; 102 int i, rc; 103 u32 temp; 104 105 cctx = rcfw->res->cctx; 106 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 107 CMDQ_BASE_OPCODE_QUERY_FUNC, 108 sizeof(req)); 109 110 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 111 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 112 &sbuf.dma_addr, GFP_KERNEL); 113 if (!sbuf.sb) 114 return -ENOMEM; 115 sb = sbuf.sb; 116 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 117 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 118 sizeof(resp), 0); 119 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 120 if (rc) 121 goto bail; 122 123 /* Extract the context from the side buffer */ 124 attr->max_qp = le32_to_cpu(sb->max_qp); 125 /* max_qp value reported by FW doesn't include the QP1 */ 126 attr->max_qp += 1; 127 attr->max_qp_rd_atom = 128 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 130 attr->max_qp_init_rd_atom = 131 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 132 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 133 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr) - 1; 134 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) { 135 /* 136 * 128 WQEs needs to be reserved for the HW (8916). Prevent 137 * reporting the max number on legacy devices 138 */ 139 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 140 } 141 142 /* Adjust for max_qp_wqes for variable wqe */ 143 if (cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 144 attr->max_qp_wqes = BNXT_VAR_MAX_WQE - 1; 145 146 attr->max_qp_sges = cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE ? 147 min_t(u32, sb->max_sge_var_wqe, BNXT_VAR_MAX_SGE) : 6; 148 attr->max_cq = le32_to_cpu(sb->max_cq); 149 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 150 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 151 attr->max_cq_wqes = min_t(u32, BNXT_QPLIB_MAX_CQ_WQES, attr->max_cq_wqes); 152 attr->max_cq_sges = attr->max_qp_sges; 153 attr->max_mr = le32_to_cpu(sb->max_mr); 154 attr->max_mw = le32_to_cpu(sb->max_mw); 155 156 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 157 attr->max_pd = 64 * 1024; 158 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 159 attr->max_ah = le32_to_cpu(sb->max_ah); 160 161 attr->max_srq = le16_to_cpu(sb->max_srq); 162 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 163 attr->max_srq_sges = sb->max_srq_sge; 164 attr->max_pkey = 1; 165 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 166 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 167 attr->l2_db_size = (sb->l2_db_space_size + 1) * 168 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 169 /* 170 * Read the max gid supported by HW. 171 * For each entry in HW GID in HW table, we consume 2 172 * GID entries in the kernel GID table. So max_gid reported 173 * to stack can be up to twice the value reported by the HW, up to 256 gids. 174 */ 175 attr->max_sgid = le32_to_cpu(sb->max_gid); 176 attr->max_sgid = min_t(u32, BNXT_QPLIB_NUM_GIDS_SUPPORTED, 2 * attr->max_sgid); 177 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 178 attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2); 179 180 if (_is_max_srq_ext_supported(attr->dev_cap_flags2)) 181 attr->max_srq += le16_to_cpu(sb->max_srq_ext); 182 183 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 184 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 185 tqm_alloc = (u8 *)&temp; 186 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 187 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 188 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 189 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 190 } 191 192 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 193 attr->max_dpi = le32_to_cpu(sb->max_dpi); 194 195 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 196 bail: 197 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 198 sbuf.sb, sbuf.dma_addr); 199 return rc; 200 } 201 202 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 203 struct bnxt_qplib_rcfw *rcfw, 204 struct bnxt_qplib_ctx *ctx) 205 { 206 struct creq_set_func_resources_resp resp = {}; 207 struct cmdq_set_func_resources req = {}; 208 struct bnxt_qplib_cmdqmsg msg = {}; 209 int rc; 210 211 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 212 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 213 sizeof(req)); 214 215 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 216 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 217 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 218 req.number_of_cq = cpu_to_le32(ctx->cq_count); 219 220 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 221 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 222 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 223 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 224 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 225 226 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 227 sizeof(resp), 0); 228 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 229 if (rc) { 230 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 231 } 232 return rc; 233 } 234 235 /* SGID */ 236 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 237 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 238 struct bnxt_qplib_gid *gid) 239 { 240 if (index >= sgid_tbl->max) { 241 dev_err(&res->pdev->dev, 242 "Index %d exceeded SGID table max (%d)\n", 243 index, sgid_tbl->max); 244 return -EINVAL; 245 } 246 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 247 return 0; 248 } 249 250 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 251 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 252 { 253 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 254 struct bnxt_qplib_res, 255 sgid_tbl); 256 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 257 int index; 258 259 /* Do we need a sgid_lock here? */ 260 if (!sgid_tbl->active) { 261 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 262 return -ENOMEM; 263 } 264 for (index = 0; index < sgid_tbl->max; index++) { 265 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 266 vlan_id == sgid_tbl->tbl[index].vlan_id) 267 break; 268 } 269 if (index == sgid_tbl->max) { 270 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 271 return 0; 272 } 273 /* Remove GID from the SGID table */ 274 if (update) { 275 struct creq_delete_gid_resp resp = {}; 276 struct bnxt_qplib_cmdqmsg msg = {}; 277 struct cmdq_delete_gid req = {}; 278 int rc; 279 280 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 281 CMDQ_BASE_OPCODE_DELETE_GID, 282 sizeof(req)); 283 if (sgid_tbl->hw_id[index] == 0xFFFF) { 284 dev_err(&res->pdev->dev, 285 "GID entry contains an invalid HW id\n"); 286 return -EINVAL; 287 } 288 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 289 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 290 sizeof(resp), 0); 291 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 292 if (rc) 293 return rc; 294 } 295 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 296 sizeof(bnxt_qplib_gid_zero)); 297 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 298 sgid_tbl->vlan[index] = 0; 299 sgid_tbl->active--; 300 dev_dbg(&res->pdev->dev, 301 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 302 index, sgid_tbl->hw_id[index], sgid_tbl->active); 303 sgid_tbl->hw_id[index] = (u16)-1; 304 305 /* unlock */ 306 return 0; 307 } 308 309 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 310 struct bnxt_qplib_gid *gid, const u8 *smac, 311 u16 vlan_id, bool update, u32 *index, 312 bool is_ugid, u32 stats_ctx_id) 313 { 314 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 315 struct bnxt_qplib_res, 316 sgid_tbl); 317 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 318 int i, free_idx; 319 320 /* Do we need a sgid_lock here? */ 321 if (sgid_tbl->active == sgid_tbl->max) { 322 dev_err(&res->pdev->dev, "SGID table is full\n"); 323 return -ENOMEM; 324 } 325 free_idx = sgid_tbl->max; 326 for (i = 0; i < sgid_tbl->max; i++) { 327 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 328 sgid_tbl->tbl[i].vlan_id == vlan_id) { 329 dev_dbg(&res->pdev->dev, 330 "SGID entry already exist in entry %d!\n", i); 331 *index = i; 332 return -EALREADY; 333 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 334 sizeof(bnxt_qplib_gid_zero)) && 335 free_idx == sgid_tbl->max) { 336 free_idx = i; 337 } 338 } 339 if (free_idx == sgid_tbl->max) { 340 dev_err(&res->pdev->dev, 341 "SGID table is FULL but count is not MAX??\n"); 342 return -ENOMEM; 343 } 344 if (update) { 345 struct creq_add_gid_resp resp = {}; 346 struct bnxt_qplib_cmdqmsg msg = {}; 347 struct cmdq_add_gid req = {}; 348 int rc; 349 350 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 351 CMDQ_BASE_OPCODE_ADD_GID, 352 sizeof(req)); 353 354 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 355 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 356 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 357 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 358 /* 359 * driver should ensure that all RoCE traffic is always VLAN 360 * tagged if RoCE traffic is running on non-zero VLAN ID or 361 * RoCE traffic is running on non-zero Priority. 362 */ 363 if ((vlan_id != 0xFFFF) || res->prio) { 364 if (vlan_id != 0xFFFF) 365 req.vlan = cpu_to_le16 366 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 367 req.vlan |= cpu_to_le16 368 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 369 CMDQ_ADD_GID_VLAN_VLAN_EN); 370 } 371 372 /* MAC in network format */ 373 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 374 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 375 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 376 377 req.stats_ctx = cpu_to_le16(CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID | 378 (u16)stats_ctx_id); 379 380 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 381 sizeof(resp), 0); 382 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 383 if (rc) 384 return rc; 385 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 386 } 387 /* Add GID to the sgid_tbl */ 388 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 389 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 390 sgid_tbl->active++; 391 if (vlan_id != 0xFFFF) 392 sgid_tbl->vlan[free_idx] = 1; 393 394 dev_dbg(&res->pdev->dev, 395 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 396 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 397 398 *index = free_idx; 399 /* unlock */ 400 return 0; 401 } 402 403 /* AH */ 404 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 405 bool block) 406 { 407 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 408 struct creq_create_ah_resp resp = {}; 409 struct bnxt_qplib_cmdqmsg msg = {}; 410 struct cmdq_create_ah req = {}; 411 u32 temp32[4]; 412 u16 temp16[3]; 413 int rc; 414 415 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 416 CMDQ_BASE_OPCODE_CREATE_AH, 417 sizeof(req)); 418 419 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 420 req.dgid[0] = cpu_to_le32(temp32[0]); 421 req.dgid[1] = cpu_to_le32(temp32[1]); 422 req.dgid[2] = cpu_to_le32(temp32[2]); 423 req.dgid[3] = cpu_to_le32(temp32[3]); 424 425 req.type = ah->nw_type; 426 req.hop_limit = ah->hop_limit; 427 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 428 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 429 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 430 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 431 req.pd_id = cpu_to_le32(ah->pd->id); 432 req.traffic_class = ah->traffic_class; 433 434 /* MAC in network format */ 435 memcpy(temp16, ah->dmac, 6); 436 req.dest_mac[0] = cpu_to_le16(temp16[0]); 437 req.dest_mac[1] = cpu_to_le16(temp16[1]); 438 req.dest_mac[2] = cpu_to_le16(temp16[2]); 439 440 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 441 sizeof(resp), block); 442 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 443 if (rc) 444 return rc; 445 446 ah->id = le32_to_cpu(resp.xid); 447 return 0; 448 } 449 450 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 451 bool block) 452 { 453 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 454 struct creq_destroy_ah_resp resp = {}; 455 struct bnxt_qplib_cmdqmsg msg = {}; 456 struct cmdq_destroy_ah req = {}; 457 int rc; 458 459 /* Clean up the AH table in the device */ 460 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 461 CMDQ_BASE_OPCODE_DESTROY_AH, 462 sizeof(req)); 463 464 req.ah_cid = cpu_to_le32(ah->id); 465 466 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 467 sizeof(resp), block); 468 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 469 return rc; 470 } 471 472 /* MRW */ 473 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 474 { 475 struct creq_deallocate_key_resp resp = {}; 476 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 477 struct cmdq_deallocate_key req = {}; 478 struct bnxt_qplib_cmdqmsg msg = {}; 479 int rc; 480 481 if (mrw->lkey == 0xFFFFFFFF) { 482 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 483 return 0; 484 } 485 486 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 487 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 488 sizeof(req)); 489 490 req.mrw_flags = mrw->type; 491 492 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 493 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 494 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 495 req.key = cpu_to_le32(mrw->rkey); 496 else 497 req.key = cpu_to_le32(mrw->lkey); 498 499 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 500 sizeof(resp), 0); 501 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 502 if (rc) 503 return rc; 504 505 /* Free the qplib's MRW memory */ 506 if (mrw->hwq.max_elements) 507 bnxt_qplib_free_hwq(res, &mrw->hwq); 508 509 return 0; 510 } 511 512 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 513 { 514 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 515 struct creq_allocate_mrw_resp resp = {}; 516 struct bnxt_qplib_cmdqmsg msg = {}; 517 struct cmdq_allocate_mrw req = {}; 518 unsigned long tmp; 519 int rc; 520 521 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 522 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 523 sizeof(req)); 524 525 req.pd_id = cpu_to_le32(mrw->pd->id); 526 req.mrw_flags = mrw->type; 527 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 528 mrw->access_flags & BNXT_QPLIB_FR_PMR) || 529 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 530 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 531 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 532 tmp = (unsigned long)mrw; 533 req.mrw_handle = cpu_to_le64(tmp); 534 535 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 536 sizeof(resp), 0); 537 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 538 if (rc) 539 return rc; 540 541 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 542 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 543 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 544 mrw->rkey = le32_to_cpu(resp.xid); 545 else 546 mrw->lkey = le32_to_cpu(resp.xid); 547 return 0; 548 } 549 550 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 551 bool block) 552 { 553 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 554 struct creq_deregister_mr_resp resp = {}; 555 struct bnxt_qplib_cmdqmsg msg = {}; 556 struct cmdq_deregister_mr req = {}; 557 int rc; 558 559 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 560 CMDQ_BASE_OPCODE_DEREGISTER_MR, 561 sizeof(req)); 562 563 req.lkey = cpu_to_le32(mrw->lkey); 564 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 565 sizeof(resp), block); 566 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 567 if (rc) 568 return rc; 569 570 /* Free the qplib's MR memory */ 571 if (mrw->hwq.max_elements) { 572 mrw->va = 0; 573 mrw->total_size = 0; 574 bnxt_qplib_free_hwq(res, &mrw->hwq); 575 } 576 577 return 0; 578 } 579 580 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 581 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 582 { 583 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 584 struct bnxt_qplib_hwq_attr hwq_attr = {}; 585 struct bnxt_qplib_sg_info sginfo = {}; 586 struct creq_register_mr_resp resp = {}; 587 struct bnxt_qplib_cmdqmsg msg = {}; 588 struct cmdq_register_mr req = {}; 589 int pages, rc; 590 u32 pg_size; 591 u16 level; 592 593 if (num_pbls) { 594 pages = roundup_pow_of_two(num_pbls); 595 /* Allocate memory for the non-leaf pages to store buf ptrs. 596 * Non-leaf pages always uses system PAGE_SIZE 597 */ 598 /* Free the hwq if it already exist, must be a rereg */ 599 if (mr->hwq.max_elements) 600 bnxt_qplib_free_hwq(res, &mr->hwq); 601 hwq_attr.res = res; 602 hwq_attr.depth = pages; 603 hwq_attr.stride = sizeof(dma_addr_t); 604 hwq_attr.type = HWQ_TYPE_MR; 605 hwq_attr.sginfo = &sginfo; 606 hwq_attr.sginfo->umem = umem; 607 hwq_attr.sginfo->npages = pages; 608 hwq_attr.sginfo->pgsize = buf_pg_size; 609 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 610 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 611 if (rc) { 612 dev_err(&res->pdev->dev, 613 "SP: Reg MR memory allocation failed\n"); 614 return -ENOMEM; 615 } 616 } 617 618 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 619 CMDQ_BASE_OPCODE_REGISTER_MR, 620 sizeof(req)); 621 622 /* Configure the request */ 623 if (mr->hwq.level == PBL_LVL_MAX) { 624 /* No PBL provided, just use system PAGE_SIZE */ 625 level = 0; 626 req.pbl = 0; 627 pg_size = PAGE_SIZE; 628 } else { 629 level = mr->hwq.level; 630 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 631 } 632 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 633 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 634 ((ilog2(pg_size) << 635 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 636 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 637 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 638 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 639 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 640 req.access = (mr->access_flags & BNXT_QPLIB_MR_ACCESS_MASK); 641 req.va = cpu_to_le64(mr->va); 642 req.key = cpu_to_le32(mr->lkey); 643 if (_is_alloc_mr_unified(res->dattr->dev_cap_flags)) 644 req.key = cpu_to_le32(mr->pd->id); 645 req.flags = cpu_to_le16(mr->flags); 646 req.mr_size = cpu_to_le64(mr->total_size); 647 648 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 649 sizeof(resp), 0); 650 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 651 if (rc) 652 goto fail; 653 654 if (_is_alloc_mr_unified(res->dattr->dev_cap_flags)) { 655 mr->lkey = le32_to_cpu(resp.xid); 656 mr->rkey = mr->lkey; 657 } 658 659 return 0; 660 661 fail: 662 if (mr->hwq.max_elements) 663 bnxt_qplib_free_hwq(res, &mr->hwq); 664 return rc; 665 } 666 667 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 668 struct bnxt_qplib_frpl *frpl, 669 int max_pg_ptrs) 670 { 671 struct bnxt_qplib_hwq_attr hwq_attr = {}; 672 struct bnxt_qplib_sg_info sginfo = {}; 673 int pg_ptrs, pages, rc; 674 675 /* Re-calculate the max to fit the HWQ allocation model */ 676 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 677 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 678 if (!pages) 679 pages++; 680 681 if (pages > MAX_PBL_LVL_1_PGS) 682 return -ENOMEM; 683 684 sginfo.pgsize = PAGE_SIZE; 685 sginfo.nopte = true; 686 687 hwq_attr.res = res; 688 hwq_attr.depth = pg_ptrs; 689 hwq_attr.stride = PAGE_SIZE; 690 hwq_attr.sginfo = &sginfo; 691 hwq_attr.type = HWQ_TYPE_CTX; 692 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 693 if (!rc) 694 frpl->max_pg_ptrs = pg_ptrs; 695 696 return rc; 697 } 698 699 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 700 struct bnxt_qplib_frpl *frpl) 701 { 702 bnxt_qplib_free_hwq(res, &frpl->hwq); 703 return 0; 704 } 705 706 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 707 struct bnxt_qplib_roce_stats *stats) 708 { 709 struct creq_query_roce_stats_resp resp = {}; 710 struct creq_query_roce_stats_resp_sb *sb; 711 struct cmdq_query_roce_stats req = {}; 712 struct bnxt_qplib_cmdqmsg msg = {}; 713 struct bnxt_qplib_rcfw_sbuf sbuf; 714 int rc; 715 716 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 717 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 718 sizeof(req)); 719 720 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 721 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 722 &sbuf.dma_addr, GFP_KERNEL); 723 if (!sbuf.sb) 724 return -ENOMEM; 725 sb = sbuf.sb; 726 727 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 728 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 729 sizeof(resp), 0); 730 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 731 if (rc) 732 goto bail; 733 /* Extract the context from the side buffer */ 734 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 735 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 736 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 737 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 738 stats->missing_resp = le64_to_cpu(sb->missing_resp); 739 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 740 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 741 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 742 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 743 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 744 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 745 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 746 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 747 stats->dup_req = le64_to_cpu(sb->dup_req); 748 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 749 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 750 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 751 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 752 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 753 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 754 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 755 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 756 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 757 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 758 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 759 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 760 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 761 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 762 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 763 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 764 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 765 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 766 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 767 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 768 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 769 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 770 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 771 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 772 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 773 if (!rcfw->init_oos_stats) { 774 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 775 rcfw->init_oos_stats = 1; 776 } else { 777 stats->res_oos_drop_count += 778 (le64_to_cpu(sb->res_oos_drop_count) - 779 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 780 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 781 } 782 783 bail: 784 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 785 sbuf.sb, sbuf.dma_addr); 786 return rc; 787 } 788 789 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 790 struct bnxt_qplib_ext_stat *estat) 791 { 792 struct creq_query_roce_stats_ext_resp resp = {}; 793 struct creq_query_roce_stats_ext_resp_sb *sb; 794 struct cmdq_query_roce_stats_ext req = {}; 795 struct bnxt_qplib_cmdqmsg msg = {}; 796 struct bnxt_qplib_rcfw_sbuf sbuf; 797 int rc; 798 799 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 800 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 801 &sbuf.dma_addr, GFP_KERNEL); 802 if (!sbuf.sb) 803 return -ENOMEM; 804 805 sb = sbuf.sb; 806 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 807 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 808 sizeof(req)); 809 810 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 811 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 812 if (bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx) && rcfw->res->is_vf) 813 req.function_id = 814 cpu_to_le32(CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID | 815 (fid << CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT)); 816 else 817 req.function_id = cpu_to_le32(fid); 818 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 819 820 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 821 sizeof(resp), 0); 822 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 823 if (rc) 824 goto bail; 825 826 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 827 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 828 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 829 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 830 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 831 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 832 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 833 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 834 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 835 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 836 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 837 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 838 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 839 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 840 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 841 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 842 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 843 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 844 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 845 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 846 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 847 848 bail: 849 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 850 sbuf.sb, sbuf.dma_addr); 851 return rc; 852 } 853 854 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 855 struct bnxt_qplib_cc_param_ext *cc_ext) 856 { 857 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 858 cc_ext->ext_mask = 0; 859 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 860 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 861 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 862 ext_req->tr_update_mode = cc_ext->tr_update_mode; 863 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 864 ext_req->fr_num_rtts = cc_ext->fr_rtt; 865 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 866 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 867 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 868 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 869 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 870 ext_req->actual_cr_factor = cc_ext->cr_factor; 871 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 872 ext_req->cp_bias_en = cc_ext->cp_bias_en; 873 ext_req->cp_bias = cc_ext->cp_bias; 874 ext_req->cnp_ecn = cc_ext->cnp_ecn; 875 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 876 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 877 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 878 ext_req->cr_width = cc_ext->cr_width; 879 ext_req->quota_period_min = cc_ext->min_quota; 880 ext_req->quota_period_max = cc_ext->max_quota; 881 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 882 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 883 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 884 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 885 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 886 ext_req->red_div = cc_ext->red_div; 887 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 888 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 889 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 890 ext_req->use_rate_table = cc_ext->low_rate_en; 891 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 892 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 893 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 894 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 895 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 896 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 897 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 898 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 899 } 900 901 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 902 struct bnxt_qplib_cc_param *cc_param) 903 { 904 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 905 struct creq_modify_roce_cc_resp resp = {}; 906 struct bnxt_qplib_cmdqmsg msg = {}; 907 struct cmdq_modify_roce_cc *req; 908 int req_size; 909 void *cmd; 910 int rc; 911 912 /* Prepare the older base command */ 913 req = &tlv_req.base_req; 914 cmd = req; 915 req_size = sizeof(*req); 916 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 917 sizeof(*req)); 918 req->modify_mask = cpu_to_le32(cc_param->mask); 919 req->enable_cc = cc_param->enable; 920 req->g = cc_param->g; 921 req->num_phases_per_state = cc_param->nph_per_state; 922 req->time_per_phase = cc_param->time_pph; 923 req->pkts_per_phase = cc_param->pkts_pph; 924 req->init_cr = cpu_to_le16(cc_param->init_cr); 925 req->init_tr = cpu_to_le16(cc_param->init_tr); 926 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 927 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 928 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 929 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 930 req->rtt = cpu_to_le16(cc_param->rtt); 931 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 932 req->cc_mode = cc_param->cc_mode; 933 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 934 935 /* For chip gen P5 onwards fill extended cmd and header */ 936 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 937 struct roce_tlv *hdr; 938 u32 payload; 939 u32 chunks; 940 941 cmd = &tlv_req; 942 req_size = sizeof(tlv_req); 943 /* Prepare primary tlv header */ 944 hdr = &tlv_req.tlv_hdr; 945 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 946 payload = sizeof(struct cmdq_modify_roce_cc); 947 __roce_1st_tlv_prep(hdr, chunks, payload, true); 948 /* Prepare secondary tlv header */ 949 hdr = (struct roce_tlv *)&tlv_req.ext_req; 950 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 951 sizeof(struct roce_tlv); 952 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 953 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 954 } 955 956 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 957 sizeof(resp), 0); 958 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 959 return rc; 960 } 961 962 int bnxt_qplib_read_context(struct bnxt_qplib_rcfw *rcfw, u8 res_type, 963 u32 xid, u32 resp_size, void *resp_va) 964 { 965 struct creq_read_context resp = {}; 966 struct bnxt_qplib_cmdqmsg msg = {}; 967 struct cmdq_read_context req = {}; 968 struct bnxt_qplib_rcfw_sbuf sbuf; 969 int rc; 970 971 sbuf.size = resp_size; 972 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 973 &sbuf.dma_addr, GFP_KERNEL); 974 if (!sbuf.sb) 975 return -ENOMEM; 976 977 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 978 CMDQ_BASE_OPCODE_READ_CONTEXT, sizeof(req)); 979 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 980 req.resp_size = resp_size / BNXT_QPLIB_CMDQE_UNITS; 981 982 req.xid = cpu_to_le32(xid); 983 req.type = res_type; 984 985 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 986 sizeof(resp), 0); 987 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 988 if (rc) 989 goto free_mem; 990 991 memcpy(resp_va, sbuf.sb, resp_size); 992 free_mem: 993 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 994 return rc; 995 } 996 997 static void bnxt_qplib_read_cc_gen1(struct bnxt_qplib_cc_param_ext *cc_ext, 998 struct creq_query_roce_cc_gen1_resp_sb_tlv *sb) 999 { 1000 cc_ext->inact_th_hi = le16_to_cpu(sb->inactivity_th_hi); 1001 cc_ext->min_delta_cnp = le16_to_cpu(sb->min_time_between_cnps); 1002 cc_ext->init_cp = le16_to_cpu(sb->init_cp); 1003 cc_ext->tr_update_mode = sb->tr_update_mode; 1004 cc_ext->tr_update_cyls = sb->tr_update_cycles; 1005 cc_ext->fr_rtt = sb->fr_num_rtts; 1006 cc_ext->ai_rate_incr = sb->ai_rate_increase; 1007 cc_ext->rr_rtt_th = le16_to_cpu(sb->reduction_relax_rtts_th); 1008 cc_ext->ar_cr_th = le16_to_cpu(sb->additional_relax_cr_th); 1009 cc_ext->cr_min_th = le16_to_cpu(sb->cr_min_th); 1010 cc_ext->bw_avg_weight = sb->bw_avg_weight; 1011 cc_ext->cr_factor = sb->actual_cr_factor; 1012 cc_ext->cr_th_max_cp = le16_to_cpu(sb->max_cp_cr_th); 1013 cc_ext->cp_bias_en = sb->cp_bias_en; 1014 cc_ext->cp_bias = sb->cp_bias; 1015 cc_ext->cnp_ecn = sb->cnp_ecn; 1016 cc_ext->rtt_jitter_en = sb->rtt_jitter_en; 1017 cc_ext->bytes_per_usec = le16_to_cpu(sb->link_bytes_per_usec); 1018 cc_ext->cc_cr_reset_th = le16_to_cpu(sb->reset_cc_cr_th); 1019 cc_ext->cr_width = sb->cr_width; 1020 cc_ext->min_quota = sb->quota_period_min; 1021 cc_ext->max_quota = sb->quota_period_max; 1022 cc_ext->abs_max_quota = sb->quota_period_abs_max; 1023 cc_ext->tr_lb = le16_to_cpu(sb->tr_lower_bound); 1024 cc_ext->cr_prob_fac = sb->cr_prob_factor; 1025 cc_ext->tr_prob_fac = sb->tr_prob_factor; 1026 cc_ext->fair_cr_th = le16_to_cpu(sb->fairness_cr_th); 1027 cc_ext->red_div = sb->red_div; 1028 cc_ext->cnp_ratio_th = sb->cnp_ratio_th; 1029 cc_ext->ai_ext_rtt = le16_to_cpu(sb->exp_ai_rtts); 1030 cc_ext->exp_crcp_ratio = sb->exp_ai_cr_cp_ratio; 1031 cc_ext->low_rate_en = sb->use_rate_table; 1032 cc_ext->cpcr_update_th = le16_to_cpu(sb->cp_exp_update_th); 1033 cc_ext->ai_rtt_th1 = le16_to_cpu(sb->high_exp_ai_rtts_th1); 1034 cc_ext->ai_rtt_th2 = le16_to_cpu(sb->high_exp_ai_rtts_th2); 1035 cc_ext->cf_rtt_th = le16_to_cpu(sb->actual_cr_cong_free_rtts_th); 1036 cc_ext->sc_cr_th1 = le16_to_cpu(sb->severe_cong_cr_th1); 1037 cc_ext->sc_cr_th2 = le16_to_cpu(sb->severe_cong_cr_th2); 1038 cc_ext->l64B_per_rtt = le32_to_cpu(sb->link64B_per_rtt); 1039 cc_ext->cc_ack_bytes = sb->cc_ack_bytes; 1040 cc_ext->reduce_cf_rtt_th = le16_to_cpu(sb->reduce_init_cong_free_rtts_th); 1041 } 1042 1043 int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res, 1044 struct bnxt_qplib_cc_param *cc_param) 1045 { 1046 struct bnxt_qplib_tlv_query_rcc_sb *ext_sb; 1047 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1048 struct creq_query_roce_cc_resp resp = {}; 1049 struct creq_query_roce_cc_resp_sb *sb; 1050 struct bnxt_qplib_cmdqmsg msg = {}; 1051 struct cmdq_query_roce_cc req = {}; 1052 struct bnxt_qplib_rcfw_sbuf sbuf; 1053 size_t resp_size; 1054 int rc; 1055 1056 /* Query the parameters from chip */ 1057 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, CMDQ_BASE_OPCODE_QUERY_ROCE_CC, 1058 sizeof(req)); 1059 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) 1060 resp_size = sizeof(*ext_sb); 1061 else 1062 resp_size = sizeof(*sb); 1063 1064 sbuf.size = ALIGN(resp_size, BNXT_QPLIB_CMDQE_UNITS); 1065 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 1066 &sbuf.dma_addr, GFP_KERNEL); 1067 if (!sbuf.sb) 1068 return -ENOMEM; 1069 1070 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 1071 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 1072 sizeof(resp), 0); 1073 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 1074 if (rc) 1075 goto out; 1076 1077 ext_sb = sbuf.sb; 1078 sb = bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? &ext_sb->base_sb : 1079 (struct creq_query_roce_cc_resp_sb *)ext_sb; 1080 1081 cc_param->enable = sb->enable_cc & CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC; 1082 cc_param->tos_ecn = (sb->tos_dscp_tos_ecn & 1083 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK) >> 1084 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT; 1085 cc_param->tos_dscp = (sb->tos_dscp_tos_ecn & 1086 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK) >> 1087 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT; 1088 cc_param->alt_tos_dscp = sb->alt_tos_dscp; 1089 cc_param->alt_vlan_pcp = sb->alt_vlan_pcp; 1090 1091 cc_param->g = sb->g; 1092 cc_param->nph_per_state = sb->num_phases_per_state; 1093 cc_param->init_cr = le16_to_cpu(sb->init_cr); 1094 cc_param->init_tr = le16_to_cpu(sb->init_tr); 1095 cc_param->cc_mode = sb->cc_mode; 1096 cc_param->inact_th = le16_to_cpu(sb->inactivity_th); 1097 cc_param->rtt = le16_to_cpu(sb->rtt); 1098 cc_param->tcp_cp = le16_to_cpu(sb->tcp_cp); 1099 cc_param->time_pph = sb->time_per_phase; 1100 cc_param->pkts_pph = sb->pkts_per_phase; 1101 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 1102 bnxt_qplib_read_cc_gen1(&cc_param->cc_ext, &ext_sb->gen1_sb); 1103 cc_param->inact_th |= (cc_param->cc_ext.inact_th_hi & 0x3F) << 16; 1104 } 1105 out: 1106 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 1107 return rc; 1108 } 1109 1110 int bnxt_qplib_create_flow(struct bnxt_qplib_res *res) 1111 { 1112 struct creq_roce_mirror_cfg_resp resp = {}; 1113 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1114 struct cmdq_roce_mirror_cfg req = {}; 1115 struct bnxt_qplib_cmdqmsg msg = {}; 1116 1117 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 1118 CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG, 1119 sizeof(req)); 1120 1121 req.mirror_flags = (u8)CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE; 1122 1123 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 1124 sizeof(resp), 0); 1125 return bnxt_qplib_rcfw_send_message(rcfw, &msg); 1126 } 1127 1128 int bnxt_qplib_destroy_flow(struct bnxt_qplib_res *res) 1129 { 1130 struct creq_roce_mirror_cfg_resp resp = {}; 1131 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1132 struct cmdq_roce_mirror_cfg req = {}; 1133 struct bnxt_qplib_cmdqmsg msg = {}; 1134 1135 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 1136 CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG, 1137 sizeof(req)); 1138 1139 req.mirror_flags &= ~((u8)CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE); 1140 1141 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 1142 sizeof(resp), 0); 1143 1144 return bnxt_qplib_rcfw_send_message(rcfw, &msg); 1145 } 1146