1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_tlv.h" 52 53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56 /* Device */ 57 58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59 { 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67 } 68 69 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, 70 char *fw_ver) 71 { 72 struct creq_query_version_resp resp = {}; 73 struct bnxt_qplib_cmdqmsg msg = {}; 74 struct cmdq_query_version req = {}; 75 int rc; 76 77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 78 CMDQ_BASE_OPCODE_QUERY_VERSION, 79 sizeof(req)); 80 81 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 82 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 83 if (rc) 84 return; 85 fw_ver[0] = resp.fw_maj; 86 fw_ver[1] = resp.fw_minor; 87 fw_ver[2] = resp.fw_bld; 88 fw_ver[3] = resp.fw_rsvd; 89 } 90 91 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 92 struct bnxt_qplib_dev_attr *attr) 93 { 94 struct creq_query_func_resp resp = {}; 95 struct bnxt_qplib_cmdqmsg msg = {}; 96 struct creq_query_func_resp_sb *sb; 97 struct bnxt_qplib_rcfw_sbuf sbuf; 98 struct bnxt_qplib_chip_ctx *cctx; 99 struct cmdq_query_func req = {}; 100 u8 *tqm_alloc; 101 int i, rc; 102 u32 temp; 103 104 cctx = rcfw->res->cctx; 105 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 106 CMDQ_BASE_OPCODE_QUERY_FUNC, 107 sizeof(req)); 108 109 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 110 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 111 &sbuf.dma_addr, GFP_KERNEL); 112 if (!sbuf.sb) 113 return -ENOMEM; 114 sb = sbuf.sb; 115 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 116 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 117 sizeof(resp), 0); 118 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 119 if (rc) 120 goto bail; 121 122 /* Extract the context from the side buffer */ 123 attr->max_qp = le32_to_cpu(sb->max_qp); 124 /* max_qp value reported by FW doesn't include the QP1 */ 125 attr->max_qp += 1; 126 attr->max_qp_rd_atom = 127 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 128 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 129 attr->max_qp_init_rd_atom = 130 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 131 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 132 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr); 133 /* 134 * 128 WQEs needs to be reserved for the HW (8916). Prevent 135 * reporting the max number 136 */ 137 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 138 139 attr->max_qp_sges = cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE ? 140 min_t(u32, sb->max_sge_var_wqe, BNXT_VAR_MAX_SGE) : 6; 141 attr->max_cq = le32_to_cpu(sb->max_cq); 142 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 143 attr->max_cq_sges = attr->max_qp_sges; 144 attr->max_mr = le32_to_cpu(sb->max_mr); 145 attr->max_mw = le32_to_cpu(sb->max_mw); 146 147 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 148 attr->max_pd = 64 * 1024; 149 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 150 attr->max_ah = le32_to_cpu(sb->max_ah); 151 152 attr->max_srq = le16_to_cpu(sb->max_srq); 153 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 154 attr->max_srq_sges = sb->max_srq_sge; 155 attr->max_pkey = 1; 156 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 157 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 158 attr->l2_db_size = (sb->l2_db_space_size + 1) * 159 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 160 attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED; 161 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 162 attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2); 163 164 bnxt_qplib_query_version(rcfw, attr->fw_ver); 165 166 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 167 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 168 tqm_alloc = (u8 *)&temp; 169 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 170 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 171 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 172 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 173 } 174 175 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 176 attr->max_dpi = le32_to_cpu(sb->max_dpi); 177 178 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 179 bail: 180 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 181 sbuf.sb, sbuf.dma_addr); 182 return rc; 183 } 184 185 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 186 struct bnxt_qplib_rcfw *rcfw, 187 struct bnxt_qplib_ctx *ctx) 188 { 189 struct creq_set_func_resources_resp resp = {}; 190 struct cmdq_set_func_resources req = {}; 191 struct bnxt_qplib_cmdqmsg msg = {}; 192 int rc; 193 194 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 195 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 196 sizeof(req)); 197 198 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 199 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 200 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 201 req.number_of_cq = cpu_to_le32(ctx->cq_count); 202 203 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 204 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 205 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 206 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 207 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 208 209 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 210 sizeof(resp), 0); 211 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 212 if (rc) { 213 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 214 } 215 return rc; 216 } 217 218 /* SGID */ 219 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 220 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 221 struct bnxt_qplib_gid *gid) 222 { 223 if (index >= sgid_tbl->max) { 224 dev_err(&res->pdev->dev, 225 "Index %d exceeded SGID table max (%d)\n", 226 index, sgid_tbl->max); 227 return -EINVAL; 228 } 229 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 230 return 0; 231 } 232 233 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 234 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 235 { 236 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 237 struct bnxt_qplib_res, 238 sgid_tbl); 239 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 240 int index; 241 242 /* Do we need a sgid_lock here? */ 243 if (!sgid_tbl->active) { 244 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 245 return -ENOMEM; 246 } 247 for (index = 0; index < sgid_tbl->max; index++) { 248 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 249 vlan_id == sgid_tbl->tbl[index].vlan_id) 250 break; 251 } 252 if (index == sgid_tbl->max) { 253 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 254 return 0; 255 } 256 /* Remove GID from the SGID table */ 257 if (update) { 258 struct creq_delete_gid_resp resp = {}; 259 struct bnxt_qplib_cmdqmsg msg = {}; 260 struct cmdq_delete_gid req = {}; 261 int rc; 262 263 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 264 CMDQ_BASE_OPCODE_DELETE_GID, 265 sizeof(req)); 266 if (sgid_tbl->hw_id[index] == 0xFFFF) { 267 dev_err(&res->pdev->dev, 268 "GID entry contains an invalid HW id\n"); 269 return -EINVAL; 270 } 271 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 272 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 273 sizeof(resp), 0); 274 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 275 if (rc) 276 return rc; 277 } 278 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 279 sizeof(bnxt_qplib_gid_zero)); 280 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 281 sgid_tbl->vlan[index] = 0; 282 sgid_tbl->active--; 283 dev_dbg(&res->pdev->dev, 284 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 285 index, sgid_tbl->hw_id[index], sgid_tbl->active); 286 sgid_tbl->hw_id[index] = (u16)-1; 287 288 /* unlock */ 289 return 0; 290 } 291 292 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 293 struct bnxt_qplib_gid *gid, const u8 *smac, 294 u16 vlan_id, bool update, u32 *index) 295 { 296 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 297 struct bnxt_qplib_res, 298 sgid_tbl); 299 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 300 int i, free_idx; 301 302 /* Do we need a sgid_lock here? */ 303 if (sgid_tbl->active == sgid_tbl->max) { 304 dev_err(&res->pdev->dev, "SGID table is full\n"); 305 return -ENOMEM; 306 } 307 free_idx = sgid_tbl->max; 308 for (i = 0; i < sgid_tbl->max; i++) { 309 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 310 sgid_tbl->tbl[i].vlan_id == vlan_id) { 311 dev_dbg(&res->pdev->dev, 312 "SGID entry already exist in entry %d!\n", i); 313 *index = i; 314 return -EALREADY; 315 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 316 sizeof(bnxt_qplib_gid_zero)) && 317 free_idx == sgid_tbl->max) { 318 free_idx = i; 319 } 320 } 321 if (free_idx == sgid_tbl->max) { 322 dev_err(&res->pdev->dev, 323 "SGID table is FULL but count is not MAX??\n"); 324 return -ENOMEM; 325 } 326 if (update) { 327 struct creq_add_gid_resp resp = {}; 328 struct bnxt_qplib_cmdqmsg msg = {}; 329 struct cmdq_add_gid req = {}; 330 int rc; 331 332 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 333 CMDQ_BASE_OPCODE_ADD_GID, 334 sizeof(req)); 335 336 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 337 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 338 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 339 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 340 /* 341 * driver should ensure that all RoCE traffic is always VLAN 342 * tagged if RoCE traffic is running on non-zero VLAN ID or 343 * RoCE traffic is running on non-zero Priority. 344 */ 345 if ((vlan_id != 0xFFFF) || res->prio) { 346 if (vlan_id != 0xFFFF) 347 req.vlan = cpu_to_le16 348 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 349 req.vlan |= cpu_to_le16 350 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 351 CMDQ_ADD_GID_VLAN_VLAN_EN); 352 } 353 354 /* MAC in network format */ 355 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 356 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 357 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 358 359 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 360 sizeof(resp), 0); 361 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 362 if (rc) 363 return rc; 364 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 365 } 366 /* Add GID to the sgid_tbl */ 367 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 368 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 369 sgid_tbl->active++; 370 if (vlan_id != 0xFFFF) 371 sgid_tbl->vlan[free_idx] = 1; 372 373 dev_dbg(&res->pdev->dev, 374 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 375 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 376 377 *index = free_idx; 378 /* unlock */ 379 return 0; 380 } 381 382 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 383 struct bnxt_qplib_gid *gid, u16 gid_idx, 384 const u8 *smac) 385 { 386 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 387 struct bnxt_qplib_res, 388 sgid_tbl); 389 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 390 struct creq_modify_gid_resp resp = {}; 391 struct bnxt_qplib_cmdqmsg msg = {}; 392 struct cmdq_modify_gid req = {}; 393 int rc; 394 395 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 396 CMDQ_BASE_OPCODE_MODIFY_GID, 397 sizeof(req)); 398 399 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 400 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 401 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 402 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 403 if (res->prio) { 404 req.vlan |= cpu_to_le16 405 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 406 CMDQ_ADD_GID_VLAN_VLAN_EN); 407 } 408 409 /* MAC in network format */ 410 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 411 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 412 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 413 414 req.gid_index = cpu_to_le16(gid_idx); 415 416 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 417 sizeof(resp), 0); 418 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 419 return rc; 420 } 421 422 /* AH */ 423 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 424 bool block) 425 { 426 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 427 struct creq_create_ah_resp resp = {}; 428 struct bnxt_qplib_cmdqmsg msg = {}; 429 struct cmdq_create_ah req = {}; 430 u32 temp32[4]; 431 u16 temp16[3]; 432 int rc; 433 434 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 435 CMDQ_BASE_OPCODE_CREATE_AH, 436 sizeof(req)); 437 438 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 439 req.dgid[0] = cpu_to_le32(temp32[0]); 440 req.dgid[1] = cpu_to_le32(temp32[1]); 441 req.dgid[2] = cpu_to_le32(temp32[2]); 442 req.dgid[3] = cpu_to_le32(temp32[3]); 443 444 req.type = ah->nw_type; 445 req.hop_limit = ah->hop_limit; 446 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 447 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 448 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 449 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 450 req.pd_id = cpu_to_le32(ah->pd->id); 451 req.traffic_class = ah->traffic_class; 452 453 /* MAC in network format */ 454 memcpy(temp16, ah->dmac, 6); 455 req.dest_mac[0] = cpu_to_le16(temp16[0]); 456 req.dest_mac[1] = cpu_to_le16(temp16[1]); 457 req.dest_mac[2] = cpu_to_le16(temp16[2]); 458 459 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 460 sizeof(resp), block); 461 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 462 if (rc) 463 return rc; 464 465 ah->id = le32_to_cpu(resp.xid); 466 return 0; 467 } 468 469 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 470 bool block) 471 { 472 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 473 struct creq_destroy_ah_resp resp = {}; 474 struct bnxt_qplib_cmdqmsg msg = {}; 475 struct cmdq_destroy_ah req = {}; 476 int rc; 477 478 /* Clean up the AH table in the device */ 479 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 480 CMDQ_BASE_OPCODE_DESTROY_AH, 481 sizeof(req)); 482 483 req.ah_cid = cpu_to_le32(ah->id); 484 485 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 486 sizeof(resp), block); 487 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 488 return rc; 489 } 490 491 /* MRW */ 492 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 493 { 494 struct creq_deallocate_key_resp resp = {}; 495 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 496 struct cmdq_deallocate_key req = {}; 497 struct bnxt_qplib_cmdqmsg msg = {}; 498 int rc; 499 500 if (mrw->lkey == 0xFFFFFFFF) { 501 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 502 return 0; 503 } 504 505 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 506 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 507 sizeof(req)); 508 509 req.mrw_flags = mrw->type; 510 511 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 512 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 513 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 514 req.key = cpu_to_le32(mrw->rkey); 515 else 516 req.key = cpu_to_le32(mrw->lkey); 517 518 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 519 sizeof(resp), 0); 520 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 521 if (rc) 522 return rc; 523 524 /* Free the qplib's MRW memory */ 525 if (mrw->hwq.max_elements) 526 bnxt_qplib_free_hwq(res, &mrw->hwq); 527 528 return 0; 529 } 530 531 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 532 { 533 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 534 struct creq_allocate_mrw_resp resp = {}; 535 struct bnxt_qplib_cmdqmsg msg = {}; 536 struct cmdq_allocate_mrw req = {}; 537 unsigned long tmp; 538 int rc; 539 540 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 541 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 542 sizeof(req)); 543 544 req.pd_id = cpu_to_le32(mrw->pd->id); 545 req.mrw_flags = mrw->type; 546 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 547 mrw->access_flags & BNXT_QPLIB_FR_PMR) || 548 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 549 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 550 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 551 tmp = (unsigned long)mrw; 552 req.mrw_handle = cpu_to_le64(tmp); 553 554 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 555 sizeof(resp), 0); 556 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 557 if (rc) 558 return rc; 559 560 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 561 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 562 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 563 mrw->rkey = le32_to_cpu(resp.xid); 564 else 565 mrw->lkey = le32_to_cpu(resp.xid); 566 return 0; 567 } 568 569 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 570 bool block) 571 { 572 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 573 struct creq_deregister_mr_resp resp = {}; 574 struct bnxt_qplib_cmdqmsg msg = {}; 575 struct cmdq_deregister_mr req = {}; 576 int rc; 577 578 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 579 CMDQ_BASE_OPCODE_DEREGISTER_MR, 580 sizeof(req)); 581 582 req.lkey = cpu_to_le32(mrw->lkey); 583 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 584 sizeof(resp), block); 585 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 586 if (rc) 587 return rc; 588 589 /* Free the qplib's MR memory */ 590 if (mrw->hwq.max_elements) { 591 mrw->va = 0; 592 mrw->total_size = 0; 593 bnxt_qplib_free_hwq(res, &mrw->hwq); 594 } 595 596 return 0; 597 } 598 599 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 600 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 601 { 602 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 603 struct bnxt_qplib_hwq_attr hwq_attr = {}; 604 struct bnxt_qplib_sg_info sginfo = {}; 605 struct creq_register_mr_resp resp = {}; 606 struct bnxt_qplib_cmdqmsg msg = {}; 607 struct cmdq_register_mr req = {}; 608 int pages, rc; 609 u32 pg_size; 610 u16 level; 611 612 if (num_pbls) { 613 pages = roundup_pow_of_two(num_pbls); 614 /* Allocate memory for the non-leaf pages to store buf ptrs. 615 * Non-leaf pages always uses system PAGE_SIZE 616 */ 617 /* Free the hwq if it already exist, must be a rereg */ 618 if (mr->hwq.max_elements) 619 bnxt_qplib_free_hwq(res, &mr->hwq); 620 hwq_attr.res = res; 621 hwq_attr.depth = pages; 622 hwq_attr.stride = sizeof(dma_addr_t); 623 hwq_attr.type = HWQ_TYPE_MR; 624 hwq_attr.sginfo = &sginfo; 625 hwq_attr.sginfo->umem = umem; 626 hwq_attr.sginfo->npages = pages; 627 hwq_attr.sginfo->pgsize = buf_pg_size; 628 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 629 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 630 if (rc) { 631 dev_err(&res->pdev->dev, 632 "SP: Reg MR memory allocation failed\n"); 633 return -ENOMEM; 634 } 635 } 636 637 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 638 CMDQ_BASE_OPCODE_REGISTER_MR, 639 sizeof(req)); 640 641 /* Configure the request */ 642 if (mr->hwq.level == PBL_LVL_MAX) { 643 /* No PBL provided, just use system PAGE_SIZE */ 644 level = 0; 645 req.pbl = 0; 646 pg_size = PAGE_SIZE; 647 } else { 648 level = mr->hwq.level; 649 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 650 } 651 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 652 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 653 ((ilog2(pg_size) << 654 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 655 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 656 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 657 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 658 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 659 req.access = (mr->access_flags & 0xFFFF); 660 req.va = cpu_to_le64(mr->va); 661 req.key = cpu_to_le32(mr->lkey); 662 if (_is_alloc_mr_unified(res->dattr->dev_cap_flags)) 663 req.key = cpu_to_le32(mr->pd->id); 664 req.flags = cpu_to_le16(mr->flags); 665 req.mr_size = cpu_to_le64(mr->total_size); 666 667 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 668 sizeof(resp), 0); 669 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 670 if (rc) 671 goto fail; 672 673 if (_is_alloc_mr_unified(res->dattr->dev_cap_flags)) { 674 mr->lkey = le32_to_cpu(resp.xid); 675 mr->rkey = mr->lkey; 676 } 677 678 return 0; 679 680 fail: 681 if (mr->hwq.max_elements) 682 bnxt_qplib_free_hwq(res, &mr->hwq); 683 return rc; 684 } 685 686 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 687 struct bnxt_qplib_frpl *frpl, 688 int max_pg_ptrs) 689 { 690 struct bnxt_qplib_hwq_attr hwq_attr = {}; 691 struct bnxt_qplib_sg_info sginfo = {}; 692 int pg_ptrs, pages, rc; 693 694 /* Re-calculate the max to fit the HWQ allocation model */ 695 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 696 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 697 if (!pages) 698 pages++; 699 700 if (pages > MAX_PBL_LVL_1_PGS) 701 return -ENOMEM; 702 703 sginfo.pgsize = PAGE_SIZE; 704 sginfo.nopte = true; 705 706 hwq_attr.res = res; 707 hwq_attr.depth = pg_ptrs; 708 hwq_attr.stride = PAGE_SIZE; 709 hwq_attr.sginfo = &sginfo; 710 hwq_attr.type = HWQ_TYPE_CTX; 711 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 712 if (!rc) 713 frpl->max_pg_ptrs = pg_ptrs; 714 715 return rc; 716 } 717 718 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 719 struct bnxt_qplib_frpl *frpl) 720 { 721 bnxt_qplib_free_hwq(res, &frpl->hwq); 722 return 0; 723 } 724 725 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 726 struct bnxt_qplib_roce_stats *stats) 727 { 728 struct creq_query_roce_stats_resp resp = {}; 729 struct creq_query_roce_stats_resp_sb *sb; 730 struct cmdq_query_roce_stats req = {}; 731 struct bnxt_qplib_cmdqmsg msg = {}; 732 struct bnxt_qplib_rcfw_sbuf sbuf; 733 int rc; 734 735 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 736 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 737 sizeof(req)); 738 739 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 740 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 741 &sbuf.dma_addr, GFP_KERNEL); 742 if (!sbuf.sb) 743 return -ENOMEM; 744 sb = sbuf.sb; 745 746 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 747 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 748 sizeof(resp), 0); 749 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 750 if (rc) 751 goto bail; 752 /* Extract the context from the side buffer */ 753 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 754 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 755 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 756 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 757 stats->missing_resp = le64_to_cpu(sb->missing_resp); 758 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 759 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 760 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 761 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 762 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 763 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 764 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 765 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 766 stats->dup_req = le64_to_cpu(sb->dup_req); 767 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 768 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 769 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 770 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 771 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 772 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 773 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 774 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 775 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 776 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 777 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 778 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 779 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 780 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 781 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 782 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 783 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 784 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 785 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 786 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 787 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 788 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 789 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 790 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 791 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 792 if (!rcfw->init_oos_stats) { 793 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 794 rcfw->init_oos_stats = 1; 795 } else { 796 stats->res_oos_drop_count += 797 (le64_to_cpu(sb->res_oos_drop_count) - 798 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 799 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 800 } 801 802 bail: 803 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 804 sbuf.sb, sbuf.dma_addr); 805 return rc; 806 } 807 808 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 809 struct bnxt_qplib_ext_stat *estat) 810 { 811 struct creq_query_roce_stats_ext_resp resp = {}; 812 struct creq_query_roce_stats_ext_resp_sb *sb; 813 struct cmdq_query_roce_stats_ext req = {}; 814 struct bnxt_qplib_cmdqmsg msg = {}; 815 struct bnxt_qplib_rcfw_sbuf sbuf; 816 int rc; 817 818 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 819 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 820 &sbuf.dma_addr, GFP_KERNEL); 821 if (!sbuf.sb) 822 return -ENOMEM; 823 824 sb = sbuf.sb; 825 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 826 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 827 sizeof(req)); 828 829 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 830 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 831 req.function_id = cpu_to_le32(fid); 832 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 833 834 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 835 sizeof(resp), 0); 836 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 837 if (rc) 838 goto bail; 839 840 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 841 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 842 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 843 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 844 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 845 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 846 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 847 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 848 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 849 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 850 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 851 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 852 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 853 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 854 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 855 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 856 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 857 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 858 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 859 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 860 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 861 862 bail: 863 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 864 sbuf.sb, sbuf.dma_addr); 865 return rc; 866 } 867 868 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 869 struct bnxt_qplib_cc_param_ext *cc_ext) 870 { 871 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 872 cc_ext->ext_mask = 0; 873 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 874 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 875 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 876 ext_req->tr_update_mode = cc_ext->tr_update_mode; 877 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 878 ext_req->fr_num_rtts = cc_ext->fr_rtt; 879 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 880 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 881 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 882 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 883 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 884 ext_req->actual_cr_factor = cc_ext->cr_factor; 885 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 886 ext_req->cp_bias_en = cc_ext->cp_bias_en; 887 ext_req->cp_bias = cc_ext->cp_bias; 888 ext_req->cnp_ecn = cc_ext->cnp_ecn; 889 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 890 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 891 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 892 ext_req->cr_width = cc_ext->cr_width; 893 ext_req->quota_period_min = cc_ext->min_quota; 894 ext_req->quota_period_max = cc_ext->max_quota; 895 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 896 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 897 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 898 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 899 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 900 ext_req->red_div = cc_ext->red_div; 901 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 902 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 903 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 904 ext_req->use_rate_table = cc_ext->low_rate_en; 905 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 906 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 907 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 908 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 909 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 910 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 911 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 912 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 913 } 914 915 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 916 struct bnxt_qplib_cc_param *cc_param) 917 { 918 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 919 struct creq_modify_roce_cc_resp resp = {}; 920 struct bnxt_qplib_cmdqmsg msg = {}; 921 struct cmdq_modify_roce_cc *req; 922 int req_size; 923 void *cmd; 924 int rc; 925 926 /* Prepare the older base command */ 927 req = &tlv_req.base_req; 928 cmd = req; 929 req_size = sizeof(*req); 930 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 931 sizeof(*req)); 932 req->modify_mask = cpu_to_le32(cc_param->mask); 933 req->enable_cc = cc_param->enable; 934 req->g = cc_param->g; 935 req->num_phases_per_state = cc_param->nph_per_state; 936 req->time_per_phase = cc_param->time_pph; 937 req->pkts_per_phase = cc_param->pkts_pph; 938 req->init_cr = cpu_to_le16(cc_param->init_cr); 939 req->init_tr = cpu_to_le16(cc_param->init_tr); 940 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 941 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 942 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 943 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 944 req->rtt = cpu_to_le16(cc_param->rtt); 945 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 946 req->cc_mode = cc_param->cc_mode; 947 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 948 949 /* For chip gen P5 onwards fill extended cmd and header */ 950 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 951 struct roce_tlv *hdr; 952 u32 payload; 953 u32 chunks; 954 955 cmd = &tlv_req; 956 req_size = sizeof(tlv_req); 957 /* Prepare primary tlv header */ 958 hdr = &tlv_req.tlv_hdr; 959 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 960 payload = sizeof(struct cmdq_modify_roce_cc); 961 __roce_1st_tlv_prep(hdr, chunks, payload, true); 962 /* Prepare secondary tlv header */ 963 hdr = (struct roce_tlv *)&tlv_req.ext_req; 964 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 965 sizeof(struct roce_tlv); 966 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 967 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 968 } 969 970 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 971 sizeof(resp), 0); 972 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 973 return rc; 974 } 975