1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_tlv.h" 52 53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56 /* Device */ 57 58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59 { 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67 } 68 69 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, 70 char *fw_ver) 71 { 72 struct creq_query_version_resp resp = {}; 73 struct bnxt_qplib_cmdqmsg msg = {}; 74 struct cmdq_query_version req = {}; 75 int rc; 76 77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 78 CMDQ_BASE_OPCODE_QUERY_VERSION, 79 sizeof(req)); 80 81 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 82 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 83 if (rc) 84 return; 85 fw_ver[0] = resp.fw_maj; 86 fw_ver[1] = resp.fw_minor; 87 fw_ver[2] = resp.fw_bld; 88 fw_ver[3] = resp.fw_rsvd; 89 } 90 91 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 92 struct bnxt_qplib_dev_attr *attr) 93 { 94 struct creq_query_func_resp resp = {}; 95 struct bnxt_qplib_cmdqmsg msg = {}; 96 struct creq_query_func_resp_sb *sb; 97 struct bnxt_qplib_rcfw_sbuf sbuf; 98 struct cmdq_query_func req = {}; 99 u8 *tqm_alloc; 100 int i, rc; 101 u32 temp; 102 103 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 104 CMDQ_BASE_OPCODE_QUERY_FUNC, 105 sizeof(req)); 106 107 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 108 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 109 &sbuf.dma_addr, GFP_KERNEL); 110 if (!sbuf.sb) 111 return -ENOMEM; 112 sb = sbuf.sb; 113 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 114 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 115 sizeof(resp), 0); 116 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 117 if (rc) 118 goto bail; 119 120 /* Extract the context from the side buffer */ 121 attr->max_qp = le32_to_cpu(sb->max_qp); 122 /* max_qp value reported by FW doesn't include the QP1 */ 123 attr->max_qp += 1; 124 attr->max_qp_rd_atom = 125 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 126 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 127 attr->max_qp_init_rd_atom = 128 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 130 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr); 131 /* 132 * 128 WQEs needs to be reserved for the HW (8916). Prevent 133 * reporting the max number 134 */ 135 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 136 attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx) ? 137 6 : sb->max_sge; 138 attr->max_cq = le32_to_cpu(sb->max_cq); 139 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 140 attr->max_cq_sges = attr->max_qp_sges; 141 attr->max_mr = le32_to_cpu(sb->max_mr); 142 attr->max_mw = le32_to_cpu(sb->max_mw); 143 144 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 145 attr->max_pd = 64 * 1024; 146 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 147 attr->max_ah = le32_to_cpu(sb->max_ah); 148 149 attr->max_srq = le16_to_cpu(sb->max_srq); 150 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 151 attr->max_srq_sges = sb->max_srq_sge; 152 attr->max_pkey = 1; 153 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 154 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 155 attr->l2_db_size = (sb->l2_db_space_size + 1) * 156 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 157 attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED; 158 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 159 attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2); 160 161 bnxt_qplib_query_version(rcfw, attr->fw_ver); 162 163 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 164 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 165 tqm_alloc = (u8 *)&temp; 166 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 167 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 168 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 169 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 170 } 171 172 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 173 attr->max_dpi = le32_to_cpu(sb->max_dpi); 174 175 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 176 bail: 177 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 178 sbuf.sb, sbuf.dma_addr); 179 return rc; 180 } 181 182 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 183 struct bnxt_qplib_rcfw *rcfw, 184 struct bnxt_qplib_ctx *ctx) 185 { 186 struct creq_set_func_resources_resp resp = {}; 187 struct cmdq_set_func_resources req = {}; 188 struct bnxt_qplib_cmdqmsg msg = {}; 189 int rc; 190 191 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 192 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 193 sizeof(req)); 194 195 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 196 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 197 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 198 req.number_of_cq = cpu_to_le32(ctx->cq_count); 199 200 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 201 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 202 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 203 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 204 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 205 206 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 207 sizeof(resp), 0); 208 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 209 if (rc) { 210 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 211 } 212 return rc; 213 } 214 215 /* SGID */ 216 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 217 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 218 struct bnxt_qplib_gid *gid) 219 { 220 if (index >= sgid_tbl->max) { 221 dev_err(&res->pdev->dev, 222 "Index %d exceeded SGID table max (%d)\n", 223 index, sgid_tbl->max); 224 return -EINVAL; 225 } 226 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 227 return 0; 228 } 229 230 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 231 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 232 { 233 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 234 struct bnxt_qplib_res, 235 sgid_tbl); 236 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 237 int index; 238 239 /* Do we need a sgid_lock here? */ 240 if (!sgid_tbl->active) { 241 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 242 return -ENOMEM; 243 } 244 for (index = 0; index < sgid_tbl->max; index++) { 245 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 246 vlan_id == sgid_tbl->tbl[index].vlan_id) 247 break; 248 } 249 if (index == sgid_tbl->max) { 250 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 251 return 0; 252 } 253 /* Remove GID from the SGID table */ 254 if (update) { 255 struct creq_delete_gid_resp resp = {}; 256 struct bnxt_qplib_cmdqmsg msg = {}; 257 struct cmdq_delete_gid req = {}; 258 int rc; 259 260 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 261 CMDQ_BASE_OPCODE_DELETE_GID, 262 sizeof(req)); 263 if (sgid_tbl->hw_id[index] == 0xFFFF) { 264 dev_err(&res->pdev->dev, 265 "GID entry contains an invalid HW id\n"); 266 return -EINVAL; 267 } 268 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 269 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 270 sizeof(resp), 0); 271 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 272 if (rc) 273 return rc; 274 } 275 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 276 sizeof(bnxt_qplib_gid_zero)); 277 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 278 sgid_tbl->vlan[index] = 0; 279 sgid_tbl->active--; 280 dev_dbg(&res->pdev->dev, 281 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 282 index, sgid_tbl->hw_id[index], sgid_tbl->active); 283 sgid_tbl->hw_id[index] = (u16)-1; 284 285 /* unlock */ 286 return 0; 287 } 288 289 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 290 struct bnxt_qplib_gid *gid, const u8 *smac, 291 u16 vlan_id, bool update, u32 *index) 292 { 293 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 294 struct bnxt_qplib_res, 295 sgid_tbl); 296 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 297 int i, free_idx; 298 299 /* Do we need a sgid_lock here? */ 300 if (sgid_tbl->active == sgid_tbl->max) { 301 dev_err(&res->pdev->dev, "SGID table is full\n"); 302 return -ENOMEM; 303 } 304 free_idx = sgid_tbl->max; 305 for (i = 0; i < sgid_tbl->max; i++) { 306 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 307 sgid_tbl->tbl[i].vlan_id == vlan_id) { 308 dev_dbg(&res->pdev->dev, 309 "SGID entry already exist in entry %d!\n", i); 310 *index = i; 311 return -EALREADY; 312 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 313 sizeof(bnxt_qplib_gid_zero)) && 314 free_idx == sgid_tbl->max) { 315 free_idx = i; 316 } 317 } 318 if (free_idx == sgid_tbl->max) { 319 dev_err(&res->pdev->dev, 320 "SGID table is FULL but count is not MAX??\n"); 321 return -ENOMEM; 322 } 323 if (update) { 324 struct creq_add_gid_resp resp = {}; 325 struct bnxt_qplib_cmdqmsg msg = {}; 326 struct cmdq_add_gid req = {}; 327 int rc; 328 329 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 330 CMDQ_BASE_OPCODE_ADD_GID, 331 sizeof(req)); 332 333 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 334 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 335 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 336 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 337 /* 338 * driver should ensure that all RoCE traffic is always VLAN 339 * tagged if RoCE traffic is running on non-zero VLAN ID or 340 * RoCE traffic is running on non-zero Priority. 341 */ 342 if ((vlan_id != 0xFFFF) || res->prio) { 343 if (vlan_id != 0xFFFF) 344 req.vlan = cpu_to_le16 345 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 346 req.vlan |= cpu_to_le16 347 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 348 CMDQ_ADD_GID_VLAN_VLAN_EN); 349 } 350 351 /* MAC in network format */ 352 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 353 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 354 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 355 356 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 357 sizeof(resp), 0); 358 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 359 if (rc) 360 return rc; 361 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 362 } 363 /* Add GID to the sgid_tbl */ 364 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 365 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 366 sgid_tbl->active++; 367 if (vlan_id != 0xFFFF) 368 sgid_tbl->vlan[free_idx] = 1; 369 370 dev_dbg(&res->pdev->dev, 371 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 372 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 373 374 *index = free_idx; 375 /* unlock */ 376 return 0; 377 } 378 379 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 380 struct bnxt_qplib_gid *gid, u16 gid_idx, 381 const u8 *smac) 382 { 383 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 384 struct bnxt_qplib_res, 385 sgid_tbl); 386 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 387 struct creq_modify_gid_resp resp = {}; 388 struct bnxt_qplib_cmdqmsg msg = {}; 389 struct cmdq_modify_gid req = {}; 390 int rc; 391 392 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 393 CMDQ_BASE_OPCODE_MODIFY_GID, 394 sizeof(req)); 395 396 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 397 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 398 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 399 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 400 if (res->prio) { 401 req.vlan |= cpu_to_le16 402 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 403 CMDQ_ADD_GID_VLAN_VLAN_EN); 404 } 405 406 /* MAC in network format */ 407 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 408 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 409 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 410 411 req.gid_index = cpu_to_le16(gid_idx); 412 413 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 414 sizeof(resp), 0); 415 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 416 return rc; 417 } 418 419 /* AH */ 420 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 421 bool block) 422 { 423 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 424 struct creq_create_ah_resp resp = {}; 425 struct bnxt_qplib_cmdqmsg msg = {}; 426 struct cmdq_create_ah req = {}; 427 u32 temp32[4]; 428 u16 temp16[3]; 429 int rc; 430 431 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 432 CMDQ_BASE_OPCODE_CREATE_AH, 433 sizeof(req)); 434 435 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 436 req.dgid[0] = cpu_to_le32(temp32[0]); 437 req.dgid[1] = cpu_to_le32(temp32[1]); 438 req.dgid[2] = cpu_to_le32(temp32[2]); 439 req.dgid[3] = cpu_to_le32(temp32[3]); 440 441 req.type = ah->nw_type; 442 req.hop_limit = ah->hop_limit; 443 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 444 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 445 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 446 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 447 req.pd_id = cpu_to_le32(ah->pd->id); 448 req.traffic_class = ah->traffic_class; 449 450 /* MAC in network format */ 451 memcpy(temp16, ah->dmac, 6); 452 req.dest_mac[0] = cpu_to_le16(temp16[0]); 453 req.dest_mac[1] = cpu_to_le16(temp16[1]); 454 req.dest_mac[2] = cpu_to_le16(temp16[2]); 455 456 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 457 sizeof(resp), block); 458 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 459 if (rc) 460 return rc; 461 462 ah->id = le32_to_cpu(resp.xid); 463 return 0; 464 } 465 466 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 467 bool block) 468 { 469 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 470 struct creq_destroy_ah_resp resp = {}; 471 struct bnxt_qplib_cmdqmsg msg = {}; 472 struct cmdq_destroy_ah req = {}; 473 int rc; 474 475 /* Clean up the AH table in the device */ 476 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 477 CMDQ_BASE_OPCODE_DESTROY_AH, 478 sizeof(req)); 479 480 req.ah_cid = cpu_to_le32(ah->id); 481 482 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 483 sizeof(resp), block); 484 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 485 return rc; 486 } 487 488 /* MRW */ 489 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 490 { 491 struct creq_deallocate_key_resp resp = {}; 492 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 493 struct cmdq_deallocate_key req = {}; 494 struct bnxt_qplib_cmdqmsg msg = {}; 495 int rc; 496 497 if (mrw->lkey == 0xFFFFFFFF) { 498 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 499 return 0; 500 } 501 502 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 503 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 504 sizeof(req)); 505 506 req.mrw_flags = mrw->type; 507 508 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 509 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 510 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 511 req.key = cpu_to_le32(mrw->rkey); 512 else 513 req.key = cpu_to_le32(mrw->lkey); 514 515 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 516 sizeof(resp), 0); 517 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 518 if (rc) 519 return rc; 520 521 /* Free the qplib's MRW memory */ 522 if (mrw->hwq.max_elements) 523 bnxt_qplib_free_hwq(res, &mrw->hwq); 524 525 return 0; 526 } 527 528 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 529 { 530 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 531 struct creq_allocate_mrw_resp resp = {}; 532 struct bnxt_qplib_cmdqmsg msg = {}; 533 struct cmdq_allocate_mrw req = {}; 534 unsigned long tmp; 535 int rc; 536 537 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 538 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 539 sizeof(req)); 540 541 req.pd_id = cpu_to_le32(mrw->pd->id); 542 req.mrw_flags = mrw->type; 543 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 544 mrw->flags & BNXT_QPLIB_FR_PMR) || 545 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 546 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 547 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 548 tmp = (unsigned long)mrw; 549 req.mrw_handle = cpu_to_le64(tmp); 550 551 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 552 sizeof(resp), 0); 553 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 554 if (rc) 555 return rc; 556 557 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 558 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 559 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 560 mrw->rkey = le32_to_cpu(resp.xid); 561 else 562 mrw->lkey = le32_to_cpu(resp.xid); 563 return 0; 564 } 565 566 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 567 bool block) 568 { 569 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 570 struct creq_deregister_mr_resp resp = {}; 571 struct bnxt_qplib_cmdqmsg msg = {}; 572 struct cmdq_deregister_mr req = {}; 573 int rc; 574 575 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 576 CMDQ_BASE_OPCODE_DEREGISTER_MR, 577 sizeof(req)); 578 579 req.lkey = cpu_to_le32(mrw->lkey); 580 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 581 sizeof(resp), block); 582 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 583 if (rc) 584 return rc; 585 586 /* Free the qplib's MR memory */ 587 if (mrw->hwq.max_elements) { 588 mrw->va = 0; 589 mrw->total_size = 0; 590 bnxt_qplib_free_hwq(res, &mrw->hwq); 591 } 592 593 return 0; 594 } 595 596 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 597 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 598 { 599 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 600 struct bnxt_qplib_hwq_attr hwq_attr = {}; 601 struct bnxt_qplib_sg_info sginfo = {}; 602 struct creq_register_mr_resp resp = {}; 603 struct bnxt_qplib_cmdqmsg msg = {}; 604 struct cmdq_register_mr req = {}; 605 int pages, rc; 606 u32 pg_size; 607 u16 level; 608 609 if (num_pbls) { 610 pages = roundup_pow_of_two(num_pbls); 611 /* Allocate memory for the non-leaf pages to store buf ptrs. 612 * Non-leaf pages always uses system PAGE_SIZE 613 */ 614 /* Free the hwq if it already exist, must be a rereg */ 615 if (mr->hwq.max_elements) 616 bnxt_qplib_free_hwq(res, &mr->hwq); 617 hwq_attr.res = res; 618 hwq_attr.depth = pages; 619 hwq_attr.stride = sizeof(dma_addr_t); 620 hwq_attr.type = HWQ_TYPE_MR; 621 hwq_attr.sginfo = &sginfo; 622 hwq_attr.sginfo->umem = umem; 623 hwq_attr.sginfo->npages = pages; 624 hwq_attr.sginfo->pgsize = buf_pg_size; 625 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 626 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 627 if (rc) { 628 dev_err(&res->pdev->dev, 629 "SP: Reg MR memory allocation failed\n"); 630 return -ENOMEM; 631 } 632 } 633 634 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 635 CMDQ_BASE_OPCODE_REGISTER_MR, 636 sizeof(req)); 637 638 /* Configure the request */ 639 if (mr->hwq.level == PBL_LVL_MAX) { 640 /* No PBL provided, just use system PAGE_SIZE */ 641 level = 0; 642 req.pbl = 0; 643 pg_size = PAGE_SIZE; 644 } else { 645 level = mr->hwq.level; 646 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 647 } 648 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 649 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 650 ((ilog2(pg_size) << 651 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 652 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 653 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 654 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 655 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 656 req.access = (mr->flags & 0xFFFF); 657 req.va = cpu_to_le64(mr->va); 658 req.key = cpu_to_le32(mr->lkey); 659 req.mr_size = cpu_to_le64(mr->total_size); 660 661 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 662 sizeof(resp), 0); 663 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 664 if (rc) 665 goto fail; 666 667 return 0; 668 669 fail: 670 if (mr->hwq.max_elements) 671 bnxt_qplib_free_hwq(res, &mr->hwq); 672 return rc; 673 } 674 675 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 676 struct bnxt_qplib_frpl *frpl, 677 int max_pg_ptrs) 678 { 679 struct bnxt_qplib_hwq_attr hwq_attr = {}; 680 struct bnxt_qplib_sg_info sginfo = {}; 681 int pg_ptrs, pages, rc; 682 683 /* Re-calculate the max to fit the HWQ allocation model */ 684 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 685 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 686 if (!pages) 687 pages++; 688 689 if (pages > MAX_PBL_LVL_1_PGS) 690 return -ENOMEM; 691 692 sginfo.pgsize = PAGE_SIZE; 693 sginfo.nopte = true; 694 695 hwq_attr.res = res; 696 hwq_attr.depth = pg_ptrs; 697 hwq_attr.stride = PAGE_SIZE; 698 hwq_attr.sginfo = &sginfo; 699 hwq_attr.type = HWQ_TYPE_CTX; 700 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 701 if (!rc) 702 frpl->max_pg_ptrs = pg_ptrs; 703 704 return rc; 705 } 706 707 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 708 struct bnxt_qplib_frpl *frpl) 709 { 710 bnxt_qplib_free_hwq(res, &frpl->hwq); 711 return 0; 712 } 713 714 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 715 struct bnxt_qplib_roce_stats *stats) 716 { 717 struct creq_query_roce_stats_resp resp = {}; 718 struct creq_query_roce_stats_resp_sb *sb; 719 struct cmdq_query_roce_stats req = {}; 720 struct bnxt_qplib_cmdqmsg msg = {}; 721 struct bnxt_qplib_rcfw_sbuf sbuf; 722 int rc; 723 724 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 725 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 726 sizeof(req)); 727 728 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 729 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 730 &sbuf.dma_addr, GFP_KERNEL); 731 if (!sbuf.sb) 732 return -ENOMEM; 733 sb = sbuf.sb; 734 735 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 736 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 737 sizeof(resp), 0); 738 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 739 if (rc) 740 goto bail; 741 /* Extract the context from the side buffer */ 742 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 743 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 744 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 745 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 746 stats->missing_resp = le64_to_cpu(sb->missing_resp); 747 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 748 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 749 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 750 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 751 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 752 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 753 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 754 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 755 stats->dup_req = le64_to_cpu(sb->dup_req); 756 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 757 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 758 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 759 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 760 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 761 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 762 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 763 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 764 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 765 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 766 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 767 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 768 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 769 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 770 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 771 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 772 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 773 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 774 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 775 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 776 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 777 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 778 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 779 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 780 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 781 if (!rcfw->init_oos_stats) { 782 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 783 rcfw->init_oos_stats = 1; 784 } else { 785 stats->res_oos_drop_count += 786 (le64_to_cpu(sb->res_oos_drop_count) - 787 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 788 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 789 } 790 791 bail: 792 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 793 sbuf.sb, sbuf.dma_addr); 794 return rc; 795 } 796 797 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 798 struct bnxt_qplib_ext_stat *estat) 799 { 800 struct creq_query_roce_stats_ext_resp resp = {}; 801 struct creq_query_roce_stats_ext_resp_sb *sb; 802 struct cmdq_query_roce_stats_ext req = {}; 803 struct bnxt_qplib_cmdqmsg msg = {}; 804 struct bnxt_qplib_rcfw_sbuf sbuf; 805 int rc; 806 807 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 808 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 809 &sbuf.dma_addr, GFP_KERNEL); 810 if (!sbuf.sb) 811 return -ENOMEM; 812 813 sb = sbuf.sb; 814 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 815 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 816 sizeof(req)); 817 818 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 819 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 820 req.function_id = cpu_to_le32(fid); 821 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 822 823 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 824 sizeof(resp), 0); 825 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 826 if (rc) 827 goto bail; 828 829 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 830 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 831 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 832 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 833 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 834 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 835 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 836 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 837 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 838 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 839 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 840 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 841 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 842 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 843 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 844 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 845 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 846 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 847 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 848 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 849 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 850 851 bail: 852 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 853 sbuf.sb, sbuf.dma_addr); 854 return rc; 855 } 856 857 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 858 struct bnxt_qplib_cc_param_ext *cc_ext) 859 { 860 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 861 cc_ext->ext_mask = 0; 862 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 863 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 864 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 865 ext_req->tr_update_mode = cc_ext->tr_update_mode; 866 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 867 ext_req->fr_num_rtts = cc_ext->fr_rtt; 868 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 869 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 870 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 871 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 872 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 873 ext_req->actual_cr_factor = cc_ext->cr_factor; 874 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 875 ext_req->cp_bias_en = cc_ext->cp_bias_en; 876 ext_req->cp_bias = cc_ext->cp_bias; 877 ext_req->cnp_ecn = cc_ext->cnp_ecn; 878 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 879 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 880 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 881 ext_req->cr_width = cc_ext->cr_width; 882 ext_req->quota_period_min = cc_ext->min_quota; 883 ext_req->quota_period_max = cc_ext->max_quota; 884 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 885 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 886 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 887 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 888 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 889 ext_req->red_div = cc_ext->red_div; 890 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 891 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 892 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 893 ext_req->use_rate_table = cc_ext->low_rate_en; 894 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 895 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 896 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 897 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 898 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 899 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 900 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 901 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 902 } 903 904 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 905 struct bnxt_qplib_cc_param *cc_param) 906 { 907 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 908 struct creq_modify_roce_cc_resp resp = {}; 909 struct bnxt_qplib_cmdqmsg msg = {}; 910 struct cmdq_modify_roce_cc *req; 911 int req_size; 912 void *cmd; 913 int rc; 914 915 /* Prepare the older base command */ 916 req = &tlv_req.base_req; 917 cmd = req; 918 req_size = sizeof(*req); 919 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 920 sizeof(*req)); 921 req->modify_mask = cpu_to_le32(cc_param->mask); 922 req->enable_cc = cc_param->enable; 923 req->g = cc_param->g; 924 req->num_phases_per_state = cc_param->nph_per_state; 925 req->time_per_phase = cc_param->time_pph; 926 req->pkts_per_phase = cc_param->pkts_pph; 927 req->init_cr = cpu_to_le16(cc_param->init_cr); 928 req->init_tr = cpu_to_le16(cc_param->init_tr); 929 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 930 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 931 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 932 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 933 req->rtt = cpu_to_le16(cc_param->rtt); 934 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 935 req->cc_mode = cc_param->cc_mode; 936 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 937 938 /* For chip gen P5 onwards fill extended cmd and header */ 939 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 940 struct roce_tlv *hdr; 941 u32 payload; 942 u32 chunks; 943 944 cmd = &tlv_req; 945 req_size = sizeof(tlv_req); 946 /* Prepare primary tlv header */ 947 hdr = &tlv_req.tlv_hdr; 948 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 949 payload = sizeof(struct cmdq_modify_roce_cc); 950 __roce_1st_tlv_prep(hdr, chunks, payload, true); 951 /* Prepare secondary tlv header */ 952 hdr = (struct roce_tlv *)&tlv_req.ext_req; 953 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 954 sizeof(struct roce_tlv); 955 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 956 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 957 } 958 959 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 960 sizeof(resp), 0); 961 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 962 return rc; 963 } 964