1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: QPLib resource manager (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RES_H__ 40 #define __BNXT_QPLIB_RES_H__ 41 42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; 43 44 #define CHIP_NUM_57508 0x1750 45 #define CHIP_NUM_57504 0x1751 46 #define CHIP_NUM_57502 0x1752 47 48 struct bnxt_qplib_drv_modes { 49 u8 wqe_mode; 50 bool db_push; 51 }; 52 53 struct bnxt_qplib_chip_ctx { 54 u16 chip_num; 55 u8 chip_rev; 56 u8 chip_metal; 57 u16 hw_stats_size; 58 u16 hwrm_cmd_max_timeout; 59 struct bnxt_qplib_drv_modes modes; 60 u64 hwrm_intf_ver; 61 }; 62 63 #define BNXT_QPLIB_DBR_PF_DB_OFFSET 0x10000 64 #define BNXT_QPLIB_DBR_VF_DB_OFFSET 0x4000 65 66 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 67 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 68 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) 69 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG) 70 71 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1)) 72 73 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \ 74 ((HWQ_CMP(hwq->prod, hwq)\ 75 - HWQ_CMP(hwq->cons, hwq))\ 76 & (hwq->max_elements - 1))) 77 enum bnxt_qplib_hwq_type { 78 HWQ_TYPE_CTX, 79 HWQ_TYPE_QUEUE, 80 HWQ_TYPE_L2_CMPL, 81 HWQ_TYPE_MR 82 }; 83 84 #define MAX_PBL_LVL_0_PGS 1 85 #define MAX_PBL_LVL_1_PGS 512 86 #define MAX_PBL_LVL_1_PGS_SHIFT 9 87 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256 88 #define MAX_PBL_LVL_2_PGS (256 * 512) 89 #define MAX_PDL_LVL_SHIFT 9 90 91 enum bnxt_qplib_pbl_lvl { 92 PBL_LVL_0, 93 PBL_LVL_1, 94 PBL_LVL_2, 95 PBL_LVL_MAX 96 }; 97 98 #define ROCE_PG_SIZE_4K (4 * 1024) 99 #define ROCE_PG_SIZE_8K (8 * 1024) 100 #define ROCE_PG_SIZE_64K (64 * 1024) 101 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024) 102 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024) 103 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024) 104 105 enum bnxt_qplib_hwrm_pg_size { 106 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0, 107 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1, 108 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2, 109 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3, 110 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4, 111 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5, 112 }; 113 114 struct bnxt_qplib_reg_desc { 115 u8 bar_id; 116 resource_size_t bar_base; 117 unsigned long offset; 118 void __iomem *bar_reg; 119 size_t len; 120 }; 121 122 struct bnxt_qplib_pbl { 123 u32 pg_count; 124 u32 pg_size; 125 void **pg_arr; 126 dma_addr_t *pg_map_arr; 127 }; 128 129 struct bnxt_qplib_sg_info { 130 struct ib_umem *umem; 131 u32 npages; 132 u32 pgshft; 133 u32 pgsize; 134 bool nopte; 135 }; 136 137 struct bnxt_qplib_hwq_attr { 138 struct bnxt_qplib_res *res; 139 struct bnxt_qplib_sg_info *sginfo; 140 enum bnxt_qplib_hwq_type type; 141 u32 depth; 142 u32 stride; 143 u32 aux_stride; 144 u32 aux_depth; 145 }; 146 147 struct bnxt_qplib_hwq { 148 struct pci_dev *pdev; 149 /* lock to protect qplib_hwq */ 150 spinlock_t lock; 151 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1]; 152 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */ 153 /* ptr for easy access to the PBL entries */ 154 void **pbl_ptr; 155 /* ptr for easy access to the dma_addr */ 156 dma_addr_t *pbl_dma_ptr; 157 u32 max_elements; 158 u32 depth; 159 u16 element_size; /* Size of each entry */ 160 u16 qe_ppg; /* queue entry per page */ 161 162 u32 prod; /* raw */ 163 u32 cons; /* raw */ 164 u8 cp_bit; 165 u8 is_user; 166 u64 *pad_pg; 167 u32 pad_stride; 168 u32 pad_pgofft; 169 }; 170 171 struct bnxt_qplib_db_info { 172 void __iomem *db; 173 void __iomem *priv_db; 174 struct bnxt_qplib_hwq *hwq; 175 u32 xid; 176 u32 max_slot; 177 }; 178 179 /* Tables */ 180 struct bnxt_qplib_pd_tbl { 181 unsigned long *tbl; 182 u32 max; 183 }; 184 185 struct bnxt_qplib_sgid_tbl { 186 struct bnxt_qplib_gid_info *tbl; 187 u16 *hw_id; 188 u16 max; 189 u16 active; 190 void *ctx; 191 u8 *vlan; 192 }; 193 194 enum { 195 BNXT_QPLIB_DPI_TYPE_KERNEL = 0, 196 BNXT_QPLIB_DPI_TYPE_UC = 1, 197 BNXT_QPLIB_DPI_TYPE_WC = 2 198 }; 199 200 struct bnxt_qplib_dpi { 201 u32 dpi; 202 u32 bit; 203 void __iomem *dbr; 204 u64 umdbr; 205 u8 type; 206 }; 207 208 struct bnxt_qplib_dpi_tbl { 209 void **app_tbl; 210 unsigned long *tbl; 211 u16 max; 212 struct bnxt_qplib_reg_desc ucreg; /* Hold entire DB bar. */ 213 struct bnxt_qplib_reg_desc wcreg; 214 void __iomem *priv_db; 215 }; 216 217 struct bnxt_qplib_stats { 218 dma_addr_t dma_map; 219 void *dma; 220 u32 size; 221 u32 fw_id; 222 }; 223 224 struct bnxt_qplib_vf_res { 225 u32 max_qp_per_vf; 226 u32 max_mrw_per_vf; 227 u32 max_srq_per_vf; 228 u32 max_cq_per_vf; 229 u32 max_gid_per_vf; 230 }; 231 232 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448 233 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64 234 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64 235 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128 236 237 #define MAX_TQM_ALLOC_REQ 48 238 #define MAX_TQM_ALLOC_BLK_SIZE 8 239 struct bnxt_qplib_tqm_ctx { 240 struct bnxt_qplib_hwq pde; 241 u8 pde_level; /* Original level */ 242 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ]; 243 u8 qcount[MAX_TQM_ALLOC_REQ]; 244 }; 245 246 struct bnxt_qplib_ctx { 247 u32 qpc_count; 248 struct bnxt_qplib_hwq qpc_tbl; 249 u32 mrw_count; 250 struct bnxt_qplib_hwq mrw_tbl; 251 u32 srqc_count; 252 struct bnxt_qplib_hwq srqc_tbl; 253 u32 cq_count; 254 struct bnxt_qplib_hwq cq_tbl; 255 struct bnxt_qplib_hwq tim_tbl; 256 struct bnxt_qplib_tqm_ctx tqm_ctx; 257 struct bnxt_qplib_stats stats; 258 struct bnxt_qplib_vf_res vf_res; 259 }; 260 261 struct bnxt_qplib_res { 262 struct pci_dev *pdev; 263 struct bnxt_qplib_chip_ctx *cctx; 264 struct bnxt_qplib_dev_attr *dattr; 265 struct net_device *netdev; 266 struct bnxt_qplib_rcfw *rcfw; 267 struct bnxt_qplib_pd_tbl pd_tbl; 268 struct bnxt_qplib_sgid_tbl sgid_tbl; 269 struct bnxt_qplib_dpi_tbl dpi_tbl; 270 /* To protect the dpi table bit map */ 271 struct mutex dpi_tbl_lock; 272 bool prio; 273 bool is_vf; 274 }; 275 276 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx) 277 { 278 return (cctx->chip_num == CHIP_NUM_57508 || 279 cctx->chip_num == CHIP_NUM_57504 || 280 cctx->chip_num == CHIP_NUM_57502); 281 } 282 283 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res) 284 { 285 return bnxt_qplib_is_chip_gen_p5(res->cctx) ? 286 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL; 287 } 288 289 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx) 290 { 291 return bnxt_qplib_is_chip_gen_p5(cctx) ? 292 RING_ALLOC_REQ_RING_TYPE_NQ : 293 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL; 294 } 295 296 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq) 297 { 298 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 299 struct bnxt_qplib_pbl *pbl; 300 301 pbl = &hwq->pbl[PBL_LVL_0]; 302 switch (pbl->pg_size) { 303 case ROCE_PG_SIZE_4K: 304 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 305 break; 306 case ROCE_PG_SIZE_8K: 307 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K; 308 break; 309 case ROCE_PG_SIZE_64K: 310 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K; 311 break; 312 case ROCE_PG_SIZE_2M: 313 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M; 314 break; 315 case ROCE_PG_SIZE_8M: 316 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M; 317 break; 318 case ROCE_PG_SIZE_1G: 319 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G; 320 break; 321 default: 322 break; 323 } 324 325 return pg_size; 326 } 327 328 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq, 329 u32 indx, u64 *pg) 330 { 331 u32 pg_num, pg_idx; 332 333 pg_num = (indx / hwq->qe_ppg); 334 pg_idx = (indx % hwq->qe_ppg); 335 if (pg) 336 *pg = (u64)&hwq->pbl_ptr[pg_num]; 337 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx); 338 } 339 340 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx) 341 { 342 idx += hwq->prod; 343 if (idx >= hwq->depth) 344 idx -= hwq->depth; 345 return bnxt_qplib_get_qe(hwq, idx, NULL); 346 } 347 348 #define to_bnxt_qplib(ptr, type, member) \ 349 container_of(ptr, type, member) 350 351 struct bnxt_qplib_pd; 352 struct bnxt_qplib_dev_attr; 353 354 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, 355 struct bnxt_qplib_hwq *hwq); 356 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, 357 struct bnxt_qplib_hwq_attr *hwq_attr); 358 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl, 359 struct bnxt_qplib_pd *pd); 360 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, 361 struct bnxt_qplib_pd_tbl *pd_tbl, 362 struct bnxt_qplib_pd *pd); 363 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res, 364 struct bnxt_qplib_dpi *dpi, 365 void *app, u8 type); 366 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, 367 struct bnxt_qplib_dpi *dpi); 368 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); 369 int bnxt_qplib_init_res(struct bnxt_qplib_res *res); 370 void bnxt_qplib_free_res(struct bnxt_qplib_res *res); 371 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 372 struct net_device *netdev, 373 struct bnxt_qplib_dev_attr *dev_attr); 374 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 375 struct bnxt_qplib_ctx *ctx); 376 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, 377 struct bnxt_qplib_ctx *ctx, 378 bool virt_fn, bool is_p5); 379 int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res); 380 void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res); 381 382 int bnxt_qplib_determine_atomics(struct pci_dev *dev); 383 384 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt) 385 { 386 hwq->prod = (hwq->prod + cnt) % hwq->depth; 387 } 388 389 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq, 390 u32 cnt) 391 { 392 hwq->cons = (hwq->cons + cnt) % hwq->depth; 393 } 394 395 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info, 396 bool arm) 397 { 398 u32 key; 399 400 key = info->hwq->cons & (info->hwq->max_elements - 1); 401 key |= (CMPL_DOORBELL_IDX_VALID | 402 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK)); 403 if (!arm) 404 key |= CMPL_DOORBELL_MASK; 405 writel(key, info->db); 406 } 407 408 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info, 409 u32 type) 410 { 411 u64 key = 0; 412 413 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 414 key <<= 32; 415 key |= (info->hwq->cons & (info->hwq->max_elements - 1)) & 416 DBC_DBC_INDEX_MASK; 417 writeq(key, info->db); 418 } 419 420 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info, 421 u32 type) 422 { 423 u64 key = 0; 424 425 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 426 key <<= 32; 427 key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK; 428 writeq(key, info->db); 429 } 430 431 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info, 432 u32 type) 433 { 434 u64 key = 0; 435 436 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 437 key <<= 32; 438 writeq(key, info->priv_db); 439 } 440 441 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info, 442 u32 th) 443 { 444 u64 key = 0; 445 446 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th; 447 key <<= 32; 448 key |= th & DBC_DBC_INDEX_MASK; 449 writeq(key, info->priv_db); 450 } 451 452 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info, 453 struct bnxt_qplib_chip_ctx *cctx, 454 bool arm) 455 { 456 u32 type; 457 458 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; 459 if (bnxt_qplib_is_chip_gen_p5(cctx)) 460 bnxt_qplib_ring_db(info, type); 461 else 462 bnxt_qplib_ring_db32(info, arm); 463 } 464 465 static inline bool _is_ext_stats_supported(u16 dev_cap_flags) 466 { 467 return dev_cap_flags & 468 CREQ_QUERY_FUNC_RESP_SB_EXT_STATS; 469 } 470 #endif /* __BNXT_QPLIB_RES_H__ */ 471