1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: QPLib resource manager (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RES_H__ 40 #define __BNXT_QPLIB_RES_H__ 41 42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; 43 44 #define CHIP_NUM_57508 0x1750 45 #define CHIP_NUM_57504 0x1751 46 #define CHIP_NUM_57502 0x1752 47 #define CHIP_NUM_58818 0xd818 48 #define CHIP_NUM_57608 0x1760 49 50 #define BNXT_QPLIB_DBR_VALID (0x1UL << 26) 51 #define BNXT_QPLIB_DBR_EPOCH_SHIFT 24 52 #define BNXT_QPLIB_DBR_TOGGLE_SHIFT 25 53 54 struct bnxt_qplib_drv_modes { 55 u8 wqe_mode; 56 bool db_push; 57 bool dbr_pacing; 58 u32 toggle_bits; 59 }; 60 61 enum bnxt_re_toggle_modes { 62 BNXT_QPLIB_CQ_TOGGLE_BIT = 0x1, 63 BNXT_QPLIB_SRQ_TOGGLE_BIT = 0x2, 64 }; 65 66 struct bnxt_qplib_chip_ctx { 67 u16 chip_num; 68 u8 chip_rev; 69 u8 chip_metal; 70 u16 hw_stats_size; 71 u16 hwrm_cmd_max_timeout; 72 struct bnxt_qplib_drv_modes modes; 73 u64 hwrm_intf_ver; 74 u32 dbr_stat_db_fifo; 75 }; 76 77 struct bnxt_qplib_db_pacing_data { 78 u32 do_pacing; 79 u32 pacing_th; 80 u32 alarm_th; 81 u32 fifo_max_depth; 82 u32 fifo_room_mask; 83 u32 fifo_room_shift; 84 u32 grc_reg_offset; 85 u32 dev_err_state; 86 }; 87 88 #define BNXT_QPLIB_DBR_PF_DB_OFFSET 0x10000 89 #define BNXT_QPLIB_DBR_VF_DB_OFFSET 0x4000 90 91 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 92 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 93 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) 94 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG) 95 96 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1)) 97 98 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \ 99 ((HWQ_CMP(hwq->prod, hwq)\ 100 - HWQ_CMP(hwq->cons, hwq))\ 101 & (hwq->max_elements - 1))) 102 enum bnxt_qplib_hwq_type { 103 HWQ_TYPE_CTX, 104 HWQ_TYPE_QUEUE, 105 HWQ_TYPE_L2_CMPL, 106 HWQ_TYPE_MR 107 }; 108 109 #define MAX_PBL_LVL_0_PGS 1 110 #define MAX_PBL_LVL_1_PGS 512 111 #define MAX_PBL_LVL_1_PGS_SHIFT 9 112 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256 113 #define MAX_PBL_LVL_2_PGS (256 * 512) 114 #define MAX_PDL_LVL_SHIFT 9 115 116 enum bnxt_qplib_pbl_lvl { 117 PBL_LVL_0, 118 PBL_LVL_1, 119 PBL_LVL_2, 120 PBL_LVL_MAX 121 }; 122 123 #define ROCE_PG_SIZE_4K (4 * 1024) 124 #define ROCE_PG_SIZE_8K (8 * 1024) 125 #define ROCE_PG_SIZE_64K (64 * 1024) 126 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024) 127 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024) 128 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024) 129 130 enum bnxt_qplib_hwrm_pg_size { 131 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0, 132 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1, 133 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2, 134 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3, 135 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4, 136 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5, 137 }; 138 139 struct bnxt_qplib_reg_desc { 140 u8 bar_id; 141 resource_size_t bar_base; 142 unsigned long offset; 143 void __iomem *bar_reg; 144 size_t len; 145 }; 146 147 struct bnxt_qplib_pbl { 148 u32 pg_count; 149 u32 pg_size; 150 void **pg_arr; 151 dma_addr_t *pg_map_arr; 152 }; 153 154 struct bnxt_qplib_sg_info { 155 struct ib_umem *umem; 156 u32 npages; 157 u32 pgshft; 158 u32 pgsize; 159 bool nopte; 160 }; 161 162 struct bnxt_qplib_hwq_attr { 163 struct bnxt_qplib_res *res; 164 struct bnxt_qplib_sg_info *sginfo; 165 enum bnxt_qplib_hwq_type type; 166 u32 depth; 167 u32 stride; 168 u32 aux_stride; 169 u32 aux_depth; 170 }; 171 172 struct bnxt_qplib_hwq { 173 struct pci_dev *pdev; 174 /* lock to protect qplib_hwq */ 175 spinlock_t lock; 176 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1]; 177 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */ 178 /* ptr for easy access to the PBL entries */ 179 void **pbl_ptr; 180 /* ptr for easy access to the dma_addr */ 181 dma_addr_t *pbl_dma_ptr; 182 u32 max_elements; 183 u32 depth; 184 u16 element_size; /* Size of each entry */ 185 u16 qe_ppg; /* queue entry per page */ 186 187 u32 prod; /* raw */ 188 u32 cons; /* raw */ 189 u8 cp_bit; 190 u8 is_user; 191 u64 *pad_pg; 192 u32 pad_stride; 193 u32 pad_pgofft; 194 }; 195 196 struct bnxt_qplib_db_info { 197 void __iomem *db; 198 void __iomem *priv_db; 199 struct bnxt_qplib_hwq *hwq; 200 u32 xid; 201 u32 max_slot; 202 u32 flags; 203 u8 toggle; 204 }; 205 206 enum bnxt_qplib_db_info_flags_mask { 207 BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT = 0x0UL, 208 BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT = 0x1UL, 209 BNXT_QPLIB_FLAG_EPOCH_CONS_MASK = 0x1UL, 210 BNXT_QPLIB_FLAG_EPOCH_PROD_MASK = 0x2UL, 211 }; 212 213 enum bnxt_qplib_db_epoch_flag_shift { 214 BNXT_QPLIB_DB_EPOCH_CONS_SHIFT = BNXT_QPLIB_DBR_EPOCH_SHIFT, 215 BNXT_QPLIB_DB_EPOCH_PROD_SHIFT = (BNXT_QPLIB_DBR_EPOCH_SHIFT - 1), 216 }; 217 218 /* Tables */ 219 struct bnxt_qplib_pd_tbl { 220 unsigned long *tbl; 221 u32 max; 222 }; 223 224 struct bnxt_qplib_sgid_tbl { 225 struct bnxt_qplib_gid_info *tbl; 226 u16 *hw_id; 227 u16 max; 228 u16 active; 229 void *ctx; 230 u8 *vlan; 231 }; 232 233 enum { 234 BNXT_QPLIB_DPI_TYPE_KERNEL = 0, 235 BNXT_QPLIB_DPI_TYPE_UC = 1, 236 BNXT_QPLIB_DPI_TYPE_WC = 2 237 }; 238 239 struct bnxt_qplib_dpi { 240 u32 dpi; 241 u32 bit; 242 void __iomem *dbr; 243 u64 umdbr; 244 u8 type; 245 }; 246 247 struct bnxt_qplib_dpi_tbl { 248 void **app_tbl; 249 unsigned long *tbl; 250 u16 max; 251 struct bnxt_qplib_reg_desc ucreg; /* Hold entire DB bar. */ 252 struct bnxt_qplib_reg_desc wcreg; 253 void __iomem *priv_db; 254 }; 255 256 struct bnxt_qplib_stats { 257 dma_addr_t dma_map; 258 void *dma; 259 u32 size; 260 u32 fw_id; 261 }; 262 263 struct bnxt_qplib_vf_res { 264 u32 max_qp_per_vf; 265 u32 max_mrw_per_vf; 266 u32 max_srq_per_vf; 267 u32 max_cq_per_vf; 268 u32 max_gid_per_vf; 269 }; 270 271 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448 272 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64 273 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64 274 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128 275 276 #define MAX_TQM_ALLOC_REQ 48 277 #define MAX_TQM_ALLOC_BLK_SIZE 8 278 struct bnxt_qplib_tqm_ctx { 279 struct bnxt_qplib_hwq pde; 280 u8 pde_level; /* Original level */ 281 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ]; 282 u8 qcount[MAX_TQM_ALLOC_REQ]; 283 }; 284 285 struct bnxt_qplib_ctx { 286 u32 qpc_count; 287 struct bnxt_qplib_hwq qpc_tbl; 288 u32 mrw_count; 289 struct bnxt_qplib_hwq mrw_tbl; 290 u32 srqc_count; 291 struct bnxt_qplib_hwq srqc_tbl; 292 u32 cq_count; 293 struct bnxt_qplib_hwq cq_tbl; 294 struct bnxt_qplib_hwq tim_tbl; 295 struct bnxt_qplib_tqm_ctx tqm_ctx; 296 struct bnxt_qplib_stats stats; 297 struct bnxt_qplib_vf_res vf_res; 298 }; 299 300 struct bnxt_qplib_res { 301 struct pci_dev *pdev; 302 struct bnxt_qplib_chip_ctx *cctx; 303 struct bnxt_qplib_dev_attr *dattr; 304 struct net_device *netdev; 305 struct bnxt_qplib_rcfw *rcfw; 306 struct bnxt_qplib_pd_tbl pd_tbl; 307 /* To protect the pd table bit map */ 308 struct mutex pd_tbl_lock; 309 struct bnxt_qplib_sgid_tbl sgid_tbl; 310 struct bnxt_qplib_dpi_tbl dpi_tbl; 311 /* To protect the dpi table bit map */ 312 struct mutex dpi_tbl_lock; 313 bool prio; 314 bool is_vf; 315 struct bnxt_qplib_db_pacing_data *pacing_data; 316 }; 317 318 static inline bool bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx *cctx) 319 { 320 return (cctx->chip_num == CHIP_NUM_58818 || 321 cctx->chip_num == CHIP_NUM_57608); 322 } 323 324 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx) 325 { 326 return (cctx->chip_num == CHIP_NUM_57508 || 327 cctx->chip_num == CHIP_NUM_57504 || 328 cctx->chip_num == CHIP_NUM_57502); 329 } 330 331 static inline bool bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx *cctx) 332 { 333 return bnxt_qplib_is_chip_gen_p5(cctx) || bnxt_qplib_is_chip_gen_p7(cctx); 334 } 335 336 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res) 337 { 338 return bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? 339 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL; 340 } 341 342 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx) 343 { 344 return bnxt_qplib_is_chip_gen_p5_p7(cctx) ? 345 RING_ALLOC_REQ_RING_TYPE_NQ : 346 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL; 347 } 348 349 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq) 350 { 351 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 352 struct bnxt_qplib_pbl *pbl; 353 354 pbl = &hwq->pbl[PBL_LVL_0]; 355 switch (pbl->pg_size) { 356 case ROCE_PG_SIZE_4K: 357 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 358 break; 359 case ROCE_PG_SIZE_8K: 360 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K; 361 break; 362 case ROCE_PG_SIZE_64K: 363 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K; 364 break; 365 case ROCE_PG_SIZE_2M: 366 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M; 367 break; 368 case ROCE_PG_SIZE_8M: 369 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M; 370 break; 371 case ROCE_PG_SIZE_1G: 372 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G; 373 break; 374 default: 375 break; 376 } 377 378 return pg_size; 379 } 380 381 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq, 382 u32 indx, u64 *pg) 383 { 384 u32 pg_num, pg_idx; 385 386 pg_num = (indx / hwq->qe_ppg); 387 pg_idx = (indx % hwq->qe_ppg); 388 if (pg) 389 *pg = (u64)&hwq->pbl_ptr[pg_num]; 390 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx); 391 } 392 393 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx) 394 { 395 idx += hwq->prod; 396 if (idx >= hwq->depth) 397 idx -= hwq->depth; 398 return bnxt_qplib_get_qe(hwq, idx, NULL); 399 } 400 401 #define to_bnxt_qplib(ptr, type, member) \ 402 container_of(ptr, type, member) 403 404 struct bnxt_qplib_pd; 405 struct bnxt_qplib_dev_attr; 406 407 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, 408 struct bnxt_qplib_hwq *hwq); 409 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, 410 struct bnxt_qplib_hwq_attr *hwq_attr); 411 int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res, 412 struct bnxt_qplib_pd *pd); 413 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, 414 struct bnxt_qplib_pd_tbl *pd_tbl, 415 struct bnxt_qplib_pd *pd); 416 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res, 417 struct bnxt_qplib_dpi *dpi, 418 void *app, u8 type); 419 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, 420 struct bnxt_qplib_dpi *dpi); 421 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); 422 int bnxt_qplib_init_res(struct bnxt_qplib_res *res); 423 void bnxt_qplib_free_res(struct bnxt_qplib_res *res); 424 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 425 struct net_device *netdev, 426 struct bnxt_qplib_dev_attr *dev_attr); 427 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 428 struct bnxt_qplib_ctx *ctx); 429 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, 430 struct bnxt_qplib_ctx *ctx, 431 bool virt_fn, bool is_p5); 432 int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res); 433 void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res); 434 435 int bnxt_qplib_determine_atomics(struct pci_dev *dev); 436 437 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info *dbinfo, 438 struct bnxt_qplib_hwq *hwq, u32 cnt) 439 { 440 /* move prod and update toggle/epoch if wrap around */ 441 hwq->prod += cnt; 442 if (hwq->prod >= hwq->depth) { 443 hwq->prod %= hwq->depth; 444 dbinfo->flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT; 445 } 446 } 447 448 static inline void bnxt_qplib_hwq_incr_cons(u32 max_elements, u32 *cons, u32 cnt, 449 u32 *dbinfo_flags) 450 { 451 /* move cons and update toggle/epoch if wrap around */ 452 *cons += cnt; 453 if (*cons >= max_elements) { 454 *cons %= max_elements; 455 *dbinfo_flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT; 456 } 457 } 458 459 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info, 460 bool arm) 461 { 462 u32 key = 0; 463 464 key |= info->hwq->cons | (CMPL_DOORBELL_IDX_VALID | 465 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK)); 466 if (!arm) 467 key |= CMPL_DOORBELL_MASK; 468 writel(key, info->db); 469 } 470 471 #define BNXT_QPLIB_INIT_DBHDR(xid, type, indx, toggle) \ 472 (((u64)(((xid) & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | \ 473 (type) | BNXT_QPLIB_DBR_VALID) << 32) | (indx) | \ 474 (((u32)(toggle)) << (BNXT_QPLIB_DBR_TOGGLE_SHIFT))) 475 476 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info, 477 u32 type) 478 { 479 u64 key = 0; 480 u32 indx; 481 u8 toggle = 0; 482 483 if (type == DBC_DBC_TYPE_CQ_ARMALL || 484 type == DBC_DBC_TYPE_CQ_ARMSE) 485 toggle = info->toggle; 486 487 indx = (info->hwq->cons & DBC_DBC_INDEX_MASK) | 488 ((info->flags & BNXT_QPLIB_FLAG_EPOCH_CONS_MASK) << 489 BNXT_QPLIB_DB_EPOCH_CONS_SHIFT); 490 491 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, indx, toggle); 492 writeq(key, info->db); 493 } 494 495 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info, 496 u32 type) 497 { 498 u64 key = 0; 499 u32 indx; 500 501 indx = (((info->hwq->prod / info->max_slot) & DBC_DBC_INDEX_MASK) | 502 ((info->flags & BNXT_QPLIB_FLAG_EPOCH_PROD_MASK) << 503 BNXT_QPLIB_DB_EPOCH_PROD_SHIFT)); 504 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, indx, 0); 505 writeq(key, info->db); 506 } 507 508 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info, 509 u32 type) 510 { 511 u64 key = 0; 512 u8 toggle = 0; 513 514 if (type == DBC_DBC_TYPE_CQ_ARMENA || type == DBC_DBC_TYPE_SRQ_ARMENA) 515 toggle = info->toggle; 516 /* Index always at 0 */ 517 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, 0, toggle); 518 writeq(key, info->priv_db); 519 } 520 521 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info, 522 u32 th) 523 { 524 u64 key = 0; 525 526 key = BNXT_QPLIB_INIT_DBHDR(info->xid, DBC_DBC_TYPE_SRQ_ARM, th, info->toggle); 527 writeq(key, info->priv_db); 528 } 529 530 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info, 531 struct bnxt_qplib_chip_ctx *cctx, 532 bool arm) 533 { 534 u32 type; 535 536 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; 537 if (bnxt_qplib_is_chip_gen_p5_p7(cctx)) 538 bnxt_qplib_ring_db(info, type); 539 else 540 bnxt_qplib_ring_db32(info, arm); 541 } 542 543 static inline bool _is_ext_stats_supported(u16 dev_cap_flags) 544 { 545 return dev_cap_flags & 546 CREQ_QUERY_FUNC_RESP_SB_EXT_STATS; 547 } 548 549 static inline bool _is_hw_retx_supported(u16 dev_cap_flags) 550 { 551 return dev_cap_flags & 552 (CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED | 553 CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED); 554 } 555 556 #define BNXT_RE_HW_RETX(a) _is_hw_retx_supported((a)) 557 558 static inline bool _is_host_msn_table(u16 dev_cap_ext_flags2) 559 { 560 return (dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK) == 561 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE; 562 } 563 564 static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx) 565 { 566 return cctx->modes.dbr_pacing; 567 } 568 569 static inline bool _is_alloc_mr_unified(u16 dev_cap_flags) 570 { 571 return dev_cap_flags & CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC; 572 } 573 574 static inline bool _is_relaxed_ordering_supported(u16 dev_cap_ext_flags2) 575 { 576 return dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED; 577 } 578 579 #endif /* __BNXT_QPLIB_RES_H__ */ 580