xref: /linux/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h (revision dd5b2498d845f925904cb2afabb6ba11bfc317c5)
1 /*
2  * Broadcom NetXtreme-E RoCE driver.
3  *
4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * BSD license below:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  *
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  * Description: RDMA Controller HW interface (header)
37  */
38 
39 #ifndef __BNXT_QPLIB_RCFW_H__
40 #define __BNXT_QPLIB_RCFW_H__
41 
42 #define RCFW_CMDQ_TRIG_VAL		1
43 #define RCFW_COMM_PCI_BAR_REGION	0
44 #define RCFW_COMM_CONS_PCI_BAR_REGION	2
45 #define RCFW_COMM_BASE_OFFSET		0x600
46 #define RCFW_PF_COMM_PROD_OFFSET	0xc
47 #define RCFW_VF_COMM_PROD_OFFSET	0xc
48 #define RCFW_COMM_TRIG_OFFSET		0x100
49 #define RCFW_COMM_SIZE			0x104
50 
51 #define RCFW_DBR_PCI_BAR_REGION		2
52 #define RCFW_DBR_BASE_PAGE_SHIFT	12
53 
54 #define RCFW_CMD_PREP(req, CMD, cmd_flags)				\
55 	do {								\
56 		memset(&(req), 0, sizeof((req)));			\
57 		(req).opcode = CMDQ_BASE_OPCODE_##CMD;			\
58 		(req).cmd_size = (sizeof((req)) +			\
59 				BNXT_QPLIB_CMDQE_UNITS - 1) /		\
60 				BNXT_QPLIB_CMDQE_UNITS;			\
61 		(req).flags = cpu_to_le16(cmd_flags);			\
62 	} while (0)
63 
64 #define RCFW_CMD_WAIT_TIME_MS		20000 /* 20 Seconds timeout */
65 
66 /* Cmdq contains a fix number of a 16-Byte slots */
67 struct bnxt_qplib_cmdqe {
68 	u8		data[16];
69 };
70 
71 /* CMDQ elements */
72 #define BNXT_QPLIB_CMDQE_MAX_CNT_256	256
73 #define BNXT_QPLIB_CMDQE_MAX_CNT_8192	8192
74 #define BNXT_QPLIB_CMDQE_UNITS		sizeof(struct bnxt_qplib_cmdqe)
75 #define BNXT_QPLIB_CMDQE_BYTES(depth)	((depth) * BNXT_QPLIB_CMDQE_UNITS)
76 
77 static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
78 {
79 	u32 npages;
80 
81 	npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
82 	if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
83 		npages++;
84 	return npages;
85 }
86 
87 static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
88 {
89 	return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
90 }
91 
92 static inline u32 bnxt_qplib_cmdqe_cnt_per_pg(u32 depth)
93 {
94 	return (bnxt_qplib_cmdqe_page_size(depth) /
95 		 BNXT_QPLIB_CMDQE_UNITS);
96 }
97 
98 #define MAX_CMDQ_IDX(depth)		((depth) - 1)
99 
100 static inline u32 bnxt_qplib_max_cmdq_idx_per_pg(u32 depth)
101 {
102 	return (bnxt_qplib_cmdqe_cnt_per_pg(depth) - 1);
103 }
104 
105 #define RCFW_MAX_COOKIE_VALUE		0x7FFF
106 #define RCFW_CMD_IS_BLOCKING		0x8000
107 #define RCFW_BLOCKED_CMD_WAIT_COUNT	0x4E20
108 
109 #define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
110 
111 static inline u32 get_cmdq_pg(u32 val, u32 depth)
112 {
113 	return (val & ~(bnxt_qplib_max_cmdq_idx_per_pg(depth))) /
114 		(bnxt_qplib_cmdqe_cnt_per_pg(depth));
115 }
116 
117 static inline u32 get_cmdq_idx(u32 val, u32 depth)
118 {
119 	return val & (bnxt_qplib_max_cmdq_idx_per_pg(depth));
120 }
121 
122 /* Crsq buf is 1024-Byte */
123 struct bnxt_qplib_crsbe {
124 	u8			data[1024];
125 };
126 
127 /* CREQ */
128 /* Allocate 1 per QP for async error notification for now */
129 #define BNXT_QPLIB_CREQE_MAX_CNT	(64 * 1024)
130 #define BNXT_QPLIB_CREQE_UNITS		16	/* 16-Bytes per prod unit */
131 #define BNXT_QPLIB_CREQE_CNT_PER_PG	(PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
132 
133 #define MAX_CREQ_IDX			(BNXT_QPLIB_CREQE_MAX_CNT - 1)
134 #define MAX_CREQ_IDX_PER_PG		(BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
135 
136 static inline u32 get_creq_pg(u32 val)
137 {
138 	return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
139 }
140 
141 static inline u32 get_creq_idx(u32 val)
142 {
143 	return val & MAX_CREQ_IDX_PER_PG;
144 }
145 
146 #define BNXT_QPLIB_CREQE_PER_PG	(PAGE_SIZE / sizeof(struct creq_base))
147 
148 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit)			\
149 	(!!((hdr)->v & CREQ_BASE_V) ==				\
150 	   !((raw_cons) & (cp_bit)))
151 
152 #define CREQ_DB_KEY_CP			(0x2 << CMPL_DOORBELL_KEY_SFT)
153 #define CREQ_DB_IDX_VALID		CMPL_DOORBELL_IDX_VALID
154 #define CREQ_DB_IRQ_DIS			CMPL_DOORBELL_MASK
155 #define CREQ_DB_CP_FLAGS_REARM		(CREQ_DB_KEY_CP |	\
156 					 CREQ_DB_IDX_VALID)
157 #define CREQ_DB_CP_FLAGS		(CREQ_DB_KEY_CP |	\
158 					 CREQ_DB_IDX_VALID |	\
159 					 CREQ_DB_IRQ_DIS)
160 
161 static inline void bnxt_qplib_ring_creq_db64(void __iomem *db, u32 index,
162 					     u32 xid, bool arm)
163 {
164 	u64 val = 0;
165 
166 	val = xid & DBC_DBC_XID_MASK;
167 	val |= DBC_DBC_PATH_ROCE;
168 	val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
169 	val <<= 32;
170 	val |= index & DBC_DBC_INDEX_MASK;
171 
172 	writeq(val, db);
173 }
174 
175 static inline void bnxt_qplib_ring_creq_db_rearm(void __iomem *db, u32 raw_cons,
176 						 u32 max_elements, u32 xid,
177 						 bool gen_p5)
178 {
179 	u32 index = raw_cons & (max_elements - 1);
180 
181 	if (gen_p5)
182 		bnxt_qplib_ring_creq_db64(db, index, xid, true);
183 	else
184 		writel(CREQ_DB_CP_FLAGS_REARM | (index & DBC_DBC32_XID_MASK),
185 		       db);
186 }
187 
188 static inline void bnxt_qplib_ring_creq_db(void __iomem *db, u32 raw_cons,
189 					   u32 max_elements, u32 xid,
190 					   bool gen_p5)
191 {
192 	u32 index = raw_cons & (max_elements - 1);
193 
194 	if (gen_p5)
195 		bnxt_qplib_ring_creq_db64(db, index, xid, true);
196 	else
197 		writel(CREQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK),
198 		       db);
199 }
200 
201 #define CREQ_ENTRY_POLL_BUDGET		0x100
202 
203 /* HWQ */
204 
205 struct bnxt_qplib_crsq {
206 	struct creq_qp_event	*resp;
207 	u32			req_size;
208 };
209 
210 struct bnxt_qplib_rcfw_sbuf {
211 	void *sb;
212 	dma_addr_t dma_addr;
213 	u32 size;
214 };
215 
216 struct bnxt_qplib_qp_node {
217 	u32 qp_id;              /* QP id */
218 	void *qp_handle;        /* ptr to qplib_qp */
219 };
220 
221 #define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
222 
223 /* RCFW Communication Channels */
224 struct bnxt_qplib_rcfw {
225 	struct pci_dev		*pdev;
226 	struct bnxt_qplib_res	*res;
227 	int			vector;
228 	struct tasklet_struct	worker;
229 	bool			requested;
230 	unsigned long		*cmdq_bitmap;
231 	u32			bmap_size;
232 	unsigned long		flags;
233 #define FIRMWARE_INITIALIZED_FLAG	0
234 #define FIRMWARE_FIRST_FLAG		31
235 #define FIRMWARE_TIMED_OUT		3
236 	wait_queue_head_t	waitq;
237 	int			(*aeq_handler)(struct bnxt_qplib_rcfw *,
238 					       void *, void *);
239 	u32			seq_num;
240 
241 	/* Bar region info */
242 	void __iomem		*cmdq_bar_reg_iomem;
243 	u16			cmdq_bar_reg;
244 	u16			cmdq_bar_reg_prod_off;
245 	u16			cmdq_bar_reg_trig_off;
246 	u16			creq_ring_id;
247 	u16			creq_bar_reg;
248 	void __iomem		*creq_bar_reg_iomem;
249 
250 	/* Cmd-Resp and Async Event notification queue */
251 	struct bnxt_qplib_hwq	creq;
252 	u64			creq_qp_event_processed;
253 	u64			creq_func_event_processed;
254 
255 	/* Actual Cmd and Resp Queues */
256 	struct bnxt_qplib_hwq	cmdq;
257 	struct bnxt_qplib_crsq	*crsqe_tbl;
258 	int qp_tbl_size;
259 	struct bnxt_qplib_qp_node *qp_tbl;
260 	u64 oos_prev;
261 	u32 init_oos_stats;
262 	u32 cmdq_depth;
263 };
264 
265 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
266 int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
267 				  struct bnxt_qplib_rcfw *rcfw,
268 				  struct bnxt_qplib_ctx *ctx,
269 				  int qp_tbl_sz);
270 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
271 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
272 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
273 			      bool need_init);
274 int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
275 				   struct bnxt_qplib_rcfw *rcfw,
276 				   int msix_vector,
277 				   int cp_bar_reg_off, int virt_fn,
278 				   int (*aeq_handler)(struct bnxt_qplib_rcfw *,
279 						      void *aeqe, void *obj));
280 
281 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
282 				struct bnxt_qplib_rcfw *rcfw,
283 				u32 size);
284 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
285 			       struct bnxt_qplib_rcfw_sbuf *sbuf);
286 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
287 				 struct cmdq_base *req, struct creq_base *resp,
288 				 void *sbuf, u8 is_block);
289 
290 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
291 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
292 			 struct bnxt_qplib_ctx *ctx, int is_virtfn);
293 void bnxt_qplib_mark_qp_error(void *qp_handle);
294 #endif /* __BNXT_QPLIB_RCFW_H__ */
295