1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Main component of the bnxt_re driver 37 */ 38 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/ethtool.h> 42 #include <linux/mutex.h> 43 #include <linux/list.h> 44 #include <linux/rculist.h> 45 #include <linux/spinlock.h> 46 #include <linux/pci.h> 47 #include <net/dcbnl.h> 48 #include <net/ipv6.h> 49 #include <net/addrconf.h> 50 #include <linux/if_ether.h> 51 #include <linux/auxiliary_bus.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/ib_user_verbs.h> 55 #include <rdma/ib_umem.h> 56 #include <rdma/ib_addr.h> 57 #include <linux/hashtable.h> 58 59 #include "bnxt_ulp.h" 60 #include "roce_hsi.h" 61 #include "qplib_res.h" 62 #include "qplib_sp.h" 63 #include "qplib_fp.h" 64 #include "qplib_rcfw.h" 65 #include "bnxt_re.h" 66 #include "ib_verbs.h" 67 #include <rdma/bnxt_re-abi.h> 68 #include "bnxt.h" 69 #include "hw_counters.h" 70 71 static char version[] = 72 BNXT_RE_DESC "\n"; 73 74 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>"); 75 MODULE_DESCRIPTION(BNXT_RE_DESC); 76 MODULE_LICENSE("Dual BSD/GPL"); 77 78 /* globals */ 79 static DEFINE_MUTEX(bnxt_re_mutex); 80 81 static void bnxt_re_stop_irq(void *handle); 82 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev); 83 static int bnxt_re_netdev_event(struct notifier_block *notifier, 84 unsigned long event, void *ptr); 85 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev); 86 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev); 87 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev); 88 89 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 90 u32 *offset); 91 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 92 { 93 struct bnxt_qplib_chip_ctx *cctx; 94 struct bnxt_en_dev *en_dev; 95 struct bnxt_qplib_res *res; 96 u32 l2db_len = 0; 97 u32 offset = 0; 98 u32 barlen; 99 int rc; 100 101 res = &rdev->qplib_res; 102 en_dev = rdev->en_dev; 103 cctx = rdev->chip_ctx; 104 105 /* Issue qcfg */ 106 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset); 107 if (rc) 108 dev_info(rdev_to_dev(rdev), 109 "Couldn't get DB bar size, Low latency framework is disabled\n"); 110 /* set register offsets for both UC and WC */ 111 if (bnxt_qplib_is_chip_gen_p7(cctx)) { 112 res->dpi_tbl.ucreg.offset = offset; 113 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 114 } else { 115 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET : 116 BNXT_QPLIB_DBR_PF_DB_OFFSET; 117 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset; 118 } 119 120 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size 121 * is equal to the DB-Bar actual size. This indicates that L2 122 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping 123 * in such cases and DB-push will be disabled. 124 */ 125 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION); 126 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) { 127 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 128 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n"); 129 } 130 } 131 132 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode) 133 { 134 struct bnxt_qplib_chip_ctx *cctx; 135 136 cctx = rdev->chip_ctx; 137 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 138 mode : BNXT_QPLIB_WQE_MODE_STATIC; 139 if (bnxt_re_hwrm_qcaps(rdev)) 140 dev_err(rdev_to_dev(rdev), 141 "Failed to query hwrm qcaps\n"); 142 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) 143 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT; 144 } 145 146 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev) 147 { 148 struct bnxt_qplib_chip_ctx *chip_ctx; 149 150 if (!rdev->chip_ctx) 151 return; 152 chip_ctx = rdev->chip_ctx; 153 rdev->chip_ctx = NULL; 154 rdev->rcfw.res = NULL; 155 rdev->qplib_res.cctx = NULL; 156 rdev->qplib_res.pdev = NULL; 157 rdev->qplib_res.netdev = NULL; 158 kfree(chip_ctx); 159 } 160 161 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) 162 { 163 struct bnxt_qplib_chip_ctx *chip_ctx; 164 struct bnxt_en_dev *en_dev; 165 int rc; 166 167 en_dev = rdev->en_dev; 168 169 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL); 170 if (!chip_ctx) 171 return -ENOMEM; 172 chip_ctx->chip_num = en_dev->chip_num; 173 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size; 174 175 rdev->chip_ctx = chip_ctx; 176 /* rest members to follow eventually */ 177 178 rdev->qplib_res.cctx = rdev->chip_ctx; 179 rdev->rcfw.res = &rdev->qplib_res; 180 rdev->qplib_res.dattr = &rdev->dev_attr; 181 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev); 182 183 bnxt_re_set_drv_mode(rdev, wqe_mode); 184 185 bnxt_re_set_db_offset(rdev); 186 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res); 187 if (rc) 188 return rc; 189 190 if (bnxt_qplib_determine_atomics(en_dev->pdev)) 191 ibdev_info(&rdev->ibdev, 192 "platform doesn't support global atomics."); 193 return 0; 194 } 195 196 /* SR-IOV helper functions */ 197 198 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev) 199 { 200 if (BNXT_EN_VF(rdev->en_dev)) 201 rdev->is_virtfn = 1; 202 } 203 204 /* Set the maximum number of each resource that the driver actually wants 205 * to allocate. This may be up to the maximum number the firmware has 206 * reserved for the function. The driver may choose to allocate fewer 207 * resources than the firmware maximum. 208 */ 209 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev) 210 { 211 struct bnxt_qplib_dev_attr *attr; 212 struct bnxt_qplib_ctx *ctx; 213 int i; 214 215 attr = &rdev->dev_attr; 216 ctx = &rdev->qplib_ctx; 217 218 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT, 219 attr->max_qp); 220 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K; 221 /* Use max_mr from fw since max_mrw does not get set */ 222 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr); 223 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT, 224 attr->max_srq); 225 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq); 226 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 227 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) 228 rdev->qplib_ctx.tqm_ctx.qcount[i] = 229 rdev->dev_attr.tqm_alloc_reqs[i]; 230 } 231 232 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf) 233 { 234 struct bnxt_qplib_vf_res *vf_res; 235 u32 mrws = 0; 236 u32 vf_pct; 237 u32 nvfs; 238 239 vf_res = &qplib_ctx->vf_res; 240 /* 241 * Reserve a set of resources for the PF. Divide the remaining 242 * resources among the VFs 243 */ 244 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF; 245 nvfs = num_vf; 246 num_vf = 100 * num_vf; 247 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf; 248 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf; 249 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf; 250 /* 251 * The driver allows many more MRs than other resources. If the 252 * firmware does also, then reserve a fixed amount for the PF and 253 * divide the rest among VFs. VFs may use many MRs for NFS 254 * mounts, ISER, NVME applications, etc. If the firmware severely 255 * restricts the number of MRs, then let PF have half and divide 256 * the rest among VFs, as for the other resource types. 257 */ 258 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) { 259 mrws = qplib_ctx->mrw_count * vf_pct; 260 nvfs = num_vf; 261 } else { 262 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF; 263 } 264 vf_res->max_mrw_per_vf = (mrws / nvfs); 265 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF; 266 } 267 268 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev) 269 { 270 u32 num_vfs; 271 272 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res)); 273 bnxt_re_limit_pf_res(rdev); 274 275 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 276 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs; 277 if (num_vfs) 278 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs); 279 } 280 281 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev) 282 { 283 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev); 284 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 285 bnxt_re_set_resource_limits(rdev); 286 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw, 287 &rdev->qplib_ctx); 288 } 289 } 290 291 static void bnxt_re_shutdown(struct auxiliary_device *adev) 292 { 293 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 294 295 if (!rdev) 296 return; 297 ib_unregister_device(&rdev->ibdev); 298 bnxt_re_dev_uninit(rdev); 299 } 300 301 static void bnxt_re_stop_irq(void *handle) 302 { 303 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 304 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw; 305 struct bnxt_qplib_nq *nq; 306 int indx; 307 308 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) { 309 nq = &rdev->nq[indx - 1]; 310 bnxt_qplib_nq_stop_irq(nq, false); 311 } 312 313 bnxt_qplib_rcfw_stop_irq(rcfw, false); 314 } 315 316 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent) 317 { 318 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 319 struct bnxt_msix_entry *msix_ent = rdev->en_dev->msix_entries; 320 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw; 321 struct bnxt_qplib_nq *nq; 322 int indx, rc; 323 324 if (!ent) { 325 /* Not setting the f/w timeout bit in rcfw. 326 * During the driver unload the first command 327 * to f/w will timeout and that will set the 328 * timeout bit. 329 */ 330 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n"); 331 return; 332 } 333 334 /* Vectors may change after restart, so update with new vectors 335 * in device sctructure. 336 */ 337 for (indx = 0; indx < rdev->num_msix; indx++) 338 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector; 339 340 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector, 341 false); 342 if (rc) { 343 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n"); 344 return; 345 } 346 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) { 347 nq = &rdev->nq[indx - 1]; 348 rc = bnxt_qplib_nq_start_irq(nq, indx - 1, 349 msix_ent[indx].vector, false); 350 if (rc) { 351 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n", 352 indx - 1); 353 return; 354 } 355 } 356 } 357 358 static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 359 .ulp_irq_stop = bnxt_re_stop_irq, 360 .ulp_irq_restart = bnxt_re_start_irq 361 }; 362 363 /* RoCE -> Net driver */ 364 365 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev) 366 { 367 struct bnxt_en_dev *en_dev; 368 int rc; 369 370 en_dev = rdev->en_dev; 371 372 rc = bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev); 373 if (!rc) 374 rdev->qplib_res.pdev = rdev->en_dev->pdev; 375 return rc; 376 } 377 378 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd) 379 { 380 hdr->req_type = cpu_to_le16(opcd); 381 hdr->cmpl_ring = cpu_to_le16(-1); 382 hdr->target_id = cpu_to_le16(-1); 383 } 384 385 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg, 386 int msg_len, void *resp, int resp_max_len, 387 int timeout) 388 { 389 fw_msg->msg = msg; 390 fw_msg->msg_len = msg_len; 391 fw_msg->resp = resp; 392 fw_msg->resp_max_len = resp_max_len; 393 fw_msg->timeout = timeout; 394 } 395 396 /* Query device config using common hwrm */ 397 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 398 u32 *offset) 399 { 400 struct bnxt_en_dev *en_dev = rdev->en_dev; 401 struct hwrm_func_qcfg_output resp = {0}; 402 struct hwrm_func_qcfg_input req = {0}; 403 struct bnxt_fw_msg fw_msg = {}; 404 int rc; 405 406 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG); 407 req.fid = cpu_to_le16(0xffff); 408 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 409 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 410 rc = bnxt_send_msg(en_dev, &fw_msg); 411 if (!rc) { 412 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024); 413 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024); 414 } 415 return rc; 416 } 417 418 /* Query function capabilities using common hwrm */ 419 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev) 420 { 421 struct bnxt_en_dev *en_dev = rdev->en_dev; 422 struct hwrm_func_qcaps_output resp = {}; 423 struct hwrm_func_qcaps_input req = {}; 424 struct bnxt_qplib_chip_ctx *cctx; 425 struct bnxt_fw_msg fw_msg = {}; 426 u32 flags_ext2; 427 int rc; 428 429 cctx = rdev->chip_ctx; 430 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS); 431 req.fid = cpu_to_le16(0xffff); 432 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 433 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 434 435 rc = bnxt_send_msg(en_dev, &fw_msg); 436 if (rc) 437 return rc; 438 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE; 439 440 flags_ext2 = le32_to_cpu(resp.flags_ext2); 441 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED || 442 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED; 443 return 0; 444 } 445 446 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev) 447 { 448 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 449 struct hwrm_func_dbr_pacing_qcfg_output resp = {}; 450 struct hwrm_func_dbr_pacing_qcfg_input req = {}; 451 struct bnxt_en_dev *en_dev = rdev->en_dev; 452 struct bnxt_qplib_chip_ctx *cctx; 453 struct bnxt_fw_msg fw_msg = {}; 454 int rc; 455 456 cctx = rdev->chip_ctx; 457 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG); 458 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 459 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 460 rc = bnxt_send_msg(en_dev, &fw_msg); 461 if (rc) 462 return rc; 463 464 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 465 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) == 466 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC) 467 cctx->dbr_stat_db_fifo = 468 le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 469 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK; 470 471 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth); 472 if (!pacing_data->fifo_max_depth) 473 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx); 474 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask); 475 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift; 476 477 return 0; 478 } 479 480 /* Update the pacing tunable parameters to the default values */ 481 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev) 482 { 483 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 484 485 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing; 486 pacing_data->pacing_th = rdev->pacing.pacing_algo_th; 487 pacing_data->alarm_th = 488 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 489 } 490 491 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev) 492 { 493 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 494 u32 read_val, fifo_occup; 495 496 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off); 497 fifo_occup = pacing_data->fifo_max_depth - 498 ((read_val & pacing_data->fifo_room_mask) >> 499 pacing_data->fifo_room_shift); 500 return fifo_occup; 501 } 502 503 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev) 504 { 505 u32 max_occup, fifo_occup; 506 507 fifo_occup = __get_fifo_occupancy(rdev); 508 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1; 509 if (fifo_occup == max_occup) 510 return true; 511 512 return false; 513 } 514 515 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev) 516 { 517 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 518 u32 fifo_occup; 519 520 /* loop shouldn't run infintely as the occupancy usually goes 521 * below pacing algo threshold as soon as pacing kicks in. 522 */ 523 while (1) { 524 fifo_occup = __get_fifo_occupancy(rdev); 525 /* Fifo occupancy cannot be greater the MAX FIFO depth */ 526 if (fifo_occup > pacing_data->fifo_max_depth) 527 break; 528 529 if (fifo_occup < pacing_data->pacing_th) 530 break; 531 } 532 } 533 534 static void bnxt_re_db_fifo_check(struct work_struct *work) 535 { 536 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 537 dbq_fifo_check_work); 538 struct bnxt_qplib_db_pacing_data *pacing_data; 539 u32 pacing_save; 540 541 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 542 return; 543 pacing_data = rdev->qplib_res.pacing_data; 544 pacing_save = rdev->pacing.do_pacing_save; 545 __wait_for_fifo_occupancy_below_th(rdev); 546 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 547 if (pacing_save > rdev->pacing.dbr_def_do_pacing) { 548 /* Double the do_pacing value during the congestion */ 549 pacing_save = pacing_save << 1; 550 } else { 551 /* 552 * when a new congestion is detected increase the do_pacing 553 * by 8 times. And also increase the pacing_th by 4 times. The 554 * reason to increase pacing_th is to give more space for the 555 * queue to oscillate down without getting empty, but also more 556 * room for the queue to increase without causing another alarm. 557 */ 558 pacing_save = pacing_save << 3; 559 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4; 560 } 561 562 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING) 563 pacing_save = BNXT_RE_MAX_DBR_DO_PACING; 564 565 pacing_data->do_pacing = pacing_save; 566 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 567 pacing_data->alarm_th = 568 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 569 schedule_delayed_work(&rdev->dbq_pacing_work, 570 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 571 rdev->stats.pacing.alerts++; 572 mutex_unlock(&rdev->pacing.dbq_lock); 573 } 574 575 static void bnxt_re_pacing_timer_exp(struct work_struct *work) 576 { 577 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 578 dbq_pacing_work.work); 579 struct bnxt_qplib_db_pacing_data *pacing_data; 580 u32 fifo_occup; 581 582 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 583 return; 584 585 pacing_data = rdev->qplib_res.pacing_data; 586 fifo_occup = __get_fifo_occupancy(rdev); 587 588 if (fifo_occup > pacing_data->pacing_th) 589 goto restart_timer; 590 591 /* 592 * Instead of immediately going back to the default do_pacing 593 * reduce it by 1/8 times and restart the timer. 594 */ 595 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3); 596 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing); 597 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) { 598 bnxt_re_set_default_pacing_data(rdev); 599 rdev->stats.pacing.complete++; 600 goto dbq_unlock; 601 } 602 603 restart_timer: 604 schedule_delayed_work(&rdev->dbq_pacing_work, 605 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 606 rdev->stats.pacing.resched++; 607 dbq_unlock: 608 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 609 mutex_unlock(&rdev->pacing.dbq_lock); 610 } 611 612 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev) 613 { 614 struct bnxt_qplib_db_pacing_data *pacing_data; 615 616 if (!rdev->pacing.dbr_pacing) 617 return; 618 mutex_lock(&rdev->pacing.dbq_lock); 619 pacing_data = rdev->qplib_res.pacing_data; 620 621 /* 622 * Increase the alarm_th to max so that other user lib instances do not 623 * keep alerting the driver. 624 */ 625 pacing_data->alarm_th = pacing_data->fifo_max_depth; 626 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING; 627 cancel_work_sync(&rdev->dbq_fifo_check_work); 628 schedule_work(&rdev->dbq_fifo_check_work); 629 mutex_unlock(&rdev->pacing.dbq_lock); 630 } 631 632 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev) 633 { 634 /* Allocate a page for app use */ 635 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL); 636 if (!rdev->pacing.dbr_page) 637 return -ENOMEM; 638 639 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE); 640 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page; 641 642 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) { 643 free_page((u64)rdev->pacing.dbr_page); 644 rdev->pacing.dbr_page = NULL; 645 return -EIO; 646 } 647 648 /* MAP HW window 2 for reading db fifo depth */ 649 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK, 650 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 651 rdev->pacing.dbr_db_fifo_reg_off = 652 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) + 653 BNXT_RE_GRC_FIFO_REG_BASE; 654 rdev->pacing.dbr_bar_addr = 655 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off; 656 657 if (is_dbr_fifo_full(rdev)) { 658 free_page((u64)rdev->pacing.dbr_page); 659 rdev->pacing.dbr_page = NULL; 660 return -EIO; 661 } 662 663 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD; 664 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME; 665 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION; 666 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing; 667 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off; 668 bnxt_re_set_default_pacing_data(rdev); 669 /* Initialize worker for DBR Pacing */ 670 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check); 671 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp); 672 return 0; 673 } 674 675 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev) 676 { 677 cancel_work_sync(&rdev->dbq_fifo_check_work); 678 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 679 if (rdev->pacing.dbr_page) 680 free_page((u64)rdev->pacing.dbr_page); 681 682 rdev->pacing.dbr_page = NULL; 683 rdev->pacing.dbr_pacing = false; 684 } 685 686 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev, 687 u16 fw_ring_id, int type) 688 { 689 struct bnxt_en_dev *en_dev; 690 struct hwrm_ring_free_input req = {}; 691 struct hwrm_ring_free_output resp; 692 struct bnxt_fw_msg fw_msg = {}; 693 int rc = -EINVAL; 694 695 if (!rdev) 696 return rc; 697 698 en_dev = rdev->en_dev; 699 700 if (!en_dev) 701 return rc; 702 703 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 704 return 0; 705 706 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE); 707 req.ring_type = type; 708 req.ring_id = cpu_to_le16(fw_ring_id); 709 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 710 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 711 rc = bnxt_send_msg(en_dev, &fw_msg); 712 if (rc) 713 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x", 714 req.ring_id, rc); 715 return rc; 716 } 717 718 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev, 719 struct bnxt_re_ring_attr *ring_attr, 720 u16 *fw_ring_id) 721 { 722 struct bnxt_en_dev *en_dev = rdev->en_dev; 723 struct hwrm_ring_alloc_input req = {}; 724 struct hwrm_ring_alloc_output resp; 725 struct bnxt_fw_msg fw_msg = {}; 726 int rc = -EINVAL; 727 728 if (!en_dev) 729 return rc; 730 731 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC); 732 req.enables = 0; 733 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]); 734 if (ring_attr->pages > 1) { 735 /* Page size is in log2 units */ 736 req.page_size = BNXT_PAGE_SHIFT; 737 req.page_tbl_depth = 1; 738 } 739 req.fbo = 0; 740 /* Association of ring index with doorbell index and MSIX number */ 741 req.logical_id = cpu_to_le16(ring_attr->lrid); 742 req.length = cpu_to_le32(ring_attr->depth + 1); 743 req.ring_type = ring_attr->type; 744 req.int_mode = ring_attr->mode; 745 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 746 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 747 rc = bnxt_send_msg(en_dev, &fw_msg); 748 if (!rc) 749 *fw_ring_id = le16_to_cpu(resp.ring_id); 750 751 return rc; 752 } 753 754 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev, 755 u32 fw_stats_ctx_id) 756 { 757 struct bnxt_en_dev *en_dev = rdev->en_dev; 758 struct hwrm_stat_ctx_free_input req = {}; 759 struct hwrm_stat_ctx_free_output resp = {}; 760 struct bnxt_fw_msg fw_msg = {}; 761 int rc = -EINVAL; 762 763 if (!en_dev) 764 return rc; 765 766 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 767 return 0; 768 769 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE); 770 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id); 771 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 772 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 773 rc = bnxt_send_msg(en_dev, &fw_msg); 774 if (rc) 775 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x", 776 rc); 777 778 return rc; 779 } 780 781 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, 782 dma_addr_t dma_map, 783 u32 *fw_stats_ctx_id) 784 { 785 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx; 786 struct hwrm_stat_ctx_alloc_output resp = {}; 787 struct hwrm_stat_ctx_alloc_input req = {}; 788 struct bnxt_en_dev *en_dev = rdev->en_dev; 789 struct bnxt_fw_msg fw_msg = {}; 790 int rc = -EINVAL; 791 792 *fw_stats_ctx_id = INVALID_STATS_CTX_ID; 793 794 if (!en_dev) 795 return rc; 796 797 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC); 798 req.update_period_ms = cpu_to_le32(1000); 799 req.stats_dma_addr = cpu_to_le64(dma_map); 800 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size); 801 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE; 802 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 803 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 804 rc = bnxt_send_msg(en_dev, &fw_msg); 805 if (!rc) 806 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id); 807 808 return rc; 809 } 810 811 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext) 812 { 813 } 814 815 /* Device */ 816 817 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev) 818 { 819 struct ib_device *ibdev = 820 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE); 821 if (!ibdev) 822 return NULL; 823 824 return container_of(ibdev, struct bnxt_re_dev, ibdev); 825 } 826 827 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 828 char *buf) 829 { 830 struct bnxt_re_dev *rdev = 831 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 832 833 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor); 834 } 835 static DEVICE_ATTR_RO(hw_rev); 836 837 static ssize_t hca_type_show(struct device *device, 838 struct device_attribute *attr, char *buf) 839 { 840 struct bnxt_re_dev *rdev = 841 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 842 843 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc); 844 } 845 static DEVICE_ATTR_RO(hca_type); 846 847 static struct attribute *bnxt_re_attributes[] = { 848 &dev_attr_hw_rev.attr, 849 &dev_attr_hca_type.attr, 850 NULL 851 }; 852 853 static const struct attribute_group bnxt_re_dev_attr_group = { 854 .attrs = bnxt_re_attributes, 855 }; 856 857 static const struct ib_device_ops bnxt_re_dev_ops = { 858 .owner = THIS_MODULE, 859 .driver_id = RDMA_DRIVER_BNXT_RE, 860 .uverbs_abi_ver = BNXT_RE_ABI_VERSION, 861 862 .add_gid = bnxt_re_add_gid, 863 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats, 864 .alloc_mr = bnxt_re_alloc_mr, 865 .alloc_pd = bnxt_re_alloc_pd, 866 .alloc_ucontext = bnxt_re_alloc_ucontext, 867 .create_ah = bnxt_re_create_ah, 868 .create_cq = bnxt_re_create_cq, 869 .create_qp = bnxt_re_create_qp, 870 .create_srq = bnxt_re_create_srq, 871 .create_user_ah = bnxt_re_create_ah, 872 .dealloc_pd = bnxt_re_dealloc_pd, 873 .dealloc_ucontext = bnxt_re_dealloc_ucontext, 874 .del_gid = bnxt_re_del_gid, 875 .dereg_mr = bnxt_re_dereg_mr, 876 .destroy_ah = bnxt_re_destroy_ah, 877 .destroy_cq = bnxt_re_destroy_cq, 878 .destroy_qp = bnxt_re_destroy_qp, 879 .destroy_srq = bnxt_re_destroy_srq, 880 .device_group = &bnxt_re_dev_attr_group, 881 .disassociate_ucontext = bnxt_re_disassociate_ucontext, 882 .get_dev_fw_str = bnxt_re_query_fw_str, 883 .get_dma_mr = bnxt_re_get_dma_mr, 884 .get_hw_stats = bnxt_re_ib_get_hw_stats, 885 .get_link_layer = bnxt_re_get_link_layer, 886 .get_port_immutable = bnxt_re_get_port_immutable, 887 .map_mr_sg = bnxt_re_map_mr_sg, 888 .mmap = bnxt_re_mmap, 889 .mmap_free = bnxt_re_mmap_free, 890 .modify_qp = bnxt_re_modify_qp, 891 .modify_srq = bnxt_re_modify_srq, 892 .poll_cq = bnxt_re_poll_cq, 893 .post_recv = bnxt_re_post_recv, 894 .post_send = bnxt_re_post_send, 895 .post_srq_recv = bnxt_re_post_srq_recv, 896 .query_ah = bnxt_re_query_ah, 897 .query_device = bnxt_re_query_device, 898 .query_pkey = bnxt_re_query_pkey, 899 .query_port = bnxt_re_query_port, 900 .query_qp = bnxt_re_query_qp, 901 .query_srq = bnxt_re_query_srq, 902 .reg_user_mr = bnxt_re_reg_user_mr, 903 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf, 904 .req_notify_cq = bnxt_re_req_notify_cq, 905 .resize_cq = bnxt_re_resize_cq, 906 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah), 907 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq), 908 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd), 909 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp), 910 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq), 911 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx), 912 }; 913 914 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev) 915 { 916 struct ib_device *ibdev = &rdev->ibdev; 917 int ret; 918 919 /* ib device init */ 920 ibdev->node_type = RDMA_NODE_IB_CA; 921 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA", 922 strlen(BNXT_RE_DESC) + 5); 923 ibdev->phys_port_cnt = 1; 924 925 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr); 926 927 ibdev->num_comp_vectors = rdev->num_msix - 1; 928 ibdev->dev.parent = &rdev->en_dev->pdev->dev; 929 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY; 930 931 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 932 ibdev->driver_def = bnxt_re_uapi_defs; 933 934 ib_set_device_ops(ibdev, &bnxt_re_dev_ops); 935 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1); 936 if (ret) 937 return ret; 938 939 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX); 940 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ); 941 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev); 942 } 943 944 static struct bnxt_re_dev *bnxt_re_dev_add(struct bnxt_aux_priv *aux_priv, 945 struct bnxt_en_dev *en_dev) 946 { 947 struct bnxt_re_dev *rdev; 948 949 /* Allocate bnxt_re_dev instance here */ 950 rdev = ib_alloc_device(bnxt_re_dev, ibdev); 951 if (!rdev) { 952 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!", 953 ROCE_DRV_MODULE_NAME); 954 return NULL; 955 } 956 /* Default values */ 957 rdev->nb.notifier_call = NULL; 958 rdev->netdev = en_dev->net; 959 rdev->en_dev = en_dev; 960 rdev->id = rdev->en_dev->pdev->devfn; 961 INIT_LIST_HEAD(&rdev->qp_list); 962 mutex_init(&rdev->qp_lock); 963 mutex_init(&rdev->pacing.dbq_lock); 964 atomic_set(&rdev->stats.res.qp_count, 0); 965 atomic_set(&rdev->stats.res.cq_count, 0); 966 atomic_set(&rdev->stats.res.srq_count, 0); 967 atomic_set(&rdev->stats.res.mr_count, 0); 968 atomic_set(&rdev->stats.res.mw_count, 0); 969 atomic_set(&rdev->stats.res.ah_count, 0); 970 atomic_set(&rdev->stats.res.pd_count, 0); 971 rdev->cosq[0] = 0xFFFF; 972 rdev->cosq[1] = 0xFFFF; 973 974 return rdev; 975 } 976 977 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event 978 *unaffi_async) 979 { 980 switch (unaffi_async->event) { 981 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 982 break; 983 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 984 break; 985 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 986 break; 987 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 988 break; 989 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 990 break; 991 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 992 break; 993 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 994 break; 995 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 996 break; 997 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 998 break; 999 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 1000 break; 1001 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 1002 break; 1003 default: 1004 return -EINVAL; 1005 } 1006 return 0; 1007 } 1008 1009 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, 1010 struct bnxt_re_qp *qp) 1011 { 1012 struct bnxt_re_srq *srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq, 1013 qplib_srq); 1014 struct creq_qp_error_notification *err_event; 1015 struct ib_event event = {}; 1016 unsigned int flags; 1017 1018 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR && 1019 rdma_is_kernel_res(&qp->ib_qp.res)) { 1020 flags = bnxt_re_lock_cqs(qp); 1021 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1022 bnxt_re_unlock_cqs(qp, flags); 1023 } 1024 1025 event.device = &qp->rdev->ibdev; 1026 event.element.qp = &qp->ib_qp; 1027 event.event = IB_EVENT_QP_FATAL; 1028 1029 err_event = (struct creq_qp_error_notification *)qp_event; 1030 1031 switch (err_event->req_err_state_reason) { 1032 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR: 1033 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT: 1034 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT: 1035 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2: 1036 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3: 1037 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP: 1038 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND: 1039 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG: 1040 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE: 1041 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR: 1042 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR: 1043 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR: 1044 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR: 1045 event.event = IB_EVENT_QP_ACCESS_ERR; 1046 break; 1047 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1: 1048 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4: 1049 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH: 1050 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR: 1051 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR: 1052 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR: 1053 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR: 1054 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR: 1055 event.event = IB_EVENT_QP_REQ_ERR; 1056 break; 1057 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR: 1058 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR: 1059 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR: 1060 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR: 1061 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR: 1062 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR: 1063 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR: 1064 event.event = IB_EVENT_QP_FATAL; 1065 break; 1066 1067 default: 1068 break; 1069 } 1070 1071 switch (err_event->res_err_state_reason) { 1072 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX: 1073 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH: 1074 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT: 1075 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY: 1076 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR: 1077 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION: 1078 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR: 1079 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY: 1080 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR: 1081 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION: 1082 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR: 1083 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC: 1084 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND: 1085 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY: 1086 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR: 1087 event.event = IB_EVENT_QP_ACCESS_ERR; 1088 break; 1089 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE: 1090 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR: 1091 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE: 1092 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE: 1093 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR: 1094 event.event = IB_EVENT_QP_REQ_ERR; 1095 break; 1096 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW: 1097 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR: 1098 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR: 1099 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR: 1100 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR: 1101 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR: 1102 event.event = IB_EVENT_QP_FATAL; 1103 break; 1104 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR: 1105 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR: 1106 if (srq) 1107 event.event = IB_EVENT_SRQ_ERR; 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 if (err_event->res_err_state_reason || err_event->req_err_state_reason) { 1114 ibdev_dbg(&qp->rdev->ibdev, 1115 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n", 1116 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user", 1117 qp->qplib_qp.id, 1118 err_event->sq_cons_idx, 1119 err_event->rq_cons_idx, 1120 err_event->req_slow_path_state, 1121 err_event->req_err_state_reason, 1122 err_event->res_slow_path_state, 1123 err_event->res_err_state_reason); 1124 } else { 1125 if (srq) 1126 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 1127 } 1128 1129 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) { 1130 (*srq->ib_srq.event_handler)(&event, 1131 srq->ib_srq.srq_context); 1132 } else if (event.device && qp->ib_qp.event_handler) { 1133 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context); 1134 } 1135 1136 return 0; 1137 } 1138 1139 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq) 1140 { 1141 struct creq_cq_error_notification *cqerr; 1142 struct ib_event ibevent = {}; 1143 1144 cqerr = event; 1145 switch (cqerr->cq_err_reason) { 1146 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR: 1147 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR: 1148 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR: 1149 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR: 1150 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR: 1151 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR: 1152 ibevent.event = IB_EVENT_CQ_ERR; 1153 break; 1154 default: 1155 break; 1156 } 1157 1158 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) { 1159 ibevent.element.cq = &cq->ib_cq; 1160 ibevent.device = &cq->rdev->ibdev; 1161 1162 ibdev_dbg(&cq->rdev->ibdev, 1163 "%s err reason %d\n", __func__, cqerr->cq_err_reason); 1164 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context); 1165 } 1166 1167 return 0; 1168 } 1169 1170 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async, 1171 void *obj) 1172 { 1173 struct bnxt_qplib_qp *lib_qp; 1174 struct bnxt_qplib_cq *lib_cq; 1175 struct bnxt_re_qp *qp; 1176 struct bnxt_re_cq *cq; 1177 int rc = 0; 1178 u8 event; 1179 1180 if (!obj) 1181 return rc; /* QP was already dead, still return success */ 1182 1183 event = affi_async->event; 1184 switch (event) { 1185 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 1186 lib_qp = obj; 1187 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp); 1188 rc = bnxt_re_handle_qp_async_event(affi_async, qp); 1189 break; 1190 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION: 1191 lib_cq = obj; 1192 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq); 1193 rc = bnxt_re_handle_cq_async_error(affi_async, cq); 1194 break; 1195 default: 1196 rc = -EINVAL; 1197 } 1198 return rc; 1199 } 1200 1201 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw, 1202 void *aeqe, void *obj) 1203 { 1204 struct creq_qp_event *affi_async; 1205 struct creq_func_event *unaffi_async; 1206 u8 type; 1207 int rc; 1208 1209 type = ((struct creq_base *)aeqe)->type; 1210 if (type == CREQ_BASE_TYPE_FUNC_EVENT) { 1211 unaffi_async = aeqe; 1212 rc = bnxt_re_handle_unaffi_async_event(unaffi_async); 1213 } else { 1214 affi_async = aeqe; 1215 rc = bnxt_re_handle_affi_async_event(affi_async, obj); 1216 } 1217 1218 return rc; 1219 } 1220 1221 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq, 1222 struct bnxt_qplib_srq *handle, u8 event) 1223 { 1224 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq, 1225 qplib_srq); 1226 struct ib_event ib_event; 1227 1228 ib_event.device = &srq->rdev->ibdev; 1229 ib_event.element.srq = &srq->ib_srq; 1230 1231 if (srq->ib_srq.event_handler) { 1232 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 1233 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 1234 (*srq->ib_srq.event_handler)(&ib_event, 1235 srq->ib_srq.srq_context); 1236 } 1237 return 0; 1238 } 1239 1240 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq, 1241 struct bnxt_qplib_cq *handle) 1242 { 1243 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq, 1244 qplib_cq); 1245 u32 *cq_ptr; 1246 1247 if (cq->ib_cq.comp_handler) { 1248 if (cq->uctx_cq_page) { 1249 cq_ptr = (u32 *)cq->uctx_cq_page; 1250 *cq_ptr = cq->qplib_cq.toggle; 1251 } 1252 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context); 1253 } 1254 1255 return 0; 1256 } 1257 1258 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev) 1259 { 1260 int i; 1261 1262 for (i = 1; i < rdev->num_msix; i++) 1263 bnxt_qplib_disable_nq(&rdev->nq[i - 1]); 1264 1265 if (rdev->qplib_res.rcfw) 1266 bnxt_qplib_cleanup_res(&rdev->qplib_res); 1267 } 1268 1269 static int bnxt_re_init_res(struct bnxt_re_dev *rdev) 1270 { 1271 int num_vec_enabled = 0; 1272 int rc = 0, i; 1273 u32 db_offt; 1274 1275 bnxt_qplib_init_res(&rdev->qplib_res); 1276 1277 for (i = 1; i < rdev->num_msix ; i++) { 1278 db_offt = rdev->en_dev->msix_entries[i].db_offset; 1279 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1], 1280 i - 1, rdev->en_dev->msix_entries[i].vector, 1281 db_offt, &bnxt_re_cqn_handler, 1282 &bnxt_re_srqn_handler); 1283 if (rc) { 1284 ibdev_err(&rdev->ibdev, 1285 "Failed to enable NQ with rc = 0x%x", rc); 1286 goto fail; 1287 } 1288 num_vec_enabled++; 1289 } 1290 return 0; 1291 fail: 1292 for (i = num_vec_enabled; i >= 0; i--) 1293 bnxt_qplib_disable_nq(&rdev->nq[i]); 1294 return rc; 1295 } 1296 1297 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev) 1298 { 1299 u8 type; 1300 int i; 1301 1302 for (i = 0; i < rdev->num_msix - 1; i++) { 1303 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1304 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1305 bnxt_qplib_free_nq(&rdev->nq[i]); 1306 rdev->nq[i].res = NULL; 1307 } 1308 } 1309 1310 static void bnxt_re_free_res(struct bnxt_re_dev *rdev) 1311 { 1312 bnxt_re_free_nq_res(rdev); 1313 1314 if (rdev->qplib_res.dpi_tbl.max) { 1315 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1316 &rdev->dpi_privileged); 1317 } 1318 if (rdev->qplib_res.rcfw) { 1319 bnxt_qplib_free_res(&rdev->qplib_res); 1320 rdev->qplib_res.rcfw = NULL; 1321 } 1322 } 1323 1324 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev) 1325 { 1326 struct bnxt_re_ring_attr rattr = {}; 1327 int num_vec_created = 0; 1328 int rc, i; 1329 u8 type; 1330 1331 /* Configure and allocate resources for qplib */ 1332 rdev->qplib_res.rcfw = &rdev->rcfw; 1333 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1334 if (rc) 1335 goto fail; 1336 1337 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev, 1338 rdev->netdev, &rdev->dev_attr); 1339 if (rc) 1340 goto fail; 1341 1342 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res, 1343 &rdev->dpi_privileged, 1344 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL); 1345 if (rc) 1346 goto dealloc_res; 1347 1348 for (i = 0; i < rdev->num_msix - 1; i++) { 1349 struct bnxt_qplib_nq *nq; 1350 1351 nq = &rdev->nq[i]; 1352 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT; 1353 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]); 1354 if (rc) { 1355 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x", 1356 i, rc); 1357 goto free_nq; 1358 } 1359 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1360 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1361 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count; 1362 rattr.type = type; 1363 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1364 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1; 1365 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx; 1366 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id); 1367 if (rc) { 1368 ibdev_err(&rdev->ibdev, 1369 "Failed to allocate NQ fw id with rc = 0x%x", 1370 rc); 1371 bnxt_qplib_free_nq(&rdev->nq[i]); 1372 goto free_nq; 1373 } 1374 num_vec_created++; 1375 } 1376 return 0; 1377 free_nq: 1378 for (i = num_vec_created - 1; i >= 0; i--) { 1379 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1380 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1381 bnxt_qplib_free_nq(&rdev->nq[i]); 1382 } 1383 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1384 &rdev->dpi_privileged); 1385 dealloc_res: 1386 bnxt_qplib_free_res(&rdev->qplib_res); 1387 1388 fail: 1389 rdev->qplib_res.rcfw = NULL; 1390 return rc; 1391 } 1392 1393 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 1394 u8 port_num, enum ib_event_type event) 1395 { 1396 struct ib_event ib_event; 1397 1398 ib_event.device = ibdev; 1399 if (qp) { 1400 ib_event.element.qp = qp; 1401 ib_event.event = event; 1402 if (qp->event_handler) 1403 qp->event_handler(&ib_event, qp->qp_context); 1404 1405 } else { 1406 ib_event.element.port_num = port_num; 1407 ib_event.event = event; 1408 ib_dispatch_event(&ib_event); 1409 } 1410 } 1411 1412 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev, 1413 struct bnxt_re_qp *qp) 1414 { 1415 return (qp->ib_qp.qp_type == IB_QPT_GSI) || 1416 (qp == rdev->gsi_ctx.gsi_sqp); 1417 } 1418 1419 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev) 1420 { 1421 int mask = IB_QP_STATE; 1422 struct ib_qp_attr qp_attr; 1423 struct bnxt_re_qp *qp; 1424 1425 qp_attr.qp_state = IB_QPS_ERR; 1426 mutex_lock(&rdev->qp_lock); 1427 list_for_each_entry(qp, &rdev->qp_list, list) { 1428 /* Modify the state of all QPs except QP1/Shadow QP */ 1429 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) { 1430 if (qp->qplib_qp.state != 1431 CMDQ_MODIFY_QP_NEW_STATE_RESET && 1432 qp->qplib_qp.state != 1433 CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1434 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp, 1435 1, IB_EVENT_QP_FATAL); 1436 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask, 1437 NULL); 1438 } 1439 } 1440 } 1441 mutex_unlock(&rdev->qp_lock); 1442 } 1443 1444 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev) 1445 { 1446 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 1447 struct bnxt_qplib_gid gid; 1448 u16 gid_idx, index; 1449 int rc = 0; 1450 1451 if (!ib_device_try_get(&rdev->ibdev)) 1452 return 0; 1453 1454 for (index = 0; index < sgid_tbl->active; index++) { 1455 gid_idx = sgid_tbl->hw_id[index]; 1456 1457 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero, 1458 sizeof(bnxt_qplib_gid_zero))) 1459 continue; 1460 /* need to modify the VLAN enable setting of non VLAN GID only 1461 * as setting is done for VLAN GID while adding GID 1462 */ 1463 if (sgid_tbl->vlan[index]) 1464 continue; 1465 1466 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid)); 1467 1468 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx, 1469 rdev->qplib_res.netdev->dev_addr); 1470 } 1471 1472 ib_device_put(&rdev->ibdev); 1473 return rc; 1474 } 1475 1476 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev) 1477 { 1478 u32 prio_map = 0, tmp_map = 0; 1479 struct net_device *netdev; 1480 struct dcb_app app = {}; 1481 1482 netdev = rdev->netdev; 1483 1484 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE; 1485 app.protocol = ETH_P_IBOE; 1486 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1487 prio_map = tmp_map; 1488 1489 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM; 1490 app.protocol = ROCE_V2_UDP_DPORT; 1491 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1492 prio_map |= tmp_map; 1493 1494 return prio_map; 1495 } 1496 1497 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev) 1498 { 1499 u8 prio_map = 0; 1500 1501 /* Get priority for roce */ 1502 prio_map = bnxt_re_get_priority_mask(rdev); 1503 1504 if (prio_map == rdev->cur_prio_map) 1505 return 0; 1506 rdev->cur_prio_map = prio_map; 1507 /* Actual priorities are not programmed as they are already 1508 * done by L2 driver; just enable or disable priority vlan tagging 1509 */ 1510 if ((prio_map == 0 && rdev->qplib_res.prio) || 1511 (prio_map != 0 && !rdev->qplib_res.prio)) { 1512 rdev->qplib_res.prio = prio_map; 1513 bnxt_re_update_gid(rdev); 1514 } 1515 1516 return 0; 1517 } 1518 1519 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev) 1520 { 1521 struct bnxt_en_dev *en_dev = rdev->en_dev; 1522 struct hwrm_ver_get_output resp = {}; 1523 struct hwrm_ver_get_input req = {}; 1524 struct bnxt_qplib_chip_ctx *cctx; 1525 struct bnxt_fw_msg fw_msg = {}; 1526 int rc; 1527 1528 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET); 1529 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 1530 req.hwrm_intf_min = HWRM_VERSION_MINOR; 1531 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 1532 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 1533 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 1534 rc = bnxt_send_msg(en_dev, &fw_msg); 1535 if (rc) { 1536 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x", 1537 rc); 1538 return; 1539 } 1540 1541 cctx = rdev->chip_ctx; 1542 cctx->hwrm_intf_ver = 1543 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 | 1544 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 | 1545 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 | 1546 le16_to_cpu(resp.hwrm_intf_patch); 1547 1548 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout); 1549 1550 if (!cctx->hwrm_cmd_max_timeout) 1551 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT; 1552 } 1553 1554 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev) 1555 { 1556 int rc; 1557 u32 event; 1558 1559 /* Register ib dev */ 1560 rc = bnxt_re_register_ib(rdev); 1561 if (rc) { 1562 pr_err("Failed to register with IB: %#x\n", rc); 1563 return rc; 1564 } 1565 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully"); 1566 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags); 1567 1568 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ? 1569 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 1570 1571 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event); 1572 1573 return rc; 1574 } 1575 1576 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev) 1577 { 1578 u8 type; 1579 int rc; 1580 1581 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags)) 1582 cancel_delayed_work_sync(&rdev->worker); 1583 1584 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, 1585 &rdev->flags)) 1586 bnxt_re_cleanup_res(rdev); 1587 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags)) 1588 bnxt_re_free_res(rdev); 1589 1590 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) { 1591 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw); 1592 if (rc) 1593 ibdev_warn(&rdev->ibdev, 1594 "Failed to deinitialize RCFW: %#x", rc); 1595 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1596 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1597 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1598 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1599 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1600 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1601 } 1602 1603 rdev->num_msix = 0; 1604 1605 if (rdev->pacing.dbr_pacing) 1606 bnxt_re_deinitialize_dbr_pacing(rdev); 1607 1608 bnxt_re_destroy_chip_ctx(rdev); 1609 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) 1610 bnxt_unregister_dev(rdev->en_dev); 1611 } 1612 1613 /* worker thread for polling periodic events. Now used for QoS programming*/ 1614 static void bnxt_re_worker(struct work_struct *work) 1615 { 1616 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 1617 worker.work); 1618 1619 bnxt_re_setup_qos(rdev); 1620 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1621 } 1622 1623 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode) 1624 { 1625 struct bnxt_re_ring_attr rattr = {}; 1626 struct bnxt_qplib_creq_ctx *creq; 1627 u32 db_offt; 1628 int vid; 1629 u8 type; 1630 int rc; 1631 1632 /* Registered a new RoCE device instance to netdev */ 1633 rc = bnxt_re_register_netdev(rdev); 1634 if (rc) { 1635 ibdev_err(&rdev->ibdev, 1636 "Failed to register with netedev: %#x\n", rc); 1637 return -EINVAL; 1638 } 1639 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1640 1641 rc = bnxt_re_setup_chip_ctx(rdev, wqe_mode); 1642 if (rc) { 1643 bnxt_unregister_dev(rdev->en_dev); 1644 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1645 ibdev_err(&rdev->ibdev, "Failed to get chip context\n"); 1646 return -EINVAL; 1647 } 1648 1649 /* Check whether VF or PF */ 1650 bnxt_re_get_sriov_func_type(rdev); 1651 1652 if (!rdev->en_dev->ulp_tbl->msix_requested) { 1653 ibdev_err(&rdev->ibdev, 1654 "Failed to get MSI-X vectors: %#x\n", rc); 1655 rc = -EINVAL; 1656 goto fail; 1657 } 1658 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n", 1659 rdev->en_dev->ulp_tbl->msix_requested); 1660 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested; 1661 1662 bnxt_re_query_hwrm_intf_version(rdev); 1663 1664 /* Establish RCFW Communication Channel to initialize the context 1665 * memory for the function and all child VFs 1666 */ 1667 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw, 1668 &rdev->qplib_ctx, 1669 BNXT_RE_MAX_QPC_COUNT); 1670 if (rc) { 1671 ibdev_err(&rdev->ibdev, 1672 "Failed to allocate RCFW Channel: %#x\n", rc); 1673 goto fail; 1674 } 1675 1676 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1677 creq = &rdev->rcfw.creq; 1678 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1679 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count; 1680 rattr.type = type; 1681 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1682 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1; 1683 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx; 1684 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id); 1685 if (rc) { 1686 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc); 1687 goto free_rcfw; 1688 } 1689 db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset; 1690 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector; 1691 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw, 1692 vid, db_offt, 1693 &bnxt_re_aeq_handler); 1694 if (rc) { 1695 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n", 1696 rc); 1697 goto free_ring; 1698 } 1699 1700 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) { 1701 rc = bnxt_re_initialize_dbr_pacing(rdev); 1702 if (!rc) { 1703 rdev->pacing.dbr_pacing = true; 1704 } else { 1705 ibdev_err(&rdev->ibdev, 1706 "DBR pacing disabled with error : %d\n", rc); 1707 rdev->pacing.dbr_pacing = false; 1708 } 1709 } 1710 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1711 if (rc) 1712 goto disable_rcfw; 1713 1714 bnxt_re_set_resource_limits(rdev); 1715 1716 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0, 1717 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)); 1718 if (rc) { 1719 ibdev_err(&rdev->ibdev, 1720 "Failed to allocate QPLIB context: %#x\n", rc); 1721 goto disable_rcfw; 1722 } 1723 rc = bnxt_re_net_stats_ctx_alloc(rdev, 1724 rdev->qplib_ctx.stats.dma_map, 1725 &rdev->qplib_ctx.stats.fw_id); 1726 if (rc) { 1727 ibdev_err(&rdev->ibdev, 1728 "Failed to allocate stats context: %#x\n", rc); 1729 goto free_ctx; 1730 } 1731 1732 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx, 1733 rdev->is_virtfn); 1734 if (rc) { 1735 ibdev_err(&rdev->ibdev, 1736 "Failed to initialize RCFW: %#x\n", rc); 1737 goto free_sctx; 1738 } 1739 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags); 1740 1741 /* Resources based on the 'new' device caps */ 1742 rc = bnxt_re_alloc_res(rdev); 1743 if (rc) { 1744 ibdev_err(&rdev->ibdev, 1745 "Failed to allocate resources: %#x\n", rc); 1746 goto fail; 1747 } 1748 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags); 1749 rc = bnxt_re_init_res(rdev); 1750 if (rc) { 1751 ibdev_err(&rdev->ibdev, 1752 "Failed to initialize resources: %#x\n", rc); 1753 goto fail; 1754 } 1755 1756 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags); 1757 1758 if (!rdev->is_virtfn) { 1759 rc = bnxt_re_setup_qos(rdev); 1760 if (rc) 1761 ibdev_info(&rdev->ibdev, 1762 "RoCE priority not yet configured\n"); 1763 1764 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker); 1765 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags); 1766 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1767 /* 1768 * Use the total VF count since the actual VF count may not be 1769 * available at this point. 1770 */ 1771 bnxt_re_vf_res_config(rdev); 1772 } 1773 hash_init(rdev->cq_hash); 1774 1775 return 0; 1776 free_sctx: 1777 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1778 free_ctx: 1779 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1780 disable_rcfw: 1781 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1782 free_ring: 1783 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1784 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1785 free_rcfw: 1786 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1787 fail: 1788 bnxt_re_dev_uninit(rdev); 1789 1790 return rc; 1791 } 1792 1793 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 wqe_mode) 1794 { 1795 struct bnxt_aux_priv *aux_priv = 1796 container_of(adev, struct bnxt_aux_priv, aux_dev); 1797 struct bnxt_en_dev *en_dev; 1798 struct bnxt_re_dev *rdev; 1799 int rc; 1800 1801 /* en_dev should never be NULL as long as adev and aux_dev are valid. */ 1802 en_dev = aux_priv->edev; 1803 1804 rdev = bnxt_re_dev_add(aux_priv, en_dev); 1805 if (!rdev || !rdev_to_dev(rdev)) { 1806 rc = -ENOMEM; 1807 goto exit; 1808 } 1809 1810 rc = bnxt_re_dev_init(rdev, wqe_mode); 1811 if (rc) 1812 goto re_dev_dealloc; 1813 1814 rc = bnxt_re_ib_init(rdev); 1815 if (rc) { 1816 pr_err("Failed to register with IB: %s", 1817 aux_priv->aux_dev.name); 1818 goto re_dev_uninit; 1819 } 1820 auxiliary_set_drvdata(adev, rdev); 1821 1822 return 0; 1823 1824 re_dev_uninit: 1825 bnxt_re_dev_uninit(rdev); 1826 re_dev_dealloc: 1827 ib_dealloc_device(&rdev->ibdev); 1828 exit: 1829 return rc; 1830 } 1831 1832 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 1833 { 1834 struct bnxt_qplib_cc_param cc_param = {}; 1835 1836 /* Do not enable congestion control on VFs */ 1837 if (rdev->is_virtfn) 1838 return; 1839 1840 /* Currently enabling only for GenP5 adapters */ 1841 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 1842 return; 1843 1844 if (enable) { 1845 cc_param.enable = 1; 1846 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE; 1847 } 1848 1849 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE | 1850 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 1851 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 1852 1853 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 1854 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 1855 } 1856 1857 /* 1858 * "Notifier chain callback can be invoked for the same chain from 1859 * different CPUs at the same time". 1860 * 1861 * For cases when the netdev is already present, our call to the 1862 * register_netdevice_notifier() will actually get the rtnl_lock() 1863 * before sending NETDEV_REGISTER and (if up) NETDEV_UP 1864 * events. 1865 * 1866 * But for cases when the netdev is not already present, the notifier 1867 * chain is subjected to be invoked from different CPUs simultaneously. 1868 * 1869 * This is protected by the netdev_mutex. 1870 */ 1871 static int bnxt_re_netdev_event(struct notifier_block *notifier, 1872 unsigned long event, void *ptr) 1873 { 1874 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr); 1875 struct bnxt_re_dev *rdev; 1876 1877 real_dev = rdma_vlan_dev_real_dev(netdev); 1878 if (!real_dev) 1879 real_dev = netdev; 1880 1881 if (real_dev != netdev) 1882 goto exit; 1883 1884 rdev = bnxt_re_from_netdev(real_dev); 1885 if (!rdev) 1886 return NOTIFY_DONE; 1887 1888 1889 switch (event) { 1890 case NETDEV_UP: 1891 case NETDEV_DOWN: 1892 case NETDEV_CHANGE: 1893 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 1894 netif_carrier_ok(real_dev) ? 1895 IB_EVENT_PORT_ACTIVE : 1896 IB_EVENT_PORT_ERR); 1897 break; 1898 default: 1899 break; 1900 } 1901 ib_device_put(&rdev->ibdev); 1902 exit: 1903 return NOTIFY_DONE; 1904 } 1905 1906 #define BNXT_ADEV_NAME "bnxt_en" 1907 1908 static void bnxt_re_remove(struct auxiliary_device *adev) 1909 { 1910 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1911 1912 if (!rdev) 1913 return; 1914 1915 mutex_lock(&bnxt_re_mutex); 1916 if (rdev->nb.notifier_call) { 1917 unregister_netdevice_notifier(&rdev->nb); 1918 rdev->nb.notifier_call = NULL; 1919 } else { 1920 /* If notifier is null, we should have already done a 1921 * clean up before coming here. 1922 */ 1923 goto skip_remove; 1924 } 1925 bnxt_re_setup_cc(rdev, false); 1926 ib_unregister_device(&rdev->ibdev); 1927 bnxt_re_dev_uninit(rdev); 1928 ib_dealloc_device(&rdev->ibdev); 1929 skip_remove: 1930 mutex_unlock(&bnxt_re_mutex); 1931 } 1932 1933 static int bnxt_re_probe(struct auxiliary_device *adev, 1934 const struct auxiliary_device_id *id) 1935 { 1936 struct bnxt_re_dev *rdev; 1937 int rc; 1938 1939 mutex_lock(&bnxt_re_mutex); 1940 rc = bnxt_re_add_device(adev, BNXT_QPLIB_WQE_MODE_STATIC); 1941 if (rc) { 1942 mutex_unlock(&bnxt_re_mutex); 1943 return rc; 1944 } 1945 1946 rdev = auxiliary_get_drvdata(adev); 1947 1948 rdev->nb.notifier_call = bnxt_re_netdev_event; 1949 rc = register_netdevice_notifier(&rdev->nb); 1950 if (rc) { 1951 rdev->nb.notifier_call = NULL; 1952 pr_err("%s: Cannot register to netdevice_notifier", 1953 ROCE_DRV_MODULE_NAME); 1954 goto err; 1955 } 1956 1957 bnxt_re_setup_cc(rdev, true); 1958 mutex_unlock(&bnxt_re_mutex); 1959 return 0; 1960 1961 err: 1962 mutex_unlock(&bnxt_re_mutex); 1963 bnxt_re_remove(adev); 1964 1965 return rc; 1966 } 1967 1968 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state) 1969 { 1970 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1971 1972 if (!rdev) 1973 return 0; 1974 1975 mutex_lock(&bnxt_re_mutex); 1976 /* L2 driver may invoke this callback during device error/crash or device 1977 * reset. Current RoCE driver doesn't recover the device in case of 1978 * error. Handle the error by dispatching fatal events to all qps 1979 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 1980 * L2 driver want to modify the MSIx table. 1981 */ 1982 1983 ibdev_info(&rdev->ibdev, "Handle device suspend call"); 1984 /* Check the current device state from bnxt_en_dev and move the 1985 * device to detached state if FW_FATAL_COND is set. 1986 * This prevents more commands to HW during clean-up, 1987 * in case the device is already in error. 1988 */ 1989 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) 1990 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 1991 1992 bnxt_re_dev_stop(rdev); 1993 bnxt_re_stop_irq(rdev); 1994 /* Move the device states to detached and avoid sending any more 1995 * commands to HW 1996 */ 1997 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 1998 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 1999 wake_up_all(&rdev->rcfw.cmdq.waitq); 2000 mutex_unlock(&bnxt_re_mutex); 2001 2002 return 0; 2003 } 2004 2005 static int bnxt_re_resume(struct auxiliary_device *adev) 2006 { 2007 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 2008 2009 if (!rdev) 2010 return 0; 2011 2012 mutex_lock(&bnxt_re_mutex); 2013 /* L2 driver may invoke this callback during device recovery, resume. 2014 * reset. Current RoCE driver doesn't recover the device in case of 2015 * error. Handle the error by dispatching fatal events to all qps 2016 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 2017 * L2 driver want to modify the MSIx table. 2018 */ 2019 2020 ibdev_info(&rdev->ibdev, "Handle device resume call"); 2021 mutex_unlock(&bnxt_re_mutex); 2022 2023 return 0; 2024 } 2025 2026 static const struct auxiliary_device_id bnxt_re_id_table[] = { 2027 { .name = BNXT_ADEV_NAME ".rdma", }, 2028 {}, 2029 }; 2030 2031 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table); 2032 2033 static struct auxiliary_driver bnxt_re_driver = { 2034 .name = "rdma", 2035 .probe = bnxt_re_probe, 2036 .remove = bnxt_re_remove, 2037 .shutdown = bnxt_re_shutdown, 2038 .suspend = bnxt_re_suspend, 2039 .resume = bnxt_re_resume, 2040 .id_table = bnxt_re_id_table, 2041 }; 2042 2043 static int __init bnxt_re_mod_init(void) 2044 { 2045 int rc; 2046 2047 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version); 2048 rc = auxiliary_driver_register(&bnxt_re_driver); 2049 if (rc) { 2050 pr_err("%s: Failed to register auxiliary driver\n", 2051 ROCE_DRV_MODULE_NAME); 2052 return rc; 2053 } 2054 return 0; 2055 } 2056 2057 static void __exit bnxt_re_mod_exit(void) 2058 { 2059 auxiliary_driver_unregister(&bnxt_re_driver); 2060 } 2061 2062 module_init(bnxt_re_mod_init); 2063 module_exit(bnxt_re_mod_exit); 2064