1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Main component of the bnxt_re driver 37 */ 38 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/ethtool.h> 42 #include <linux/mutex.h> 43 #include <linux/list.h> 44 #include <linux/rculist.h> 45 #include <linux/spinlock.h> 46 #include <linux/pci.h> 47 #include <net/dcbnl.h> 48 #include <net/ipv6.h> 49 #include <net/addrconf.h> 50 #include <linux/if_ether.h> 51 #include <linux/auxiliary_bus.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/ib_user_verbs.h> 55 #include <rdma/ib_umem.h> 56 #include <rdma/ib_addr.h> 57 #include <linux/hashtable.h> 58 59 #include "bnxt_ulp.h" 60 #include "roce_hsi.h" 61 #include "qplib_res.h" 62 #include "qplib_sp.h" 63 #include "qplib_fp.h" 64 #include "qplib_rcfw.h" 65 #include "bnxt_re.h" 66 #include "ib_verbs.h" 67 #include <rdma/bnxt_re-abi.h> 68 #include "bnxt.h" 69 #include "hw_counters.h" 70 71 static char version[] = 72 BNXT_RE_DESC "\n"; 73 74 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>"); 75 MODULE_DESCRIPTION(BNXT_RE_DESC); 76 MODULE_LICENSE("Dual BSD/GPL"); 77 78 /* globals */ 79 static DEFINE_MUTEX(bnxt_re_mutex); 80 81 static void bnxt_re_stop_irq(void *handle); 82 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev); 83 static int bnxt_re_netdev_event(struct notifier_block *notifier, 84 unsigned long event, void *ptr); 85 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev); 86 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev); 87 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev); 88 89 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 90 u32 *offset); 91 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 92 { 93 struct bnxt_qplib_chip_ctx *cctx; 94 struct bnxt_en_dev *en_dev; 95 struct bnxt_qplib_res *res; 96 u32 l2db_len = 0; 97 u32 offset = 0; 98 u32 barlen; 99 int rc; 100 101 res = &rdev->qplib_res; 102 en_dev = rdev->en_dev; 103 cctx = rdev->chip_ctx; 104 105 /* Issue qcfg */ 106 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset); 107 if (rc) 108 dev_info(rdev_to_dev(rdev), 109 "Couldn't get DB bar size, Low latency framework is disabled\n"); 110 /* set register offsets for both UC and WC */ 111 if (bnxt_qplib_is_chip_gen_p7(cctx)) { 112 res->dpi_tbl.ucreg.offset = offset; 113 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 114 } else { 115 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET : 116 BNXT_QPLIB_DBR_PF_DB_OFFSET; 117 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset; 118 } 119 120 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size 121 * is equal to the DB-Bar actual size. This indicates that L2 122 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping 123 * in such cases and DB-push will be disabled. 124 */ 125 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION); 126 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) { 127 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 128 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n"); 129 } 130 } 131 132 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode) 133 { 134 struct bnxt_qplib_chip_ctx *cctx; 135 136 cctx = rdev->chip_ctx; 137 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 138 mode : BNXT_QPLIB_WQE_MODE_STATIC; 139 if (bnxt_re_hwrm_qcaps(rdev)) 140 dev_err(rdev_to_dev(rdev), 141 "Failed to query hwrm qcaps\n"); 142 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) 143 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT; 144 } 145 146 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev) 147 { 148 struct bnxt_qplib_chip_ctx *chip_ctx; 149 150 if (!rdev->chip_ctx) 151 return; 152 chip_ctx = rdev->chip_ctx; 153 rdev->chip_ctx = NULL; 154 rdev->rcfw.res = NULL; 155 rdev->qplib_res.cctx = NULL; 156 rdev->qplib_res.pdev = NULL; 157 rdev->qplib_res.netdev = NULL; 158 kfree(chip_ctx); 159 } 160 161 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) 162 { 163 struct bnxt_qplib_chip_ctx *chip_ctx; 164 struct bnxt_en_dev *en_dev; 165 int rc; 166 167 en_dev = rdev->en_dev; 168 169 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL); 170 if (!chip_ctx) 171 return -ENOMEM; 172 chip_ctx->chip_num = en_dev->chip_num; 173 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size; 174 175 rdev->chip_ctx = chip_ctx; 176 /* rest members to follow eventually */ 177 178 rdev->qplib_res.cctx = rdev->chip_ctx; 179 rdev->rcfw.res = &rdev->qplib_res; 180 rdev->qplib_res.dattr = &rdev->dev_attr; 181 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev); 182 183 bnxt_re_set_drv_mode(rdev, wqe_mode); 184 185 bnxt_re_set_db_offset(rdev); 186 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res); 187 if (rc) 188 return rc; 189 190 if (bnxt_qplib_determine_atomics(en_dev->pdev)) 191 ibdev_info(&rdev->ibdev, 192 "platform doesn't support global atomics."); 193 return 0; 194 } 195 196 /* SR-IOV helper functions */ 197 198 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev) 199 { 200 if (BNXT_EN_VF(rdev->en_dev)) 201 rdev->is_virtfn = 1; 202 } 203 204 /* Set the maximum number of each resource that the driver actually wants 205 * to allocate. This may be up to the maximum number the firmware has 206 * reserved for the function. The driver may choose to allocate fewer 207 * resources than the firmware maximum. 208 */ 209 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev) 210 { 211 struct bnxt_qplib_dev_attr *attr; 212 struct bnxt_qplib_ctx *ctx; 213 int i; 214 215 attr = &rdev->dev_attr; 216 ctx = &rdev->qplib_ctx; 217 218 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT, 219 attr->max_qp); 220 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K; 221 /* Use max_mr from fw since max_mrw does not get set */ 222 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr); 223 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT, 224 attr->max_srq); 225 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq); 226 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 227 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) 228 rdev->qplib_ctx.tqm_ctx.qcount[i] = 229 rdev->dev_attr.tqm_alloc_reqs[i]; 230 } 231 232 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf) 233 { 234 struct bnxt_qplib_vf_res *vf_res; 235 u32 mrws = 0; 236 u32 vf_pct; 237 u32 nvfs; 238 239 vf_res = &qplib_ctx->vf_res; 240 /* 241 * Reserve a set of resources for the PF. Divide the remaining 242 * resources among the VFs 243 */ 244 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF; 245 nvfs = num_vf; 246 num_vf = 100 * num_vf; 247 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf; 248 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf; 249 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf; 250 /* 251 * The driver allows many more MRs than other resources. If the 252 * firmware does also, then reserve a fixed amount for the PF and 253 * divide the rest among VFs. VFs may use many MRs for NFS 254 * mounts, ISER, NVME applications, etc. If the firmware severely 255 * restricts the number of MRs, then let PF have half and divide 256 * the rest among VFs, as for the other resource types. 257 */ 258 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) { 259 mrws = qplib_ctx->mrw_count * vf_pct; 260 nvfs = num_vf; 261 } else { 262 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF; 263 } 264 vf_res->max_mrw_per_vf = (mrws / nvfs); 265 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF; 266 } 267 268 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev) 269 { 270 u32 num_vfs; 271 272 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res)); 273 bnxt_re_limit_pf_res(rdev); 274 275 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 276 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs; 277 if (num_vfs) 278 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs); 279 } 280 281 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev) 282 { 283 284 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 285 return; 286 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev); 287 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 288 bnxt_re_set_resource_limits(rdev); 289 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw, 290 &rdev->qplib_ctx); 291 } 292 } 293 294 static void bnxt_re_shutdown(struct auxiliary_device *adev) 295 { 296 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 297 298 if (!rdev) 299 return; 300 ib_unregister_device(&rdev->ibdev); 301 bnxt_re_dev_uninit(rdev); 302 } 303 304 static void bnxt_re_stop_irq(void *handle) 305 { 306 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 307 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw; 308 struct bnxt_qplib_nq *nq; 309 int indx; 310 311 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) { 312 nq = &rdev->nq[indx - 1]; 313 bnxt_qplib_nq_stop_irq(nq, false); 314 } 315 316 bnxt_qplib_rcfw_stop_irq(rcfw, false); 317 } 318 319 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent) 320 { 321 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 322 struct bnxt_msix_entry *msix_ent = rdev->en_dev->msix_entries; 323 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw; 324 struct bnxt_qplib_nq *nq; 325 int indx, rc; 326 327 if (!ent) { 328 /* Not setting the f/w timeout bit in rcfw. 329 * During the driver unload the first command 330 * to f/w will timeout and that will set the 331 * timeout bit. 332 */ 333 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n"); 334 return; 335 } 336 337 /* Vectors may change after restart, so update with new vectors 338 * in device sctructure. 339 */ 340 for (indx = 0; indx < rdev->num_msix; indx++) 341 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector; 342 343 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector, 344 false); 345 if (rc) { 346 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n"); 347 return; 348 } 349 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) { 350 nq = &rdev->nq[indx - 1]; 351 rc = bnxt_qplib_nq_start_irq(nq, indx - 1, 352 msix_ent[indx].vector, false); 353 if (rc) { 354 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n", 355 indx - 1); 356 return; 357 } 358 } 359 } 360 361 static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 362 .ulp_irq_stop = bnxt_re_stop_irq, 363 .ulp_irq_restart = bnxt_re_start_irq 364 }; 365 366 /* RoCE -> Net driver */ 367 368 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev) 369 { 370 struct bnxt_en_dev *en_dev; 371 int rc; 372 373 en_dev = rdev->en_dev; 374 375 rc = bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev); 376 if (!rc) 377 rdev->qplib_res.pdev = rdev->en_dev->pdev; 378 return rc; 379 } 380 381 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd) 382 { 383 hdr->req_type = cpu_to_le16(opcd); 384 hdr->cmpl_ring = cpu_to_le16(-1); 385 hdr->target_id = cpu_to_le16(-1); 386 } 387 388 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg, 389 int msg_len, void *resp, int resp_max_len, 390 int timeout) 391 { 392 fw_msg->msg = msg; 393 fw_msg->msg_len = msg_len; 394 fw_msg->resp = resp; 395 fw_msg->resp_max_len = resp_max_len; 396 fw_msg->timeout = timeout; 397 } 398 399 /* Query device config using common hwrm */ 400 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 401 u32 *offset) 402 { 403 struct bnxt_en_dev *en_dev = rdev->en_dev; 404 struct hwrm_func_qcfg_output resp = {0}; 405 struct hwrm_func_qcfg_input req = {0}; 406 struct bnxt_fw_msg fw_msg = {}; 407 int rc; 408 409 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG); 410 req.fid = cpu_to_le16(0xffff); 411 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 412 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 413 rc = bnxt_send_msg(en_dev, &fw_msg); 414 if (!rc) { 415 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024); 416 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024); 417 } 418 return rc; 419 } 420 421 /* Query function capabilities using common hwrm */ 422 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev) 423 { 424 struct bnxt_en_dev *en_dev = rdev->en_dev; 425 struct hwrm_func_qcaps_output resp = {}; 426 struct hwrm_func_qcaps_input req = {}; 427 struct bnxt_qplib_chip_ctx *cctx; 428 struct bnxt_fw_msg fw_msg = {}; 429 int rc; 430 431 cctx = rdev->chip_ctx; 432 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS); 433 req.fid = cpu_to_le16(0xffff); 434 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 435 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 436 437 rc = bnxt_send_msg(en_dev, &fw_msg); 438 if (rc) 439 return rc; 440 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE; 441 442 cctx->modes.dbr_pacing = 443 le32_to_cpu(resp.flags_ext2) & 444 FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED; 445 return 0; 446 } 447 448 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev) 449 { 450 struct hwrm_func_dbr_pacing_qcfg_output resp = {}; 451 struct hwrm_func_dbr_pacing_qcfg_input req = {}; 452 struct bnxt_en_dev *en_dev = rdev->en_dev; 453 struct bnxt_qplib_chip_ctx *cctx; 454 struct bnxt_fw_msg fw_msg = {}; 455 int rc; 456 457 cctx = rdev->chip_ctx; 458 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG); 459 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 460 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 461 rc = bnxt_send_msg(en_dev, &fw_msg); 462 if (rc) 463 return rc; 464 465 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 466 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) == 467 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC) 468 cctx->dbr_stat_db_fifo = 469 le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 470 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK; 471 return 0; 472 } 473 474 /* Update the pacing tunable parameters to the default values */ 475 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev) 476 { 477 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 478 479 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing; 480 pacing_data->pacing_th = rdev->pacing.pacing_algo_th; 481 pacing_data->alarm_th = 482 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 483 } 484 485 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev) 486 { 487 u32 read_val, fifo_occup; 488 489 /* loop shouldn't run infintely as the occupancy usually goes 490 * below pacing algo threshold as soon as pacing kicks in. 491 */ 492 while (1) { 493 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off); 494 fifo_occup = BNXT_RE_MAX_FIFO_DEPTH - 495 ((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >> 496 BNXT_RE_DB_FIFO_ROOM_SHIFT); 497 /* Fifo occupancy cannot be greater the MAX FIFO depth */ 498 if (fifo_occup > BNXT_RE_MAX_FIFO_DEPTH) 499 break; 500 501 if (fifo_occup < rdev->qplib_res.pacing_data->pacing_th) 502 break; 503 } 504 } 505 506 static void bnxt_re_db_fifo_check(struct work_struct *work) 507 { 508 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 509 dbq_fifo_check_work); 510 struct bnxt_qplib_db_pacing_data *pacing_data; 511 u32 pacing_save; 512 513 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 514 return; 515 pacing_data = rdev->qplib_res.pacing_data; 516 pacing_save = rdev->pacing.do_pacing_save; 517 __wait_for_fifo_occupancy_below_th(rdev); 518 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 519 if (pacing_save > rdev->pacing.dbr_def_do_pacing) { 520 /* Double the do_pacing value during the congestion */ 521 pacing_save = pacing_save << 1; 522 } else { 523 /* 524 * when a new congestion is detected increase the do_pacing 525 * by 8 times. And also increase the pacing_th by 4 times. The 526 * reason to increase pacing_th is to give more space for the 527 * queue to oscillate down without getting empty, but also more 528 * room for the queue to increase without causing another alarm. 529 */ 530 pacing_save = pacing_save << 3; 531 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4; 532 } 533 534 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING) 535 pacing_save = BNXT_RE_MAX_DBR_DO_PACING; 536 537 pacing_data->do_pacing = pacing_save; 538 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 539 pacing_data->alarm_th = 540 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 541 schedule_delayed_work(&rdev->dbq_pacing_work, 542 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 543 rdev->stats.pacing.alerts++; 544 mutex_unlock(&rdev->pacing.dbq_lock); 545 } 546 547 static void bnxt_re_pacing_timer_exp(struct work_struct *work) 548 { 549 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 550 dbq_pacing_work.work); 551 struct bnxt_qplib_db_pacing_data *pacing_data; 552 u32 read_val, fifo_occup; 553 554 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 555 return; 556 557 pacing_data = rdev->qplib_res.pacing_data; 558 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off); 559 fifo_occup = BNXT_RE_MAX_FIFO_DEPTH - 560 ((read_val & BNXT_RE_DB_FIFO_ROOM_MASK) >> 561 BNXT_RE_DB_FIFO_ROOM_SHIFT); 562 563 if (fifo_occup > pacing_data->pacing_th) 564 goto restart_timer; 565 566 /* 567 * Instead of immediately going back to the default do_pacing 568 * reduce it by 1/8 times and restart the timer. 569 */ 570 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3); 571 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing); 572 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) { 573 bnxt_re_set_default_pacing_data(rdev); 574 rdev->stats.pacing.complete++; 575 goto dbq_unlock; 576 } 577 578 restart_timer: 579 schedule_delayed_work(&rdev->dbq_pacing_work, 580 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 581 rdev->stats.pacing.resched++; 582 dbq_unlock: 583 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 584 mutex_unlock(&rdev->pacing.dbq_lock); 585 } 586 587 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev) 588 { 589 struct bnxt_qplib_db_pacing_data *pacing_data; 590 591 if (!rdev->pacing.dbr_pacing) 592 return; 593 mutex_lock(&rdev->pacing.dbq_lock); 594 pacing_data = rdev->qplib_res.pacing_data; 595 596 /* 597 * Increase the alarm_th to max so that other user lib instances do not 598 * keep alerting the driver. 599 */ 600 pacing_data->alarm_th = BNXT_RE_MAX_FIFO_DEPTH; 601 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING; 602 cancel_work_sync(&rdev->dbq_fifo_check_work); 603 schedule_work(&rdev->dbq_fifo_check_work); 604 mutex_unlock(&rdev->pacing.dbq_lock); 605 } 606 607 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev) 608 { 609 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) 610 return -EIO; 611 612 /* Allocate a page for app use */ 613 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL); 614 if (!rdev->pacing.dbr_page) 615 return -ENOMEM; 616 617 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE); 618 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page; 619 620 /* MAP HW window 2 for reading db fifo depth */ 621 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK, 622 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 623 rdev->pacing.dbr_db_fifo_reg_off = 624 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) + 625 BNXT_RE_GRC_FIFO_REG_BASE; 626 rdev->pacing.dbr_bar_addr = 627 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off; 628 629 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD; 630 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME; 631 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION; 632 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing; 633 rdev->qplib_res.pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH; 634 rdev->qplib_res.pacing_data->fifo_room_mask = BNXT_RE_DB_FIFO_ROOM_MASK; 635 rdev->qplib_res.pacing_data->fifo_room_shift = BNXT_RE_DB_FIFO_ROOM_SHIFT; 636 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off; 637 bnxt_re_set_default_pacing_data(rdev); 638 /* Initialize worker for DBR Pacing */ 639 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check); 640 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp); 641 return 0; 642 } 643 644 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev) 645 { 646 cancel_work_sync(&rdev->dbq_fifo_check_work); 647 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 648 if (rdev->pacing.dbr_page) 649 free_page((u64)rdev->pacing.dbr_page); 650 651 rdev->pacing.dbr_page = NULL; 652 rdev->pacing.dbr_pacing = false; 653 } 654 655 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev, 656 u16 fw_ring_id, int type) 657 { 658 struct bnxt_en_dev *en_dev; 659 struct hwrm_ring_free_input req = {}; 660 struct hwrm_ring_free_output resp; 661 struct bnxt_fw_msg fw_msg = {}; 662 int rc = -EINVAL; 663 664 if (!rdev) 665 return rc; 666 667 en_dev = rdev->en_dev; 668 669 if (!en_dev) 670 return rc; 671 672 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 673 return 0; 674 675 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE); 676 req.ring_type = type; 677 req.ring_id = cpu_to_le16(fw_ring_id); 678 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 679 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 680 rc = bnxt_send_msg(en_dev, &fw_msg); 681 if (rc) 682 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x", 683 req.ring_id, rc); 684 return rc; 685 } 686 687 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev, 688 struct bnxt_re_ring_attr *ring_attr, 689 u16 *fw_ring_id) 690 { 691 struct bnxt_en_dev *en_dev = rdev->en_dev; 692 struct hwrm_ring_alloc_input req = {}; 693 struct hwrm_ring_alloc_output resp; 694 struct bnxt_fw_msg fw_msg = {}; 695 int rc = -EINVAL; 696 697 if (!en_dev) 698 return rc; 699 700 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC); 701 req.enables = 0; 702 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]); 703 if (ring_attr->pages > 1) { 704 /* Page size is in log2 units */ 705 req.page_size = BNXT_PAGE_SHIFT; 706 req.page_tbl_depth = 1; 707 } 708 req.fbo = 0; 709 /* Association of ring index with doorbell index and MSIX number */ 710 req.logical_id = cpu_to_le16(ring_attr->lrid); 711 req.length = cpu_to_le32(ring_attr->depth + 1); 712 req.ring_type = ring_attr->type; 713 req.int_mode = ring_attr->mode; 714 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 715 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 716 rc = bnxt_send_msg(en_dev, &fw_msg); 717 if (!rc) 718 *fw_ring_id = le16_to_cpu(resp.ring_id); 719 720 return rc; 721 } 722 723 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev, 724 u32 fw_stats_ctx_id) 725 { 726 struct bnxt_en_dev *en_dev = rdev->en_dev; 727 struct hwrm_stat_ctx_free_input req = {}; 728 struct hwrm_stat_ctx_free_output resp = {}; 729 struct bnxt_fw_msg fw_msg = {}; 730 int rc = -EINVAL; 731 732 if (!en_dev) 733 return rc; 734 735 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 736 return 0; 737 738 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE); 739 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id); 740 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 741 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 742 rc = bnxt_send_msg(en_dev, &fw_msg); 743 if (rc) 744 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x", 745 rc); 746 747 return rc; 748 } 749 750 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, 751 dma_addr_t dma_map, 752 u32 *fw_stats_ctx_id) 753 { 754 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx; 755 struct hwrm_stat_ctx_alloc_output resp = {}; 756 struct hwrm_stat_ctx_alloc_input req = {}; 757 struct bnxt_en_dev *en_dev = rdev->en_dev; 758 struct bnxt_fw_msg fw_msg = {}; 759 int rc = -EINVAL; 760 761 *fw_stats_ctx_id = INVALID_STATS_CTX_ID; 762 763 if (!en_dev) 764 return rc; 765 766 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC); 767 req.update_period_ms = cpu_to_le32(1000); 768 req.stats_dma_addr = cpu_to_le64(dma_map); 769 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size); 770 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE; 771 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 772 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 773 rc = bnxt_send_msg(en_dev, &fw_msg); 774 if (!rc) 775 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id); 776 777 return rc; 778 } 779 780 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext) 781 { 782 } 783 784 /* Device */ 785 786 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev) 787 { 788 struct ib_device *ibdev = 789 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE); 790 if (!ibdev) 791 return NULL; 792 793 return container_of(ibdev, struct bnxt_re_dev, ibdev); 794 } 795 796 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 797 char *buf) 798 { 799 struct bnxt_re_dev *rdev = 800 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 801 802 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor); 803 } 804 static DEVICE_ATTR_RO(hw_rev); 805 806 static ssize_t hca_type_show(struct device *device, 807 struct device_attribute *attr, char *buf) 808 { 809 struct bnxt_re_dev *rdev = 810 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 811 812 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc); 813 } 814 static DEVICE_ATTR_RO(hca_type); 815 816 static struct attribute *bnxt_re_attributes[] = { 817 &dev_attr_hw_rev.attr, 818 &dev_attr_hca_type.attr, 819 NULL 820 }; 821 822 static const struct attribute_group bnxt_re_dev_attr_group = { 823 .attrs = bnxt_re_attributes, 824 }; 825 826 static const struct ib_device_ops bnxt_re_dev_ops = { 827 .owner = THIS_MODULE, 828 .driver_id = RDMA_DRIVER_BNXT_RE, 829 .uverbs_abi_ver = BNXT_RE_ABI_VERSION, 830 831 .add_gid = bnxt_re_add_gid, 832 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats, 833 .alloc_mr = bnxt_re_alloc_mr, 834 .alloc_pd = bnxt_re_alloc_pd, 835 .alloc_ucontext = bnxt_re_alloc_ucontext, 836 .create_ah = bnxt_re_create_ah, 837 .create_cq = bnxt_re_create_cq, 838 .create_qp = bnxt_re_create_qp, 839 .create_srq = bnxt_re_create_srq, 840 .create_user_ah = bnxt_re_create_ah, 841 .dealloc_pd = bnxt_re_dealloc_pd, 842 .dealloc_ucontext = bnxt_re_dealloc_ucontext, 843 .del_gid = bnxt_re_del_gid, 844 .dereg_mr = bnxt_re_dereg_mr, 845 .destroy_ah = bnxt_re_destroy_ah, 846 .destroy_cq = bnxt_re_destroy_cq, 847 .destroy_qp = bnxt_re_destroy_qp, 848 .destroy_srq = bnxt_re_destroy_srq, 849 .device_group = &bnxt_re_dev_attr_group, 850 .disassociate_ucontext = bnxt_re_disassociate_ucontext, 851 .get_dev_fw_str = bnxt_re_query_fw_str, 852 .get_dma_mr = bnxt_re_get_dma_mr, 853 .get_hw_stats = bnxt_re_ib_get_hw_stats, 854 .get_link_layer = bnxt_re_get_link_layer, 855 .get_port_immutable = bnxt_re_get_port_immutable, 856 .map_mr_sg = bnxt_re_map_mr_sg, 857 .mmap = bnxt_re_mmap, 858 .mmap_free = bnxt_re_mmap_free, 859 .modify_qp = bnxt_re_modify_qp, 860 .modify_srq = bnxt_re_modify_srq, 861 .poll_cq = bnxt_re_poll_cq, 862 .post_recv = bnxt_re_post_recv, 863 .post_send = bnxt_re_post_send, 864 .post_srq_recv = bnxt_re_post_srq_recv, 865 .query_ah = bnxt_re_query_ah, 866 .query_device = bnxt_re_query_device, 867 .query_pkey = bnxt_re_query_pkey, 868 .query_port = bnxt_re_query_port, 869 .query_qp = bnxt_re_query_qp, 870 .query_srq = bnxt_re_query_srq, 871 .reg_user_mr = bnxt_re_reg_user_mr, 872 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf, 873 .req_notify_cq = bnxt_re_req_notify_cq, 874 .resize_cq = bnxt_re_resize_cq, 875 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah), 876 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq), 877 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd), 878 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp), 879 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq), 880 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx), 881 }; 882 883 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev) 884 { 885 struct ib_device *ibdev = &rdev->ibdev; 886 int ret; 887 888 /* ib device init */ 889 ibdev->node_type = RDMA_NODE_IB_CA; 890 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA", 891 strlen(BNXT_RE_DESC) + 5); 892 ibdev->phys_port_cnt = 1; 893 894 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr); 895 896 ibdev->num_comp_vectors = rdev->num_msix - 1; 897 ibdev->dev.parent = &rdev->en_dev->pdev->dev; 898 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY; 899 900 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 901 ibdev->driver_def = bnxt_re_uapi_defs; 902 903 ib_set_device_ops(ibdev, &bnxt_re_dev_ops); 904 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1); 905 if (ret) 906 return ret; 907 908 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX); 909 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ); 910 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev); 911 } 912 913 static struct bnxt_re_dev *bnxt_re_dev_add(struct bnxt_aux_priv *aux_priv, 914 struct bnxt_en_dev *en_dev) 915 { 916 struct bnxt_re_dev *rdev; 917 918 /* Allocate bnxt_re_dev instance here */ 919 rdev = ib_alloc_device(bnxt_re_dev, ibdev); 920 if (!rdev) { 921 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!", 922 ROCE_DRV_MODULE_NAME); 923 return NULL; 924 } 925 /* Default values */ 926 rdev->nb.notifier_call = NULL; 927 rdev->netdev = en_dev->net; 928 rdev->en_dev = en_dev; 929 rdev->id = rdev->en_dev->pdev->devfn; 930 INIT_LIST_HEAD(&rdev->qp_list); 931 mutex_init(&rdev->qp_lock); 932 mutex_init(&rdev->pacing.dbq_lock); 933 atomic_set(&rdev->stats.res.qp_count, 0); 934 atomic_set(&rdev->stats.res.cq_count, 0); 935 atomic_set(&rdev->stats.res.srq_count, 0); 936 atomic_set(&rdev->stats.res.mr_count, 0); 937 atomic_set(&rdev->stats.res.mw_count, 0); 938 atomic_set(&rdev->stats.res.ah_count, 0); 939 atomic_set(&rdev->stats.res.pd_count, 0); 940 rdev->cosq[0] = 0xFFFF; 941 rdev->cosq[1] = 0xFFFF; 942 943 return rdev; 944 } 945 946 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event 947 *unaffi_async) 948 { 949 switch (unaffi_async->event) { 950 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 951 break; 952 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 953 break; 954 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 955 break; 956 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 957 break; 958 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 959 break; 960 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 961 break; 962 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 963 break; 964 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 965 break; 966 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 967 break; 968 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 969 break; 970 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 971 break; 972 default: 973 return -EINVAL; 974 } 975 return 0; 976 } 977 978 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, 979 struct bnxt_re_qp *qp) 980 { 981 struct bnxt_re_srq *srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq, 982 qplib_srq); 983 struct creq_qp_error_notification *err_event; 984 struct ib_event event = {}; 985 unsigned int flags; 986 987 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR && 988 rdma_is_kernel_res(&qp->ib_qp.res)) { 989 flags = bnxt_re_lock_cqs(qp); 990 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 991 bnxt_re_unlock_cqs(qp, flags); 992 } 993 994 event.device = &qp->rdev->ibdev; 995 event.element.qp = &qp->ib_qp; 996 event.event = IB_EVENT_QP_FATAL; 997 998 err_event = (struct creq_qp_error_notification *)qp_event; 999 1000 switch (err_event->req_err_state_reason) { 1001 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR: 1002 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT: 1003 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT: 1004 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2: 1005 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3: 1006 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP: 1007 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND: 1008 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG: 1009 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE: 1010 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR: 1011 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR: 1012 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR: 1013 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR: 1014 event.event = IB_EVENT_QP_ACCESS_ERR; 1015 break; 1016 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1: 1017 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4: 1018 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH: 1019 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR: 1020 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR: 1021 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR: 1022 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR: 1023 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR: 1024 event.event = IB_EVENT_QP_REQ_ERR; 1025 break; 1026 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR: 1027 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR: 1028 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR: 1029 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR: 1030 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR: 1031 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR: 1032 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR: 1033 event.event = IB_EVENT_QP_FATAL; 1034 break; 1035 1036 default: 1037 break; 1038 } 1039 1040 switch (err_event->res_err_state_reason) { 1041 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX: 1042 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH: 1043 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT: 1044 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY: 1045 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR: 1046 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION: 1047 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR: 1048 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY: 1049 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR: 1050 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION: 1051 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR: 1052 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC: 1053 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND: 1054 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY: 1055 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR: 1056 event.event = IB_EVENT_QP_ACCESS_ERR; 1057 break; 1058 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE: 1059 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR: 1060 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE: 1061 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE: 1062 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR: 1063 event.event = IB_EVENT_QP_REQ_ERR; 1064 break; 1065 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW: 1066 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR: 1067 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR: 1068 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR: 1069 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR: 1070 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR: 1071 event.event = IB_EVENT_QP_FATAL; 1072 break; 1073 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR: 1074 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR: 1075 if (srq) 1076 event.event = IB_EVENT_SRQ_ERR; 1077 break; 1078 default: 1079 break; 1080 } 1081 1082 if (err_event->res_err_state_reason || err_event->req_err_state_reason) { 1083 ibdev_dbg(&qp->rdev->ibdev, 1084 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n", 1085 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user", 1086 qp->qplib_qp.id, 1087 err_event->sq_cons_idx, 1088 err_event->rq_cons_idx, 1089 err_event->req_slow_path_state, 1090 err_event->req_err_state_reason, 1091 err_event->res_slow_path_state, 1092 err_event->res_err_state_reason); 1093 } else { 1094 if (srq) 1095 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 1096 } 1097 1098 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) { 1099 (*srq->ib_srq.event_handler)(&event, 1100 srq->ib_srq.srq_context); 1101 } else if (event.device && qp->ib_qp.event_handler) { 1102 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context); 1103 } 1104 1105 return 0; 1106 } 1107 1108 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq) 1109 { 1110 struct creq_cq_error_notification *cqerr; 1111 struct ib_event ibevent = {}; 1112 1113 cqerr = event; 1114 switch (cqerr->cq_err_reason) { 1115 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR: 1116 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR: 1117 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR: 1118 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR: 1119 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR: 1120 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR: 1121 ibevent.event = IB_EVENT_CQ_ERR; 1122 break; 1123 default: 1124 break; 1125 } 1126 1127 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) { 1128 ibevent.element.cq = &cq->ib_cq; 1129 ibevent.device = &cq->rdev->ibdev; 1130 1131 ibdev_dbg(&cq->rdev->ibdev, 1132 "%s err reason %d\n", __func__, cqerr->cq_err_reason); 1133 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context); 1134 } 1135 1136 return 0; 1137 } 1138 1139 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async, 1140 void *obj) 1141 { 1142 struct bnxt_qplib_qp *lib_qp; 1143 struct bnxt_qplib_cq *lib_cq; 1144 struct bnxt_re_qp *qp; 1145 struct bnxt_re_cq *cq; 1146 int rc = 0; 1147 u8 event; 1148 1149 if (!obj) 1150 return rc; /* QP was already dead, still return success */ 1151 1152 event = affi_async->event; 1153 switch (event) { 1154 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 1155 lib_qp = obj; 1156 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp); 1157 rc = bnxt_re_handle_qp_async_event(affi_async, qp); 1158 break; 1159 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION: 1160 lib_cq = obj; 1161 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq); 1162 rc = bnxt_re_handle_cq_async_error(affi_async, cq); 1163 break; 1164 default: 1165 rc = -EINVAL; 1166 } 1167 return rc; 1168 } 1169 1170 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw, 1171 void *aeqe, void *obj) 1172 { 1173 struct creq_qp_event *affi_async; 1174 struct creq_func_event *unaffi_async; 1175 u8 type; 1176 int rc; 1177 1178 type = ((struct creq_base *)aeqe)->type; 1179 if (type == CREQ_BASE_TYPE_FUNC_EVENT) { 1180 unaffi_async = aeqe; 1181 rc = bnxt_re_handle_unaffi_async_event(unaffi_async); 1182 } else { 1183 affi_async = aeqe; 1184 rc = bnxt_re_handle_affi_async_event(affi_async, obj); 1185 } 1186 1187 return rc; 1188 } 1189 1190 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq, 1191 struct bnxt_qplib_srq *handle, u8 event) 1192 { 1193 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq, 1194 qplib_srq); 1195 struct ib_event ib_event; 1196 1197 ib_event.device = &srq->rdev->ibdev; 1198 ib_event.element.srq = &srq->ib_srq; 1199 1200 if (srq->ib_srq.event_handler) { 1201 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 1202 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 1203 (*srq->ib_srq.event_handler)(&ib_event, 1204 srq->ib_srq.srq_context); 1205 } 1206 return 0; 1207 } 1208 1209 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq, 1210 struct bnxt_qplib_cq *handle) 1211 { 1212 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq, 1213 qplib_cq); 1214 u32 *cq_ptr; 1215 1216 if (cq->ib_cq.comp_handler) { 1217 if (cq->uctx_cq_page) { 1218 cq_ptr = (u32 *)cq->uctx_cq_page; 1219 *cq_ptr = cq->qplib_cq.toggle; 1220 } 1221 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context); 1222 } 1223 1224 return 0; 1225 } 1226 1227 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev) 1228 { 1229 int i; 1230 1231 for (i = 1; i < rdev->num_msix; i++) 1232 bnxt_qplib_disable_nq(&rdev->nq[i - 1]); 1233 1234 if (rdev->qplib_res.rcfw) 1235 bnxt_qplib_cleanup_res(&rdev->qplib_res); 1236 } 1237 1238 static int bnxt_re_init_res(struct bnxt_re_dev *rdev) 1239 { 1240 int num_vec_enabled = 0; 1241 int rc = 0, i; 1242 u32 db_offt; 1243 1244 bnxt_qplib_init_res(&rdev->qplib_res); 1245 1246 for (i = 1; i < rdev->num_msix ; i++) { 1247 db_offt = rdev->en_dev->msix_entries[i].db_offset; 1248 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1], 1249 i - 1, rdev->en_dev->msix_entries[i].vector, 1250 db_offt, &bnxt_re_cqn_handler, 1251 &bnxt_re_srqn_handler); 1252 if (rc) { 1253 ibdev_err(&rdev->ibdev, 1254 "Failed to enable NQ with rc = 0x%x", rc); 1255 goto fail; 1256 } 1257 num_vec_enabled++; 1258 } 1259 return 0; 1260 fail: 1261 for (i = num_vec_enabled; i >= 0; i--) 1262 bnxt_qplib_disable_nq(&rdev->nq[i]); 1263 return rc; 1264 } 1265 1266 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev) 1267 { 1268 u8 type; 1269 int i; 1270 1271 for (i = 0; i < rdev->num_msix - 1; i++) { 1272 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1273 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1274 bnxt_qplib_free_nq(&rdev->nq[i]); 1275 rdev->nq[i].res = NULL; 1276 } 1277 } 1278 1279 static void bnxt_re_free_res(struct bnxt_re_dev *rdev) 1280 { 1281 bnxt_re_free_nq_res(rdev); 1282 1283 if (rdev->qplib_res.dpi_tbl.max) { 1284 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1285 &rdev->dpi_privileged); 1286 } 1287 if (rdev->qplib_res.rcfw) { 1288 bnxt_qplib_free_res(&rdev->qplib_res); 1289 rdev->qplib_res.rcfw = NULL; 1290 } 1291 } 1292 1293 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev) 1294 { 1295 struct bnxt_re_ring_attr rattr = {}; 1296 int num_vec_created = 0; 1297 int rc, i; 1298 u8 type; 1299 1300 /* Configure and allocate resources for qplib */ 1301 rdev->qplib_res.rcfw = &rdev->rcfw; 1302 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1303 if (rc) 1304 goto fail; 1305 1306 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev, 1307 rdev->netdev, &rdev->dev_attr); 1308 if (rc) 1309 goto fail; 1310 1311 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res, 1312 &rdev->dpi_privileged, 1313 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL); 1314 if (rc) 1315 goto dealloc_res; 1316 1317 for (i = 0; i < rdev->num_msix - 1; i++) { 1318 struct bnxt_qplib_nq *nq; 1319 1320 nq = &rdev->nq[i]; 1321 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT; 1322 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]); 1323 if (rc) { 1324 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x", 1325 i, rc); 1326 goto free_nq; 1327 } 1328 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1329 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1330 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count; 1331 rattr.type = type; 1332 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1333 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1; 1334 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx; 1335 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id); 1336 if (rc) { 1337 ibdev_err(&rdev->ibdev, 1338 "Failed to allocate NQ fw id with rc = 0x%x", 1339 rc); 1340 bnxt_qplib_free_nq(&rdev->nq[i]); 1341 goto free_nq; 1342 } 1343 num_vec_created++; 1344 } 1345 return 0; 1346 free_nq: 1347 for (i = num_vec_created - 1; i >= 0; i--) { 1348 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1349 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 1350 bnxt_qplib_free_nq(&rdev->nq[i]); 1351 } 1352 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1353 &rdev->dpi_privileged); 1354 dealloc_res: 1355 bnxt_qplib_free_res(&rdev->qplib_res); 1356 1357 fail: 1358 rdev->qplib_res.rcfw = NULL; 1359 return rc; 1360 } 1361 1362 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 1363 u8 port_num, enum ib_event_type event) 1364 { 1365 struct ib_event ib_event; 1366 1367 ib_event.device = ibdev; 1368 if (qp) { 1369 ib_event.element.qp = qp; 1370 ib_event.event = event; 1371 if (qp->event_handler) 1372 qp->event_handler(&ib_event, qp->qp_context); 1373 1374 } else { 1375 ib_event.element.port_num = port_num; 1376 ib_event.event = event; 1377 ib_dispatch_event(&ib_event); 1378 } 1379 } 1380 1381 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev, 1382 struct bnxt_re_qp *qp) 1383 { 1384 return (qp->ib_qp.qp_type == IB_QPT_GSI) || 1385 (qp == rdev->gsi_ctx.gsi_sqp); 1386 } 1387 1388 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev) 1389 { 1390 int mask = IB_QP_STATE; 1391 struct ib_qp_attr qp_attr; 1392 struct bnxt_re_qp *qp; 1393 1394 qp_attr.qp_state = IB_QPS_ERR; 1395 mutex_lock(&rdev->qp_lock); 1396 list_for_each_entry(qp, &rdev->qp_list, list) { 1397 /* Modify the state of all QPs except QP1/Shadow QP */ 1398 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) { 1399 if (qp->qplib_qp.state != 1400 CMDQ_MODIFY_QP_NEW_STATE_RESET && 1401 qp->qplib_qp.state != 1402 CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1403 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp, 1404 1, IB_EVENT_QP_FATAL); 1405 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask, 1406 NULL); 1407 } 1408 } 1409 } 1410 mutex_unlock(&rdev->qp_lock); 1411 } 1412 1413 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev) 1414 { 1415 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 1416 struct bnxt_qplib_gid gid; 1417 u16 gid_idx, index; 1418 int rc = 0; 1419 1420 if (!ib_device_try_get(&rdev->ibdev)) 1421 return 0; 1422 1423 for (index = 0; index < sgid_tbl->active; index++) { 1424 gid_idx = sgid_tbl->hw_id[index]; 1425 1426 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero, 1427 sizeof(bnxt_qplib_gid_zero))) 1428 continue; 1429 /* need to modify the VLAN enable setting of non VLAN GID only 1430 * as setting is done for VLAN GID while adding GID 1431 */ 1432 if (sgid_tbl->vlan[index]) 1433 continue; 1434 1435 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid)); 1436 1437 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx, 1438 rdev->qplib_res.netdev->dev_addr); 1439 } 1440 1441 ib_device_put(&rdev->ibdev); 1442 return rc; 1443 } 1444 1445 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev) 1446 { 1447 u32 prio_map = 0, tmp_map = 0; 1448 struct net_device *netdev; 1449 struct dcb_app app = {}; 1450 1451 netdev = rdev->netdev; 1452 1453 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE; 1454 app.protocol = ETH_P_IBOE; 1455 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1456 prio_map = tmp_map; 1457 1458 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM; 1459 app.protocol = ROCE_V2_UDP_DPORT; 1460 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1461 prio_map |= tmp_map; 1462 1463 return prio_map; 1464 } 1465 1466 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev) 1467 { 1468 u8 prio_map = 0; 1469 1470 /* Get priority for roce */ 1471 prio_map = bnxt_re_get_priority_mask(rdev); 1472 1473 if (prio_map == rdev->cur_prio_map) 1474 return 0; 1475 rdev->cur_prio_map = prio_map; 1476 /* Actual priorities are not programmed as they are already 1477 * done by L2 driver; just enable or disable priority vlan tagging 1478 */ 1479 if ((prio_map == 0 && rdev->qplib_res.prio) || 1480 (prio_map != 0 && !rdev->qplib_res.prio)) { 1481 rdev->qplib_res.prio = prio_map; 1482 bnxt_re_update_gid(rdev); 1483 } 1484 1485 return 0; 1486 } 1487 1488 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev) 1489 { 1490 struct bnxt_en_dev *en_dev = rdev->en_dev; 1491 struct hwrm_ver_get_output resp = {}; 1492 struct hwrm_ver_get_input req = {}; 1493 struct bnxt_qplib_chip_ctx *cctx; 1494 struct bnxt_fw_msg fw_msg = {}; 1495 int rc; 1496 1497 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET); 1498 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 1499 req.hwrm_intf_min = HWRM_VERSION_MINOR; 1500 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 1501 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 1502 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 1503 rc = bnxt_send_msg(en_dev, &fw_msg); 1504 if (rc) { 1505 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x", 1506 rc); 1507 return; 1508 } 1509 1510 cctx = rdev->chip_ctx; 1511 cctx->hwrm_intf_ver = 1512 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 | 1513 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 | 1514 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 | 1515 le16_to_cpu(resp.hwrm_intf_patch); 1516 1517 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout); 1518 1519 if (!cctx->hwrm_cmd_max_timeout) 1520 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT; 1521 } 1522 1523 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev) 1524 { 1525 int rc; 1526 u32 event; 1527 1528 /* Register ib dev */ 1529 rc = bnxt_re_register_ib(rdev); 1530 if (rc) { 1531 pr_err("Failed to register with IB: %#x\n", rc); 1532 return rc; 1533 } 1534 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully"); 1535 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags); 1536 1537 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ? 1538 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 1539 1540 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event); 1541 1542 return rc; 1543 } 1544 1545 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev) 1546 { 1547 u8 type; 1548 int rc; 1549 1550 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags)) 1551 cancel_delayed_work_sync(&rdev->worker); 1552 1553 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, 1554 &rdev->flags)) 1555 bnxt_re_cleanup_res(rdev); 1556 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags)) 1557 bnxt_re_free_res(rdev); 1558 1559 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) { 1560 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw); 1561 if (rc) 1562 ibdev_warn(&rdev->ibdev, 1563 "Failed to deinitialize RCFW: %#x", rc); 1564 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1565 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1566 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1567 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1568 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1569 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1570 } 1571 1572 rdev->num_msix = 0; 1573 1574 if (rdev->pacing.dbr_pacing) 1575 bnxt_re_deinitialize_dbr_pacing(rdev); 1576 1577 bnxt_re_destroy_chip_ctx(rdev); 1578 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) 1579 bnxt_unregister_dev(rdev->en_dev); 1580 } 1581 1582 /* worker thread for polling periodic events. Now used for QoS programming*/ 1583 static void bnxt_re_worker(struct work_struct *work) 1584 { 1585 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 1586 worker.work); 1587 1588 bnxt_re_setup_qos(rdev); 1589 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1590 } 1591 1592 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode) 1593 { 1594 struct bnxt_re_ring_attr rattr = {}; 1595 struct bnxt_qplib_creq_ctx *creq; 1596 u32 db_offt; 1597 int vid; 1598 u8 type; 1599 int rc; 1600 1601 /* Registered a new RoCE device instance to netdev */ 1602 rc = bnxt_re_register_netdev(rdev); 1603 if (rc) { 1604 ibdev_err(&rdev->ibdev, 1605 "Failed to register with netedev: %#x\n", rc); 1606 return -EINVAL; 1607 } 1608 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1609 1610 rc = bnxt_re_setup_chip_ctx(rdev, wqe_mode); 1611 if (rc) { 1612 bnxt_unregister_dev(rdev->en_dev); 1613 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1614 ibdev_err(&rdev->ibdev, "Failed to get chip context\n"); 1615 return -EINVAL; 1616 } 1617 1618 /* Check whether VF or PF */ 1619 bnxt_re_get_sriov_func_type(rdev); 1620 1621 if (!rdev->en_dev->ulp_tbl->msix_requested) { 1622 ibdev_err(&rdev->ibdev, 1623 "Failed to get MSI-X vectors: %#x\n", rc); 1624 rc = -EINVAL; 1625 goto fail; 1626 } 1627 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n", 1628 rdev->en_dev->ulp_tbl->msix_requested); 1629 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested; 1630 1631 bnxt_re_query_hwrm_intf_version(rdev); 1632 1633 /* Establish RCFW Communication Channel to initialize the context 1634 * memory for the function and all child VFs 1635 */ 1636 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw, 1637 &rdev->qplib_ctx, 1638 BNXT_RE_MAX_QPC_COUNT); 1639 if (rc) { 1640 ibdev_err(&rdev->ibdev, 1641 "Failed to allocate RCFW Channel: %#x\n", rc); 1642 goto fail; 1643 } 1644 1645 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1646 creq = &rdev->rcfw.creq; 1647 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1648 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count; 1649 rattr.type = type; 1650 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1651 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1; 1652 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx; 1653 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id); 1654 if (rc) { 1655 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc); 1656 goto free_rcfw; 1657 } 1658 db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset; 1659 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector; 1660 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw, 1661 vid, db_offt, 1662 &bnxt_re_aeq_handler); 1663 if (rc) { 1664 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n", 1665 rc); 1666 goto free_ring; 1667 } 1668 1669 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) { 1670 rc = bnxt_re_initialize_dbr_pacing(rdev); 1671 if (!rc) { 1672 rdev->pacing.dbr_pacing = true; 1673 } else { 1674 ibdev_err(&rdev->ibdev, 1675 "DBR pacing disabled with error : %d\n", rc); 1676 rdev->pacing.dbr_pacing = false; 1677 } 1678 } 1679 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1680 if (rc) 1681 goto disable_rcfw; 1682 1683 bnxt_re_set_resource_limits(rdev); 1684 1685 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0, 1686 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)); 1687 if (rc) { 1688 ibdev_err(&rdev->ibdev, 1689 "Failed to allocate QPLIB context: %#x\n", rc); 1690 goto disable_rcfw; 1691 } 1692 rc = bnxt_re_net_stats_ctx_alloc(rdev, 1693 rdev->qplib_ctx.stats.dma_map, 1694 &rdev->qplib_ctx.stats.fw_id); 1695 if (rc) { 1696 ibdev_err(&rdev->ibdev, 1697 "Failed to allocate stats context: %#x\n", rc); 1698 goto free_ctx; 1699 } 1700 1701 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx, 1702 rdev->is_virtfn); 1703 if (rc) { 1704 ibdev_err(&rdev->ibdev, 1705 "Failed to initialize RCFW: %#x\n", rc); 1706 goto free_sctx; 1707 } 1708 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags); 1709 1710 /* Resources based on the 'new' device caps */ 1711 rc = bnxt_re_alloc_res(rdev); 1712 if (rc) { 1713 ibdev_err(&rdev->ibdev, 1714 "Failed to allocate resources: %#x\n", rc); 1715 goto fail; 1716 } 1717 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags); 1718 rc = bnxt_re_init_res(rdev); 1719 if (rc) { 1720 ibdev_err(&rdev->ibdev, 1721 "Failed to initialize resources: %#x\n", rc); 1722 goto fail; 1723 } 1724 1725 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags); 1726 1727 if (!rdev->is_virtfn) { 1728 rc = bnxt_re_setup_qos(rdev); 1729 if (rc) 1730 ibdev_info(&rdev->ibdev, 1731 "RoCE priority not yet configured\n"); 1732 1733 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker); 1734 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags); 1735 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1736 /* 1737 * Use the total VF count since the actual VF count may not be 1738 * available at this point. 1739 */ 1740 bnxt_re_vf_res_config(rdev); 1741 } 1742 hash_init(rdev->cq_hash); 1743 1744 return 0; 1745 free_sctx: 1746 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1747 free_ctx: 1748 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1749 disable_rcfw: 1750 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1751 free_ring: 1752 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1753 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1754 free_rcfw: 1755 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1756 fail: 1757 bnxt_re_dev_uninit(rdev); 1758 1759 return rc; 1760 } 1761 1762 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 wqe_mode) 1763 { 1764 struct bnxt_aux_priv *aux_priv = 1765 container_of(adev, struct bnxt_aux_priv, aux_dev); 1766 struct bnxt_en_dev *en_dev; 1767 struct bnxt_re_dev *rdev; 1768 int rc; 1769 1770 /* en_dev should never be NULL as long as adev and aux_dev are valid. */ 1771 en_dev = aux_priv->edev; 1772 1773 rdev = bnxt_re_dev_add(aux_priv, en_dev); 1774 if (!rdev || !rdev_to_dev(rdev)) { 1775 rc = -ENOMEM; 1776 goto exit; 1777 } 1778 1779 rc = bnxt_re_dev_init(rdev, wqe_mode); 1780 if (rc) 1781 goto re_dev_dealloc; 1782 1783 rc = bnxt_re_ib_init(rdev); 1784 if (rc) { 1785 pr_err("Failed to register with IB: %s", 1786 aux_priv->aux_dev.name); 1787 goto re_dev_uninit; 1788 } 1789 auxiliary_set_drvdata(adev, rdev); 1790 1791 return 0; 1792 1793 re_dev_uninit: 1794 bnxt_re_dev_uninit(rdev); 1795 re_dev_dealloc: 1796 ib_dealloc_device(&rdev->ibdev); 1797 exit: 1798 return rc; 1799 } 1800 1801 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 1802 { 1803 struct bnxt_qplib_cc_param cc_param = {}; 1804 1805 /* Do not enable congestion control on VFs */ 1806 if (rdev->is_virtfn) 1807 return; 1808 1809 /* Currently enabling only for GenP5 adapters */ 1810 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 1811 return; 1812 1813 if (enable) { 1814 cc_param.enable = 1; 1815 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE; 1816 } 1817 1818 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE | 1819 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 1820 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 1821 1822 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 1823 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 1824 } 1825 1826 /* 1827 * "Notifier chain callback can be invoked for the same chain from 1828 * different CPUs at the same time". 1829 * 1830 * For cases when the netdev is already present, our call to the 1831 * register_netdevice_notifier() will actually get the rtnl_lock() 1832 * before sending NETDEV_REGISTER and (if up) NETDEV_UP 1833 * events. 1834 * 1835 * But for cases when the netdev is not already present, the notifier 1836 * chain is subjected to be invoked from different CPUs simultaneously. 1837 * 1838 * This is protected by the netdev_mutex. 1839 */ 1840 static int bnxt_re_netdev_event(struct notifier_block *notifier, 1841 unsigned long event, void *ptr) 1842 { 1843 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr); 1844 struct bnxt_re_dev *rdev; 1845 1846 real_dev = rdma_vlan_dev_real_dev(netdev); 1847 if (!real_dev) 1848 real_dev = netdev; 1849 1850 if (real_dev != netdev) 1851 goto exit; 1852 1853 rdev = bnxt_re_from_netdev(real_dev); 1854 if (!rdev) 1855 return NOTIFY_DONE; 1856 1857 1858 switch (event) { 1859 case NETDEV_UP: 1860 case NETDEV_DOWN: 1861 case NETDEV_CHANGE: 1862 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 1863 netif_carrier_ok(real_dev) ? 1864 IB_EVENT_PORT_ACTIVE : 1865 IB_EVENT_PORT_ERR); 1866 break; 1867 default: 1868 break; 1869 } 1870 ib_device_put(&rdev->ibdev); 1871 exit: 1872 return NOTIFY_DONE; 1873 } 1874 1875 #define BNXT_ADEV_NAME "bnxt_en" 1876 1877 static void bnxt_re_remove(struct auxiliary_device *adev) 1878 { 1879 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1880 1881 if (!rdev) 1882 return; 1883 1884 mutex_lock(&bnxt_re_mutex); 1885 if (rdev->nb.notifier_call) { 1886 unregister_netdevice_notifier(&rdev->nb); 1887 rdev->nb.notifier_call = NULL; 1888 } else { 1889 /* If notifier is null, we should have already done a 1890 * clean up before coming here. 1891 */ 1892 goto skip_remove; 1893 } 1894 bnxt_re_setup_cc(rdev, false); 1895 ib_unregister_device(&rdev->ibdev); 1896 bnxt_re_dev_uninit(rdev); 1897 ib_dealloc_device(&rdev->ibdev); 1898 skip_remove: 1899 mutex_unlock(&bnxt_re_mutex); 1900 } 1901 1902 static int bnxt_re_probe(struct auxiliary_device *adev, 1903 const struct auxiliary_device_id *id) 1904 { 1905 struct bnxt_re_dev *rdev; 1906 int rc; 1907 1908 mutex_lock(&bnxt_re_mutex); 1909 rc = bnxt_re_add_device(adev, BNXT_QPLIB_WQE_MODE_STATIC); 1910 if (rc) { 1911 mutex_unlock(&bnxt_re_mutex); 1912 return rc; 1913 } 1914 1915 rdev = auxiliary_get_drvdata(adev); 1916 1917 rdev->nb.notifier_call = bnxt_re_netdev_event; 1918 rc = register_netdevice_notifier(&rdev->nb); 1919 if (rc) { 1920 rdev->nb.notifier_call = NULL; 1921 pr_err("%s: Cannot register to netdevice_notifier", 1922 ROCE_DRV_MODULE_NAME); 1923 goto err; 1924 } 1925 1926 bnxt_re_setup_cc(rdev, true); 1927 mutex_unlock(&bnxt_re_mutex); 1928 return 0; 1929 1930 err: 1931 mutex_unlock(&bnxt_re_mutex); 1932 bnxt_re_remove(adev); 1933 1934 return rc; 1935 } 1936 1937 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state) 1938 { 1939 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1940 1941 if (!rdev) 1942 return 0; 1943 1944 mutex_lock(&bnxt_re_mutex); 1945 /* L2 driver may invoke this callback during device error/crash or device 1946 * reset. Current RoCE driver doesn't recover the device in case of 1947 * error. Handle the error by dispatching fatal events to all qps 1948 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 1949 * L2 driver want to modify the MSIx table. 1950 */ 1951 1952 ibdev_info(&rdev->ibdev, "Handle device suspend call"); 1953 /* Check the current device state from bnxt_en_dev and move the 1954 * device to detached state if FW_FATAL_COND is set. 1955 * This prevents more commands to HW during clean-up, 1956 * in case the device is already in error. 1957 */ 1958 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) 1959 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 1960 1961 bnxt_re_dev_stop(rdev); 1962 bnxt_re_stop_irq(rdev); 1963 /* Move the device states to detached and avoid sending any more 1964 * commands to HW 1965 */ 1966 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 1967 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 1968 wake_up_all(&rdev->rcfw.cmdq.waitq); 1969 mutex_unlock(&bnxt_re_mutex); 1970 1971 return 0; 1972 } 1973 1974 static int bnxt_re_resume(struct auxiliary_device *adev) 1975 { 1976 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1977 1978 if (!rdev) 1979 return 0; 1980 1981 mutex_lock(&bnxt_re_mutex); 1982 /* L2 driver may invoke this callback during device recovery, resume. 1983 * reset. Current RoCE driver doesn't recover the device in case of 1984 * error. Handle the error by dispatching fatal events to all qps 1985 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 1986 * L2 driver want to modify the MSIx table. 1987 */ 1988 1989 ibdev_info(&rdev->ibdev, "Handle device resume call"); 1990 mutex_unlock(&bnxt_re_mutex); 1991 1992 return 0; 1993 } 1994 1995 static const struct auxiliary_device_id bnxt_re_id_table[] = { 1996 { .name = BNXT_ADEV_NAME ".rdma", }, 1997 {}, 1998 }; 1999 2000 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table); 2001 2002 static struct auxiliary_driver bnxt_re_driver = { 2003 .name = "rdma", 2004 .probe = bnxt_re_probe, 2005 .remove = bnxt_re_remove, 2006 .shutdown = bnxt_re_shutdown, 2007 .suspend = bnxt_re_suspend, 2008 .resume = bnxt_re_resume, 2009 .id_table = bnxt_re_id_table, 2010 }; 2011 2012 static int __init bnxt_re_mod_init(void) 2013 { 2014 int rc; 2015 2016 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version); 2017 rc = auxiliary_driver_register(&bnxt_re_driver); 2018 if (rc) { 2019 pr_err("%s: Failed to register auxiliary driver\n", 2020 ROCE_DRV_MODULE_NAME); 2021 return rc; 2022 } 2023 return 0; 2024 } 2025 2026 static void __exit bnxt_re_mod_exit(void) 2027 { 2028 auxiliary_driver_unregister(&bnxt_re_driver); 2029 } 2030 2031 module_init(bnxt_re_mod_init); 2032 module_exit(bnxt_re_mod_exit); 2033